1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the PPC specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCSubtarget.h"
14 #include "GISel/PPCCallLowering.h"
15 #include "GISel/PPCLegalizerInfo.h"
16 #include "GISel/PPCRegisterBankInfo.h"
17 #include "PPC.h"
18 #include "PPCRegisterInfo.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineScheduler.h"
23 #include "llvm/IR/Attributes.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/IR/GlobalValue.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include <cstdlib>
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "ppc-subtarget"
34 
35 #define GET_SUBTARGETINFO_TARGET_DESC
36 #define GET_SUBTARGETINFO_CTOR
37 #include "PPCGenSubtargetInfo.inc"
38 
39 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
40 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
41 
42 static cl::opt<bool>
43     EnableMachinePipeliner("ppc-enable-pipeliner",
44                            cl::desc("Enable Machine Pipeliner for PPC"),
45                            cl::init(false), cl::Hidden);
46 
47 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
48                                                             StringRef FS) {
49   initializeEnvironment();
50   initSubtargetFeatures(CPU, FS);
51   return *this;
52 }
53 
54 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
55                            const std::string &FS, const PPCTargetMachine &TM)
56     : PPCGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TargetTriple(TT),
57       IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
58               TargetTriple.getArch() == Triple::ppc64le),
59       TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
60       InstrInfo(*this), TLInfo(TM, *this) {
61   CallLoweringInfo.reset(new PPCCallLowering(*getTargetLowering()));
62   Legalizer.reset(new PPCLegalizerInfo(*this));
63   auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo());
64   RegBankInfo.reset(RBI);
65 
66   InstSelector.reset(createPPCInstructionSelector(
67       *static_cast<const PPCTargetMachine *>(&TM), *this, *RBI));
68 }
69 
70 void PPCSubtarget::initializeEnvironment() {
71   StackAlignment = Align(16);
72   CPUDirective = PPC::DIR_NONE;
73   HasMFOCRF = false;
74   Has64BitSupport = false;
75   Use64BitRegs = false;
76   UseCRBits = false;
77   HasHardFloat = false;
78   HasAltivec = false;
79   HasSPE = false;
80   HasEFPU2 = false;
81   HasFPU = false;
82   HasVSX = false;
83   NeedsTwoConstNR = false;
84   HasP8Vector = false;
85   HasP8Altivec = false;
86   HasP8Crypto = false;
87   HasP9Vector = false;
88   HasP9Altivec = false;
89   HasMMA = false;
90   HasROPProtection = false;
91   HasP10Vector = false;
92   HasPrefixInstrs = false;
93   HasPCRelativeMemops = false;
94   HasFCPSGN = false;
95   HasFSQRT = false;
96   HasFRE = false;
97   HasFRES = false;
98   HasFRSQRTE = false;
99   HasFRSQRTES = false;
100   HasRecipPrec = false;
101   HasSTFIWX = false;
102   HasLFIWAX = false;
103   HasFPRND = false;
104   HasFPCVT = false;
105   HasISEL = false;
106   HasBPERMD = false;
107   HasExtDiv = false;
108   HasCMPB = false;
109   HasLDBRX = false;
110   IsBookE = false;
111   HasOnlyMSYNC = false;
112   IsPPC4xx = false;
113   IsPPC6xx = false;
114   IsE500 = false;
115   FeatureMFTB = false;
116   AllowsUnalignedFPAccess = false;
117   DeprecatedDST = false;
118   HasICBT = false;
119   HasInvariantFunctionDescriptors = false;
120   HasPartwordAtomics = false;
121   HasDirectMove = false;
122   HasHTM = false;
123   HasFloat128 = false;
124   HasFusion = false;
125   HasStoreFusion = false;
126   HasAddiLoadFusion = false;
127   HasAddisLoadFusion = false;
128   IsISA3_0 = false;
129   IsISA3_1 = false;
130   UseLongCalls = false;
131   SecurePlt = false;
132   VectorsUseTwoUnits = false;
133   UsePPCPreRASchedStrategy = false;
134   UsePPCPostRASchedStrategy = false;
135   PairedVectorMemops = false;
136   PredictableSelectIsExpensive = false;
137   HasModernAIXAs = false;
138   IsAIX = false;
139 
140   HasPOPCNTD = POPCNTD_Unavailable;
141 }
142 
143 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
144   // Determine default and user specified characteristics
145   std::string CPUName = std::string(CPU);
146   if (CPUName.empty() || CPU == "generic") {
147     // If cross-compiling with -march=ppc64le without -mcpu
148     if (TargetTriple.getArch() == Triple::ppc64le)
149       CPUName = "ppc64le";
150     else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe)
151       CPUName = "e500";
152     else
153       CPUName = "generic";
154   }
155 
156   // Initialize scheduling itinerary for the specified CPU.
157   InstrItins = getInstrItineraryForCPU(CPUName);
158 
159   // Parse features string.
160   ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
161 
162   // If the user requested use of 64-bit regs, but the cpu selected doesn't
163   // support it, ignore.
164   if (IsPPC64 && has64BitSupport())
165     Use64BitRegs = true;
166 
167   if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) ||
168       TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() ||
169       TargetTriple.isMusl())
170     SecurePlt = true;
171 
172   if (HasSPE && IsPPC64)
173     report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
174   if (HasSPE && (HasAltivec || HasVSX || HasFPU))
175     report_fatal_error(
176         "SPE and traditional floating point cannot both be enabled.\n", false);
177 
178   // If not SPE, set standard FPU
179   if (!HasSPE)
180     HasFPU = true;
181 
182   StackAlignment = getPlatformStackAlignment();
183 
184   // Determine endianness.
185   IsLittleEndian = TM.isLittleEndian();
186 }
187 
188 bool PPCSubtarget::enableMachineScheduler() const { return true; }
189 
190 bool PPCSubtarget::enableMachinePipeliner() const {
191   return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner;
192 }
193 
194 bool PPCSubtarget::useDFAforSMS() const { return false; }
195 
196 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
197 bool PPCSubtarget::enablePostRAScheduler() const { return true; }
198 
199 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
200   return TargetSubtargetInfo::ANTIDEP_ALL;
201 }
202 
203 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
204   CriticalPathRCs.clear();
205   CriticalPathRCs.push_back(isPPC64() ?
206                             &PPC::G8RCRegClass : &PPC::GPRCRegClass);
207 }
208 
209 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
210                                        unsigned NumRegionInstrs) const {
211   // The GenericScheduler that we use defaults to scheduling bottom up only.
212   // We want to schedule from both the top and the bottom and so we set
213   // OnlyBottomUp to false.
214   // We want to do bi-directional scheduling since it provides a more balanced
215   // schedule leading to better performance.
216   Policy.OnlyBottomUp = false;
217   // Spilling is generally expensive on all PPC cores, so always enable
218   // register-pressure tracking.
219   Policy.ShouldTrackPressure = true;
220 }
221 
222 bool PPCSubtarget::useAA() const {
223   return true;
224 }
225 
226 bool PPCSubtarget::enableSubRegLiveness() const {
227   return UseSubRegLiveness;
228 }
229 
230 bool PPCSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
231   // Large code model always uses the TOC even for local symbols.
232   if (TM.getCodeModel() == CodeModel::Large)
233     return true;
234   if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
235     return false;
236   return true;
237 }
238 
239 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
240 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
241 
242 bool PPCSubtarget::isUsingPCRelativeCalls() const {
243   return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() &&
244          CodeModel::Medium == getTargetMachine().getCodeModel();
245 }
246 
247 // GlobalISEL
248 const CallLowering *PPCSubtarget::getCallLowering() const {
249   return CallLoweringInfo.get();
250 }
251 
252 const RegisterBankInfo *PPCSubtarget::getRegBankInfo() const {
253   return RegBankInfo.get();
254 }
255 
256 const LegalizerInfo *PPCSubtarget::getLegalizerInfo() const {
257   return Legalizer.get();
258 }
259 
260 InstructionSelector *PPCSubtarget::getInstructionSelector() const {
261   return InstSelector.get();
262 }
263