1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the PPC specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCSubtarget.h"
14 #include "GISel/PPCCallLowering.h"
15 #include "GISel/PPCLegalizerInfo.h"
16 #include "GISel/PPCRegisterBankInfo.h"
17 #include "PPC.h"
18 #include "PPCRegisterInfo.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineScheduler.h"
23 #include "llvm/IR/Attributes.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/IR/GlobalValue.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include <cstdlib>
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "ppc-subtarget"
34 
35 #define GET_SUBTARGETINFO_TARGET_DESC
36 #define GET_SUBTARGETINFO_CTOR
37 #include "PPCGenSubtargetInfo.inc"
38 
39 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
40 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
41 
42 static cl::opt<bool>
43     EnableMachinePipeliner("ppc-enable-pipeliner",
44                            cl::desc("Enable Machine Pipeliner for PPC"),
45                            cl::init(false), cl::Hidden);
46 
47 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
48                                                             StringRef FS) {
49   initializeEnvironment();
50   initSubtargetFeatures(CPU, FS);
51   return *this;
52 }
53 
54 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
55                            const std::string &FS, const PPCTargetMachine &TM)
56     : PPCGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TargetTriple(TT),
57       IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
58               TargetTriple.getArch() == Triple::ppc64le),
59       TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
60       InstrInfo(*this), TLInfo(TM, *this) {
61   CallLoweringInfo.reset(new PPCCallLowering(*getTargetLowering()));
62   Legalizer.reset(new PPCLegalizerInfo(*this));
63   auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo());
64   RegBankInfo.reset(RBI);
65 
66   InstSelector.reset(createPPCInstructionSelector(
67       *static_cast<const PPCTargetMachine *>(&TM), *this, *RBI));
68 }
69 
70 void PPCSubtarget::initializeEnvironment() {
71   StackAlignment = Align(16);
72   CPUDirective = PPC::DIR_NONE;
73   HasMFOCRF = false;
74   Has64BitSupport = false;
75   Use64BitRegs = false;
76   UseCRBits = false;
77   HasHardFloat = false;
78   HasAltivec = false;
79   HasSPE = false;
80   HasFPU = false;
81   HasVSX = false;
82   NeedsTwoConstNR = false;
83   HasP8Vector = false;
84   HasP8Altivec = false;
85   HasP8Crypto = false;
86   HasP9Vector = false;
87   HasP9Altivec = false;
88   HasMMA = false;
89   HasP10Vector = false;
90   HasPrefixInstrs = false;
91   HasPCRelativeMemops = false;
92   HasFCPSGN = false;
93   HasFSQRT = false;
94   HasFRE = false;
95   HasFRES = false;
96   HasFRSQRTE = false;
97   HasFRSQRTES = false;
98   HasRecipPrec = false;
99   HasSTFIWX = false;
100   HasLFIWAX = false;
101   HasFPRND = false;
102   HasFPCVT = false;
103   HasISEL = false;
104   HasBPERMD = false;
105   HasExtDiv = false;
106   HasCMPB = false;
107   HasLDBRX = false;
108   IsBookE = false;
109   HasOnlyMSYNC = false;
110   IsPPC4xx = false;
111   IsPPC6xx = false;
112   IsE500 = false;
113   FeatureMFTB = false;
114   AllowsUnalignedFPAccess = false;
115   DeprecatedDST = false;
116   HasICBT = false;
117   HasInvariantFunctionDescriptors = false;
118   HasPartwordAtomics = false;
119   HasDirectMove = false;
120   HasHTM = false;
121   HasFloat128 = false;
122   HasFusion = false;
123   HasStoreFusion = false;
124   HasAddiLoadFusion = false;
125   HasAddisLoadFusion = false;
126   IsISA3_0 = false;
127   IsISA3_1 = false;
128   UseLongCalls = false;
129   SecurePlt = false;
130   VectorsUseTwoUnits = false;
131   UsePPCPreRASchedStrategy = false;
132   UsePPCPostRASchedStrategy = false;
133   PairedVectorMemops = false;
134   PredictableSelectIsExpensive = false;
135 
136   HasPOPCNTD = POPCNTD_Unavailable;
137 }
138 
139 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
140   // Determine default and user specified characteristics
141   std::string CPUName = std::string(CPU);
142   if (CPUName.empty() || CPU == "generic") {
143     // If cross-compiling with -march=ppc64le without -mcpu
144     if (TargetTriple.getArch() == Triple::ppc64le)
145       CPUName = "ppc64le";
146     else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe)
147       CPUName = "e500";
148     else
149       CPUName = "generic";
150   }
151 
152   // Initialize scheduling itinerary for the specified CPU.
153   InstrItins = getInstrItineraryForCPU(CPUName);
154 
155   // Parse features string.
156   ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
157 
158   // If the user requested use of 64-bit regs, but the cpu selected doesn't
159   // support it, ignore.
160   if (IsPPC64 && has64BitSupport())
161     Use64BitRegs = true;
162 
163   if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) ||
164       TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() ||
165       TargetTriple.isMusl())
166     SecurePlt = true;
167 
168   if (HasSPE && IsPPC64)
169     report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
170   if (HasSPE && (HasAltivec || HasVSX || HasFPU))
171     report_fatal_error(
172         "SPE and traditional floating point cannot both be enabled.\n", false);
173 
174   // If not SPE, set standard FPU
175   if (!HasSPE)
176     HasFPU = true;
177 
178   StackAlignment = getPlatformStackAlignment();
179 
180   // Determine endianness.
181   // FIXME: Part of the TargetMachine.
182   IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le ||
183                     TargetTriple.getArch() == Triple::ppcle);
184 }
185 
186 bool PPCSubtarget::enableMachineScheduler() const { return true; }
187 
188 bool PPCSubtarget::enableMachinePipeliner() const {
189   return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner;
190 }
191 
192 bool PPCSubtarget::useDFAforSMS() const { return false; }
193 
194 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
195 bool PPCSubtarget::enablePostRAScheduler() const { return true; }
196 
197 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
198   return TargetSubtargetInfo::ANTIDEP_ALL;
199 }
200 
201 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
202   CriticalPathRCs.clear();
203   CriticalPathRCs.push_back(isPPC64() ?
204                             &PPC::G8RCRegClass : &PPC::GPRCRegClass);
205 }
206 
207 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
208                                        unsigned NumRegionInstrs) const {
209   // The GenericScheduler that we use defaults to scheduling bottom up only.
210   // We want to schedule from both the top and the bottom and so we set
211   // OnlyBottomUp to false.
212   // We want to do bi-directional scheduling since it provides a more balanced
213   // schedule leading to better performance.
214   Policy.OnlyBottomUp = false;
215   // Spilling is generally expensive on all PPC cores, so always enable
216   // register-pressure tracking.
217   Policy.ShouldTrackPressure = true;
218 }
219 
220 bool PPCSubtarget::useAA() const {
221   return true;
222 }
223 
224 bool PPCSubtarget::enableSubRegLiveness() const {
225   return UseSubRegLiveness;
226 }
227 
228 bool PPCSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
229   // Large code model always uses the TOC even for local symbols.
230   if (TM.getCodeModel() == CodeModel::Large)
231     return true;
232   if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
233     return false;
234   return true;
235 }
236 
237 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
238 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
239 
240 bool PPCSubtarget::isUsingPCRelativeCalls() const {
241   return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() &&
242          CodeModel::Medium == getTargetMachine().getCodeModel();
243 }
244 
245 // GlobalISEL
246 const CallLowering *PPCSubtarget::getCallLowering() const {
247   return CallLoweringInfo.get();
248 }
249 
250 const RegisterBankInfo *PPCSubtarget::getRegBankInfo() const {
251   return RegBankInfo.get();
252 }
253 
254 const LegalizerInfo *PPCSubtarget::getLegalizerInfo() const {
255   return Legalizer.get();
256 }
257 
258 InstructionSelector *PPCSubtarget::getInstructionSelector() const {
259   return InstSelector.get();
260 }
261