1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the PPC specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "PPCSubtarget.h" 14 #include "PPC.h" 15 #include "PPCRegisterInfo.h" 16 #include "PPCTargetMachine.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/MachineScheduler.h" 19 #include "llvm/IR/Attributes.h" 20 #include "llvm/IR/Function.h" 21 #include "llvm/IR/GlobalValue.h" 22 #include "llvm/Support/CommandLine.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Target/TargetMachine.h" 25 #include <cstdlib> 26 27 using namespace llvm; 28 29 #define DEBUG_TYPE "ppc-subtarget" 30 31 #define GET_SUBTARGETINFO_TARGET_DESC 32 #define GET_SUBTARGETINFO_CTOR 33 #include "PPCGenSubtargetInfo.inc" 34 35 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness", 36 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden); 37 38 static cl::opt<bool> 39 EnableMachinePipeliner("ppc-enable-pipeliner", 40 cl::desc("Enable Machine Pipeliner for PPC"), 41 cl::init(false), cl::Hidden); 42 43 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, 44 StringRef FS) { 45 initializeEnvironment(); 46 initSubtargetFeatures(CPU, FS); 47 return *this; 48 } 49 50 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU, 51 const std::string &FS, const PPCTargetMachine &TM) 52 : PPCGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TargetTriple(TT), 53 IsPPC64(TargetTriple.getArch() == Triple::ppc64 || 54 TargetTriple.getArch() == Triple::ppc64le), 55 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)), 56 InstrInfo(*this), TLInfo(TM, *this) {} 57 58 void PPCSubtarget::initializeEnvironment() { 59 StackAlignment = Align(16); 60 CPUDirective = PPC::DIR_NONE; 61 HasMFOCRF = false; 62 Has64BitSupport = false; 63 Use64BitRegs = false; 64 UseCRBits = false; 65 HasHardFloat = false; 66 HasAltivec = false; 67 HasSPE = false; 68 HasFPU = false; 69 HasVSX = false; 70 NeedsTwoConstNR = false; 71 HasP8Vector = false; 72 HasP8Altivec = false; 73 HasP8Crypto = false; 74 HasP9Vector = false; 75 HasP9Altivec = false; 76 HasMMA = false; 77 HasP10Vector = false; 78 HasPrefixInstrs = false; 79 HasPCRelativeMemops = false; 80 HasFCPSGN = false; 81 HasFSQRT = false; 82 HasFRE = false; 83 HasFRES = false; 84 HasFRSQRTE = false; 85 HasFRSQRTES = false; 86 HasRecipPrec = false; 87 HasSTFIWX = false; 88 HasLFIWAX = false; 89 HasFPRND = false; 90 HasFPCVT = false; 91 HasISEL = false; 92 HasBPERMD = false; 93 HasExtDiv = false; 94 HasCMPB = false; 95 HasLDBRX = false; 96 IsBookE = false; 97 HasOnlyMSYNC = false; 98 IsPPC4xx = false; 99 IsPPC6xx = false; 100 IsE500 = false; 101 FeatureMFTB = false; 102 AllowsUnalignedFPAccess = false; 103 DeprecatedDST = false; 104 HasICBT = false; 105 HasInvariantFunctionDescriptors = false; 106 HasPartwordAtomics = false; 107 HasDirectMove = false; 108 HasHTM = false; 109 HasFloat128 = false; 110 HasFusion = false; 111 HasStoreFusion = false; 112 HasAddiLoadFusion = false; 113 HasAddisLoadFusion = false; 114 IsISA3_0 = false; 115 IsISA3_1 = false; 116 UseLongCalls = false; 117 SecurePlt = false; 118 VectorsUseTwoUnits = false; 119 UsePPCPreRASchedStrategy = false; 120 UsePPCPostRASchedStrategy = false; 121 PairedVectorMemops = false; 122 PredictableSelectIsExpensive = false; 123 124 HasPOPCNTD = POPCNTD_Unavailable; 125 } 126 127 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 128 // Determine default and user specified characteristics 129 std::string CPUName = std::string(CPU); 130 if (CPUName.empty() || CPU == "generic") { 131 // If cross-compiling with -march=ppc64le without -mcpu 132 if (TargetTriple.getArch() == Triple::ppc64le) 133 CPUName = "ppc64le"; 134 else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe) 135 CPUName = "e500"; 136 else 137 CPUName = "generic"; 138 } 139 140 // Initialize scheduling itinerary for the specified CPU. 141 InstrItins = getInstrItineraryForCPU(CPUName); 142 143 // Parse features string. 144 ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS); 145 146 // If the user requested use of 64-bit regs, but the cpu selected doesn't 147 // support it, ignore. 148 if (IsPPC64 && has64BitSupport()) 149 Use64BitRegs = true; 150 151 if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) || 152 TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() || 153 TargetTriple.isMusl()) 154 SecurePlt = true; 155 156 if (HasSPE && IsPPC64) 157 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false); 158 if (HasSPE && (HasAltivec || HasVSX || HasFPU)) 159 report_fatal_error( 160 "SPE and traditional floating point cannot both be enabled.\n", false); 161 162 // If not SPE, set standard FPU 163 if (!HasSPE) 164 HasFPU = true; 165 166 StackAlignment = getPlatformStackAlignment(); 167 168 // Determine endianness. 169 // FIXME: Part of the TargetMachine. 170 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le); 171 } 172 173 bool PPCSubtarget::enableMachineScheduler() const { return true; } 174 175 bool PPCSubtarget::enableMachinePipeliner() const { 176 return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner; 177 } 178 179 bool PPCSubtarget::useDFAforSMS() const { return false; } 180 181 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 182 bool PPCSubtarget::enablePostRAScheduler() const { return true; } 183 184 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { 185 return TargetSubtargetInfo::ANTIDEP_ALL; 186 } 187 188 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 189 CriticalPathRCs.clear(); 190 CriticalPathRCs.push_back(isPPC64() ? 191 &PPC::G8RCRegClass : &PPC::GPRCRegClass); 192 } 193 194 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 195 unsigned NumRegionInstrs) const { 196 // The GenericScheduler that we use defaults to scheduling bottom up only. 197 // We want to schedule from both the top and the bottom and so we set 198 // OnlyBottomUp to false. 199 // We want to do bi-directional scheduling since it provides a more balanced 200 // schedule leading to better performance. 201 Policy.OnlyBottomUp = false; 202 // Spilling is generally expensive on all PPC cores, so always enable 203 // register-pressure tracking. 204 Policy.ShouldTrackPressure = true; 205 } 206 207 bool PPCSubtarget::useAA() const { 208 return true; 209 } 210 211 bool PPCSubtarget::enableSubRegLiveness() const { 212 return UseSubRegLiveness; 213 } 214 215 bool PPCSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const { 216 // Large code model always uses the TOC even for local symbols. 217 if (TM.getCodeModel() == CodeModel::Large) 218 return true; 219 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) 220 return false; 221 return true; 222 } 223 224 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); } 225 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); } 226 227 bool PPCSubtarget::isUsingPCRelativeCalls() const { 228 return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() && 229 CodeModel::Medium == getTargetMachine().getCodeModel(); 230 } 231