1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the PPC specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "PPCSubtarget.h" 14 #include "PPC.h" 15 #include "PPCRegisterInfo.h" 16 #include "PPCTargetMachine.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/MachineScheduler.h" 19 #include "llvm/IR/Attributes.h" 20 #include "llvm/IR/Function.h" 21 #include "llvm/IR/GlobalValue.h" 22 #include "llvm/Support/CommandLine.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Target/TargetMachine.h" 25 #include <cstdlib> 26 27 using namespace llvm; 28 29 #define DEBUG_TYPE "ppc-subtarget" 30 31 #define GET_SUBTARGETINFO_TARGET_DESC 32 #define GET_SUBTARGETINFO_CTOR 33 #include "PPCGenSubtargetInfo.inc" 34 35 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness", 36 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden); 37 38 static cl::opt<bool> 39 EnableMachinePipeliner("ppc-enable-pipeliner", 40 cl::desc("Enable Machine Pipeliner for PPC"), 41 cl::init(false), cl::Hidden); 42 43 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, 44 StringRef FS) { 45 initializeEnvironment(); 46 initSubtargetFeatures(CPU, FS); 47 return *this; 48 } 49 50 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU, 51 const std::string &FS, const PPCTargetMachine &TM) 52 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), 53 IsPPC64(TargetTriple.getArch() == Triple::ppc64 || 54 TargetTriple.getArch() == Triple::ppc64le), 55 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)), 56 InstrInfo(*this), TLInfo(TM, *this) {} 57 58 void PPCSubtarget::initializeEnvironment() { 59 StackAlignment = Align(16); 60 CPUDirective = PPC::DIR_NONE; 61 HasMFOCRF = false; 62 Has64BitSupport = false; 63 Use64BitRegs = false; 64 UseCRBits = false; 65 HasHardFloat = false; 66 HasAltivec = false; 67 HasSPE = false; 68 HasFPU = false; 69 HasVSX = false; 70 NeedsTwoConstNR = false; 71 HasP8Vector = false; 72 HasP8Altivec = false; 73 HasP8Crypto = false; 74 HasP9Vector = false; 75 HasP9Altivec = false; 76 HasP10Vector = false; 77 HasPrefixInstrs = false; 78 HasPCRelativeMemops = false; 79 HasFCPSGN = false; 80 HasFSQRT = false; 81 HasFRE = false; 82 HasFRES = false; 83 HasFRSQRTE = false; 84 HasFRSQRTES = false; 85 HasRecipPrec = false; 86 HasSTFIWX = false; 87 HasLFIWAX = false; 88 HasFPRND = false; 89 HasFPCVT = false; 90 HasISEL = false; 91 HasBPERMD = false; 92 HasExtDiv = false; 93 HasCMPB = false; 94 HasLDBRX = false; 95 IsBookE = false; 96 HasOnlyMSYNC = false; 97 IsPPC4xx = false; 98 IsPPC6xx = false; 99 IsE500 = false; 100 FeatureMFTB = false; 101 AllowsUnalignedFPAccess = false; 102 DeprecatedDST = false; 103 HasICBT = false; 104 HasInvariantFunctionDescriptors = false; 105 HasPartwordAtomics = false; 106 HasDirectMove = false; 107 HasHTM = false; 108 HasFloat128 = false; 109 HasFusion = false; 110 HasAddiLoadFusion = false; 111 HasAddisLoadFusion = false; 112 IsISA3_0 = false; 113 IsISA3_1 = false; 114 UseLongCalls = false; 115 SecurePlt = false; 116 VectorsUseTwoUnits = false; 117 UsePPCPreRASchedStrategy = false; 118 UsePPCPostRASchedStrategy = false; 119 PairedVectorMemops = false; 120 PredictableSelectIsExpensive = false; 121 122 HasPOPCNTD = POPCNTD_Unavailable; 123 } 124 125 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 126 // Determine default and user specified characteristics 127 std::string CPUName = std::string(CPU); 128 if (CPUName.empty() || CPU == "generic") { 129 // If cross-compiling with -march=ppc64le without -mcpu 130 if (TargetTriple.getArch() == Triple::ppc64le) 131 CPUName = "ppc64le"; 132 else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe) 133 CPUName = "e500"; 134 else 135 CPUName = "generic"; 136 } 137 138 // Initialize scheduling itinerary for the specified CPU. 139 InstrItins = getInstrItineraryForCPU(CPUName); 140 141 // Parse features string. 142 ParseSubtargetFeatures(CPUName, FS); 143 144 // If the user requested use of 64-bit regs, but the cpu selected doesn't 145 // support it, ignore. 146 if (IsPPC64 && has64BitSupport()) 147 Use64BitRegs = true; 148 149 if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) || 150 TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() || 151 TargetTriple.isMusl()) 152 SecurePlt = true; 153 154 if (HasSPE && IsPPC64) 155 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false); 156 if (HasSPE && (HasAltivec || HasVSX || HasFPU)) 157 report_fatal_error( 158 "SPE and traditional floating point cannot both be enabled.\n", false); 159 160 // If not SPE, set standard FPU 161 if (!HasSPE) 162 HasFPU = true; 163 164 StackAlignment = getPlatformStackAlignment(); 165 166 // Determine endianness. 167 // FIXME: Part of the TargetMachine. 168 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le); 169 } 170 171 bool PPCSubtarget::enableMachineScheduler() const { return true; } 172 173 bool PPCSubtarget::enableMachinePipeliner() const { 174 return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner; 175 } 176 177 bool PPCSubtarget::useDFAforSMS() const { return false; } 178 179 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 180 bool PPCSubtarget::enablePostRAScheduler() const { return true; } 181 182 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { 183 return TargetSubtargetInfo::ANTIDEP_ALL; 184 } 185 186 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 187 CriticalPathRCs.clear(); 188 CriticalPathRCs.push_back(isPPC64() ? 189 &PPC::G8RCRegClass : &PPC::GPRCRegClass); 190 } 191 192 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 193 unsigned NumRegionInstrs) const { 194 // The GenericScheduler that we use defaults to scheduling bottom up only. 195 // We want to schedule from both the top and the bottom and so we set 196 // OnlyBottomUp to false. 197 // We want to do bi-directional scheduling since it provides a more balanced 198 // schedule leading to better performance. 199 Policy.OnlyBottomUp = false; 200 // Spilling is generally expensive on all PPC cores, so always enable 201 // register-pressure tracking. 202 Policy.ShouldTrackPressure = true; 203 } 204 205 bool PPCSubtarget::useAA() const { 206 return true; 207 } 208 209 bool PPCSubtarget::enableSubRegLiveness() const { 210 return UseSubRegLiveness; 211 } 212 213 bool PPCSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const { 214 // Large code model always uses the TOC even for local symbols. 215 if (TM.getCodeModel() == CodeModel::Large) 216 return true; 217 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) 218 return false; 219 return true; 220 } 221 222 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); } 223 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); } 224 225 bool PPCSubtarget::isUsingPCRelativeCalls() const { 226 return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() && 227 CodeModel::Medium == getTargetMachine().getCodeModel(); 228 } 229