1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the PPC specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "PPCSubtarget.h" 14 #include "PPC.h" 15 #include "PPCRegisterInfo.h" 16 #include "PPCTargetMachine.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/MachineScheduler.h" 19 #include "llvm/IR/Attributes.h" 20 #include "llvm/IR/Function.h" 21 #include "llvm/IR/GlobalValue.h" 22 #include "llvm/Support/CommandLine.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Target/TargetMachine.h" 25 #include <cstdlib> 26 27 using namespace llvm; 28 29 #define DEBUG_TYPE "ppc-subtarget" 30 31 #define GET_SUBTARGETINFO_TARGET_DESC 32 #define GET_SUBTARGETINFO_CTOR 33 #include "PPCGenSubtargetInfo.inc" 34 35 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness", 36 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden); 37 38 static cl::opt<bool> QPXStackUnaligned("qpx-stack-unaligned", 39 cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"), 40 cl::Hidden); 41 42 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, 43 StringRef FS) { 44 initializeEnvironment(); 45 initSubtargetFeatures(CPU, FS); 46 return *this; 47 } 48 49 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU, 50 const std::string &FS, const PPCTargetMachine &TM) 51 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), 52 IsPPC64(TargetTriple.getArch() == Triple::ppc64 || 53 TargetTriple.getArch() == Triple::ppc64le), 54 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)), 55 InstrInfo(*this), TLInfo(TM, *this) {} 56 57 void PPCSubtarget::initializeEnvironment() { 58 StackAlignment = 16; 59 DarwinDirective = PPC::DIR_NONE; 60 HasMFOCRF = false; 61 Has64BitSupport = false; 62 Use64BitRegs = false; 63 UseCRBits = false; 64 HasHardFloat = false; 65 HasAltivec = false; 66 HasSPE = false; 67 HasFPU = false; 68 HasQPX = false; 69 HasVSX = false; 70 HasP8Vector = false; 71 HasP8Altivec = false; 72 HasP8Crypto = false; 73 HasP9Vector = false; 74 HasP9Altivec = false; 75 HasFCPSGN = false; 76 HasFSQRT = false; 77 HasFRE = false; 78 HasFRES = false; 79 HasFRSQRTE = false; 80 HasFRSQRTES = false; 81 HasRecipPrec = false; 82 HasSTFIWX = false; 83 HasLFIWAX = false; 84 HasFPRND = false; 85 HasFPCVT = false; 86 HasISEL = false; 87 HasBPERMD = false; 88 HasExtDiv = false; 89 HasCMPB = false; 90 HasLDBRX = false; 91 IsBookE = false; 92 HasOnlyMSYNC = false; 93 IsPPC4xx = false; 94 IsPPC6xx = false; 95 IsE500 = false; 96 FeatureMFTB = false; 97 DeprecatedDST = false; 98 HasLazyResolverStubs = false; 99 HasICBT = false; 100 HasInvariantFunctionDescriptors = false; 101 HasPartwordAtomics = false; 102 HasDirectMove = false; 103 IsQPXStackUnaligned = false; 104 HasHTM = false; 105 HasFusion = false; 106 HasFloat128 = false; 107 IsISA3_0 = false; 108 UseLongCalls = false; 109 SecurePlt = false; 110 111 HasPOPCNTD = POPCNTD_Unavailable; 112 } 113 114 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 115 // Determine default and user specified characteristics 116 std::string CPUName = CPU; 117 if (CPUName.empty() || CPU == "generic") { 118 // If cross-compiling with -march=ppc64le without -mcpu 119 if (TargetTriple.getArch() == Triple::ppc64le) 120 CPUName = "ppc64le"; 121 else 122 CPUName = "generic"; 123 } 124 125 // Initialize scheduling itinerary for the specified CPU. 126 InstrItins = getInstrItineraryForCPU(CPUName); 127 128 // Parse features string. 129 ParseSubtargetFeatures(CPUName, FS); 130 131 // If the user requested use of 64-bit regs, but the cpu selected doesn't 132 // support it, ignore. 133 if (IsPPC64 && has64BitSupport()) 134 Use64BitRegs = true; 135 136 // Set up darwin-specific properties. 137 if (isDarwin()) 138 HasLazyResolverStubs = true; 139 140 if (HasSPE && IsPPC64) 141 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false); 142 if (HasSPE && (HasAltivec || HasQPX || HasVSX || HasFPU)) 143 report_fatal_error( 144 "SPE and traditional floating point cannot both be enabled.\n", false); 145 146 // If not SPE, set standard FPU 147 if (!HasSPE) 148 HasFPU = true; 149 150 // QPX requires a 32-byte aligned stack. Note that we need to do this if 151 // we're compiling for a BG/Q system regardless of whether or not QPX 152 // is enabled because external functions will assume this alignment. 153 IsQPXStackUnaligned = QPXStackUnaligned; 154 StackAlignment = getPlatformStackAlignment(); 155 156 // Determine endianness. 157 // FIXME: Part of the TargetMachine. 158 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le); 159 } 160 161 /// Return true if accesses to the specified global have to go through a dyld 162 /// lazy resolution stub. This means that an extra load is required to get the 163 /// address of the global. 164 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const { 165 if (!HasLazyResolverStubs) 166 return false; 167 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) 168 return true; 169 // 32 bit macho has no relocation for a-b if a is undefined, even if b is in 170 // the section that is being relocated. This means we have to use o load even 171 // for GVs that are known to be local to the dso. 172 if (GV->isDeclarationForLinker() || GV->hasCommonLinkage()) 173 return true; 174 return false; 175 } 176 177 bool PPCSubtarget::enableMachineScheduler() const { 178 return true; 179 } 180 181 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 182 bool PPCSubtarget::enablePostRAScheduler() const { return true; } 183 184 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { 185 return TargetSubtargetInfo::ANTIDEP_ALL; 186 } 187 188 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 189 CriticalPathRCs.clear(); 190 CriticalPathRCs.push_back(isPPC64() ? 191 &PPC::G8RCRegClass : &PPC::GPRCRegClass); 192 } 193 194 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 195 unsigned NumRegionInstrs) const { 196 // The GenericScheduler that we use defaults to scheduling bottom up only. 197 // We want to schedule from both the top and the bottom and so we set 198 // OnlyBottomUp to false. 199 // We want to do bi-directional scheduling since it provides a more balanced 200 // schedule leading to better performance. 201 Policy.OnlyBottomUp = false; 202 // Spilling is generally expensive on all PPC cores, so always enable 203 // register-pressure tracking. 204 Policy.ShouldTrackPressure = true; 205 } 206 207 bool PPCSubtarget::useAA() const { 208 return true; 209 } 210 211 bool PPCSubtarget::enableSubRegLiveness() const { 212 return UseSubRegLiveness; 213 } 214 215 unsigned char 216 PPCSubtarget::classifyGlobalReference(const GlobalValue *GV) const { 217 // Note that currently we don't generate non-pic references. 218 // If a caller wants that, this will have to be updated. 219 220 // Large code model always uses the TOC even for local symbols. 221 if (TM.getCodeModel() == CodeModel::Large) 222 return PPCII::MO_PIC_FLAG | PPCII::MO_NLP_FLAG; 223 224 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) 225 return PPCII::MO_PIC_FLAG; 226 return PPCII::MO_PIC_FLAG | PPCII::MO_NLP_FLAG; 227 } 228 229 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); } 230 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); } 231