1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the PPC specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCSubtarget.h" 15 #include "PPC.h" 16 #include "PPCRegisterInfo.h" 17 #include "PPCTargetMachine.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/CodeGen/MachineScheduler.h" 20 #include "llvm/IR/Attributes.h" 21 #include "llvm/IR/Function.h" 22 #include "llvm/IR/GlobalValue.h" 23 #include "llvm/Support/CommandLine.h" 24 #include "llvm/Support/Host.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Target/TargetMachine.h" 27 #include <cstdlib> 28 29 using namespace llvm; 30 31 #define DEBUG_TYPE "ppc-subtarget" 32 33 #define GET_SUBTARGETINFO_TARGET_DESC 34 #define GET_SUBTARGETINFO_CTOR 35 #include "PPCGenSubtargetInfo.inc" 36 37 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness", 38 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden); 39 40 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, 41 StringRef FS) { 42 initializeEnvironment(); 43 initSubtargetFeatures(CPU, FS); 44 return *this; 45 } 46 47 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, 48 const std::string &FS, const PPCTargetMachine &TM) 49 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), 50 IsPPC64(TargetTriple.getArch() == Triple::ppc64 || 51 TargetTriple.getArch() == Triple::ppc64le), 52 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)), 53 InstrInfo(*this), TLInfo(TM, *this), TSInfo(TM.getDataLayout()) {} 54 55 void PPCSubtarget::initializeEnvironment() { 56 StackAlignment = 16; 57 DarwinDirective = PPC::DIR_NONE; 58 HasMFOCRF = false; 59 Has64BitSupport = false; 60 Use64BitRegs = false; 61 UseCRBits = false; 62 HasAltivec = false; 63 HasSPE = false; 64 HasQPX = false; 65 HasVSX = false; 66 HasP8Vector = false; 67 HasP8Altivec = false; 68 HasFCPSGN = false; 69 HasFSQRT = false; 70 HasFRE = false; 71 HasFRES = false; 72 HasFRSQRTE = false; 73 HasFRSQRTES = false; 74 HasRecipPrec = false; 75 HasSTFIWX = false; 76 HasLFIWAX = false; 77 HasFPRND = false; 78 HasFPCVT = false; 79 HasISEL = false; 80 HasPOPCNTD = false; 81 HasCMPB = false; 82 HasLDBRX = false; 83 IsBookE = false; 84 HasOnlyMSYNC = false; 85 IsPPC4xx = false; 86 IsPPC6xx = false; 87 IsE500 = false; 88 DeprecatedMFTB = false; 89 DeprecatedDST = false; 90 HasLazyResolverStubs = false; 91 HasICBT = false; 92 HasInvariantFunctionDescriptors = false; 93 } 94 95 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 96 // Determine default and user specified characteristics 97 std::string CPUName = CPU; 98 if (CPUName.empty()) { 99 // If cross-compiling with -march=ppc64le without -mcpu 100 if (TargetTriple.getArch() == Triple::ppc64le) 101 CPUName = "ppc64le"; 102 else 103 CPUName = "generic"; 104 } 105 #if (defined(__APPLE__) || defined(__linux__)) && \ 106 (defined(__ppc__) || defined(__powerpc__)) 107 if (CPUName == "generic") 108 CPUName = sys::getHostCPUName(); 109 #endif 110 111 // Initialize scheduling itinerary for the specified CPU. 112 InstrItins = getInstrItineraryForCPU(CPUName); 113 114 // Parse features string. 115 ParseSubtargetFeatures(CPUName, FS); 116 117 // If the user requested use of 64-bit regs, but the cpu selected doesn't 118 // support it, ignore. 119 if (IsPPC64 && has64BitSupport()) 120 Use64BitRegs = true; 121 122 // Set up darwin-specific properties. 123 if (isDarwin()) 124 HasLazyResolverStubs = true; 125 126 // QPX requires a 32-byte aligned stack. Note that we need to do this if 127 // we're compiling for a BG/Q system regardless of whether or not QPX 128 // is enabled because external functions will assume this alignment. 129 if (hasQPX() || isBGQ()) 130 StackAlignment = 32; 131 132 // Determine endianness. 133 // FIXME: Part of the TargetMachine. 134 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le); 135 } 136 137 /// hasLazyResolverStub - Return true if accesses to the specified global have 138 /// to go through a dyld lazy resolution stub. This means that an extra load 139 /// is required to get the address of the global. 140 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const { 141 // We never have stubs if HasLazyResolverStubs=false or if in static mode. 142 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static) 143 return false; 144 bool isDecl = GV->isDeclaration(); 145 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage()) 146 return false; 147 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || 148 GV->hasCommonLinkage() || isDecl; 149 } 150 151 // Embedded cores need aggressive scheduling (and some others also benefit). 152 static bool needsAggressiveScheduling(unsigned Directive) { 153 switch (Directive) { 154 default: return false; 155 case PPC::DIR_440: 156 case PPC::DIR_A2: 157 case PPC::DIR_E500mc: 158 case PPC::DIR_E5500: 159 case PPC::DIR_PWR7: 160 case PPC::DIR_PWR8: 161 return true; 162 } 163 } 164 165 bool PPCSubtarget::enableMachineScheduler() const { 166 // Enable MI scheduling for the embedded cores. 167 // FIXME: Enable this for all cores (some additional modeling 168 // may be necessary). 169 return needsAggressiveScheduling(DarwinDirective); 170 } 171 172 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 173 bool PPCSubtarget::enablePostMachineScheduler() const { return true; } 174 175 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { 176 return TargetSubtargetInfo::ANTIDEP_ALL; 177 } 178 179 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 180 CriticalPathRCs.clear(); 181 CriticalPathRCs.push_back(isPPC64() ? 182 &PPC::G8RCRegClass : &PPC::GPRCRegClass); 183 } 184 185 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 186 MachineInstr *begin, 187 MachineInstr *end, 188 unsigned NumRegionInstrs) const { 189 if (needsAggressiveScheduling(DarwinDirective)) { 190 Policy.OnlyTopDown = false; 191 Policy.OnlyBottomUp = false; 192 } 193 194 // Spilling is generally expensive on all PPC cores, so always enable 195 // register-pressure tracking. 196 Policy.ShouldTrackPressure = true; 197 } 198 199 bool PPCSubtarget::useAA() const { 200 // Use AA during code generation for the embedded cores. 201 return needsAggressiveScheduling(DarwinDirective); 202 } 203 204 bool PPCSubtarget::enableSubRegLiveness() const { 205 return UseSubRegLiveness; 206 } 207 208 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); } 209 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); } 210