1//===-- PPCScheduleP9.td - PPC P9 Scheduling Definitions ---*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the POWER9 processor.
11//
12//===----------------------------------------------------------------------===//
13include "PPCInstrInfo.td"
14
15def P9Model : SchedMachineModel {
16  let IssueWidth = 8;
17
18  let LoadLatency = 5;
19
20  let MispredictPenalty = 16;
21
22  // Try to make sure we have at least 10 dispatch groups in a loop.
23  let LoopMicroOpBufferSize = 60;
24
25  let CompleteModel = 0;
26
27}
28
29let SchedModel = P9Model in {
30
31  // ***************** Processor Resources *****************
32
33  //Dispatcher:
34  def DISPATCHER : ProcResource<12>;
35
36  // Issue Ports
37  def IP_AGEN : ProcResource<4>;
38  def IP_EXEC : ProcResource<4>;
39  def IP_EXECE : ProcResource<2> {
40    //Even Exec Ports
41    let Super = IP_EXEC;
42  }
43  def IP_EXECO : ProcResource<2> {
44    //Odd Exec Ports
45    let Super = IP_EXEC;
46  }
47
48  // Pipeline Groups
49  def ALU : ProcResource<4>;
50  def ALUE : ProcResource<2> {
51    //Even ALU pipelines
52    let Super = ALU;
53  }
54  def ALUO : ProcResource<2> {
55    //Odd ALU pipelines
56    let Super = ALU;
57  }
58  def DIV : ProcResource<2>;
59  def DP : ProcResource<4>;
60  def DPE : ProcResource<2> {
61    //Even DP pipelines
62    let Super = DP;
63  }
64  def DPO : ProcResource<2> {
65    //Odd DP pipelines
66    let Super = DP;
67  }
68  def LS : ProcResource<4>;
69  def PM : ProcResource<2>;
70  def DFU : ProcResource<1>;
71
72  def TestGroup : ProcResGroup<[ALU, DP]>;
73
74  // ***************** SchedWriteRes Definitions *****************
75
76  //Dispatcher
77  def DISP_1C : SchedWriteRes<[DISPATCHER]> {
78    let NumMicroOps = 0;
79    let Latency = 1;
80  }
81
82  // Issue Ports
83  def IP_AGEN_1C : SchedWriteRes<[IP_AGEN]> {
84    let NumMicroOps = 0;
85    let Latency = 1;
86  }
87
88  def IP_EXEC_1C : SchedWriteRes<[IP_EXEC]> {
89    let NumMicroOps = 0;
90    let Latency = 1;
91  }
92
93  def IP_EXECE_1C : SchedWriteRes<[IP_EXECE]> {
94    let NumMicroOps = 0;
95    let Latency = 1;
96  }
97
98  def IP_EXECO_1C : SchedWriteRes<[IP_EXECO]> {
99    let NumMicroOps = 0;
100    let Latency = 1;
101  }
102
103  //Pipeline Groups
104  def P9_ALU_2C : SchedWriteRes<[ALU]> {
105    let Latency = 2;
106  }
107
108  def P9_ALUE_2C : SchedWriteRes<[ALUE]> {
109    let Latency = 2;
110  }
111
112  def P9_ALUO_2C : SchedWriteRes<[ALUO]> {
113    let Latency = 2;
114  }
115
116  def P9_ALU_3C : SchedWriteRes<[ALU]> {
117    let Latency = 3;
118  }
119
120  def P9_ALUE_3C : SchedWriteRes<[ALUE]> {
121    let Latency = 3;
122  }
123
124  def P9_ALUO_3C : SchedWriteRes<[ALUO]> {
125    let Latency = 3;
126  }
127
128  def P9_ALU_4C : SchedWriteRes<[ALU]> {
129    let Latency = 4;
130  }
131
132  def P9_ALUE_4C : SchedWriteRes<[ALUE]> {
133    let Latency = 4;
134  }
135
136  def P9_ALUO_4C : SchedWriteRes<[ALUO]> {
137    let Latency = 4;
138  }
139
140  def P9_ALU_5C : SchedWriteRes<[ALU]> {
141    let Latency = 5;
142  }
143
144  def P9_ALU_6C : SchedWriteRes<[ALU]> {
145    let Latency = 6;
146  }
147
148  def P9_DIV_16C_8 : SchedWriteRes<[DIV]> {
149    let ResourceCycles = [8];
150    let Latency = 16;
151  }
152
153  def P9_DIV_24C_8 : SchedWriteRes<[DIV]> {
154    let ResourceCycles = [8];
155    let Latency = 24;
156  }
157
158  def P9_DIV_40C_8 : SchedWriteRes<[DIV]> {
159    let ResourceCycles = [8];
160    let Latency = 40;
161  }
162
163  def P9_DP_2C : SchedWriteRes<[DP]> {
164    let Latency = 2;
165  }
166
167  def P9_DP_5C : SchedWriteRes<[DP]> {
168    let Latency = 5;
169  }
170
171  def P9_DP_7C : SchedWriteRes<[DP]> {
172    let Latency = 7;
173  }
174
175  def P9_DPE_7C : SchedWriteRes<[DPE]> {
176    let Latency = 7;
177  }
178
179  def P9_DPO_7C : SchedWriteRes<[DPO]> {
180    let Latency = 7;
181  }
182
183  def P9_DP_22C_5 : SchedWriteRes<[DP]> {
184    let ResourceCycles = [5];
185    let Latency = 22;
186  }
187
188  def P9_DP_24C_8 : SchedWriteRes<[DP]> {
189    let ResourceCycles = [8];
190    let Latency = 24;
191  }
192
193  def P9_DP_26C_5 : SchedWriteRes<[DP]> {
194    let ResourceCycles = [5];
195    let Latency = 22;
196  }
197
198  def P9_DP_27C_7 : SchedWriteRes<[DP]> {
199    let ResourceCycles = [7];
200    let Latency = 27;
201  }
202
203  def P9_DP_33C_8 : SchedWriteRes<[DP]> {
204    let ResourceCycles = [8];
205    let Latency = 33;
206  }
207
208  def P9_DP_36C_10 : SchedWriteRes<[DP]> {
209    let ResourceCycles = [10];
210    let Latency = 36;
211  }
212
213  def P9_PM_3C : SchedWriteRes<[PM]> {
214    let Latency = 3;
215  }
216
217  def P9_PM_7C : SchedWriteRes<[PM]> {
218    let Latency = 3;
219  }
220
221  def P9_LS_1C : SchedWriteRes<[LS]> {
222    let Latency = 1;
223  }
224
225  def P9_LS_4C : SchedWriteRes<[LS]> {
226    let Latency = 4;
227  }
228
229  def P9_LS_5C : SchedWriteRes<[LS]> {
230    let Latency = 5;
231  }
232
233  def P9_DFU_12C : SchedWriteRes<[DFU]> {
234    let Latency = 12;
235  }
236
237  def P9_DFU_24C : SchedWriteRes<[DFU]> {
238    let Latency = 24;
239    let ResourceCycles = [12];
240  }
241
242  def P9_DFU_58C : SchedWriteRes<[DFU]> {
243    let Latency = 58;
244    let ResourceCycles = [44];
245  }
246
247  def P9_DFU_76C : SchedWriteRes<[TestGroup, DFU]> {
248    let Latency = 76;
249    let ResourceCycles = [62];
250  }
251  // ***************** WriteSeq Definitions *****************
252
253  def P9_LoadAndALUOp_6C : WriteSequence<[P9_LS_4C, P9_ALU_2C]>;
254  def P9_LoadAndALUOp_7C : WriteSequence<[P9_LS_5C, P9_ALU_2C]>;
255  def P9_LoadAndPMOp_8C : WriteSequence<[P9_LS_5C, P9_PM_3C]>;
256  def P9_IntDivAndALUOp_26C_8 : WriteSequence<[P9_DIV_24C_8, P9_ALU_2C]>;
257  def P9_IntDivAndALUOp_42C_8 : WriteSequence<[P9_DIV_40C_8, P9_ALU_2C]>;
258  def P9_StoreAndALUOp_4C : WriteSequence<[P9_LS_1C, P9_ALU_3C]>;
259  def P9_ALUOpAndALUOp_4C : WriteSequence<[P9_ALU_2C, P9_ALU_2C]>;
260
261  // ***************** Defining Itinerary Class Resources *****************
262
263  def : ItinRW<[P9_DFU_76C, IP_EXEC_1C, DISP_1C, DISP_1C], [IIC_IntSimple,
264                                         IIC_IntGeneral]>;
265
266  def : ItinRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
267               [IIC_IntISEL, IIC_IntRotate, IIC_IntShift]>;
268
269  def : ItinRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C], [IIC_IntCompare]>;
270
271  def : ItinRW<[P9_DP_5C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
272               [IIC_IntMulHW, IIC_IntMulHWU, IIC_IntMulLI]>;
273
274  def : ItinRW<[P9_LS_5C, IP_EXEC_1C, DISP_1C, DISP_1C],
275               [IIC_LdStLoad, IIC_LdStLD]>;
276
277  def : ItinRW<[P9_LS_4C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
278                DISP_1C, DISP_1C, DISP_1C, DISP_1C],
279               [IIC_LdStLoadUpd, IIC_LdStLDU]>;
280
281  def : ItinRW<[P9_LS_4C, P9_ALU_2C, IP_EXECE_1C, IP_EXECO_1C,
282                DISP_1C, DISP_1C, DISP_1C, DISP_1C],
283               [IIC_LdStLoadUpdX, IIC_LdStLDUX]>;
284
285  def : ItinRW<[P9_LS_1C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C,
286                DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
287               [IIC_LdStSTFDU]>;
288
289  def : ItinRW<[P9_LoadAndALUOp_6C,
290                IP_AGEN_1C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
291               [IIC_LdStLHA, IIC_LdStLWA]>;
292
293  def : ItinRW<[P9_LoadAndALUOp_6C, P9_ALU_2C,
294                IP_AGEN_1C, IP_EXEC_1C, IP_EXEC_1C,
295                DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
296               [IIC_LdStLHAU, IIC_LdStLHAUX]>;
297
298  // IIC_LdStLMW contains two microcoded insns. This is not accurate, but
299  // those insns are not used that much, if at all.
300  def : ItinRW<[P9_LS_4C, IP_EXEC_1C, DISP_1C, DISP_1C],
301               [IIC_LdStLWARX, IIC_LdStLDARX, IIC_LdStLMW]>;
302
303  def : ItinRW<[P9_LS_1C, IP_EXEC_1C, IP_AGEN_1C, DISP_1C, DISP_1C, DISP_1C],
304               [IIC_LdStSTFD, IIC_LdStSTD, IIC_LdStStore]>;
305
306  def : ItinRW<[P9_LS_1C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C,
307                DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
308               [IIC_LdStSTDU, IIC_LdStSTDUX]>;
309
310  def : ItinRW<[P9_StoreAndALUOp_4C, IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C,
311                DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
312               [IIC_LdStSTDCX, IIC_LdStSTWCX]>;
313
314  def : ItinRW<[P9_ALU_5C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
315               [IIC_BrCR, IIC_IntMTFSB0]>;
316
317  def : ItinRW<[P9_ALUOpAndALUOp_4C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
318                IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C,
319                DISP_1C, DISP_1C, DISP_1C], [IIC_SprMFCR, IIC_SprMFCRF]>;
320
321  // This class should be broken down to instruction level, once some missing
322  // info is obtained.
323  def : ItinRW<[P9_LoadAndALUOp_6C, IP_EXEC_1C, IP_AGEN_1C,
324                DISP_1C, DISP_1C, DISP_1C], [IIC_SprMTSPR]>;
325
326  def : ItinRW<[P9_DP_7C, IP_EXEC_1C,
327                DISP_1C, DISP_1C, DISP_1C], [IIC_FPGeneral, IIC_FPAddSub]>;
328
329  def : ItinRW<[P9_DP_36C_10, IP_EXEC_1C], [IIC_FPSqrtD]>;
330  def : ItinRW<[P9_DP_26C_5, P9_DP_26C_5, IP_EXEC_1C, IP_EXEC_1C], [IIC_FPSqrtS]>;
331
332  include "P9InstrResources.td"
333
334}
335
336