1 //===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetRegisterInfo
10 // class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
16 
17 #include "MCTargetDesc/PPCMCTargetDesc.h"
18 #include "llvm/ADT/DenseMap.h"
19 
20 #define GET_REGINFO_HEADER
21 #include "PPCGenRegisterInfo.inc"
22 
23 namespace llvm {
24 class PPCTargetMachine;
25 
26 inline static unsigned getCRFromCRBit(unsigned SrcReg) {
27   unsigned Reg = 0;
28   if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
29       SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
30     Reg = PPC::CR0;
31   else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
32            SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
33     Reg = PPC::CR1;
34   else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
35            SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
36     Reg = PPC::CR2;
37   else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
38            SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
39     Reg = PPC::CR3;
40   else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
41            SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
42     Reg = PPC::CR4;
43   else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
44            SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
45     Reg = PPC::CR5;
46   else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
47            SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
48     Reg = PPC::CR6;
49   else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
50            SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
51     Reg = PPC::CR7;
52 
53   assert(Reg != 0 && "Invalid CR bit register");
54   return Reg;
55 }
56 
57 class PPCRegisterInfo : public PPCGenRegisterInfo {
58   DenseMap<unsigned, unsigned> ImmToIdxMap;
59   const PPCTargetMachine &TM;
60 
61 public:
62   PPCRegisterInfo(const PPCTargetMachine &TM);
63 
64   /// getMappedIdxOpcForImmOpc - Return the mapped index form load/store opcode
65   /// for a given imm form load/store opcode \p ImmFormOpcode.
66   /// FIXME: move this to PPCInstrInfo class.
67   unsigned getMappedIdxOpcForImmOpc(unsigned ImmOpcode) const {
68     if (!ImmToIdxMap.count(ImmOpcode))
69       return PPC::INSTRUCTION_LIST_END;
70     return ImmToIdxMap.find(ImmOpcode)->second;
71   }
72 
73   /// getPointerRegClass - Return the register class to use to hold pointers.
74   /// This is used for addressing modes.
75   const TargetRegisterClass *
76   getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
77 
78   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
79                                MachineFunction &MF) const override;
80 
81   const TargetRegisterClass *
82   getLargestLegalSuperClass(const TargetRegisterClass *RC,
83                             const MachineFunction &MF) const override;
84 
85   /// Code Generation virtual methods...
86   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
87   const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
88   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
89                                        CallingConv::ID CC) const override;
90   const uint32_t *getNoPreservedMask() const override;
91 
92   void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
93 
94   BitVector getReservedRegs(const MachineFunction &MF) const override;
95   bool isCallerPreservedPhysReg(MCRegister PhysReg,
96                                 const MachineFunction &MF) const override;
97 
98   /// We require the register scavenger.
99   bool requiresRegisterScavenging(const MachineFunction &MF) const override {
100     return true;
101   }
102 
103   bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
104 
105   bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override {
106     return true;
107   }
108 
109   void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
110   void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const;
111   void lowerCRSpilling(MachineBasicBlock::iterator II,
112                        unsigned FrameIndex) const;
113   void lowerCRRestore(MachineBasicBlock::iterator II,
114                       unsigned FrameIndex) const;
115   void lowerCRBitSpilling(MachineBasicBlock::iterator II,
116                           unsigned FrameIndex) const;
117   void lowerCRBitRestore(MachineBasicBlock::iterator II,
118                          unsigned FrameIndex) const;
119   void lowerVRSAVESpilling(MachineBasicBlock::iterator II,
120                            unsigned FrameIndex) const;
121   void lowerVRSAVERestore(MachineBasicBlock::iterator II,
122                           unsigned FrameIndex) const;
123 
124   bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg,
125                             int &FrameIdx) const override;
126   void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
127                            unsigned FIOperandNum,
128                            RegScavenger *RS = nullptr) const override;
129 
130   // Support for virtual base registers.
131   bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
132   void materializeFrameBaseRegister(MachineBasicBlock *MBB, Register BaseReg,
133                                     int FrameIdx,
134                                     int64_t Offset) const override;
135   void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
136                          int64_t Offset) const override;
137   bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
138                           int64_t Offset) const override;
139 
140   // Debug information queries.
141   Register getFrameRegister(const MachineFunction &MF) const override;
142 
143   // Base pointer (stack realignment) support.
144   Register getBaseRegister(const MachineFunction &MF) const;
145   bool hasBasePointer(const MachineFunction &MF) const;
146 
147   /// stripRegisterPrefix - This method strips the character prefix from a
148   /// register name so that only the number is left.  Used by for linux asm.
149   static const char *stripRegisterPrefix(const char *RegName) {
150     switch (RegName[0]) {
151       case 'r':
152       case 'f':
153       case 'q': // for QPX
154       case 'v':
155         if (RegName[1] == 's')
156           return RegName + 2;
157         return RegName + 1;
158       case 'c': if (RegName[1] == 'r') return RegName + 2;
159     }
160 
161     return RegName;
162   }
163 };
164 
165 } // end namespace llvm
166 
167 #endif
168