1 //===-- PPCMachineFunctionInfo.h - Private data used for PowerPC --*- C++ -*-=// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares the PowerPC specific subclass of MachineFunctionInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H 14 #define LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H 15 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/TargetCallingConv.h" 19 20 namespace llvm { 21 22 /// PPCFunctionInfo - This class is derived from MachineFunction private 23 /// PowerPC target-specific information for each MachineFunction. 24 class PPCFunctionInfo : public MachineFunctionInfo { 25 virtual void anchor(); 26 27 /// FramePointerSaveIndex - Frame index of where the old frame pointer is 28 /// stored. Also used as an anchor for instructions that need to be altered 29 /// when using frame pointers (dyna_add, dyna_sub.) 30 int FramePointerSaveIndex = 0; 31 32 /// ReturnAddrSaveIndex - Frame index of where the return address is stored. 33 /// 34 int ReturnAddrSaveIndex = 0; 35 36 /// Frame index where the old base pointer is stored. 37 int BasePointerSaveIndex = 0; 38 39 /// Frame index where the old PIC base pointer is stored. 40 int PICBasePointerSaveIndex = 0; 41 42 /// MustSaveLR - Indicates whether LR is defined (or clobbered) in the current 43 /// function. This is only valid after the initial scan of the function by 44 /// PEI. 45 bool MustSaveLR; 46 47 /// Do we have to disable shrink-wrapping? This has to be set if we emit any 48 /// instructions that clobber LR in the entry block because discovering this 49 /// in PEI is too late (happens after shrink-wrapping); 50 bool ShrinkWrapDisabled = false; 51 52 /// Does this function have any stack spills. 53 bool HasSpills = false; 54 55 /// Does this function spill using instructions with only r+r (not r+i) 56 /// forms. 57 bool HasNonRISpills = false; 58 59 /// SpillsCR - Indicates whether CR is spilled in the current function. 60 bool SpillsCR = false; 61 62 /// Indicates whether VRSAVE is spilled in the current function. 63 bool SpillsVRSAVE = false; 64 65 /// LRStoreRequired - The bool indicates whether there is some explicit use of 66 /// the LR/LR8 stack slot that is not obvious from scanning the code. This 67 /// requires that the code generator produce a store of LR to the stack on 68 /// entry, even though LR may otherwise apparently not be used. 69 bool LRStoreRequired = false; 70 71 /// This function makes use of the PPC64 ELF TOC base pointer (register r2). 72 bool UsesTOCBasePtr = false; 73 74 /// MinReservedArea - This is the frame size that is at least reserved in a 75 /// potential caller (parameter+linkage area). 76 unsigned MinReservedArea = 0; 77 78 /// TailCallSPDelta - Stack pointer delta used when tail calling. Maximum 79 /// amount the stack pointer is adjusted to make the frame bigger for tail 80 /// calls. Used for creating an area before the register spill area. 81 int TailCallSPDelta = 0; 82 83 /// HasFastCall - Does this function contain a fast call. Used to determine 84 /// how the caller's stack pointer should be calculated (epilog/dynamicalloc). 85 bool HasFastCall = false; 86 87 /// VarArgsFrameIndex - FrameIndex for start of varargs area. 88 int VarArgsFrameIndex = 0; 89 90 /// VarArgsStackOffset - StackOffset for start of stack 91 /// arguments. 92 93 int VarArgsStackOffset = 0; 94 95 /// VarArgsNumGPR - Index of the first unused integer 96 /// register for parameter passing. 97 unsigned VarArgsNumGPR = 0; 98 99 /// VarArgsNumFPR - Index of the first unused double 100 /// register for parameter passing. 101 unsigned VarArgsNumFPR = 0; 102 103 /// CRSpillFrameIndex - FrameIndex for CR spill slot for 32-bit SVR4. 104 int CRSpillFrameIndex = 0; 105 106 /// If any of CR[2-4] need to be saved in the prologue and restored in the 107 /// epilogue then they are added to this array. This is used for the 108 /// 64-bit SVR4 ABI. 109 SmallVector<unsigned, 3> MustSaveCRs; 110 111 /// Hold onto our MachineFunction context. 112 MachineFunction &MF; 113 114 /// Whether this uses the PIC Base register or not. 115 bool UsesPICBase = false; 116 117 /// True if this function has a subset of CSRs that is handled explicitly via 118 /// copies 119 bool IsSplitCSR = false; 120 121 /// We keep track attributes for each live-in virtual registers 122 /// to use SExt/ZExt flags in later optimization. 123 std::vector<std::pair<unsigned, ISD::ArgFlagsTy>> LiveInAttrs; 124 125 public: 126 explicit PPCFunctionInfo(MachineFunction &MF) : MF(MF) {} 127 128 int getFramePointerSaveIndex() const { return FramePointerSaveIndex; } 129 void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; } 130 131 int getReturnAddrSaveIndex() const { return ReturnAddrSaveIndex; } 132 void setReturnAddrSaveIndex(int idx) { ReturnAddrSaveIndex = idx; } 133 134 int getBasePointerSaveIndex() const { return BasePointerSaveIndex; } 135 void setBasePointerSaveIndex(int Idx) { BasePointerSaveIndex = Idx; } 136 137 int getPICBasePointerSaveIndex() const { return PICBasePointerSaveIndex; } 138 void setPICBasePointerSaveIndex(int Idx) { PICBasePointerSaveIndex = Idx; } 139 140 unsigned getMinReservedArea() const { return MinReservedArea; } 141 void setMinReservedArea(unsigned size) { MinReservedArea = size; } 142 143 int getTailCallSPDelta() const { return TailCallSPDelta; } 144 void setTailCallSPDelta(int size) { TailCallSPDelta = size; } 145 146 /// MustSaveLR - This is set when the prolog/epilog inserter does its initial 147 /// scan of the function. It is true if the LR/LR8 register is ever explicitly 148 /// defined/clobbered in the machine function (e.g. by calls and movpctolr, 149 /// which is used in PIC generation), or if the LR stack slot is explicitly 150 /// referenced by builtin_return_address. 151 void setMustSaveLR(bool U) { MustSaveLR = U; } 152 bool mustSaveLR() const { return MustSaveLR; } 153 154 /// We certainly don't want to shrink wrap functions if we've emitted a 155 /// MovePCtoLR8 as that has to go into the entry, so the prologue definitely 156 /// has to go into the entry block. 157 void setShrinkWrapDisabled(bool U) { ShrinkWrapDisabled = U; } 158 bool shrinkWrapDisabled() const { return ShrinkWrapDisabled; } 159 160 void setHasSpills() { HasSpills = true; } 161 bool hasSpills() const { return HasSpills; } 162 163 void setHasNonRISpills() { HasNonRISpills = true; } 164 bool hasNonRISpills() const { return HasNonRISpills; } 165 166 void setSpillsCR() { SpillsCR = true; } 167 bool isCRSpilled() const { return SpillsCR; } 168 169 void setSpillsVRSAVE() { SpillsVRSAVE = true; } 170 bool isVRSAVESpilled() const { return SpillsVRSAVE; } 171 172 void setLRStoreRequired() { LRStoreRequired = true; } 173 bool isLRStoreRequired() const { return LRStoreRequired; } 174 175 void setUsesTOCBasePtr() { UsesTOCBasePtr = true; } 176 bool usesTOCBasePtr() const { return UsesTOCBasePtr; } 177 178 void setHasFastCall() { HasFastCall = true; } 179 bool hasFastCall() const { return HasFastCall;} 180 181 int getVarArgsFrameIndex() const { return VarArgsFrameIndex; } 182 void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; } 183 184 int getVarArgsStackOffset() const { return VarArgsStackOffset; } 185 void setVarArgsStackOffset(int Offset) { VarArgsStackOffset = Offset; } 186 187 unsigned getVarArgsNumGPR() const { return VarArgsNumGPR; } 188 void setVarArgsNumGPR(unsigned Num) { VarArgsNumGPR = Num; } 189 190 unsigned getVarArgsNumFPR() const { return VarArgsNumFPR; } 191 void setVarArgsNumFPR(unsigned Num) { VarArgsNumFPR = Num; } 192 193 /// This function associates attributes for each live-in virtual register. 194 void addLiveInAttr(unsigned VReg, ISD::ArgFlagsTy Flags) { 195 LiveInAttrs.push_back(std::make_pair(VReg, Flags)); 196 } 197 198 /// This function returns true if the specified vreg is 199 /// a live-in register and sign-extended. 200 bool isLiveInSExt(unsigned VReg) const; 201 202 /// This function returns true if the specified vreg is 203 /// a live-in register and zero-extended. 204 bool isLiveInZExt(unsigned VReg) const; 205 206 int getCRSpillFrameIndex() const { return CRSpillFrameIndex; } 207 void setCRSpillFrameIndex(int idx) { CRSpillFrameIndex = idx; } 208 209 const SmallVectorImpl<unsigned> & 210 getMustSaveCRs() const { return MustSaveCRs; } 211 void addMustSaveCR(unsigned Reg) { MustSaveCRs.push_back(Reg); } 212 213 void setUsesPICBase(bool uses) { UsesPICBase = uses; } 214 bool usesPICBase() const { return UsesPICBase; } 215 216 bool isSplitCSR() const { return IsSplitCSR; } 217 void setIsSplitCSR(bool s) { IsSplitCSR = s; } 218 219 MCSymbol *getPICOffsetSymbol() const; 220 221 MCSymbol *getGlobalEPSymbol() const; 222 MCSymbol *getLocalEPSymbol() const; 223 MCSymbol *getTOCOffsetSymbol() const; 224 }; 225 226 } // end namespace llvm 227 228 #endif // LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H 229