1//===-- PPCInstrP10.td - Power10 Instruction Set -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 6// See https://llvm.org/LICENSE.txt for license information. 7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 8// 9//===----------------------------------------------------------------------===// 10// 11// This file describes the instructions introduced for the Power10 CPU. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Naming convention for future instruction formats 17// 18// <INSTR_FORM>{_<OP_TYPE><OP_LENGTH>}+ 19// 20// Where: 21// <INSTR_FORM> - name of instruction format as per the ISA 22// (X-Form, VX-Form, etc.) 23// <OP_TYPE> - operand type 24// * FRT/RT/VT/XT/BT - target register 25// (FPR, GPR, VR, VSR, CR-bit respectively) 26// In some situations, the 'T' is replaced by 27// 'D' when describing the target register. 28// * [FR|R|V|X|B][A-Z] - register source (i.e. FRA, RA, XB, etc.) 29// * IMM - immediate (where signedness matters, 30// this is SI/UI for signed/unsigned) 31// * [R|X|FR]Tp - register pair target (i.e. FRTp, RTp) 32// * R - PC-Relative bit 33// (denotes that the address is computed pc-relative) 34// * VRM - Masked Registers 35// * AT - target accumulator 36// * N - the Nth bit in a VSR 37// * Additional 1-bit operands may be required for certain 38// instruction formats such as: MC, P, MP 39// * X / Y / P - mask values. In the instruction encoding, this is 40// represented as XMSK, YMSK and PMSK. 41// * MEM - indicates if the instruction format requires any memory 42// accesses. This does not have <OP_LENGTH> attached to it. 43// <OP_LENGTH> - the length of each operand in bits. 44// For operands that are 1 bit, the '1' is omitted from the name. 45// 46// Example: 8RR_XX4Form_IMM8_XTAB6 47// 8RR_XX4Form is the instruction format. 48// The operand is an 8-bit immediate (IMM), the destination (XT) 49// and sources (XA, XB) that are all 6-bits. The destination and 50// source registers are combined if they are of the same length. 51// Moreover, the order of operands reflects the order of operands 52// in the encoding. 53 54//-------------------------- Predicate definitions ---------------------------// 55def IsPPC32 : Predicate<"!Subtarget->isPPC64()">; 56 57 58//===----------------------------------------------------------------------===// 59// PowerPC ISA 3.1 specific type constraints. 60// 61 62def SDT_PPCSplat32 : SDTypeProfile<1, 3, [ SDTCisVT<0, v2i64>, 63 SDTCisVec<1>, SDTCisInt<2>, SDTCisInt<3> 64]>; 65def SDT_PPCAccBuild : SDTypeProfile<1, 4, [ 66 SDTCisVT<0, v512i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>, 67 SDTCisVT<3, v4i32>, SDTCisVT<4, v4i32> 68]>; 69def SDT_PPCPairBuild : SDTypeProfile<1, 2, [ 70 SDTCisVT<0, v256i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32> 71]>; 72def SDT_PPCAccExtractVsx : SDTypeProfile<1, 2, [ 73 SDTCisVT<0, v4i32>, SDTCisVT<1, v512i1>, SDTCisPtrTy<2> 74]>; 75def SDT_PPCPairExtractVsx : SDTypeProfile<1, 2, [ 76 SDTCisVT<0, v4i32>, SDTCisVT<1, v256i1>, SDTCisPtrTy<2> 77]>; 78def SDT_PPCxxmfacc : SDTypeProfile<1, 1, [ 79 SDTCisVT<0, v512i1>, SDTCisVT<1, v512i1> 80]>; 81 82//===----------------------------------------------------------------------===// 83// ISA 3.1 specific PPCISD nodes. 84// 85 86def PPCxxsplti32dx : SDNode<"PPCISD::XXSPLTI32DX", SDT_PPCSplat32, []>; 87def PPCAccBuild : SDNode<"PPCISD::ACC_BUILD", SDT_PPCAccBuild, []>; 88def PPCPairBuild : SDNode<"PPCISD::PAIR_BUILD", SDT_PPCPairBuild, []>; 89def PPCAccExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCAccExtractVsx, 90 []>; 91def PPCPairExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCPairExtractVsx, 92 []>; 93def PPCxxmfacc : SDNode<"PPCISD::XXMFACC", SDT_PPCxxmfacc, []>; 94 95//===----------------------------------------------------------------------===// 96 97// PC Relative flag (for instructions that use the address of the prefix for 98// address computations). 99class isPCRel { bit PCRel = 1; } 100 101// PowerPC specific type constraints. 102def SDT_PPCLXVRZX : SDTypeProfile<1, 2, [ 103 SDTCisVT<0, v1i128>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 104]>; 105 106// PPC Specific DAG Nodes. 107def PPClxvrzx : SDNode<"PPCISD::LXVRZX", SDT_PPCLXVRZX, 108 [SDNPHasChain, SDNPMayLoad]>; 109 110// Top-level class for prefixed instructions. 111class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr, 112 InstrItinClass itin> : Instruction { 113 field bits<64> Inst; 114 field bits<64> SoftFail = 0; 115 bit PCRel = 0; // Default value, set by isPCRel. 116 let Size = 8; 117 118 let Namespace = "PPC"; 119 let OutOperandList = OOL; 120 let InOperandList = IOL; 121 let AsmString = asmstr; 122 let Itinerary = itin; 123 let Inst{0-5} = pref; 124 let Inst{32-37} = opcode; 125 126 bits<1> PPC970_First = 0; 127 bits<1> PPC970_Single = 0; 128 bits<1> PPC970_Cracked = 0; 129 bits<3> PPC970_Unit = 0; 130 131 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 132 /// these must be reflected there! See comments there for what these are. 133 let TSFlags{0} = PPC970_First; 134 let TSFlags{1} = PPC970_Single; 135 let TSFlags{2} = PPC970_Cracked; 136 let TSFlags{5-3} = PPC970_Unit; 137 138 bits<1> Prefixed = 1; // This is a prefixed instruction. 139 let TSFlags{7} = Prefixed; 140 141 // For cases where multiple instruction definitions really represent the 142 // same underlying instruction but with one definition for 64-bit arguments 143 // and one for 32-bit arguments, this bit breaks the degeneracy between 144 // the two forms and allows TableGen to generate mapping tables. 145 bit Interpretation64Bit = 0; 146 147 // Fields used for relation models. 148 string BaseName = ""; 149} 150 151// VX-Form: [ PO VT R VB RC XO ] 152class VXForm_VTB5_RC<bits<10> xo, bits<5> R, dag OOL, dag IOL, string asmstr, 153 InstrItinClass itin, list<dag> pattern> 154 : I<4, OOL, IOL, asmstr, itin> { 155 bits<5> VT; 156 bits<5> VB; 157 bit RC = 0; 158 159 let Pattern = pattern; 160 161 let Inst{6-10} = VT; 162 let Inst{11-15} = R; 163 let Inst{16-20} = VB; 164 let Inst{21} = RC; 165 let Inst{22-31} = xo; 166} 167 168// Multiclass definition to account for record and non-record form 169// instructions of VXRForm. 170multiclass VXForm_VTB5_RCr<bits<10> xo, bits<5> R, dag OOL, dag IOL, 171 string asmbase, string asmstr, 172 InstrItinClass itin, list<dag> pattern> { 173 let BaseName = asmbase in { 174 def NAME : VXForm_VTB5_RC<xo, R, OOL, IOL, 175 !strconcat(asmbase, !strconcat(" ", asmstr)), 176 itin, pattern>, RecFormRel; 177 let Defs = [CR6] in 178 def _rec : VXForm_VTB5_RC<xo, R, OOL, IOL, 179 !strconcat(asmbase, !strconcat(". ", asmstr)), 180 itin, []>, isRecordForm, RecFormRel; 181 } 182} 183 184class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr, 185 InstrItinClass itin, list<dag> pattern> 186 : PI<1, opcode, OOL, IOL, asmstr, itin> { 187 bits<5> FRS; 188 bits<39> D_RA; 189 190 let Pattern = pattern; 191 192 // The prefix. 193 let Inst{6-7} = 2; 194 let Inst{8-10} = 0; 195 let Inst{11} = PCRel; 196 let Inst{12-13} = 0; 197 let Inst{14-31} = D_RA{33-16}; // d0 198 199 // The instruction. 200 let Inst{38-42} = FRS{4-0}; 201 let Inst{43-47} = D_RA{38-34}; // RA 202 let Inst{48-63} = D_RA{15-0}; // d1 203} 204 205class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 206 InstrItinClass itin, list<dag> pattern> 207 : PI<1, opcode, OOL, IOL, asmstr, itin> { 208 bits<5> RT; 209 bits<5> RA; 210 bits<34> SI; 211 212 let Pattern = pattern; 213 214 // The prefix. 215 let Inst{6-7} = 2; 216 let Inst{8-10} = 0; 217 let Inst{11} = PCRel; 218 let Inst{12-13} = 0; 219 let Inst{14-31} = SI{33-16}; 220 221 // The instruction. 222 let Inst{38-42} = RT; 223 let Inst{43-47} = RA; 224 let Inst{48-63} = SI{15-0}; 225} 226 227class MLS_DForm_SI34_RT5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 228 InstrItinClass itin, list<dag> pattern> 229 : PI<1, opcode, OOL, IOL, asmstr, itin> { 230 bits<5> RT; 231 bits<34> SI; 232 233 let Pattern = pattern; 234 235 // The prefix. 236 let Inst{6-7} = 2; 237 let Inst{8-10} = 0; 238 let Inst{11} = 0; 239 let Inst{12-13} = 0; 240 let Inst{14-31} = SI{33-16}; 241 242 // The instruction. 243 let Inst{38-42} = RT; 244 let Inst{43-47} = 0; 245 let Inst{48-63} = SI{15-0}; 246} 247 248multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL, 249 dag PCRel_IOL, string asmstr, 250 InstrItinClass itin> { 251 def NAME : MLS_DForm_R_SI34_RTA5<opcode, OOL, IOL, 252 !strconcat(asmstr, ", 0"), itin, []>; 253 def pc : MLS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL, 254 !strconcat(asmstr, ", 1"), itin, []>, isPCRel; 255} 256 257class 8LS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 258 InstrItinClass itin, list<dag> pattern> 259 : PI<1, opcode, OOL, IOL, asmstr, itin> { 260 bits<5> RT; 261 bits<39> D_RA; 262 263 let Pattern = pattern; 264 265 // The prefix. 266 let Inst{6-10} = 0; 267 let Inst{11} = PCRel; 268 let Inst{12-13} = 0; 269 let Inst{14-31} = D_RA{33-16}; // d0 270 271 // The instruction. 272 let Inst{38-42} = RT{4-0}; 273 let Inst{43-47} = D_RA{38-34}; // RA 274 let Inst{48-63} = D_RA{15-0}; // d1 275} 276 277// 8LS:D-Form: [ 1 0 0 // R // d0 278// PO TX T RA d1 ] 279class 8LS_DForm_R_SI34_XT6_RA5<bits<5> opcode, dag OOL, dag IOL, string asmstr, 280 InstrItinClass itin, list<dag> pattern> 281 : PI<1, { opcode, ? }, OOL, IOL, asmstr, itin> { 282 bits<6> XT; 283 bits<39> D_RA; 284 285 let Pattern = pattern; 286 287 // The prefix. 288 let Inst{6-7} = 0; 289 let Inst{8} = 0; 290 let Inst{9-10} = 0; // reserved 291 let Inst{11} = PCRel; 292 let Inst{12-13} = 0; // reserved 293 let Inst{14-31} = D_RA{33-16}; // d0 294 295 // The instruction. 296 let Inst{37} = XT{5}; 297 let Inst{38-42} = XT{4-0}; 298 let Inst{43-47} = D_RA{38-34}; // RA 299 let Inst{48-63} = D_RA{15-0}; // d1 300} 301 302// X-Form: [PO T IMM VRB XO TX] 303class XForm_XT6_IMM5_VB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 304 string asmstr, InstrItinClass itin, list<dag> pattern> 305 : I<opcode, OOL, IOL, asmstr, itin> { 306 bits<6> XT; 307 bits<5> VRB; 308 bits<5> IMM; 309 310 let Pattern = pattern; 311 let Inst{6-10} = XT{4-0}; 312 let Inst{11-15} = IMM; 313 let Inst{16-20} = VRB; 314 let Inst{21-30} = xo; 315 let Inst{31} = XT{5}; 316} 317 318class 8RR_XX4Form_IMM8_XTAB6<bits<6> opcode, bits<2> xo, 319 dag OOL, dag IOL, string asmstr, 320 InstrItinClass itin, list<dag> pattern> 321 : PI<1, opcode, OOL, IOL, asmstr, itin> { 322 bits<6> XT; 323 bits<6> XA; 324 bits<6> XB; 325 bits<6> XC; 326 bits<8> IMM; 327 328 let Pattern = pattern; 329 330 // The prefix. 331 let Inst{6-7} = 1; 332 let Inst{8} = 0; 333 let Inst{9-11} = 0; 334 let Inst{12-13} = 0; 335 let Inst{14-23} = 0; 336 let Inst{24-31} = IMM; 337 338 // The instruction. 339 let Inst{38-42} = XT{4-0}; 340 let Inst{43-47} = XA{4-0}; 341 let Inst{48-52} = XB{4-0}; 342 let Inst{53-57} = XC{4-0}; 343 let Inst{58-59} = xo; 344 let Inst{60} = XC{5}; 345 let Inst{61} = XA{5}; 346 let Inst{62} = XB{5}; 347 let Inst{63} = XT{5}; 348} 349 350class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr, 351 InstrItinClass itin, list<dag> pattern> 352 : I<4, OOL, IOL, asmstr, itin> { 353 bits<5> RD; 354 bits<5> VB; 355 bits<3> N; 356 357 let Pattern = pattern; 358 359 let Inst{6-10} = RD; 360 let Inst{11-12} = 0; 361 let Inst{13-15} = N; 362 let Inst{16-20} = VB; 363 let Inst{21-31} = xo; 364} 365 366 367// VX-Form: [PO VRT RA VRB XO]. 368// Destructive (insert) forms are suffixed with _ins. 369class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern> 370 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, gprc:$rA, vrrc:$vB), 371 !strconcat(opc, " $vD, $rA, $vB"), IIC_VecGeneral, pattern>, 372 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 373 374// VX-Form: [PO VRT RA RB XO]. 375// Destructive (insert) forms are suffixed with _ins. 376class VXForm_VRT5_RAB5_ins<bits<11> xo, string opc, list<dag> pattern> 377 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, gprc:$rA, gprc:$rB), 378 !strconcat(opc, " $vD, $rA, $rB"), IIC_VecGeneral, pattern>, 379 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 380 381// VX-Form: [ PO BF // VRA VRB XO ] 382class VXForm_BF3_VAB5<bits<11> xo, dag OOL, dag IOL, string asmstr, 383 InstrItinClass itin, list<dag> pattern> 384 : I<4, OOL, IOL, asmstr, itin> { 385 bits<3> BF; 386 bits<5> VA; 387 bits<5> VB; 388 389 let Pattern = pattern; 390 391 let Inst{6-8} = BF; 392 let Inst{9-10} = 0; 393 let Inst{11-15} = VA; 394 let Inst{16-20} = VB; 395 let Inst{21-31} = xo; 396} 397 398// VN-Form: [PO VRT VRA VRB PS SD XO] 399// SD is "Shift Direction" 400class VNForm_VTAB5_SD3<bits<6> xo, bits<2> ps, dag OOL, dag IOL, string asmstr, 401 InstrItinClass itin, list<dag> pattern> 402 : I<4, OOL, IOL, asmstr, itin> { 403 bits<5> VRT; 404 bits<5> VRA; 405 bits<5> VRB; 406 bits<3> SD; 407 408 let Pattern = pattern; 409 410 let Inst{6-10} = VRT; 411 let Inst{11-15} = VRA; 412 let Inst{16-20} = VRB; 413 let Inst{21-22} = ps; 414 let Inst{23-25} = SD; 415 let Inst{26-31} = xo; 416} 417 418class VXForm_RD5_MP_VB5<bits<11> xo, bits<4> eo, dag OOL, dag IOL, 419 string asmstr, InstrItinClass itin, list<dag> pattern> 420 : I<4, OOL, IOL, asmstr, itin> { 421 bits<5> RD; 422 bits<5> VB; 423 bit MP; 424 425 let Pattern = pattern; 426 427 let Inst{6-10} = RD; 428 let Inst{11-14} = eo; 429 let Inst{15} = MP; 430 let Inst{16-20} = VB; 431 let Inst{21-31} = xo; 432} 433 434// 8RR:D-Form: [ 1 1 0 // // imm0 435// PO T XO TX imm1 ]. 436class 8RR_DForm_IMM32_XT6<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 437 string asmstr, InstrItinClass itin, 438 list<dag> pattern> 439 : PI<1, opcode, OOL, IOL, asmstr, itin> { 440 bits<6> XT; 441 bits<32> IMM32; 442 443 let Pattern = pattern; 444 445 // The prefix. 446 let Inst{6-7} = 1; 447 let Inst{8-11} = 0; 448 let Inst{12-13} = 0; // reserved 449 let Inst{14-15} = 0; // reserved 450 let Inst{16-31} = IMM32{31-16}; 451 452 // The instruction. 453 let Inst{38-42} = XT{4-0}; 454 let Inst{43-46} = xo; 455 let Inst{47} = XT{5}; 456 let Inst{48-63} = IMM32{15-0}; 457} 458 459// 8RR:D-Form: [ 1 1 0 // // imm0 460// PO T XO IX TX imm1 ]. 461class 8RR_DForm_IMM32_XT6_IX<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 462 string asmstr, InstrItinClass itin, 463 list<dag> pattern> 464 : PI<1, opcode, OOL, IOL, asmstr, itin> { 465 bits<6> XT; 466 bit IX; 467 bits<32> IMM32; 468 469 let Pattern = pattern; 470 471 // The prefix. 472 let Inst{6-7} = 1; 473 let Inst{8-11} = 0; 474 let Inst{12-13} = 0; // reserved 475 let Inst{14-15} = 0; // reserved 476 let Inst{16-31} = IMM32{31-16}; 477 478 // The instruction. 479 let Inst{38-42} = XT{4-0}; 480 let Inst{43-45} = xo; 481 let Inst{46} = IX; 482 let Inst{47} = XT{5}; 483 let Inst{48-63} = IMM32{15-0}; 484} 485 486class 8RR_XX4Form_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, 487 string asmstr, InstrItinClass itin, list<dag> pattern> 488 : PI<1, opcode, OOL, IOL, asmstr, itin> { 489 bits<6> XT; 490 bits<6> XA; 491 bits<6> XB; 492 bits<6> XC; 493 494 let Pattern = pattern; 495 496 // The prefix. 497 let Inst{6-7} = 1; 498 let Inst{8-11} = 0; 499 let Inst{12-13} = 0; 500 let Inst{14-31} = 0; 501 502 // The instruction. 503 let Inst{38-42} = XT{4-0}; 504 let Inst{43-47} = XA{4-0}; 505 let Inst{48-52} = XB{4-0}; 506 let Inst{53-57} = XC{4-0}; 507 let Inst{58-59} = xo; 508 let Inst{60} = XC{5}; 509 let Inst{61} = XA{5}; 510 let Inst{62} = XB{5}; 511 let Inst{63} = XT{5}; 512} 513 514class 8RR_XX4Form_IMM3_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, 515 string asmstr, InstrItinClass itin, 516 list<dag> pattern> 517 : PI<1, opcode, OOL, IOL, asmstr, itin> { 518 bits<6> XT; 519 bits<6> XA; 520 bits<6> XB; 521 bits<6> XC; 522 bits<3> IMM; 523 524 let Pattern = pattern; 525 526 // The prefix. 527 let Inst{6-7} = 1; 528 let Inst{8-11} = 0; 529 let Inst{12-13} = 0; 530 let Inst{14-28} = 0; 531 let Inst{29-31} = IMM; 532 533 // The instruction. 534 let Inst{38-42} = XT{4-0}; 535 let Inst{43-47} = XA{4-0}; 536 let Inst{48-52} = XB{4-0}; 537 let Inst{53-57} = XC{4-0}; 538 let Inst{58-59} = xo; 539 let Inst{60} = XC{5}; 540 let Inst{61} = XA{5}; 541 let Inst{62} = XB{5}; 542 let Inst{63} = XT{5}; 543} 544 545// [PO BF / XO2 B XO BX /] 546class XX2_BF3_XO5_XB6_XO9<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, 547 dag IOL, string asmstr, InstrItinClass itin, 548 list<dag> pattern> 549 : I<opcode, OOL, IOL, asmstr, itin> { 550 bits<3> BF; 551 bits<6> XB; 552 553 let Pattern = pattern; 554 555 let Inst{6-8} = BF; 556 let Inst{9-10} = 0; 557 let Inst{11-15} = xo2; 558 let Inst{16-20} = XB{4-0}; 559 let Inst{21-29} = xo; 560 let Inst{30} = XB{5}; 561 let Inst{31} = 0; 562} 563 564// X-Form: [ PO RT BI /// XO / ] 565class XForm_XT5_BI5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 566 string asmstr, InstrItinClass itin, list<dag> pattern> 567 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 568 let B = 0; 569} 570 571multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL, 572 dag PCRel_IOL, string asmstr, 573 InstrItinClass itin> { 574 def NAME : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, 575 !strconcat(asmstr, ", 0"), itin, []>; 576 def pc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL, 577 !strconcat(asmstr, ", 1"), itin, []>, 578 isPCRel; 579} 580 581multiclass 8LS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL, 582 dag PCRel_IOL, string asmstr, 583 InstrItinClass itin> { 584 def NAME : 8LS_DForm_R_SI34_RTA5<opcode, OOL, IOL, 585 !strconcat(asmstr, ", 0"), itin, []>; 586 def pc : 8LS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL, 587 !strconcat(asmstr, ", 1"), itin, []>, isPCRel; 588} 589 590multiclass 8LS_DForm_R_SI34_XT6_RA5_p<bits<5> opcode, dag OOL, dag IOL, 591 dag PCRel_IOL, string asmstr, 592 InstrItinClass itin> { 593 def NAME : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, IOL, 594 !strconcat(asmstr, ", 0"), itin, []>; 595 def pc : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, PCRel_IOL, 596 !strconcat(asmstr, ", 1"), itin, []>, 597 isPCRel; 598} 599 600def PPCRegVSRpRCAsmOperand : AsmOperandClass { 601 let Name = "RegVSRpRC"; let PredicateMethod = "isVSRpEvenRegNumber"; 602} 603 604def vsrprc : RegisterOperand<VSRpRC> { 605 let ParserMatchClass = PPCRegVSRpRCAsmOperand; 606} 607 608def PPCRegVSRpEvenRCAsmOperand : AsmOperandClass { 609 let Name = "RegVSRpEvenRC"; let PredicateMethod = "isVSRpEvenRegNumber"; 610} 611 612def vsrpevenrc : RegisterOperand<VSRpRC> { 613 let ParserMatchClass = PPCRegVSRpEvenRCAsmOperand; 614 let EncoderMethod = "getVSRpEvenEncoding"; 615 let DecoderMethod = "decodeVSRpEvenOperands"; 616} 617 618class DQForm_XTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 619 string asmstr, InstrItinClass itin, list<dag> pattern> 620 : I<opcode, OOL, IOL, asmstr, itin> { 621 bits<5> XTp; 622 bits<17> DQ_RA; 623 let Pattern = pattern; 624 625 let Inst{6-9} = XTp{3-0}; 626 let Inst{10} = XTp{4}; 627 let Inst{11-15} = DQ_RA{16-12}; // Register # 628 let Inst{16-27} = DQ_RA{11-0}; // Displacement. 629 let Inst{28-31} = xo; 630} 631 632class XForm_XTp5_XAB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 633 string asmstr, InstrItinClass itin, list<dag> pattern> 634 : I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp { 635 bits<5> XTp; 636 bits<5> A; 637 bits<5> B; 638 639 let Pattern = pattern; 640 let Inst{6-9} = XTp{3-0}; 641 let Inst{10} = XTp{4}; 642 let Inst{11-15} = A; 643 let Inst{16-20} = B; 644 let Inst{21-30} = xo; 645 let Inst{31} = 0; 646} 647 648class 8LS_DForm_R_XTp5_SI34_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr, 649 InstrItinClass itin, list<dag> pattern> 650 : PI<1, opcode, OOL, IOL, asmstr, itin> { 651 bits<5> XTp; 652 bits<39> D_RA; 653 654 let Pattern = pattern; 655 656 // The prefix. 657 let Inst{6-10} = 0; 658 let Inst{11} = PCRel; 659 let Inst{12-13} = 0; 660 let Inst{14-31} = D_RA{33-16}; // Imm18 661 662 // The instruction. 663 let Inst{38-41} = XTp{3-0}; 664 let Inst{42} = XTp{4}; 665 let Inst{43-47} = D_RA{38-34}; // Register # 666 let Inst{48-63} = D_RA{15-0}; // D 667} 668 669multiclass 8LS_DForm_R_XTp5_SI34_MEM_p<bits<6> opcode, dag OOL, 670 dag IOL, dag PCRel_IOL, 671 string asmstr, InstrItinClass itin> { 672 def NAME : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, IOL, 673 !strconcat(asmstr, ", 0"), itin, []>; 674 def pc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, PCRel_IOL, 675 !strconcat(asmstr, ", 1"), itin, []>, 676 isPCRel; 677} 678 679def PPCRegACCRCAsmOperand : AsmOperandClass { 680 let Name = "RegACCRC"; let PredicateMethod = "isACCRegNumber"; 681} 682 683def acc : RegisterOperand<ACCRC> { 684 let ParserMatchClass = PPCRegACCRCAsmOperand; 685} 686 687def uacc : RegisterOperand<UACCRC> { 688 let ParserMatchClass = PPCRegACCRCAsmOperand; 689} 690 691// [PO AS XO2 XO] 692class XForm_AT3<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, 693 string asmstr, InstrItinClass itin, list<dag> pattern> 694 : I<opcode, OOL, IOL, asmstr, itin> { 695 bits<3> AT; 696 697 let Pattern = pattern; 698 699 let Inst{6-8} = AT; 700 let Inst{9-10} = 0; 701 let Inst{11-15} = xo2; 702 let Inst{16-20} = 0; 703 let Inst{21-30} = xo; 704 let Inst{31} = 0; 705} 706 707// X-Form: [ PO T EO UIM XO TX ] 708class XForm_XT6_IMM5<bits<6> opcode, bits<5> eo, bits<10> xo, dag OOL, dag IOL, 709 string asmstr, InstrItinClass itin, list<dag> pattern> 710 : I<opcode, OOL, IOL, asmstr, itin> { 711 bits<6> XT; 712 bits<5> UIM; 713 714 let Pattern = pattern; 715 716 let Inst{6-10} = XT{4-0}; 717 let Inst{11-15} = eo; 718 let Inst{16-20} = UIM; 719 let Inst{21-30} = xo; 720 let Inst{31} = XT{5}; 721} 722 723class XX3Form_AT3_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 724 string asmstr, InstrItinClass itin, 725 list<dag> pattern> 726 : I<opcode, OOL, IOL, asmstr, itin> { 727 bits<3> AT; 728 bits<6> XA; 729 bits<6> XB; 730 731 let Pattern = pattern; 732 733 let Inst{6-8} = AT; 734 let Inst{9-10} = 0; 735 let Inst{11-15} = XA{4-0}; 736 let Inst{16-20} = XB{4-0}; 737 let Inst{21-28} = xo; 738 let Inst{29} = XA{5}; 739 let Inst{30} = XB{5}; 740 let Inst{31} = 0; 741} 742 743class MMIRR_XX3Form_XY4P2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 744 string asmstr, InstrItinClass itin, 745 list<dag> pattern> 746 : PI<1, opcode, OOL, IOL, asmstr, itin> { 747 bits<3> AT; 748 bits<6> XA; 749 bits<6> XB; 750 bits<4> XMSK; 751 bits<4> YMSK; 752 bits<2> PMSK; 753 754 let Pattern = pattern; 755 756 // The prefix. 757 let Inst{6-7} = 3; 758 let Inst{8-11} = 9; 759 let Inst{12-15} = 0; 760 let Inst{16-17} = PMSK; 761 let Inst{18-23} = 0; 762 let Inst{24-27} = XMSK; 763 let Inst{28-31} = YMSK; 764 765 // The instruction. 766 let Inst{38-40} = AT; 767 let Inst{41-42} = 0; 768 let Inst{43-47} = XA{4-0}; 769 let Inst{48-52} = XB{4-0}; 770 let Inst{53-60} = xo; 771 let Inst{61} = XA{5}; 772 let Inst{62} = XB{5}; 773 let Inst{63} = 0; 774} 775 776class MMIRR_XX3Form_XY4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 777 string asmstr, InstrItinClass itin, 778 list<dag> pattern> 779 : PI<1, opcode, OOL, IOL, asmstr, itin> { 780 bits<3> AT; 781 bits<6> XA; 782 bits<6> XB; 783 bits<4> XMSK; 784 bits<4> YMSK; 785 786 let Pattern = pattern; 787 788 // The prefix. 789 let Inst{6-7} = 3; 790 let Inst{8-11} = 9; 791 let Inst{12-23} = 0; 792 let Inst{24-27} = XMSK; 793 let Inst{28-31} = YMSK; 794 795 // The instruction. 796 let Inst{38-40} = AT; 797 let Inst{41-42} = 0; 798 let Inst{43-47} = XA{4-0}; 799 let Inst{48-52} = XB{4-0}; 800 let Inst{53-60} = xo; 801 let Inst{61} = XA{5}; 802 let Inst{62} = XB{5}; 803 let Inst{63} = 0; 804} 805 806class MMIRR_XX3Form_X4Y2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 807 string asmstr, InstrItinClass itin, 808 list<dag> pattern> 809 : PI<1, opcode, OOL, IOL, asmstr, itin> { 810 bits<3> AT; 811 bits<6> XA; 812 bits<6> XB; 813 bits<4> XMSK; 814 bits<2> YMSK; 815 816 let Pattern = pattern; 817 818 // The prefix. 819 let Inst{6-7} = 3; 820 let Inst{8-11} = 9; 821 let Inst{12-23} = 0; 822 let Inst{24-27} = XMSK; 823 let Inst{28-29} = YMSK; 824 let Inst{30-31} = 0; 825 826 // The instruction. 827 let Inst{38-40} = AT; 828 let Inst{41-42} = 0; 829 let Inst{43-47} = XA{4-0}; 830 let Inst{48-52} = XB{4-0}; 831 let Inst{53-60} = xo; 832 let Inst{61} = XA{5}; 833 let Inst{62} = XB{5}; 834 let Inst{63} = 0; 835} 836 837class MMIRR_XX3Form_XY4P8_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 838 string asmstr, InstrItinClass itin, 839 list<dag> pattern> 840 : PI<1, opcode, OOL, IOL, asmstr, itin> { 841 bits<3> AT; 842 bits<6> XA; 843 bits<6> XB; 844 bits<4> XMSK; 845 bits<4> YMSK; 846 bits<8> PMSK; 847 848 let Pattern = pattern; 849 850 // The prefix. 851 let Inst{6-7} = 3; 852 let Inst{8-11} = 9; 853 let Inst{12-15} = 0; 854 let Inst{16-23} = PMSK; 855 let Inst{24-27} = XMSK; 856 let Inst{28-31} = YMSK; 857 858 // The instruction. 859 let Inst{38-40} = AT; 860 let Inst{41-42} = 0; 861 let Inst{43-47} = XA{4-0}; 862 let Inst{48-52} = XB{4-0}; 863 let Inst{53-60} = xo; 864 let Inst{61} = XA{5}; 865 let Inst{62} = XB{5}; 866 let Inst{63} = 0; 867} 868 869class MMIRR_XX3Form_XYP4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 870 string asmstr, InstrItinClass itin, 871 list<dag> pattern> 872 : PI<1, opcode, OOL, IOL, asmstr, itin> { 873 bits<3> AT; 874 bits<6> XA; 875 bits<6> XB; 876 bits<4> XMSK; 877 bits<4> YMSK; 878 bits<4> PMSK; 879 880 let Pattern = pattern; 881 882 // The prefix. 883 let Inst{6-7} = 3; 884 let Inst{8-11} = 9; 885 let Inst{12-15} = 0; 886 let Inst{16-19} = PMSK; 887 let Inst{20-23} = 0; 888 let Inst{24-27} = XMSK; 889 let Inst{28-31} = YMSK; 890 891 // The instruction. 892 let Inst{38-40} = AT; 893 let Inst{41-42} = 0; 894 let Inst{43-47} = XA{4-0}; 895 let Inst{48-52} = XB{4-0}; 896 let Inst{53-60} = xo; 897 let Inst{61} = XA{5}; 898 let Inst{62} = XB{5}; 899 let Inst{63} = 0; 900} 901 902def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">; 903def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">; 904def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">; 905 906def RCCp { 907 dag AToVSRC = (COPY_TO_REGCLASS $XA, VSRC); 908 dag BToVSRC = (COPY_TO_REGCLASS $XB, VSRC); 909} 910 911let Predicates = [PrefixInstrs] in { 912 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 913 defm PADDI8 : 914 MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA, s34imm:$SI), 915 (ins immZero:$RA, s34imm_pcrel:$SI), 916 "paddi $RT, $RA, $SI", IIC_LdStLFD>; 917 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 918 def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT), 919 (ins s34imm:$SI), 920 "pli $RT, $SI", IIC_IntSimple, []>; 921 } 922 } 923 defm PADDI : 924 MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc:$RA, s34imm:$SI), 925 (ins immZero:$RA, s34imm_pcrel:$SI), 926 "paddi $RT, $RA, $SI", IIC_LdStLFD>; 927 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 928 def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT), 929 (ins s34imm:$SI), 930 "pli $RT, $SI", IIC_IntSimple, []>; 931 } 932 933 let mayLoad = 1, mayStore = 0 in { 934 defm PLXV : 935 8LS_DForm_R_SI34_XT6_RA5_p<25, (outs vsrc:$XT), (ins memri34:$D_RA), 936 (ins memri34_pcrel:$D_RA), "plxv $XT, $D_RA", 937 IIC_LdStLFD>; 938 defm PLFS : 939 MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$FRT), (ins memri34:$D_RA), 940 (ins memri34_pcrel:$D_RA), "plfs $FRT, $D_RA", 941 IIC_LdStLFD>; 942 defm PLFD : 943 MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$FRT), (ins memri34:$D_RA), 944 (ins memri34_pcrel:$D_RA), "plfd $FRT, $D_RA", 945 IIC_LdStLFD>; 946 defm PLXSSP : 947 8LS_DForm_R_SI34_RTA5_p<43, (outs vfrc:$VRT), (ins memri34:$D_RA), 948 (ins memri34_pcrel:$D_RA), "plxssp $VRT, $D_RA", 949 IIC_LdStLFD>; 950 defm PLXSD : 951 8LS_DForm_R_SI34_RTA5_p<42, (outs vfrc:$VRT), (ins memri34:$D_RA), 952 (ins memri34_pcrel:$D_RA), "plxsd $VRT, $D_RA", 953 IIC_LdStLFD>; 954 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 955 defm PLBZ8 : 956 MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RT), (ins memri34:$D_RA), 957 (ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA", 958 IIC_LdStLFD>; 959 defm PLHZ8 : 960 MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RT), (ins memri34:$D_RA), 961 (ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA", 962 IIC_LdStLFD>; 963 defm PLHA8 : 964 MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RT), (ins memri34:$D_RA), 965 (ins memri34_pcrel:$D_RA), "plha $RT, $D_RA", 966 IIC_LdStLFD>; 967 defm PLWA8 : 968 8LS_DForm_R_SI34_RTA5_p<41, (outs g8rc:$RT), (ins memri34:$D_RA), 969 (ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA", 970 IIC_LdStLFD>; 971 defm PLWZ8 : 972 MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RT), (ins memri34:$D_RA), 973 (ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA", 974 IIC_LdStLFD>; 975 } 976 defm PLBZ : 977 MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RT), (ins memri34:$D_RA), 978 (ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA", 979 IIC_LdStLFD>; 980 defm PLHZ : 981 MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RT), (ins memri34:$D_RA), 982 (ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA", 983 IIC_LdStLFD>; 984 defm PLHA : 985 MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RT), (ins memri34:$D_RA), 986 (ins memri34_pcrel:$D_RA), "plha $RT, $D_RA", 987 IIC_LdStLFD>; 988 defm PLWZ : 989 MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RT), (ins memri34:$D_RA), 990 (ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA", 991 IIC_LdStLFD>; 992 defm PLWA : 993 8LS_DForm_R_SI34_RTA5_p<41, (outs gprc:$RT), (ins memri34:$D_RA), 994 (ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA", 995 IIC_LdStLFD>; 996 defm PLD : 997 8LS_DForm_R_SI34_RTA5_p<57, (outs g8rc:$RT), (ins memri34:$D_RA), 998 (ins memri34_pcrel:$D_RA), "pld $RT, $D_RA", 999 IIC_LdStLFD>; 1000 } 1001 1002 let mayStore = 1, mayLoad = 0 in { 1003 defm PSTXV : 1004 8LS_DForm_R_SI34_XT6_RA5_p<27, (outs), (ins vsrc:$XS, memri34:$D_RA), 1005 (ins vsrc:$XS, memri34_pcrel:$D_RA), 1006 "pstxv $XS, $D_RA", IIC_LdStLFD>; 1007 defm PSTFS : 1008 MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$FRS, memri34:$D_RA), 1009 (ins f4rc:$FRS, memri34_pcrel:$D_RA), 1010 "pstfs $FRS, $D_RA", IIC_LdStLFD>; 1011 defm PSTFD : 1012 MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$FRS, memri34:$D_RA), 1013 (ins f8rc:$FRS, memri34_pcrel:$D_RA), 1014 "pstfd $FRS, $D_RA", IIC_LdStLFD>; 1015 defm PSTXSSP : 1016 8LS_DForm_R_SI34_RTA5_p<47, (outs), (ins vfrc:$VRS, memri34:$D_RA), 1017 (ins vfrc:$VRS, memri34_pcrel:$D_RA), 1018 "pstxssp $VRS, $D_RA", IIC_LdStLFD>; 1019 defm PSTXSD : 1020 8LS_DForm_R_SI34_RTA5_p<46, (outs), (ins vfrc:$VRS, memri34:$D_RA), 1021 (ins vfrc:$VRS, memri34_pcrel:$D_RA), 1022 "pstxsd $VRS, $D_RA", IIC_LdStLFD>; 1023 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1024 defm PSTB8 : 1025 MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RS, memri34:$D_RA), 1026 (ins g8rc:$RS, memri34_pcrel:$D_RA), 1027 "pstb $RS, $D_RA", IIC_LdStLFD>; 1028 defm PSTH8 : 1029 MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RS, memri34:$D_RA), 1030 (ins g8rc:$RS, memri34_pcrel:$D_RA), 1031 "psth $RS, $D_RA", IIC_LdStLFD>; 1032 defm PSTW8 : 1033 MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RS, memri34:$D_RA), 1034 (ins g8rc:$RS, memri34_pcrel:$D_RA), 1035 "pstw $RS, $D_RA", IIC_LdStLFD>; 1036 } 1037 defm PSTB : 1038 MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RS, memri34:$D_RA), 1039 (ins gprc:$RS, memri34_pcrel:$D_RA), 1040 "pstb $RS, $D_RA", IIC_LdStLFD>; 1041 defm PSTH : 1042 MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RS, memri34:$D_RA), 1043 (ins gprc:$RS, memri34_pcrel:$D_RA), 1044 "psth $RS, $D_RA", IIC_LdStLFD>; 1045 defm PSTW : 1046 MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RS, memri34:$D_RA), 1047 (ins gprc:$RS, memri34_pcrel:$D_RA), 1048 "pstw $RS, $D_RA", IIC_LdStLFD>; 1049 defm PSTD : 1050 8LS_DForm_R_SI34_RTA5_p<61, (outs), (ins g8rc:$RS, memri34:$D_RA), 1051 (ins g8rc:$RS, memri34_pcrel:$D_RA), 1052 "pstd $RS, $D_RA", IIC_LdStLFD>; 1053 } 1054} 1055 1056def Concats { 1057 dag VecsToVecPair0 = 1058 (v256i1 (INSERT_SUBREG 1059 (INSERT_SUBREG (IMPLICIT_DEF), $vs0, sub_vsx1), 1060 $vs1, sub_vsx0)); 1061 dag VecsToVecPair1 = 1062 (v256i1 (INSERT_SUBREG 1063 (INSERT_SUBREG (IMPLICIT_DEF), $vs2, sub_vsx1), 1064 $vs3, sub_vsx0)); 1065} 1066 1067let Predicates = [PairedVectorMemops] in { 1068 def : Pat<(v256i1 (PPCPairBuild v4i32:$vs1, v4i32:$vs0)), 1069 Concats.VecsToVecPair0>; 1070 def : Pat<(v256i1 (int_ppc_vsx_assemble_pair v16i8:$vs1, v16i8:$vs0)), 1071 Concats.VecsToVecPair0>; 1072 def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 0)), 1073 (v4i32 (EXTRACT_SUBREG $v, sub_vsx0))>; 1074 def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 1)), 1075 (v4i32 (EXTRACT_SUBREG $v, sub_vsx1))>; 1076} 1077 1078let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops] in { 1079 def LXVP : DQForm_XTp5_RA17_MEM<6, 0, (outs vsrprc:$XTp), 1080 (ins memrix16:$DQ_RA), "lxvp $XTp, $DQ_RA", 1081 IIC_LdStLFD, []>; 1082 def LXVPX : XForm_XTp5_XAB5<31, 333, (outs vsrprc:$XTp), (ins memrr:$src), 1083 "lxvpx $XTp, $src", IIC_LdStLFD, 1084 []>; 1085} 1086 1087let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops] in { 1088 def STXVP : DQForm_XTp5_RA17_MEM<6, 1, (outs), (ins vsrprc:$XTp, 1089 memrix16:$DQ_RA), "stxvp $XTp, $DQ_RA", 1090 IIC_LdStLFD, []>; 1091 def STXVPX : XForm_XTp5_XAB5<31, 461, (outs), (ins vsrprc:$XTp, memrr:$dst), 1092 "stxvpx $XTp, $dst", IIC_LdStLFD, 1093 []>; 1094} 1095 1096let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs] in { 1097 defm PLXVP : 1098 8LS_DForm_R_XTp5_SI34_MEM_p<58, (outs vsrprc:$XTp), (ins memri34:$D_RA), 1099 (ins memri34_pcrel:$D_RA), "plxvp $XTp, $D_RA", 1100 IIC_LdStLFD>; 1101} 1102 1103let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs] in { 1104 defm PSTXVP : 1105 8LS_DForm_R_XTp5_SI34_MEM_p<62, (outs), (ins vsrprc:$XTp, memri34:$D_RA), 1106 (ins vsrprc:$XTp, memri34_pcrel:$D_RA), 1107 "pstxvp $XTp, $D_RA", IIC_LdStLFD>; 1108} 1109 1110let Predicates = [PairedVectorMemops] in { 1111 // Intrinsics for Paired Vector Loads. 1112 def : Pat<(v256i1 (int_ppc_vsx_lxvp DQForm:$src)), (LXVP memrix16:$src)>; 1113 def : Pat<(v256i1 (int_ppc_vsx_lxvp XForm:$src)), (LXVPX XForm:$src)>; 1114 let Predicates = [PairedVectorMemops, PrefixInstrs] in { 1115 def : Pat<(v256i1 (int_ppc_vsx_lxvp PDForm:$src)), (PLXVP memri34:$src)>; 1116 } 1117 // Intrinsics for Paired Vector Stores. 1118 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, DQForm:$dst), 1119 (STXVP $XSp, memrix16:$dst)>; 1120 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, XForm:$dst), 1121 (STXVPX $XSp, XForm:$dst)>; 1122 let Predicates = [PairedVectorMemops, PrefixInstrs] in { 1123 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, PDForm:$dst), 1124 (PSTXVP $XSp, memri34:$dst)>; 1125 } 1126} 1127 1128let Predicates = [PCRelativeMemops] in { 1129 // Load i32 1130 def : Pat<(i32 (zextloadi1 (PPCmatpcreladdr PCRelForm:$ga))), 1131 (PLBZpc $ga, 0)>; 1132 def : Pat<(i32 (extloadi1 (PPCmatpcreladdr PCRelForm:$ga))), 1133 (PLBZpc $ga, 0)>; 1134 def : Pat<(i32 (zextloadi8 (PPCmatpcreladdr PCRelForm:$ga))), 1135 (PLBZpc $ga, 0)>; 1136 def : Pat<(i32 (extloadi8 (PPCmatpcreladdr PCRelForm:$ga))), 1137 (PLBZpc $ga, 0)>; 1138 def : Pat<(i32 (sextloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1139 (PLHApc $ga, 0)>; 1140 def : Pat<(i32 (zextloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1141 (PLHZpc $ga, 0)>; 1142 def : Pat<(i32 (extloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1143 (PLHZpc $ga, 0)>; 1144 def : Pat<(i32 (load (PPCmatpcreladdr PCRelForm:$ga))), (PLWZpc $ga, 0)>; 1145 1146 // Store i32 1147 def : Pat<(truncstorei8 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1148 (PSTBpc $RS, $ga, 0)>; 1149 def : Pat<(truncstorei16 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1150 (PSTHpc $RS, $ga, 0)>; 1151 def : Pat<(store i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1152 (PSTWpc $RS, $ga, 0)>; 1153 1154 // Load i64 1155 def : Pat<(i64 (zextloadi1 (PPCmatpcreladdr PCRelForm:$ga))), 1156 (PLBZ8pc $ga, 0)>; 1157 def : Pat<(i64 (extloadi1 (PPCmatpcreladdr PCRelForm:$ga))), 1158 (PLBZ8pc $ga, 0)>; 1159 def : Pat<(i64 (zextloadi8 (PPCmatpcreladdr PCRelForm:$ga))), 1160 (PLBZ8pc $ga, 0)>; 1161 def : Pat<(i64 (extloadi8 (PPCmatpcreladdr PCRelForm:$ga))), 1162 (PLBZ8pc $ga, 0)>; 1163 def : Pat<(i64 (sextloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1164 (PLHA8pc $ga, 0)>; 1165 def : Pat<(i64 (zextloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1166 (PLHZ8pc $ga, 0)>; 1167 def : Pat<(i64 (extloadi16 (PPCmatpcreladdr PCRelForm:$ga))), 1168 (PLHZ8pc $ga, 0)>; 1169 def : Pat<(i64 (zextloadi32 (PPCmatpcreladdr PCRelForm:$ga))), 1170 (PLWZ8pc $ga, 0)>; 1171 def : Pat<(i64 (sextloadi32 (PPCmatpcreladdr PCRelForm:$ga))), 1172 (PLWA8pc $ga, 0)>; 1173 def : Pat<(i64 (extloadi32 (PPCmatpcreladdr PCRelForm:$ga))), 1174 (PLWZ8pc $ga, 0)>; 1175 def : Pat<(i64 (load (PPCmatpcreladdr PCRelForm:$ga))), (PLDpc $ga, 0)>; 1176 1177 // Store i64 1178 def : Pat<(truncstorei8 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1179 (PSTB8pc $RS, $ga, 0)>; 1180 def : Pat<(truncstorei16 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1181 (PSTH8pc $RS, $ga, 0)>; 1182 def : Pat<(truncstorei32 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1183 (PSTW8pc $RS, $ga, 0)>; 1184 def : Pat<(store i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)), 1185 (PSTDpc $RS, $ga, 0)>; 1186 1187 // Load f32 1188 def : Pat<(f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFSpc $addr, 0)>; 1189 1190 // Store f32 1191 def : Pat<(store f32:$FRS, (PPCmatpcreladdr PCRelForm:$ga)), 1192 (PSTFSpc $FRS, $ga, 0)>; 1193 1194 // Load f64 1195 def : Pat<(f64 (extloadf32 (PPCmatpcreladdr PCRelForm:$addr))), 1196 (COPY_TO_REGCLASS (PLFSpc $addr, 0), VSFRC)>; 1197 def : Pat<(f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFDpc $addr, 0)>; 1198 1199 // Store f64 1200 def : Pat<(store f64:$FRS, (PPCmatpcreladdr PCRelForm:$ga)), 1201 (PSTFDpc $FRS, $ga, 0)>; 1202 1203 // Load f128 1204 def : Pat<(f128 (load (PPCmatpcreladdr PCRelForm:$addr))), 1205 (COPY_TO_REGCLASS (PLXVpc $addr, 0), VRRC)>; 1206 1207 // Store f128 1208 def : Pat<(store f128:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1209 (PSTXVpc (COPY_TO_REGCLASS $XS, VSRC), $ga, 0)>; 1210 1211 // Load v4i32 1212 def : Pat<(v4i32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>; 1213 1214 // Store v4i32 1215 def : Pat<(store v4i32:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1216 (PSTXVpc $XS, $ga, 0)>; 1217 1218 // Load v2i64 1219 def : Pat<(v2i64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>; 1220 1221 // Store v2i64 1222 def : Pat<(store v2i64:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1223 (PSTXVpc $XS, $ga, 0)>; 1224 1225 // Load v4f32 1226 def : Pat<(v4f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>; 1227 1228 // Store v4f32 1229 def : Pat<(store v4f32:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1230 (PSTXVpc $XS, $ga, 0)>; 1231 1232 // Load v2f64 1233 def : Pat<(v2f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>; 1234 1235 // Store v2f64 1236 def : Pat<(store v2f64:$XS, (PPCmatpcreladdr PCRelForm:$ga)), 1237 (PSTXVpc $XS, $ga, 0)>; 1238 1239 // Atomic Load 1240 def : Pat<(atomic_load_8 (PPCmatpcreladdr PCRelForm:$ga)), 1241 (PLBZpc $ga, 0)>; 1242 def : Pat<(atomic_load_16 (PPCmatpcreladdr PCRelForm:$ga)), 1243 (PLHZpc $ga, 0)>; 1244 def : Pat<(atomic_load_32 (PPCmatpcreladdr PCRelForm:$ga)), 1245 (PLWZpc $ga, 0)>; 1246 def : Pat<(atomic_load_64 (PPCmatpcreladdr PCRelForm:$ga)), 1247 (PLDpc $ga, 0)>; 1248 1249 // Atomic Store 1250 def : Pat<(atomic_store_8 (PPCmatpcreladdr PCRelForm:$ga), i32:$RS), 1251 (PSTBpc $RS, $ga, 0)>; 1252 def : Pat<(atomic_store_16 (PPCmatpcreladdr PCRelForm:$ga), i32:$RS), 1253 (PSTHpc $RS, $ga, 0)>; 1254 def : Pat<(atomic_store_32 (PPCmatpcreladdr PCRelForm:$ga), i32:$RS), 1255 (PSTWpc $RS, $ga, 0)>; 1256 def : Pat<(atomic_store_8 (PPCmatpcreladdr PCRelForm:$ga), i64:$RS), 1257 (PSTB8pc $RS, $ga, 0)>; 1258 def : Pat<(atomic_store_16 (PPCmatpcreladdr PCRelForm:$ga), i64:$RS), 1259 (PSTH8pc $RS, $ga, 0)>; 1260 def : Pat<(atomic_store_32 (PPCmatpcreladdr PCRelForm:$ga), i64:$RS), 1261 (PSTW8pc $RS, $ga, 0)>; 1262 def : Pat<(atomic_store_64 (PPCmatpcreladdr PCRelForm:$ga), i64:$RS), 1263 (PSTDpc $RS, $ga, 0)>; 1264 1265 // Special Cases For PPCstore_scal_int_from_vsr 1266 def : Pat<(PPCstore_scal_int_from_vsr 1267 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), 1268 (PPCmatpcreladdr PCRelForm:$dst), 8), 1269 (PSTXSDpc (XSCVDPSXDS f64:$src), $dst, 0)>; 1270 def : Pat<(PPCstore_scal_int_from_vsr 1271 (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), 1272 (PPCmatpcreladdr PCRelForm:$dst), 8), 1273 (PSTXSDpc (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC), $dst, 0)>; 1274 1275 def : Pat<(PPCstore_scal_int_from_vsr 1276 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), 1277 (PPCmatpcreladdr PCRelForm:$dst), 8), 1278 (PSTXSDpc (XSCVDPUXDS f64:$src), $dst, 0)>; 1279 def : Pat<(PPCstore_scal_int_from_vsr 1280 (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), 1281 (PPCmatpcreladdr PCRelForm:$dst), 8), 1282 (PSTXSDpc (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC), $dst, 0)>; 1283 1284 def : Pat<(v4f32 (PPCldvsxlh (PPCmatpcreladdr PCRelForm:$addr))), 1285 (SUBREG_TO_REG (i64 1), (PLFDpc $addr, 0), sub_64)>; 1286 1287 // If the PPCmatpcreladdr node is not caught by any other pattern it should be 1288 // caught here and turned into a paddi instruction to materialize the address. 1289 def : Pat<(PPCmatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>; 1290 // PPCtlsdynamatpcreladdr node is used for TLS dynamic models to materialize 1291 // tls global address with paddi instruction. 1292 def : Pat<(PPCtlsdynamatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>; 1293 // PPCtlslocalexecmataddr node is used for TLS local exec models to 1294 // materialize tls global address with paddi instruction. 1295 def : Pat<(PPCaddTls i64:$in, (PPCtlslocalexecmataddr tglobaltlsaddr:$addr)), 1296 (PADDI8 $in, $addr)>; 1297} 1298 1299let Predicates = [PrefixInstrs] in { 1300 def XXPERMX : 1301 8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1302 vsrc:$XC, u3imm:$UIM), 1303 "xxpermx $XT, $XA, $XB, $XC, $UIM", 1304 IIC_VecPerm, []>; 1305 def XXBLENDVB : 1306 8RR_XX4Form_XTABC6<33, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1307 vsrc:$XC), "xxblendvb $XT, $XA, $XB, $XC", 1308 IIC_VecGeneral, []>; 1309 def XXBLENDVH : 1310 8RR_XX4Form_XTABC6<33, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1311 vsrc:$XC), "xxblendvh $XT, $XA, $XB, $XC", 1312 IIC_VecGeneral, []>; 1313 def XXBLENDVW : 1314 8RR_XX4Form_XTABC6<33, 2, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1315 vsrc:$XC), "xxblendvw $XT, $XA, $XB, $XC", 1316 IIC_VecGeneral, []>; 1317 def XXBLENDVD : 1318 8RR_XX4Form_XTABC6<33, 3, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1319 vsrc:$XC), "xxblendvd $XT, $XA, $XB, $XC", 1320 IIC_VecGeneral, []>; 1321} 1322 1323// XXSPLTIW/DP/32DX need extra flags to make sure the compiler does not attempt 1324// to spill part of the instruction when the values are similar. 1325let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, Predicates = [PrefixInstrs] in { 1326 def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT), 1327 (ins i32imm:$IMM32), 1328 "xxspltiw $XT, $IMM32", IIC_VecGeneral, 1329 []>; 1330 def XXSPLTIDP : 8RR_DForm_IMM32_XT6<32, 2, (outs vsrc:$XT), 1331 (ins i32imm:$IMM32), 1332 "xxspltidp $XT, $IMM32", IIC_VecGeneral, 1333 [(set v2f64:$XT, 1334 (PPCxxspltidp i32:$IMM32))]>; 1335 def XXSPLTI32DX : 1336 8RR_DForm_IMM32_XT6_IX<32, 0, (outs vsrc:$XT), 1337 (ins vsrc:$XTi, u1imm:$IX, i32imm:$IMM32), 1338 "xxsplti32dx $XT, $IX, $IMM32", IIC_VecGeneral, 1339 [(set v2i64:$XT, 1340 (PPCxxsplti32dx v2i64:$XTi, i32:$IX, 1341 i32:$IMM32))]>, 1342 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">; 1343} 1344 1345let Predicates = [IsISA3_1] in { 1346 def SETBC : XForm_XT5_BI5<31, 384, (outs gprc:$RT), (ins crbitrc:$BI), 1347 "setbc $RT, $BI", IIC_IntCompare, []>; 1348 def SETBCR : XForm_XT5_BI5<31, 416, (outs gprc:$RT), (ins crbitrc:$BI), 1349 "setbcr $RT, $BI", IIC_IntCompare, []>; 1350 def SETNBC : XForm_XT5_BI5<31, 448, (outs gprc:$RT), (ins crbitrc:$BI), 1351 "setnbc $RT, $BI", IIC_IntCompare, []>; 1352 def SETNBCR : XForm_XT5_BI5<31, 480, (outs gprc:$RT), (ins crbitrc:$BI), 1353 "setnbcr $RT, $BI", IIC_IntCompare, []>; 1354 1355 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1356 def SETBC8 : XForm_XT5_BI5<31, 384, (outs g8rc:$RT), (ins crbitrc:$BI), 1357 "setbc $RT, $BI", IIC_IntCompare, []>; 1358 def SETBCR8 : XForm_XT5_BI5<31, 416, (outs g8rc:$RT), (ins crbitrc:$BI), 1359 "setbcr $RT, $BI", IIC_IntCompare, []>; 1360 def SETNBC8 : XForm_XT5_BI5<31, 448, (outs g8rc:$RT), (ins crbitrc:$BI), 1361 "setnbc $RT, $BI", IIC_IntCompare, []>; 1362 def SETNBCR8 : XForm_XT5_BI5<31, 480, (outs g8rc:$RT), (ins crbitrc:$BI), 1363 "setnbcr $RT, $BI", IIC_IntCompare, []>; 1364 } 1365 1366 def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT), 1367 (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH), 1368 "vsldbi $VRT, $VRA, $VRB, $SH", 1369 IIC_VecGeneral, 1370 [(set v16i8:$VRT, 1371 (int_ppc_altivec_vsldbi v16i8:$VRA, 1372 v16i8:$VRB, 1373 timm:$SH))]>; 1374 def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT), 1375 (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH), 1376 "vsrdbi $VRT, $VRA, $VRB, $SH", 1377 IIC_VecGeneral, 1378 [(set v16i8:$VRT, 1379 (int_ppc_altivec_vsrdbi v16i8:$VRA, 1380 v16i8:$VRB, 1381 timm:$SH))]>; 1382 defm VSTRIBR : VXForm_VTB5_RCr<13, 1, (outs vrrc:$vT), (ins vrrc:$vB), 1383 "vstribr", "$vT, $vB", IIC_VecGeneral, 1384 [(set v16i8:$vT, 1385 (int_ppc_altivec_vstribr v16i8:$vB))]>; 1386 defm VSTRIBL : VXForm_VTB5_RCr<13, 0, (outs vrrc:$vT), (ins vrrc:$vB), 1387 "vstribl", "$vT, $vB", IIC_VecGeneral, 1388 [(set v16i8:$vT, 1389 (int_ppc_altivec_vstribl v16i8:$vB))]>; 1390 defm VSTRIHR : VXForm_VTB5_RCr<13, 3, (outs vrrc:$vT), (ins vrrc:$vB), 1391 "vstrihr", "$vT, $vB", IIC_VecGeneral, 1392 [(set v8i16:$vT, 1393 (int_ppc_altivec_vstrihr v8i16:$vB))]>; 1394 defm VSTRIHL : VXForm_VTB5_RCr<13, 2, (outs vrrc:$vT), (ins vrrc:$vB), 1395 "vstrihl", "$vT, $vB", IIC_VecGeneral, 1396 [(set v8i16:$vT, 1397 (int_ppc_altivec_vstrihl v8i16:$vB))]>; 1398 def VINSW : 1399 VXForm_1<207, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, gprc:$rB), 1400 "vinsw $vD, $rB, $UIM", IIC_VecGeneral, 1401 [(set v4i32:$vD, 1402 (int_ppc_altivec_vinsw v4i32:$vDi, i32:$rB, timm:$UIM))]>, 1403 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1404 def VINSD : 1405 VXForm_1<463, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, g8rc:$rB), 1406 "vinsd $vD, $rB, $UIM", IIC_VecGeneral, 1407 [(set v2i64:$vD, 1408 (int_ppc_altivec_vinsd v2i64:$vDi, i64:$rB, timm:$UIM))]>, 1409 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1410 def VINSBVLX : 1411 VXForm_VTB5_RA5_ins<15, "vinsbvlx", 1412 [(set v16i8:$vD, 1413 (int_ppc_altivec_vinsbvlx v16i8:$vDi, i32:$rA, 1414 v16i8:$vB))]>; 1415 def VINSBVRX : 1416 VXForm_VTB5_RA5_ins<271, "vinsbvrx", 1417 [(set v16i8:$vD, 1418 (int_ppc_altivec_vinsbvrx v16i8:$vDi, i32:$rA, 1419 v16i8:$vB))]>; 1420 def VINSHVLX : 1421 VXForm_VTB5_RA5_ins<79, "vinshvlx", 1422 [(set v8i16:$vD, 1423 (int_ppc_altivec_vinshvlx v8i16:$vDi, i32:$rA, 1424 v8i16:$vB))]>; 1425 def VINSHVRX : 1426 VXForm_VTB5_RA5_ins<335, "vinshvrx", 1427 [(set v8i16:$vD, 1428 (int_ppc_altivec_vinshvrx v8i16:$vDi, i32:$rA, 1429 v8i16:$vB))]>; 1430 def VINSWVLX : 1431 VXForm_VTB5_RA5_ins<143, "vinswvlx", 1432 [(set v4i32:$vD, 1433 (int_ppc_altivec_vinswvlx v4i32:$vDi, i32:$rA, 1434 v4i32:$vB))]>; 1435 def VINSWVRX : 1436 VXForm_VTB5_RA5_ins<399, "vinswvrx", 1437 [(set v4i32:$vD, 1438 (int_ppc_altivec_vinswvrx v4i32:$vDi, i32:$rA, 1439 v4i32:$vB))]>; 1440 def VINSBLX : 1441 VXForm_VRT5_RAB5_ins<527, "vinsblx", 1442 [(set v16i8:$vD, 1443 (int_ppc_altivec_vinsblx v16i8:$vDi, i32:$rA, 1444 i32:$rB))]>; 1445 def VINSBRX : 1446 VXForm_VRT5_RAB5_ins<783, "vinsbrx", 1447 [(set v16i8:$vD, 1448 (int_ppc_altivec_vinsbrx v16i8:$vDi, i32:$rA, 1449 i32:$rB))]>; 1450 def VINSHLX : 1451 VXForm_VRT5_RAB5_ins<591, "vinshlx", 1452 [(set v8i16:$vD, 1453 (int_ppc_altivec_vinshlx v8i16:$vDi, i32:$rA, 1454 i32:$rB))]>; 1455 def VINSHRX : 1456 VXForm_VRT5_RAB5_ins<847, "vinshrx", 1457 [(set v8i16:$vD, 1458 (int_ppc_altivec_vinshrx v8i16:$vDi, i32:$rA, 1459 i32:$rB))]>; 1460 def VINSWLX : 1461 VXForm_VRT5_RAB5_ins<655, "vinswlx", 1462 [(set v4i32:$vD, 1463 (int_ppc_altivec_vinswlx v4i32:$vDi, i32:$rA, 1464 i32:$rB))]>; 1465 def VINSWRX : 1466 VXForm_VRT5_RAB5_ins<911, "vinswrx", 1467 [(set v4i32:$vD, 1468 (int_ppc_altivec_vinswrx v4i32:$vDi, i32:$rA, 1469 i32:$rB))]>; 1470 def VINSDLX : 1471 VXForm_1<719, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB), 1472 "vinsdlx $vD, $rA, $rB", IIC_VecGeneral, 1473 [(set v2i64:$vD, 1474 (int_ppc_altivec_vinsdlx v2i64:$vDi, i64:$rA, i64:$rB))]>, 1475 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1476 def VINSDRX : 1477 VXForm_1<975, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB), 1478 "vinsdrx $vD, $rA, $rB", IIC_VecGeneral, 1479 [(set v2i64:$vD, 1480 (int_ppc_altivec_vinsdrx v2i64:$vDi, i64:$rA, i64:$rB))]>, 1481 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1482 def VEXTRACTBM : VXForm_RD5_XO5_RS5<1602, 8, (outs gprc:$rD), (ins vrrc:$vB), 1483 "vextractbm $rD, $vB", IIC_VecGeneral, 1484 [(set i32:$rD, 1485 (int_ppc_altivec_vextractbm v16i8:$vB))]>; 1486 def VEXTRACTHM : VXForm_RD5_XO5_RS5<1602, 9, (outs gprc:$rD), (ins vrrc:$vB), 1487 "vextracthm $rD, $vB", IIC_VecGeneral, 1488 [(set i32:$rD, 1489 (int_ppc_altivec_vextracthm v8i16:$vB))]>; 1490 def VEXTRACTWM : VXForm_RD5_XO5_RS5<1602, 10, (outs gprc:$rD), (ins vrrc:$vB), 1491 "vextractwm $rD, $vB", IIC_VecGeneral, 1492 [(set i32:$rD, 1493 (int_ppc_altivec_vextractwm v4i32:$vB))]>; 1494 def VEXTRACTDM : VXForm_RD5_XO5_RS5<1602, 11, (outs gprc:$rD), (ins vrrc:$vB), 1495 "vextractdm $rD, $vB", IIC_VecGeneral, 1496 [(set i32:$rD, 1497 (int_ppc_altivec_vextractdm v2i64:$vB))]>; 1498 def VEXTRACTQM : VXForm_RD5_XO5_RS5<1602, 12, (outs gprc:$rD), (ins vrrc:$vB), 1499 "vextractqm $rD, $vB", IIC_VecGeneral, 1500 [(set i32:$rD, 1501 (int_ppc_altivec_vextractqm v1i128:$vB))]>; 1502 def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$vD), (ins vrrc:$vB), 1503 "vexpandbm $vD, $vB", IIC_VecGeneral, 1504 [(set v16i8:$vD, (int_ppc_altivec_vexpandbm 1505 v16i8:$vB))]>; 1506 def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$vD), (ins vrrc:$vB), 1507 "vexpandhm $vD, $vB", IIC_VecGeneral, 1508 [(set v8i16:$vD, (int_ppc_altivec_vexpandhm 1509 v8i16:$vB))]>; 1510 def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$vD), (ins vrrc:$vB), 1511 "vexpandwm $vD, $vB", IIC_VecGeneral, 1512 [(set v4i32:$vD, (int_ppc_altivec_vexpandwm 1513 v4i32:$vB))]>; 1514 def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$vD), (ins vrrc:$vB), 1515 "vexpanddm $vD, $vB", IIC_VecGeneral, 1516 [(set v2i64:$vD, (int_ppc_altivec_vexpanddm 1517 v2i64:$vB))]>; 1518 def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$vD), (ins vrrc:$vB), 1519 "vexpandqm $vD, $vB", IIC_VecGeneral, 1520 [(set v1i128:$vD, (int_ppc_altivec_vexpandqm 1521 v1i128:$vB))]>; 1522 def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$vD), (ins g8rc:$rB), 1523 "mtvsrbm $vD, $rB", IIC_VecGeneral, 1524 [(set v16i8:$vD, 1525 (int_ppc_altivec_mtvsrbm i64:$rB))]>; 1526 def MTVSRHM : VXForm_RD5_XO5_RS5<1602, 17, (outs vrrc:$vD), (ins g8rc:$rB), 1527 "mtvsrhm $vD, $rB", IIC_VecGeneral, 1528 [(set v8i16:$vD, 1529 (int_ppc_altivec_mtvsrhm i64:$rB))]>; 1530 def MTVSRWM : VXForm_RD5_XO5_RS5<1602, 18, (outs vrrc:$vD), (ins g8rc:$rB), 1531 "mtvsrwm $vD, $rB", IIC_VecGeneral, 1532 [(set v4i32:$vD, 1533 (int_ppc_altivec_mtvsrwm i64:$rB))]>; 1534 def MTVSRDM : VXForm_RD5_XO5_RS5<1602, 19, (outs vrrc:$vD), (ins g8rc:$rB), 1535 "mtvsrdm $vD, $rB", IIC_VecGeneral, 1536 [(set v2i64:$vD, 1537 (int_ppc_altivec_mtvsrdm i64:$rB))]>; 1538 def MTVSRQM : VXForm_RD5_XO5_RS5<1602, 20, (outs vrrc:$vD), (ins g8rc:$rB), 1539 "mtvsrqm $vD, $rB", IIC_VecGeneral, 1540 [(set v1i128:$vD, 1541 (int_ppc_altivec_mtvsrqm i64:$rB))]>; 1542 def MTVSRBMI : DXForm<4, 10, (outs vrrc:$vD), (ins u16imm64:$D), 1543 "mtvsrbmi $vD, $D", IIC_VecGeneral, 1544 [(set v16i8:$vD, 1545 (int_ppc_altivec_mtvsrbm imm:$D))]>; 1546 def VCNTMBB : VXForm_RD5_MP_VB5<1602, 12, (outs g8rc:$rD), 1547 (ins vrrc:$vB, u1imm:$MP), 1548 "vcntmbb $rD, $vB, $MP", IIC_VecGeneral, 1549 [(set i64:$rD, (int_ppc_altivec_vcntmbb 1550 v16i8:$vB, timm:$MP))]>; 1551 def VCNTMBH : VXForm_RD5_MP_VB5<1602, 13, (outs g8rc:$rD), 1552 (ins vrrc:$vB, u1imm:$MP), 1553 "vcntmbh $rD, $vB, $MP", IIC_VecGeneral, 1554 [(set i64:$rD, (int_ppc_altivec_vcntmbh 1555 v8i16:$vB, timm:$MP))]>; 1556 def VCNTMBW : VXForm_RD5_MP_VB5<1602, 14, (outs g8rc:$rD), 1557 (ins vrrc:$vB, u1imm:$MP), 1558 "vcntmbw $rD, $vB, $MP", IIC_VecGeneral, 1559 [(set i64:$rD, (int_ppc_altivec_vcntmbw 1560 v4i32:$vB, timm:$MP))]>; 1561 def VCNTMBD : VXForm_RD5_MP_VB5<1602, 15, (outs g8rc:$rD), 1562 (ins vrrc:$vB, u1imm:$MP), 1563 "vcntmbd $rD, $vB, $MP", IIC_VecGeneral, 1564 [(set i64:$rD, (int_ppc_altivec_vcntmbd 1565 v2i64:$vB, timm:$MP))]>; 1566 def VEXTDUBVLX : VAForm_1a<24, (outs vrrc:$vD), 1567 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 1568 "vextdubvlx $vD, $vA, $vB, $rC", 1569 IIC_VecGeneral, 1570 [(set v2i64:$vD, 1571 (int_ppc_altivec_vextdubvlx v16i8:$vA, 1572 v16i8:$vB, 1573 i32:$rC))]>; 1574 def VEXTDUBVRX : VAForm_1a<25, (outs vrrc:$vD), 1575 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 1576 "vextdubvrx $vD, $vA, $vB, $rC", 1577 IIC_VecGeneral, 1578 [(set v2i64:$vD, 1579 (int_ppc_altivec_vextdubvrx v16i8:$vA, 1580 v16i8:$vB, 1581 i32:$rC))]>; 1582 def VEXTDUHVLX : VAForm_1a<26, (outs vrrc:$vD), 1583 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 1584 "vextduhvlx $vD, $vA, $vB, $rC", 1585 IIC_VecGeneral, 1586 [(set v2i64:$vD, 1587 (int_ppc_altivec_vextduhvlx v8i16:$vA, 1588 v8i16:$vB, 1589 i32:$rC))]>; 1590 def VEXTDUHVRX : VAForm_1a<27, (outs vrrc:$vD), 1591 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 1592 "vextduhvrx $vD, $vA, $vB, $rC", 1593 IIC_VecGeneral, 1594 [(set v2i64:$vD, 1595 (int_ppc_altivec_vextduhvrx v8i16:$vA, 1596 v8i16:$vB, 1597 i32:$rC))]>; 1598 def VEXTDUWVLX : VAForm_1a<28, (outs vrrc:$vD), 1599 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 1600 "vextduwvlx $vD, $vA, $vB, $rC", 1601 IIC_VecGeneral, 1602 [(set v2i64:$vD, 1603 (int_ppc_altivec_vextduwvlx v4i32:$vA, 1604 v4i32:$vB, 1605 i32:$rC))]>; 1606 def VEXTDUWVRX : VAForm_1a<29, (outs vrrc:$vD), 1607 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 1608 "vextduwvrx $vD, $vA, $vB, $rC", 1609 IIC_VecGeneral, 1610 [(set v2i64:$vD, 1611 (int_ppc_altivec_vextduwvrx v4i32:$vA, 1612 v4i32:$vB, 1613 i32:$rC))]>; 1614 def VEXTDDVLX : VAForm_1a<30, (outs vrrc:$vD), 1615 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 1616 "vextddvlx $vD, $vA, $vB, $rC", 1617 IIC_VecGeneral, 1618 [(set v2i64:$vD, 1619 (int_ppc_altivec_vextddvlx v2i64:$vA, 1620 v2i64:$vB, 1621 i32:$rC))]>; 1622 def VEXTDDVRX : VAForm_1a<31, (outs vrrc:$vD), 1623 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 1624 "vextddvrx $vD, $vA, $vB, $rC", 1625 IIC_VecGeneral, 1626 [(set v2i64:$vD, 1627 (int_ppc_altivec_vextddvrx v2i64:$vA, 1628 v2i64:$vB, 1629 i32:$rC))]>; 1630 def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1631 "vpdepd $vD, $vA, $vB", IIC_VecGeneral, 1632 [(set v2i64:$vD, 1633 (int_ppc_altivec_vpdepd v2i64:$vA, v2i64:$vB))]>; 1634 def VPEXTD : VXForm_1<1421, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1635 "vpextd $vD, $vA, $vB", IIC_VecGeneral, 1636 [(set v2i64:$vD, 1637 (int_ppc_altivec_vpextd v2i64:$vA, v2i64:$vB))]>; 1638 def PDEPD : XForm_6<31, 156, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 1639 "pdepd $rA, $rS, $rB", IIC_IntGeneral, 1640 [(set i64:$rA, (int_ppc_pdepd i64:$rS, i64:$rB))]>; 1641 def PEXTD : XForm_6<31, 188, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 1642 "pextd $rA, $rS, $rB", IIC_IntGeneral, 1643 [(set i64:$rA, (int_ppc_pextd i64:$rS, i64:$rB))]>; 1644 def VCFUGED : VXForm_1<1357, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1645 "vcfuged $vD, $vA, $vB", IIC_VecGeneral, 1646 [(set v2i64:$vD, 1647 (int_ppc_altivec_vcfuged v2i64:$vA, v2i64:$vB))]>; 1648 def VGNB : VXForm_RD5_N3_VB5<1228, (outs g8rc:$rD), (ins vrrc:$vB, u3imm:$N), 1649 "vgnb $rD, $vB, $N", IIC_VecGeneral, 1650 [(set i64:$rD, 1651 (int_ppc_altivec_vgnb v1i128:$vB, timm:$N))]>; 1652 def CFUGED : XForm_6<31, 220, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 1653 "cfuged $rA, $rS, $rB", IIC_IntGeneral, 1654 [(set i64:$rA, (int_ppc_cfuged i64:$rS, i64:$rB))]>; 1655 def XXEVAL : 1656 8RR_XX4Form_IMM8_XTAB6<34, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1657 vsrc:$XC, u8imm:$IMM), 1658 "xxeval $XT, $XA, $XB, $XC, $IMM", IIC_VecGeneral, 1659 [(set v2i64:$XT, (int_ppc_vsx_xxeval v2i64:$XA, 1660 v2i64:$XB, v2i64:$XC, timm:$IMM))]>; 1661 def VCLZDM : VXForm_1<1924, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1662 "vclzdm $vD, $vA, $vB", IIC_VecGeneral, 1663 [(set v2i64:$vD, 1664 (int_ppc_altivec_vclzdm v2i64:$vA, v2i64:$vB))]>; 1665 def VCTZDM : VXForm_1<1988, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1666 "vctzdm $vD, $vA, $vB", IIC_VecGeneral, 1667 [(set v2i64:$vD, 1668 (int_ppc_altivec_vctzdm v2i64:$vA, v2i64:$vB))]>; 1669 def CNTLZDM : XForm_6<31, 59, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 1670 "cntlzdm $rA, $rS, $rB", IIC_IntGeneral, 1671 [(set i64:$rA, 1672 (int_ppc_cntlzdm i64:$rS, i64:$rB))]>; 1673 def CNTTZDM : XForm_6<31, 571, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 1674 "cnttzdm $rA, $rS, $rB", IIC_IntGeneral, 1675 [(set i64:$rA, 1676 (int_ppc_cnttzdm i64:$rS, i64:$rB))]>; 1677 def XXGENPCVBM : 1678 XForm_XT6_IMM5_VB5<60, 916, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 1679 "xxgenpcvbm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 1680 def XXGENPCVHM : 1681 XForm_XT6_IMM5_VB5<60, 917, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 1682 "xxgenpcvhm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 1683 def XXGENPCVWM : 1684 XForm_XT6_IMM5_VB5<60, 948, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 1685 "xxgenpcvwm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 1686 def XXGENPCVDM : 1687 XForm_XT6_IMM5_VB5<60, 949, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 1688 "xxgenpcvdm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 1689 def VCLRLB : VXForm_1<397, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB), 1690 "vclrlb $vD, $vA, $rB", IIC_VecGeneral, 1691 [(set v16i8:$vD, 1692 (int_ppc_altivec_vclrlb v16i8:$vA, i32:$rB))]>; 1693 def VCLRRB : VXForm_1<461, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB), 1694 "vclrrb $vD, $vA, $rB", IIC_VecGeneral, 1695 [(set v16i8:$vD, 1696 (int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>; 1697 def VMULLD : VXForm_1<457, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1698 "vmulld $vD, $vA, $vB", IIC_VecGeneral, 1699 [(set v2i64:$vD, (mul v2i64:$vA, v2i64:$vB))]>; 1700 def VMULHSW : VXForm_1<905, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1701 "vmulhsw $vD, $vA, $vB", IIC_VecGeneral, 1702 [(set v4i32:$vD, (mulhs v4i32:$vA, v4i32:$vB))]>; 1703 def VMULHUW : VXForm_1<649, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1704 "vmulhuw $vD, $vA, $vB", IIC_VecGeneral, 1705 [(set v4i32:$vD, (mulhu v4i32:$vA, v4i32:$vB))]>; 1706 def VMULHSD : VXForm_1<969, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1707 "vmulhsd $vD, $vA, $vB", IIC_VecGeneral, 1708 [(set v2i64:$vD, (mulhs v2i64:$vA, v2i64:$vB))]>; 1709 def VMULHUD : VXForm_1<713, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1710 "vmulhud $vD, $vA, $vB", IIC_VecGeneral, 1711 [(set v2i64:$vD, (mulhu v2i64:$vA, v2i64:$vB))]>; 1712 def VMODSW : VXForm_1<1931, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1713 "vmodsw $vD, $vA, $vB", IIC_VecGeneral, 1714 [(set v4i32:$vD, (srem v4i32:$vA, v4i32:$vB))]>; 1715 def VMODUW : VXForm_1<1675, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1716 "vmoduw $vD, $vA, $vB", IIC_VecGeneral, 1717 [(set v4i32:$vD, (urem v4i32:$vA, v4i32:$vB))]>; 1718 def VMODSD : VXForm_1<1995, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1719 "vmodsd $vD, $vA, $vB", IIC_VecGeneral, 1720 [(set v2i64:$vD, (srem v2i64:$vA, v2i64:$vB))]>; 1721 def VMODUD : VXForm_1<1739, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1722 "vmodud $vD, $vA, $vB", IIC_VecGeneral, 1723 [(set v2i64:$vD, (urem v2i64:$vA, v2i64:$vB))]>; 1724 def VDIVSW : VXForm_1<395, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1725 "vdivsw $vD, $vA, $vB", IIC_VecGeneral, 1726 [(set v4i32:$vD, (sdiv v4i32:$vA, v4i32:$vB))]>; 1727 def VDIVUW : VXForm_1<139, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1728 "vdivuw $vD, $vA, $vB", IIC_VecGeneral, 1729 [(set v4i32:$vD, (udiv v4i32:$vA, v4i32:$vB))]>; 1730 def VDIVSD : VXForm_1<459, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1731 "vdivsd $vD, $vA, $vB", IIC_VecGeneral, 1732 [(set v2i64:$vD, (sdiv v2i64:$vA, v2i64:$vB))]>; 1733 def VDIVUD : VXForm_1<203, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1734 "vdivud $vD, $vA, $vB", IIC_VecGeneral, 1735 [(set v2i64:$vD, (udiv v2i64:$vA, v2i64:$vB))]>; 1736 def VDIVESW : VXForm_1<907, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1737 "vdivesw $vD, $vA, $vB", IIC_VecGeneral, 1738 [(set v4i32:$vD, (int_ppc_altivec_vdivesw v4i32:$vA, 1739 v4i32:$vB))]>; 1740 def VDIVEUW : VXForm_1<651, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1741 "vdiveuw $vD, $vA, $vB", IIC_VecGeneral, 1742 [(set v4i32:$vD, (int_ppc_altivec_vdiveuw v4i32:$vA, 1743 v4i32:$vB))]>; 1744 def VDIVESD : VXForm_1<971, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1745 "vdivesd $vD, $vA, $vB", IIC_VecGeneral, 1746 [(set v2i64:$vD, (int_ppc_altivec_vdivesd v2i64:$vA, 1747 v2i64:$vB))]>; 1748 def VDIVEUD : VXForm_1<715, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1749 "vdiveud $vD, $vA, $vB", IIC_VecGeneral, 1750 [(set v2i64:$vD, (int_ppc_altivec_vdiveud v2i64:$vA, 1751 v2i64:$vB))]>; 1752 def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB), 1753 "xvtlsbb $BF, $XB", IIC_VecGeneral, []>; 1754 1755 // The XFormMemOp flag for the following 8 instructions is set on 1756 // the instruction format. 1757 let mayLoad = 1, mayStore = 0 in { 1758 def LXVRBX : X_XT6_RA5_RB5<31, 13, "lxvrbx", vsrc, []>; 1759 def LXVRHX : X_XT6_RA5_RB5<31, 45, "lxvrhx", vsrc, []>; 1760 def LXVRWX : X_XT6_RA5_RB5<31, 77, "lxvrwx", vsrc, []>; 1761 def LXVRDX : X_XT6_RA5_RB5<31, 109, "lxvrdx", vsrc, []>; 1762 } 1763 1764 let mayLoad = 0, mayStore = 1 in { 1765 def STXVRBX : X_XS6_RA5_RB5<31, 141, "stxvrbx", vsrc, []>; 1766 def STXVRHX : X_XS6_RA5_RB5<31, 173, "stxvrhx", vsrc, []>; 1767 def STXVRWX : X_XS6_RA5_RB5<31, 205, "stxvrwx", vsrc, []>; 1768 def STXVRDX : X_XS6_RA5_RB5<31, 237, "stxvrdx", vsrc, []>; 1769 } 1770 1771 def VMULESD : VXForm_1<968, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1772 "vmulesd $vD, $vA, $vB", IIC_VecGeneral, 1773 [(set v1i128:$vD, (int_ppc_altivec_vmulesd v2i64:$vA, 1774 v2i64:$vB))]>; 1775 def VMULEUD : VXForm_1<712, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1776 "vmuleud $vD, $vA, $vB", IIC_VecGeneral, 1777 [(set v1i128:$vD, (int_ppc_altivec_vmuleud v2i64:$vA, 1778 v2i64:$vB))]>; 1779 def VMULOSD : VXForm_1<456, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1780 "vmulosd $vD, $vA, $vB", IIC_VecGeneral, 1781 [(set v1i128:$vD, (int_ppc_altivec_vmulosd v2i64:$vA, 1782 v2i64:$vB))]>; 1783 def VMULOUD : VXForm_1<200, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1784 "vmuloud $vD, $vA, $vB", IIC_VecGeneral, 1785 [(set v1i128:$vD, (int_ppc_altivec_vmuloud v2i64:$vA, 1786 v2i64:$vB))]>; 1787 def VMSUMCUD : VAForm_1a<23, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 1788 "vmsumcud $vD, $vA, $vB, $vC", IIC_VecGeneral, 1789 [(set v1i128:$vD, (int_ppc_altivec_vmsumcud 1790 v2i64:$vA, v2i64:$vB, v1i128:$vC))]>; 1791 def VDIVSQ : VXForm_1<267, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1792 "vdivsq $vD, $vA, $vB", IIC_VecGeneral, 1793 [(set v1i128:$vD, (sdiv v1i128:$vA, v1i128:$vB))]>; 1794 def VDIVUQ : VXForm_1<11, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1795 "vdivuq $vD, $vA, $vB", IIC_VecGeneral, 1796 [(set v1i128:$vD, (udiv v1i128:$vA, v1i128:$vB))]>; 1797 def VDIVESQ : VXForm_1<779, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1798 "vdivesq $vD, $vA, $vB", IIC_VecGeneral, 1799 [(set v1i128:$vD, (int_ppc_altivec_vdivesq v1i128:$vA, 1800 v1i128:$vB))]>; 1801 def VDIVEUQ : VXForm_1<523, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1802 "vdiveuq $vD, $vA, $vB", IIC_VecGeneral, 1803 [(set v1i128:$vD, (int_ppc_altivec_vdiveuq v1i128:$vA, 1804 v1i128:$vB))]>; 1805 def VCMPEQUQ : VCMP <455, "vcmpequq $vD, $vA, $vB" , v1i128>; 1806 def VCMPGTSQ : VCMP <903, "vcmpgtsq $vD, $vA, $vB" , v1i128>; 1807 def VCMPGTUQ : VCMP <647, "vcmpgtuq $vD, $vA, $vB" , v1i128>; 1808 def VCMPEQUQ_rec : VCMP_rec <455, "vcmpequq. $vD, $vA, $vB" , v1i128>; 1809 def VCMPGTSQ_rec : VCMP_rec <903, "vcmpgtsq. $vD, $vA, $vB" , v1i128>; 1810 def VCMPGTUQ_rec : VCMP_rec <647, "vcmpgtuq. $vD, $vA, $vB" , v1i128>; 1811 def VMODSQ : VXForm_1<1803, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1812 "vmodsq $vD, $vA, $vB", IIC_VecGeneral, 1813 [(set v1i128:$vD, (srem v1i128:$vA, v1i128:$vB))]>; 1814 def VMODUQ : VXForm_1<1547, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1815 "vmoduq $vD, $vA, $vB", IIC_VecGeneral, 1816 [(set v1i128:$vD, (urem v1i128:$vA, v1i128:$vB))]>; 1817 def VEXTSD2Q : VXForm_RD5_XO5_RS5<1538, 27, (outs vrrc:$vD), (ins vrrc:$vB), 1818 "vextsd2q $vD, $vB", IIC_VecGeneral, 1819 [(set v1i128:$vD, (int_ppc_altivec_vextsd2q v2i64:$vB))]>; 1820 def VCMPUQ : VXForm_BF3_VAB5<257, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB), 1821 "vcmpuq $BF, $vA, $vB", IIC_VecGeneral, []>; 1822 def VCMPSQ : VXForm_BF3_VAB5<321, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB), 1823 "vcmpsq $BF, $vA, $vB", IIC_VecGeneral, []>; 1824 def VRLQNM : VX1_VT5_VA5_VB5<325, "vrlqnm", 1825 [(set v1i128:$vD, 1826 (int_ppc_altivec_vrlqnm v1i128:$vA, 1827 v1i128:$vB))]>; 1828 def VRLQMI : VXForm_1<69, (outs vrrc:$vD), 1829 (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), 1830 "vrlqmi $vD, $vA, $vB", IIC_VecFP, 1831 [(set v1i128:$vD, 1832 (int_ppc_altivec_vrlqmi v1i128:$vA, v1i128:$vB, 1833 v1i128:$vDi))]>, 1834 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1835 def VSLQ : VX1_VT5_VA5_VB5<261, "vslq", []>; 1836 def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>; 1837 def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>; 1838 def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>; 1839 def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>; 1840 def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>; 1841 def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>; 1842 def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>; 1843 def LXVKQ : XForm_XT6_IMM5<60, 31, 360, (outs vsrc:$XT), (ins u5imm:$UIM), 1844 "lxvkq $XT, $UIM", IIC_VecGeneral, []>; 1845} 1846 1847let Predicates = [IsISA3_1, HasVSX] in { 1848 def XVCVSPBF16 : XX2_XT6_XO5_XB6<60, 17, 475, "xvcvspbf16", vsrc, []>; 1849 def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>; 1850 def XSMAXCQP : X_VT5_VA5_VB5<63, 676, "xsmaxcqp", 1851 [(set f128:$vT, (PPCxsmaxc f128:$vA, f128:$vB))]>; 1852 def XSMINCQP : X_VT5_VA5_VB5<63, 740, "xsmincqp", 1853 [(set f128:$vT, (PPCxsminc f128:$vA, f128:$vB))]>; 1854} 1855 1856// Multiclass defining patterns for Set Boolean Extension Reverse Instructions. 1857// This is analogous to the CRNotPat multiclass but specifically for Power10 1858// and newer subtargets since the extended forms use Set Boolean instructions. 1859// The first two anonymous patterns defined are actually a duplicate of those 1860// in CRNotPat, but it is preferable to define both multiclasses as complete 1861// ones rather than pulling that small common section out. 1862multiclass P10ReverseSetBool<dag pattern, dag result> { 1863 def : Pat<pattern, (crnot result)>; 1864 def : Pat<(not pattern), result>; 1865 1866 def : Pat<(i32 (zext pattern)), 1867 (SETBCR result)>; 1868 def : Pat<(i64 (zext pattern)), 1869 (SETBCR8 result)>; 1870 1871 def : Pat<(i32 (sext pattern)), 1872 (SETNBCR result)>; 1873 def : Pat<(i64 (sext pattern)), 1874 (SETNBCR8 result)>; 1875 1876 def : Pat<(i32 (anyext pattern)), 1877 (SETBCR result)>; 1878 def : Pat<(i64 (anyext pattern)), 1879 (SETBCR8 result)>; 1880} 1881 1882multiclass IntSetP10RevSetBool<SDNode SetCC, ValueType Ty, PatLeaf ZExtTy, 1883 ImmLeaf SExtTy, I Cmpi, I Cmpli, 1884 I Cmp, I Cmpl> { 1885 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 1886 (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_lt)>; 1887 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 1888 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_lt)>; 1889 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 1890 (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_gt)>; 1891 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 1892 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_gt)>; 1893 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 1894 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_eq)>; 1895 1896 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETUGE)), 1897 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_lt)>; 1898 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETGE)), 1899 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_lt)>; 1900 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETULE)), 1901 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_gt)>; 1902 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETLE)), 1903 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_gt)>; 1904 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETNE)), 1905 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_eq)>; 1906 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETNE)), 1907 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_eq)>; 1908} 1909 1910multiclass FSetP10RevSetBool<SDNode SetCC, ValueType Ty, I FCmp> { 1911 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 1912 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 1913 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 1914 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 1915 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 1916 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 1917 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 1918 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 1919 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)), 1920 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 1921 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 1922 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 1923 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)), 1924 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 1925} 1926 1927let Predicates = [IsISA3_1] in { 1928 def : Pat<(i32 (zext i1:$in)), 1929 (SETBC $in)>; 1930 def : Pat<(i64 (zext i1:$in)), 1931 (SETBC8 $in)>; 1932 def : Pat<(i32 (sext i1:$in)), 1933 (SETNBC $in)>; 1934 def : Pat<(i64 (sext i1:$in)), 1935 (SETNBC8 $in)>; 1936 def : Pat<(i32 (anyext i1:$in)), 1937 (SETBC $in)>; 1938 def : Pat<(i64 (anyext i1:$in)), 1939 (SETBC8 $in)>; 1940 1941 // Instantiation of the set boolean reverse patterns for 32-bit integers. 1942 defm : IntSetP10RevSetBool<setcc, i32, immZExt16, imm32SExt16, 1943 CMPWI, CMPLWI, CMPW, CMPLW>; 1944 defm : P10ReverseSetBool<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 1945 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 1946 (LO16 imm:$imm)), sub_eq)>; 1947 1948 // Instantiation of the set boolean reverse patterns for 64-bit integers. 1949 defm : IntSetP10RevSetBool<setcc, i64, immZExt16, imm64SExt16, 1950 CMPDI, CMPLDI, CMPD, CMPLD>; 1951 defm : P10ReverseSetBool<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 1952 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 1953 (LO16 imm:$imm)), sub_eq)>; 1954} 1955 1956// Instantiation of the set boolean reverse patterns for f32, f64, f128. 1957let Predicates = [IsISA3_1, HasFPU] in { 1958 defm : FSetP10RevSetBool<setcc, f32, FCMPUS>; 1959 defm : FSetP10RevSetBool<setcc, f64, FCMPUD>; 1960 defm : FSetP10RevSetBool<setcc, f128, XSCMPUQP>; 1961} 1962 1963//---------------------------- Anonymous Patterns ----------------------------// 1964let Predicates = [IsISA3_1] in { 1965 // Exploit the vector multiply high instructions using intrinsics. 1966 def : Pat<(v4i32 (int_ppc_altivec_vmulhsw v4i32:$vA, v4i32:$vB)), 1967 (v4i32 (VMULHSW $vA, $vB))>; 1968 def : Pat<(v4i32 (int_ppc_altivec_vmulhuw v4i32:$vA, v4i32:$vB)), 1969 (v4i32 (VMULHUW $vA, $vB))>; 1970 def : Pat<(v2i64 (int_ppc_altivec_vmulhsd v2i64:$vA, v2i64:$vB)), 1971 (v2i64 (VMULHSD $vA, $vB))>; 1972 def : Pat<(v2i64 (int_ppc_altivec_vmulhud v2i64:$vA, v2i64:$vB)), 1973 (v2i64 (VMULHUD $vA, $vB))>; 1974 def : Pat<(v16i8 (int_ppc_vsx_xxgenpcvbm v16i8:$VRB, imm:$IMM)), 1975 (v16i8 (COPY_TO_REGCLASS (XXGENPCVBM $VRB, imm:$IMM), VRRC))>; 1976 def : Pat<(v8i16 (int_ppc_vsx_xxgenpcvhm v8i16:$VRB, imm:$IMM)), 1977 (v8i16 (COPY_TO_REGCLASS (XXGENPCVHM $VRB, imm:$IMM), VRRC))>; 1978 def : Pat<(v4i32 (int_ppc_vsx_xxgenpcvwm v4i32:$VRB, imm:$IMM)), 1979 (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>; 1980 def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)), 1981 (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>; 1982 def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 1)), 1983 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>; 1984 def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)), 1985 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>; 1986 1987 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 8)), 1988 (v1i128 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VRRC))>; 1989 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 16)), 1990 (v1i128 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VRRC))>; 1991 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 32)), 1992 (v1i128 (COPY_TO_REGCLASS (LXVRWX ForceXForm:$src), VRRC))>; 1993 def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 64)), 1994 (v1i128 (COPY_TO_REGCLASS (LXVRDX ForceXForm:$src), VRRC))>; 1995 1996 def : Pat<(v1i128 (rotl v1i128:$vA, v1i128:$vB)), 1997 (v1i128 (VRLQ v1i128:$vA, v1i128:$vB))>; 1998 1999 def : Pat <(v2i64 (PPCxxsplti32dx v2i64:$XT, i32:$XI, i32:$IMM32)), 2000 (v2i64 (XXSPLTI32DX v2i64:$XT, i32:$XI, i32:$IMM32))>; 2001} 2002 2003let Predicates = [IsISA3_1, HasVSX] in { 2004 def : Pat<(v16i8 (int_ppc_vsx_xvcvspbf16 v16i8:$XA)), 2005 (COPY_TO_REGCLASS (XVCVSPBF16 RCCp.AToVSRC), VRRC)>; 2006 def : Pat<(v16i8 (int_ppc_vsx_xvcvbf16spn v16i8:$XA)), 2007 (COPY_TO_REGCLASS (XVCVBF16SPN RCCp.AToVSRC), VRRC)>; 2008} 2009 2010let AddedComplexity = 400, Predicates = [IsISA3_1, IsLittleEndian] in { 2011 // Store element 0 of a VSX register to memory 2012 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$src, 0)), ForceXForm:$dst), 2013 (STXVRBX (COPY_TO_REGCLASS v16i8:$src, VSRC), ForceXForm:$dst)>; 2014 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$src, 0)), ForceXForm:$dst), 2015 (STXVRHX (COPY_TO_REGCLASS v8i16:$src, VSRC), ForceXForm:$dst)>; 2016 def : Pat<(store (i32 (extractelt v4i32:$src, 0)), ForceXForm:$dst), 2017 (STXVRWX $src, ForceXForm:$dst)>; 2018 def : Pat<(store (f32 (extractelt v4f32:$src, 0)), ForceXForm:$dst), 2019 (STXVRWX $src, ForceXForm:$dst)>; 2020 def : Pat<(store (i64 (extractelt v2i64:$src, 0)), ForceXForm:$dst), 2021 (STXVRDX $src, ForceXForm:$dst)>; 2022 def : Pat<(store (f64 (extractelt v2f64:$src, 0)), ForceXForm:$dst), 2023 (STXVRDX $src, ForceXForm:$dst)>; 2024 // Load element 0 of a VSX register to memory 2025 def : Pat<(v8i16 (scalar_to_vector (i32 (extloadi16 ForceXForm:$src)))), 2026 (v8i16 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VSRC))>; 2027 def : Pat<(v16i8 (scalar_to_vector (i32 (extloadi8 ForceXForm:$src)))), 2028 (v16i8 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VSRC))>; 2029 } 2030 2031// FIXME: The swap is overkill when the shift amount is a constant. 2032// We should just fix the constant in the DAG. 2033let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in { 2034 def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)), 2035 (v1i128 (VSLQ v1i128:$VRA, 2036 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2037 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2038 def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)), 2039 (v1i128 (VSLQ v1i128:$VRA, 2040 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2041 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2042 def : Pat<(v1i128 (srl v1i128:$VRA, v1i128:$VRB)), 2043 (v1i128 (VSRQ v1i128:$VRA, 2044 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2045 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2046 def : Pat<(v1i128 (PPCsrl v1i128:$VRA, v1i128:$VRB)), 2047 (v1i128 (VSRQ v1i128:$VRA, 2048 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2049 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2050 def : Pat<(v1i128 (sra v1i128:$VRA, v1i128:$VRB)), 2051 (v1i128 (VSRAQ v1i128:$VRA, 2052 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2053 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2054 def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)), 2055 (v1i128 (VSRAQ v1i128:$VRA, 2056 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2057 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2058} 2059 2060class xxevalPattern <dag pattern, bits<8> imm> : 2061 Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)> {} 2062 2063let AddedComplexity = 400, Predicates = [PrefixInstrs] in { 2064 def : Pat<(v4i32 (build_vector i32immNonAllOneNonZero:$A, 2065 i32immNonAllOneNonZero:$A, 2066 i32immNonAllOneNonZero:$A, 2067 i32immNonAllOneNonZero:$A)), 2068 (v4i32 (XXSPLTIW imm:$A))>; 2069 def : Pat<(f32 nzFPImmAsi32:$A), 2070 (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)), 2071 VSFRC)>; 2072 def : Pat<(f64 nzFPImmAsi32:$A), 2073 (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)), 2074 VSFRC)>; 2075 2076// To replace constant pool with XXSPLTI32DX for scalars. 2077def : Pat<(f32 nzFPImmAsi64:$A), 2078 (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX(IMPLICIT_DEF), 0, 2079 (getFPAs64BitIntHi $A)), 2080 1, (getFPAs64BitIntLo $A)), 2081 VSSRC)>; 2082 2083def : Pat<(f64 nzFPImmAsi64:$A), 2084 (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX (IMPLICIT_DEF), 0, 2085 (getFPAs64BitIntHi $A)), 2086 1, (getFPAs64BitIntLo $A)), 2087 VSFRC)>; 2088 2089 // Anonymous patterns for XXEVAL 2090 // AND 2091 // and(A, B, C) 2092 def : xxevalPattern<(and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 1>; 2093 // and(A, xor(B, C)) 2094 def : xxevalPattern<(and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 6>; 2095 // and(A, or(B, C)) 2096 def : xxevalPattern<(and v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 7>; 2097 // and(A, nor(B, C)) 2098 def : xxevalPattern<(and v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 8>; 2099 // and(A, eqv(B, C)) 2100 def : xxevalPattern<(and v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 9>; 2101 // and(A, nand(B, C)) 2102 def : xxevalPattern<(and v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 14>; 2103 2104 // NAND 2105 // nand(A, B, C) 2106 def : xxevalPattern<(vnot (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 2107 !sub(255, 1)>; 2108 // nand(A, xor(B, C)) 2109 def : xxevalPattern<(vnot (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), 2110 !sub(255, 6)>; 2111 // nand(A, or(B, C)) 2112 def : xxevalPattern<(vnot (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 2113 !sub(255, 7)>; 2114 // nand(A, nor(B, C)) 2115 def : xxevalPattern<(or (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)), 2116 !sub(255, 8)>; 2117 // nand(A, eqv(B, C)) 2118 def : xxevalPattern<(or (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)), 2119 !sub(255, 9)>; 2120 // nand(A, nand(B, C)) 2121 def : xxevalPattern<(or (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)), 2122 !sub(255, 14)>; 2123 2124 // Anonymous patterns to select prefixed VSX loads and stores. 2125 // Load / Store f128 2126 def : Pat<(f128 (load PDForm:$src)), 2127 (COPY_TO_REGCLASS (PLXV memri34:$src), VRRC)>; 2128 def : Pat<(store f128:$XS, PDForm:$dst), 2129 (PSTXV (COPY_TO_REGCLASS $XS, VSRC), memri34:$dst)>; 2130 2131 // Load / Store v4i32 2132 def : Pat<(v4i32 (load PDForm:$src)), (PLXV memri34:$src)>; 2133 def : Pat<(store v4i32:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>; 2134 2135 // Load / Store v2i64 2136 def : Pat<(v2i64 (load PDForm:$src)), (PLXV memri34:$src)>; 2137 def : Pat<(store v2i64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>; 2138 2139 // Load / Store v4f32 2140 def : Pat<(v4f32 (load PDForm:$src)), (PLXV memri34:$src)>; 2141 def : Pat<(store v4f32:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>; 2142 2143 // Load / Store v2f64 2144 def : Pat<(v2f64 (load PDForm:$src)), (PLXV memri34:$src)>; 2145 def : Pat<(store v2f64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>; 2146 2147 // Cases For PPCstore_scal_int_from_vsr 2148 def : Pat<(PPCstore_scal_int_from_vsr 2149 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), PDForm:$dst, 8), 2150 (PSTXSD (XSCVDPUXDS f64:$src), PDForm:$dst)>; 2151 def : Pat<(PPCstore_scal_int_from_vsr 2152 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), PDForm:$dst, 8), 2153 (PSTXSD (XSCVDPSXDS f64:$src), PDForm:$dst)>; 2154 def : Pat<(PPCstore_scal_int_from_vsr 2155 (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), PDForm:$dst, 8), 2156 (PSTXSD (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC), 2157 PDForm:$dst)>; 2158 def : Pat<(PPCstore_scal_int_from_vsr 2159 (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), PDForm:$dst, 8), 2160 (PSTXSD (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC), 2161 PDForm:$dst)>; 2162} 2163 2164let Predicates = [PrefixInstrs] in { 2165 def : Pat<(i32 imm34:$imm), (PLI (getImmAs64BitInt imm:$imm))>; 2166 def : Pat<(i64 imm34:$imm), (PLI8 (getImmAs64BitInt imm:$imm))>; 2167 def : Pat<(v16i8 (int_ppc_vsx_xxpermx v16i8:$A, v16i8:$B, v16i8:$C, timm:$D)), 2168 (COPY_TO_REGCLASS (XXPERMX (COPY_TO_REGCLASS $A, VSRC), 2169 (COPY_TO_REGCLASS $B, VSRC), 2170 (COPY_TO_REGCLASS $C, VSRC), $D), VSRC)>; 2171 def : Pat<(v16i8 (int_ppc_vsx_xxblendvb v16i8:$A, v16i8:$B, v16i8:$C)), 2172 (COPY_TO_REGCLASS 2173 (XXBLENDVB (COPY_TO_REGCLASS $A, VSRC), 2174 (COPY_TO_REGCLASS $B, VSRC), 2175 (COPY_TO_REGCLASS $C, VSRC)), VSRC)>; 2176 def : Pat<(v8i16 (int_ppc_vsx_xxblendvh v8i16:$A, v8i16:$B, v8i16:$C)), 2177 (COPY_TO_REGCLASS 2178 (XXBLENDVH (COPY_TO_REGCLASS $A, VSRC), 2179 (COPY_TO_REGCLASS $B, VSRC), 2180 (COPY_TO_REGCLASS $C, VSRC)), VSRC)>; 2181 def : Pat<(int_ppc_vsx_xxblendvw v4i32:$A, v4i32:$B, v4i32:$C), 2182 (XXBLENDVW $A, $B, $C)>; 2183 def : Pat<(int_ppc_vsx_xxblendvd v2i64:$A, v2i64:$B, v2i64:$C), 2184 (XXBLENDVD $A, $B, $C)>; 2185 2186 // Anonymous patterns to select prefixed loads and stores. 2187 // Load i32 2188 def : Pat<(i32 (extloadi1 PDForm:$src)), (PLBZ memri34:$src)>; 2189 def : Pat<(i32 (zextloadi1 PDForm:$src)), (PLBZ memri34:$src)>; 2190 def : Pat<(i32 (extloadi8 PDForm:$src)), (PLBZ memri34:$src)>; 2191 def : Pat<(i32 (zextloadi8 PDForm:$src)), (PLBZ memri34:$src)>; 2192 def : Pat<(i32 (extloadi16 PDForm:$src)), (PLHZ memri34:$src)>; 2193 def : Pat<(i32 (zextloadi16 PDForm:$src)), (PLHZ memri34:$src)>; 2194 def : Pat<(i32 (sextloadi16 PDForm:$src)), (PLHA memri34:$src)>; 2195 def : Pat<(i32 (load PDForm:$src)), (PLWZ memri34:$src)>; 2196 2197 // Store i32 2198 def : Pat<(truncstorei8 i32:$rS, PDForm:$dst), (PSTB gprc:$rS, memri34:$dst)>; 2199 def : Pat<(truncstorei16 i32:$rS, PDForm:$dst), (PSTH gprc:$rS, memri34:$dst)>; 2200 def : Pat<(store i32:$rS, PDForm:$dst), (PSTW gprc:$rS, memri34:$dst)>; 2201 2202 // Load i64 2203 def : Pat<(i64 (extloadi1 PDForm:$src)), (PLBZ8 memri34:$src)>; 2204 def : Pat<(i64 (zextloadi1 PDForm:$src)), (PLBZ8 memri34:$src)>; 2205 def : Pat<(i64 (extloadi8 PDForm:$src)), (PLBZ8 memri34:$src)>; 2206 def : Pat<(i64 (zextloadi8 PDForm:$src)), (PLBZ8 memri34:$src)>; 2207 def : Pat<(i64 (extloadi16 PDForm:$src)), (PLHZ8 memri34:$src)>; 2208 def : Pat<(i64 (zextloadi16 PDForm:$src)), (PLHZ8 memri34:$src)>; 2209 def : Pat<(i64 (sextloadi16 PDForm:$src)), (PLHA8 memri34:$src)>; 2210 def : Pat<(i64 (extloadi32 PDForm:$src)), (PLWZ8 memri34:$src)>; 2211 def : Pat<(i64 (zextloadi32 PDForm:$src)), (PLWZ8 memri34:$src)>; 2212 def : Pat<(i64 (sextloadi32 PDForm:$src)), (PLWA8 memri34:$src)>; 2213 def : Pat<(i64 (load PDForm:$src)), (PLD memri34:$src)>; 2214 2215 // Store i64 2216 def : Pat<(truncstorei8 i64:$rS, PDForm:$dst), (PSTB8 g8rc:$rS, memri34:$dst)>; 2217 def : Pat<(truncstorei16 i64:$rS, PDForm:$dst), (PSTH8 g8rc:$rS, memri34:$dst)>; 2218 def : Pat<(truncstorei32 i64:$rS, PDForm:$dst), (PSTW8 g8rc:$rS, memri34:$dst)>; 2219 def : Pat<(store i64:$rS, PDForm:$dst), (PSTD g8rc:$rS, memri34:$dst)>; 2220 2221 // Load / Store f32 2222 def : Pat<(f32 (load PDForm:$src)), (PLFS memri34:$src)>; 2223 def : Pat<(store f32:$FRS, PDForm:$dst), (PSTFS $FRS, memri34:$dst)>; 2224 2225 // Load / Store f64 2226 def : Pat<(f64 (extloadf32 PDForm:$src)), 2227 (COPY_TO_REGCLASS (PLFS memri34:$src), VSFRC)>; 2228 def : Pat<(f64 (load PDForm:$src)), (PLFD memri34:$src)>; 2229 def : Pat<(store f64:$FRS, PDForm:$dst), (PSTFD $FRS, memri34:$dst)>; 2230 2231 // Atomic Load 2232 def : Pat<(atomic_load_8 PDForm:$src), (PLBZ memri34:$src)>; 2233 def : Pat<(atomic_load_16 PDForm:$src), (PLHZ memri34:$src)>; 2234 def : Pat<(atomic_load_32 PDForm:$src), (PLWZ memri34:$src)>; 2235 def : Pat<(atomic_load_64 PDForm:$src), (PLD memri34:$src)>; 2236 2237 // Atomic Store 2238 def : Pat<(atomic_store_8 PDForm:$dst, i32:$RS), (PSTB $RS, memri34:$dst)>; 2239 def : Pat<(atomic_store_16 PDForm:$dst, i32:$RS), (PSTH $RS, memri34:$dst)>; 2240 def : Pat<(atomic_store_32 PDForm:$dst, i32:$RS), (PSTW $RS, memri34:$dst)>; 2241 def : Pat<(atomic_store_64 PDForm:$dst, i64:$RS), (PSTD $RS, memri34:$dst)>; 2242 2243 // Prefixed fpext to v2f64 2244 def : Pat<(v4f32 (PPCldvsxlh PDForm:$src)), 2245 (SUBREG_TO_REG (i64 1), (PLFD PDForm:$src), sub_64)>; 2246} 2247 2248def InsertEltShift { 2249 dag Sub32 = (i32 (EXTRACT_SUBREG $rB, sub_32)); 2250 dag Sub32Left1 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 1, 0, 30); 2251 dag Sub32Left2 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 2, 0, 29); 2252 dag Left1 = (RLWINM $rB, 1, 0, 30); 2253 dag Left2 = (RLWINM $rB, 2, 0, 29); 2254 dag Left3 = (RLWINM8 $rB, 3, 0, 28); 2255} 2256 2257let Predicates = [IsISA3_1, HasVSX, IsLittleEndian] in { 2258 // Indexed vector insert element 2259 def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i64:$rB)), 2260 (VINSBRX $vDi, InsertEltShift.Sub32, $rA)>; 2261 def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i64:$rB)), 2262 (VINSHRX $vDi, InsertEltShift.Sub32Left1, $rA)>; 2263 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i64:$rB)), 2264 (VINSWRX $vDi, InsertEltShift.Sub32Left2, $rA)>; 2265 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, i64:$rB)), 2266 (VINSDRX $vDi, InsertEltShift.Left3, $rA)>; 2267 2268 def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i64:$rB)), 2269 (VINSWVRX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>; 2270 2271 def : Pat<(v2f64 (insertelt v2f64:$vDi, f64:$A, i64:$rB)), 2272 (VINSDRX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>; 2273 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load DSForm:$rA)), i64:$rB)), 2274 (VINSDRX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>; 2275 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load PDForm:$rA)), i64:$rB)), 2276 (VINSDRX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>; 2277 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load XForm:$rA)), i64:$rB)), 2278 (VINSDRX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>; 2279 let AddedComplexity = 400 in { 2280 // Immediate vector insert element 2281 foreach Idx = [0, 1, 2, 3] in { 2282 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, Idx)), 2283 (VINSW $vDi, !mul(!sub(3, Idx), 4), $rA)>; 2284 } 2285 foreach i = [0, 1] in 2286 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, (i64 i))), 2287 (VINSD $vDi, !mul(!sub(1, i), 8), $rA)>; 2288 } 2289} 2290 2291let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC32] in { 2292 // Indexed vector insert element 2293 def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i32:$rB)), 2294 (VINSBLX $vDi, $rB, $rA)>; 2295 def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i32:$rB)), 2296 (VINSHLX $vDi, InsertEltShift.Left1, $rA)>; 2297 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i32:$rB)), 2298 (VINSWLX $vDi, InsertEltShift.Left2, $rA)>; 2299 2300 def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i32:$rB)), 2301 (VINSWVLX $vDi, InsertEltShift.Left2, (XSCVDPSPN $rA))>; 2302} 2303 2304let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC64] in { 2305 // Indexed vector insert element 2306 def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i64:$rB)), 2307 (VINSBLX $vDi, InsertEltShift.Sub32, $rA)>; 2308 def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i64:$rB)), 2309 (VINSHLX $vDi, InsertEltShift.Sub32Left1, $rA)>; 2310 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i64:$rB)), 2311 (VINSWLX $vDi, InsertEltShift.Sub32Left2, $rA)>; 2312 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, i64:$rB)), 2313 (VINSDLX $vDi, InsertEltShift.Left3, $rA)>; 2314 2315 def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i64:$rB)), 2316 (VINSWVLX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>; 2317 2318 def : Pat<(v2f64 (insertelt v2f64:$vDi, f64:$A, i64:$rB)), 2319 (VINSDLX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>; 2320 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load DSForm:$rA)), i64:$rB)), 2321 (VINSDLX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>; 2322 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load PDForm:$rA)), i64:$rB)), 2323 (VINSDLX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>; 2324 def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load XForm:$rA)), i64:$rB)), 2325 (VINSDLX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>; 2326} 2327 2328let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX, IsBigEndian] in { 2329 // Immediate vector insert element 2330 foreach Ty = [i32, i64] in { 2331 foreach Idx = [0, 1, 2, 3] in { 2332 def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, (Ty Idx))), 2333 (VINSW $vDi, !mul(Idx, 4), $rA)>; 2334 } 2335 } 2336 2337 foreach Idx = [0, 1] in 2338 def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, Idx)), 2339 (VINSD $vDi, !mul(Idx, 8), $rA)>; 2340} 2341