1//-------------------------- Predicate definitions ---------------------------//
2def IsPPC32 : Predicate<"!Subtarget->isPPC64()">;
3
4// Mask immediates for MMA instructions (2, 4 and 8 bits).
5def Msk2Imm : ImmLeaf<i32, [{ return isUInt<2>(Imm); }]>;
6def Msk4Imm : ImmLeaf<i32, [{ return isUInt<4>(Imm); }]>;
7def Msk8Imm : ImmLeaf<i32, [{ return isUInt<8>(Imm); }]>;
8
9//===----------------------------------------------------------------------===//
10// PowerPC ISA 3.1 specific type constraints.
11//
12
13def SDT_PPCSplat32 : SDTypeProfile<1, 3, [ SDTCisVT<0, v2i64>,
14  SDTCisVec<1>, SDTCisInt<2>, SDTCisInt<3>
15]>;
16def SDT_PPCAccBuild : SDTypeProfile<1, 4, [
17  SDTCisVT<0, v512i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>,
18                       SDTCisVT<3, v4i32>, SDTCisVT<4, v4i32>
19]>;
20def SDT_PPCPairBuild : SDTypeProfile<1, 2, [
21  SDTCisVT<0, v256i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>
22]>;
23def SDT_PPCAccExtractVsx : SDTypeProfile<1, 2, [
24  SDTCisVT<0, v4i32>, SDTCisVT<1, v512i1>, SDTCisPtrTy<2>
25]>;
26def SDT_PPCPairExtractVsx : SDTypeProfile<1, 2, [
27  SDTCisVT<0, v4i32>, SDTCisVT<1, v256i1>, SDTCisPtrTy<2>
28]>;
29def SDT_PPCxxmfacc : SDTypeProfile<1, 1, [
30  SDTCisVT<0, v512i1>, SDTCisVT<1, v512i1>
31]>;
32
33//===----------------------------------------------------------------------===//
34// ISA 3.1 specific PPCISD nodes.
35//
36
37def PPCxxsplti32dx : SDNode<"PPCISD::XXSPLTI32DX", SDT_PPCSplat32, []>;
38def PPCAccBuild : SDNode<"PPCISD::ACC_BUILD", SDT_PPCAccBuild, []>;
39def PPCPairBuild : SDNode<"PPCISD::PAIR_BUILD", SDT_PPCPairBuild, []>;
40def PPCAccExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCAccExtractVsx,
41                       []>;
42def PPCPairExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCPairExtractVsx,
43                        []>;
44def PPCxxmfacc : SDNode<"PPCISD::XXMFACC", SDT_PPCxxmfacc, []>;
45
46//===----------------------------------------------------------------------===//
47
48// PC Relative flag (for instructions that use the address of the prefix for
49// address computations).
50class isPCRel { bit PCRel = 1; }
51
52// PowerPC specific type constraints.
53def SDT_PPCLXVRZX : SDTypeProfile<1, 2, [
54  SDTCisVT<0, v1i128>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
55]>;
56
57// PPC Specific DAG Nodes.
58def PPClxvrzx : SDNode<"PPCISD::LXVRZX", SDT_PPCLXVRZX,
59                       [SDNPHasChain, SDNPMayLoad]>;
60
61// Top-level class for prefixed instructions.
62class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,
63         InstrItinClass itin> : Instruction {
64  field bits<64> Inst;
65  field bits<64> SoftFail = 0;
66  bit PCRel = 0; // Default value, set by isPCRel.
67  let Size = 8;
68
69  let Namespace = "PPC";
70  let OutOperandList = OOL;
71  let InOperandList = IOL;
72  let AsmString = asmstr;
73  let Itinerary = itin;
74  let Inst{0-5} = pref;
75  let Inst{32-37} = opcode;
76
77  bits<1> PPC970_First = 0;
78  bits<1> PPC970_Single = 0;
79  bits<1> PPC970_Cracked = 0;
80  bits<3> PPC970_Unit = 0;
81
82  /// These fields correspond to the fields in PPCInstrInfo.h.  Any changes to
83  /// these must be reflected there!  See comments there for what these are.
84  let TSFlags{0}   = PPC970_First;
85  let TSFlags{1}   = PPC970_Single;
86  let TSFlags{2}   = PPC970_Cracked;
87  let TSFlags{5-3} = PPC970_Unit;
88
89  bits<1> Prefixed = 1;  // This is a prefixed instruction.
90  let TSFlags{7}  = Prefixed;
91
92  // For cases where multiple instruction definitions really represent the
93  // same underlying instruction but with one definition for 64-bit arguments
94  // and one for 32-bit arguments, this bit breaks the degeneracy between
95  // the two forms and allows TableGen to generate mapping tables.
96  bit Interpretation64Bit = 0;
97
98  // Fields used for relation models.
99  string BaseName = "";
100}
101
102// VX-Form: [ PO VT R VB RC XO ]
103class VXForm_VTB5_RC<bits<10> xo, bits<5> R, dag OOL, dag IOL, string asmstr,
104                      InstrItinClass itin, list<dag> pattern>
105  : I<4, OOL, IOL, asmstr, itin> {
106  bits<5> VT;
107  bits<5> VB;
108  bit RC = 0;
109
110  let Pattern = pattern;
111
112  let Inst{6-10} = VT;
113  let Inst{11-15} = R;
114  let Inst{16-20} = VB;
115  let Inst{21} = RC;
116  let Inst{22-31} = xo;
117}
118
119// Multiclass definition to account for record and non-record form
120// instructions of VXRForm.
121multiclass VXForm_VTB5_RCr<bits<10> xo, bits<5> R, dag OOL, dag IOL,
122                            string asmbase, string asmstr,
123                            InstrItinClass itin, list<dag> pattern> {
124  let BaseName = asmbase in {
125    def NAME : VXForm_VTB5_RC<xo, R, OOL, IOL,
126                               !strconcat(asmbase, !strconcat(" ", asmstr)),
127                               itin, pattern>, RecFormRel;
128    let Defs = [CR6] in
129    def _rec : VXForm_VTB5_RC<xo, R, OOL, IOL,
130                               !strconcat(asmbase, !strconcat(". ", asmstr)),
131                               itin, []>, isRecordForm, RecFormRel;
132  }
133}
134
135class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
136                                InstrItinClass itin, list<dag> pattern>
137  : PI<1, opcode, OOL, IOL, asmstr, itin> {
138  bits<5> FRS;
139  bits<39> D_RA;
140
141  let Pattern = pattern;
142
143  // The prefix.
144  let Inst{6-7} = 2;
145  let Inst{8-10} = 0;
146  let Inst{11} = PCRel;
147  let Inst{12-13} = 0;
148  let Inst{14-31} = D_RA{33-16}; // d0
149
150  // The instruction.
151  let Inst{38-42} = FRS{4-0};
152  let Inst{43-47} = D_RA{38-34}; // RA
153  let Inst{48-63} = D_RA{15-0}; // d1
154}
155
156class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
157                            InstrItinClass itin, list<dag> pattern>
158  : PI<1, opcode, OOL, IOL, asmstr, itin> {
159  bits<5> RT;
160  bits<5> RA;
161  bits<34> SI;
162
163  let Pattern = pattern;
164
165  // The prefix.
166  let Inst{6-7} = 2;
167  let Inst{8-10} = 0;
168  let Inst{11} = PCRel;
169  let Inst{12-13} = 0;
170  let Inst{14-31} = SI{33-16};
171
172  // The instruction.
173  let Inst{38-42} = RT;
174  let Inst{43-47} = RA;
175  let Inst{48-63} = SI{15-0};
176}
177
178class MLS_DForm_SI34_RT5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
179                         InstrItinClass itin, list<dag> pattern>
180  : PI<1, opcode, OOL, IOL, asmstr, itin> {
181  bits<5> RT;
182  bits<34> SI;
183
184  let Pattern = pattern;
185
186  // The prefix.
187  let Inst{6-7} = 2;
188  let Inst{8-10} = 0;
189  let Inst{11} = 0;
190  let Inst{12-13} = 0;
191  let Inst{14-31} = SI{33-16};
192
193  // The instruction.
194  let Inst{38-42} = RT;
195  let Inst{43-47} = 0;
196  let Inst{48-63} = SI{15-0};
197}
198
199multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
200                                   dag PCRel_IOL, string asmstr,
201                                   InstrItinClass itin> {
202  def NAME : MLS_DForm_R_SI34_RTA5<opcode, OOL, IOL,
203                                   !strconcat(asmstr, ", 0"), itin, []>;
204  def pc : MLS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL,
205                                 !strconcat(asmstr, ", 1"), itin, []>, isPCRel;
206}
207
208class 8LS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
209                            InstrItinClass itin, list<dag> pattern>
210  : PI<1, opcode, OOL, IOL, asmstr, itin> {
211  bits<5> RT;
212  bits<39> D_RA;
213
214  let Pattern = pattern;
215
216  // The prefix.
217  let Inst{6-10} = 0;
218  let Inst{11} = PCRel;
219  let Inst{12-13} = 0;
220  let Inst{14-31} = D_RA{33-16}; // d0
221
222  // The instruction.
223  let Inst{38-42} = RT{4-0};
224  let Inst{43-47} = D_RA{38-34}; // RA
225  let Inst{48-63} = D_RA{15-0}; // d1
226}
227
228// 8LS:D-Form: [ 1 0 0 // R // d0
229//               PO TX T RA d1 ]
230class 8LS_DForm_R_SI34_XT6_RA5<bits<5> opcode, dag OOL, dag IOL, string asmstr,
231                               InstrItinClass itin, list<dag> pattern>
232  : PI<1, { opcode, ? }, OOL, IOL, asmstr, itin> {
233  bits<6> XT;
234  bits<39> D_RA;
235
236  let Pattern = pattern;
237
238  // The prefix.
239  let Inst{6-7} = 0;
240  let Inst{8} = 0;
241  let Inst{9-10} = 0; // reserved
242  let Inst{11} = PCRel;
243  let Inst{12-13} = 0; // reserved
244  let Inst{14-31} = D_RA{33-16}; // d0
245
246  // The instruction.
247  let Inst{37} = XT{5};
248  let Inst{38-42} = XT{4-0};
249  let Inst{43-47} = D_RA{38-34}; // RA
250  let Inst{48-63} = D_RA{15-0}; // d1
251}
252
253// X-Form: [PO T IMM VRB XO TX]
254class XForm_XT6_IMM5_VB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
255                         string asmstr, InstrItinClass itin, list<dag> pattern>
256  : I<opcode, OOL, IOL, asmstr, itin> {
257  bits<6> XT;
258  bits<5> VRB;
259  bits<5> IMM;
260
261  let Pattern = pattern;
262  let Inst{6-10} = XT{4-0};
263  let Inst{11-15} = IMM;
264  let Inst{16-20} = VRB;
265  let Inst{21-30} = xo;
266  let Inst{31} = XT{5};
267}
268
269class 8RR_XX4Form_IMM8_XTAB6<bits<6> opcode, bits<2> xo,
270                             dag OOL, dag IOL, string asmstr,
271                             InstrItinClass itin, list<dag> pattern>
272  : PI<1, opcode, OOL, IOL, asmstr, itin> {
273    bits<6> XT;
274    bits<6> XA;
275    bits<6> XB;
276    bits<6> XC;
277    bits<8> IMM;
278
279    let Pattern = pattern;
280
281    // The prefix.
282    let Inst{6-7} = 1;
283    let Inst{8} = 0;
284    let Inst{9-11} = 0;
285    let Inst{12-13} = 0;
286    let Inst{14-23} = 0;
287    let Inst{24-31} = IMM;
288
289    // The instruction.
290    let Inst{38-42} = XT{4-0};
291    let Inst{43-47} = XA{4-0};
292    let Inst{48-52} = XB{4-0};
293    let Inst{53-57} = XC{4-0};
294    let Inst{58-59} = xo;
295    let Inst{60} = XC{5};
296    let Inst{61} = XA{5};
297    let Inst{62} = XB{5};
298    let Inst{63} = XT{5};
299}
300
301class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
302                        InstrItinClass itin, list<dag> pattern>
303  : I<4, OOL, IOL, asmstr, itin> {
304  bits<5> RD;
305  bits<5> VB;
306  bits<3> N;
307
308  let Pattern = pattern;
309
310  let Inst{6-10}  = RD;
311  let Inst{11-12} = 0;
312  let Inst{13-15} = N;
313  let Inst{16-20} = VB;
314  let Inst{21-31} = xo;
315}
316
317
318// VX-Form: [PO VRT RA VRB XO].
319// Destructive (insert) forms are suffixed with _ins.
320class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern>
321  : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, gprc:$rA, vrrc:$vB),
322             !strconcat(opc, " $vD, $rA, $vB"), IIC_VecGeneral, pattern>,
323             RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
324
325// VX-Form: [PO VRT RA RB XO].
326// Destructive (insert) forms are suffixed with _ins.
327class VXForm_VRT5_RAB5_ins<bits<11> xo, string opc, list<dag> pattern>
328  : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, gprc:$rA, gprc:$rB),
329             !strconcat(opc, " $vD, $rA, $rB"), IIC_VecGeneral, pattern>,
330             RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
331
332// VX-Form: [ PO BF // VRA VRB XO ]
333class VXForm_BF3_VAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
334                      InstrItinClass itin, list<dag> pattern>
335  : I<4, OOL, IOL, asmstr, itin> {
336  bits<3> BF;
337  bits<5> VA;
338  bits<5> VB;
339
340  let Pattern = pattern;
341
342  let Inst{6-8} = BF;
343  let Inst{9-10} = 0;
344  let Inst{11-15} = VA;
345  let Inst{16-20} = VB;
346  let Inst{21-31} = xo;
347}
348
349// VN-Form: [PO VRT VRA VRB PS SD XO]
350// SD is "Shift Direction"
351class VNForm_VTAB5_SD3<bits<6> xo, bits<2> ps, dag OOL, dag IOL, string asmstr,
352                       InstrItinClass itin, list<dag> pattern>
353    : I<4, OOL, IOL, asmstr, itin> {
354  bits<5> VRT;
355  bits<5> VRA;
356  bits<5> VRB;
357  bits<3> SD;
358
359  let Pattern = pattern;
360
361  let Inst{6-10}  = VRT;
362  let Inst{11-15} = VRA;
363  let Inst{16-20} = VRB;
364  let Inst{21-22} = ps;
365  let Inst{23-25} = SD;
366  let Inst{26-31} = xo;
367}
368
369class VXForm_RD5_MP_VB5<bits<11> xo, bits<4> eo, dag OOL, dag IOL,
370                        string asmstr, InstrItinClass itin, list<dag> pattern>
371  : I<4, OOL, IOL, asmstr, itin> {
372  bits<5> RD;
373  bits<5> VB;
374  bit MP;
375
376  let Pattern = pattern;
377
378  let Inst{6-10}  = RD;
379  let Inst{11-14} = eo;
380  let Inst{15} = MP;
381  let Inst{16-20} = VB;
382  let Inst{21-31} = xo;
383}
384
385// 8RR:D-Form: [ 1 1 0 // // imm0
386//               PO T XO TX imm1 ].
387class 8RR_DForm_IMM32_XT6<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
388                          string asmstr, InstrItinClass itin,
389                          list<dag> pattern>
390  : PI<1, opcode, OOL, IOL, asmstr, itin> {
391  bits<6> XT;
392  bits<32> IMM32;
393
394  let Pattern = pattern;
395
396  // The prefix.
397  let Inst{6-7} = 1;
398  let Inst{8-11} = 0;
399  let Inst{12-13} = 0; // reserved
400  let Inst{14-15} = 0; // reserved
401  let Inst{16-31} = IMM32{31-16};
402
403  // The instruction.
404  let Inst{38-42} = XT{4-0};
405  let Inst{43-46} = xo;
406  let Inst{47} = XT{5};
407  let Inst{48-63} = IMM32{15-0};
408}
409
410// 8RR:D-Form: [ 1 1 0 // // imm0
411//               PO T XO IX TX imm1 ].
412class 8RR_DForm_IMM32_XT6_IX<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
413                             string asmstr, InstrItinClass itin,
414                             list<dag> pattern>
415  : PI<1, opcode, OOL, IOL, asmstr, itin> {
416  bits<6> XT;
417  bit IX;
418  bits<32> IMM32;
419
420  let Pattern = pattern;
421
422  // The prefix.
423  let Inst{6-7} = 1;
424  let Inst{8-11} = 0;
425  let Inst{12-13} = 0; // reserved
426  let Inst{14-15} = 0; // reserved
427  let Inst{16-31} = IMM32{31-16};
428
429  // The instruction.
430  let Inst{38-42} = XT{4-0};
431  let Inst{43-45} = xo;
432  let Inst{46} = IX;
433  let Inst{47} = XT{5};
434  let Inst{48-63} = IMM32{15-0};
435}
436
437class 8RR_XX4Form_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL,
438                         string asmstr, InstrItinClass itin, list<dag> pattern>
439  : PI<1, opcode, OOL, IOL, asmstr, itin> {
440  bits<6> XT;
441  bits<6> XA;
442  bits<6> XB;
443  bits<6> XC;
444
445  let Pattern = pattern;
446
447  // The prefix.
448  let Inst{6-7} = 1;
449  let Inst{8-11} = 0;
450  let Inst{12-13} = 0;
451  let Inst{14-31} = 0;
452
453  // The instruction.
454  let Inst{38-42} = XT{4-0};
455  let Inst{43-47} = XA{4-0};
456  let Inst{48-52} = XB{4-0};
457  let Inst{53-57} = XC{4-0};
458  let Inst{58-59} = xo;
459  let Inst{60} = XC{5};
460  let Inst{61} = XA{5};
461  let Inst{62} = XB{5};
462  let Inst{63} = XT{5};
463}
464
465class 8RR_XX4Form_IMM3_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL,
466                              string asmstr, InstrItinClass itin,
467                              list<dag> pattern>
468  : PI<1, opcode, OOL, IOL, asmstr, itin> {
469  bits<6> XT;
470  bits<6> XA;
471  bits<6> XB;
472  bits<6> XC;
473  bits<3> IMM;
474
475  let Pattern = pattern;
476
477  // The prefix.
478  let Inst{6-7} = 1;
479  let Inst{8-11} = 0;
480  let Inst{12-13} = 0;
481  let Inst{14-28} = 0;
482  let Inst{29-31} = IMM;
483
484  // The instruction.
485  let Inst{38-42} = XT{4-0};
486  let Inst{43-47} = XA{4-0};
487  let Inst{48-52} = XB{4-0};
488  let Inst{53-57} = XC{4-0};
489  let Inst{58-59} = xo;
490  let Inst{60} = XC{5};
491  let Inst{61} = XA{5};
492  let Inst{62} = XB{5};
493  let Inst{63} = XT{5};
494}
495
496// [PO BF / XO2 B XO BX /]
497class XX2_BF3_XO5_XB6_XO9<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL,
498                          dag IOL, string asmstr, InstrItinClass itin,
499                          list<dag> pattern>
500  : I<opcode, OOL, IOL, asmstr, itin> {
501  bits<3> BF;
502  bits<6> XB;
503
504  let Pattern = pattern;
505
506  let Inst{6-8}   = BF;
507  let Inst{9-10}  = 0;
508  let Inst{11-15} = xo2;
509  let Inst{16-20} = XB{4-0};
510  let Inst{21-29} = xo;
511  let Inst{30}    = XB{5};
512  let Inst{31}    = 0;
513}
514
515// X-Form: [ PO RT BI /// XO / ]
516class XForm_XT5_BI5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
517                    string asmstr, InstrItinClass itin, list<dag> pattern>
518  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
519  let B = 0;
520}
521
522multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
523                                       dag PCRel_IOL, string asmstr,
524                                       InstrItinClass itin> {
525  def NAME : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL,
526                                       !strconcat(asmstr, ", 0"), itin, []>;
527  def pc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL,
528                                     !strconcat(asmstr, ", 1"), itin, []>,
529                                     isPCRel;
530}
531
532multiclass 8LS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
533                                   dag PCRel_IOL, string asmstr,
534                                   InstrItinClass itin> {
535  def NAME : 8LS_DForm_R_SI34_RTA5<opcode, OOL, IOL,
536                                   !strconcat(asmstr, ", 0"), itin, []>;
537  def pc : 8LS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL,
538                                 !strconcat(asmstr, ", 1"), itin, []>, isPCRel;
539}
540
541multiclass 8LS_DForm_R_SI34_XT6_RA5_p<bits<5> opcode, dag OOL, dag IOL,
542                                      dag PCRel_IOL, string asmstr,
543                                      InstrItinClass itin> {
544  def NAME : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, IOL,
545                                      !strconcat(asmstr, ", 0"), itin, []>;
546  def pc : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, PCRel_IOL,
547                                    !strconcat(asmstr, ", 1"), itin, []>,
548                                    isPCRel;
549}
550
551def PPCRegVSRpRCAsmOperand : AsmOperandClass {
552  let Name = "RegVSRpRC"; let PredicateMethod = "isVSRpEvenRegNumber";
553}
554
555def vsrprc : RegisterOperand<VSRpRC> {
556  let ParserMatchClass = PPCRegVSRpRCAsmOperand;
557}
558
559def PPCRegVSRpEvenRCAsmOperand : AsmOperandClass {
560  let Name = "RegVSRpEvenRC"; let PredicateMethod = "isVSRpEvenRegNumber";
561}
562
563def vsrpevenrc : RegisterOperand<VSRpRC> {
564  let ParserMatchClass = PPCRegVSRpEvenRCAsmOperand;
565  let EncoderMethod = "getVSRpEvenEncoding";
566  let DecoderMethod = "decodeVSRpEvenOperands";
567}
568
569class DQForm_XTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
570                           string asmstr, InstrItinClass itin, list<dag> pattern>
571  : I<opcode, OOL, IOL, asmstr, itin> {
572  bits<5> XTp;
573  bits<17> DQ_RA;
574  let Pattern = pattern;
575
576  let Inst{6-9} = XTp{3-0};
577  let Inst{10} = XTp{4};
578  let Inst{11-15} = DQ_RA{16-12};  // Register #
579  let Inst{16-27} = DQ_RA{11-0};   // Displacement.
580  let Inst{28-31} = xo;
581}
582
583class XForm_XTp5_XAB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
584                      string asmstr, InstrItinClass itin, list<dag> pattern>
585  : I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp {
586  bits<5> XTp;
587  bits<5> A;
588  bits<5> B;
589
590  let Pattern = pattern;
591  let Inst{6-9} = XTp{3-0};
592  let Inst{10} = XTp{4};
593  let Inst{11-15} = A;
594  let Inst{16-20} = B;
595  let Inst{21-30} = xo;
596  let Inst{31} = 0;
597}
598
599class 8LS_DForm_R_XTp5_SI34_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
600                                InstrItinClass itin, list<dag> pattern>
601  : PI<1, opcode, OOL, IOL, asmstr, itin> {
602  bits<5> XTp;
603  bits<39> D_RA;
604
605  let Pattern = pattern;
606
607  // The prefix.
608  let Inst{6-10} = 0;
609  let Inst{11} = PCRel;
610  let Inst{12-13} = 0;
611  let Inst{14-31} = D_RA{33-16}; // Imm18
612
613  // The instruction.
614  let Inst{38-41} = XTp{3-0};
615  let Inst{42}    = XTp{4};
616  let Inst{43-47} = D_RA{38-34};   // Register #
617  let Inst{48-63} = D_RA{15-0};    // D
618}
619
620multiclass 8LS_DForm_R_XTp5_SI34_MEM_p<bits<6> opcode, dag OOL,
621                                       dag IOL, dag PCRel_IOL,
622                                       string asmstr, InstrItinClass itin> {
623  def NAME : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, IOL,
624                                       !strconcat(asmstr, ", 0"), itin, []>;
625  def pc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, PCRel_IOL,
626                                     !strconcat(asmstr, ", 1"), itin, []>,
627                                     isPCRel;
628}
629
630def PPCRegACCRCAsmOperand : AsmOperandClass {
631  let Name = "RegACCRC"; let PredicateMethod = "isACCRegNumber";
632}
633
634def acc : RegisterOperand<ACCRC> {
635  let ParserMatchClass = PPCRegACCRCAsmOperand;
636}
637
638def uacc : RegisterOperand<UACCRC> {
639  let ParserMatchClass = PPCRegACCRCAsmOperand;
640}
641
642// [PO AS XO2 XO]
643class XForm_AT3<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
644                    string asmstr, InstrItinClass itin, list<dag> pattern>
645  : I<opcode, OOL, IOL, asmstr, itin> {
646  bits<3> AT;
647
648  let Pattern = pattern;
649
650  let Inst{6-8}  = AT;
651  let Inst{9-10}  = 0;
652  let Inst{11-15} = xo2;
653  let Inst{16-20} = 0;
654  let Inst{21-30} = xo;
655  let Inst{31} = 0;
656}
657
658class XX3Form_AT3_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
659                           string asmstr, InstrItinClass itin,
660                           list<dag> pattern>
661  : I<opcode, OOL, IOL, asmstr, itin> {
662  bits<3> AT;
663  bits<6> XA;
664  bits<6> XB;
665
666  let Pattern = pattern;
667
668  let Inst{6-8} = AT;
669  let Inst{9-10} = 0;
670  let Inst{11-15} = XA{4-0};
671  let Inst{16-20} = XB{4-0};
672  let Inst{21-28} = xo;
673  let Inst{29}    = XA{5};
674  let Inst{30}    = XB{5};
675  let Inst{31} = 0;
676}
677
678class MMIRR_XX3Form_XY4P2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
679                               string asmstr, InstrItinClass itin,
680                               list<dag> pattern>
681  : PI<1, opcode, OOL, IOL, asmstr, itin> {
682  bits<3> AT;
683  bits<6> XA;
684  bits<6> XB;
685  bits<4> XMSK;
686  bits<4> YMSK;
687  bits<2> PMSK;
688
689  let Pattern = pattern;
690
691  // The prefix.
692  let Inst{6-7} = 3;
693  let Inst{8-11} = 9;
694  let Inst{12-15} = 0;
695  let Inst{16-17} = PMSK;
696  let Inst{18-23} = 0;
697  let Inst{24-27} = XMSK;
698  let Inst{28-31} = YMSK;
699
700  // The instruction.
701  let Inst{38-40} = AT;
702  let Inst{41-42} = 0;
703  let Inst{43-47} = XA{4-0};
704  let Inst{48-52} = XB{4-0};
705  let Inst{53-60} = xo;
706  let Inst{61} = XA{5};
707  let Inst{62} = XB{5};
708  let Inst{63} = 0;
709}
710
711class MMIRR_XX3Form_XY4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
712                             string asmstr, InstrItinClass itin,
713                             list<dag> pattern>
714  : PI<1, opcode, OOL, IOL, asmstr, itin> {
715  bits<3> AT;
716  bits<6> XA;
717  bits<6> XB;
718  bits<4> XMSK;
719  bits<4> YMSK;
720
721  let Pattern = pattern;
722
723  // The prefix.
724  let Inst{6-7} = 3;
725  let Inst{8-11} = 9;
726  let Inst{12-23} = 0;
727  let Inst{24-27} = XMSK;
728  let Inst{28-31} = YMSK;
729
730  // The instruction.
731  let Inst{38-40} = AT;
732  let Inst{41-42} = 0;
733  let Inst{43-47} = XA{4-0};
734  let Inst{48-52} = XB{4-0};
735  let Inst{53-60} = xo;
736  let Inst{61} = XA{5};
737  let Inst{62} = XB{5};
738  let Inst{63} = 0;
739}
740
741class MMIRR_XX3Form_X4Y2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
742                              string asmstr, InstrItinClass itin,
743                              list<dag> pattern>
744  : PI<1, opcode, OOL, IOL, asmstr, itin> {
745  bits<3> AT;
746  bits<6> XA;
747  bits<6> XB;
748  bits<4> XMSK;
749  bits<2> YMSK;
750
751  let Pattern = pattern;
752
753  // The prefix.
754  let Inst{6-7} = 3;
755  let Inst{8-11} = 9;
756  let Inst{12-23} = 0;
757  let Inst{24-27} = XMSK;
758  let Inst{28-29} = YMSK;
759  let Inst{30-31} = 0;
760
761  // The instruction.
762  let Inst{38-40} = AT;
763  let Inst{41-42} = 0;
764  let Inst{43-47} = XA{4-0};
765  let Inst{48-52} = XB{4-0};
766  let Inst{53-60} = xo;
767  let Inst{61} = XA{5};
768  let Inst{62} = XB{5};
769  let Inst{63} = 0;
770}
771
772class MMIRR_XX3Form_XY4P8_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
773                               string asmstr, InstrItinClass itin,
774                               list<dag> pattern>
775  : PI<1, opcode, OOL, IOL, asmstr, itin> {
776  bits<3> AT;
777  bits<6> XA;
778  bits<6> XB;
779  bits<4> XMSK;
780  bits<4> YMSK;
781  bits<8> PMSK;
782
783  let Pattern = pattern;
784
785  // The prefix.
786  let Inst{6-7} = 3;
787  let Inst{8-11} = 9;
788  let Inst{12-15} = 0;
789  let Inst{16-23} = PMSK;
790  let Inst{24-27} = XMSK;
791  let Inst{28-31} = YMSK;
792
793  // The instruction.
794  let Inst{38-40} = AT;
795  let Inst{41-42} = 0;
796  let Inst{43-47} = XA{4-0};
797  let Inst{48-52} = XB{4-0};
798  let Inst{53-60} = xo;
799  let Inst{61} = XA{5};
800  let Inst{62} = XB{5};
801  let Inst{63} = 0;
802}
803
804class MMIRR_XX3Form_XYP4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
805                              string asmstr, InstrItinClass itin,
806                              list<dag> pattern>
807  : PI<1, opcode, OOL, IOL, asmstr, itin> {
808  bits<3> AT;
809  bits<6> XA;
810  bits<6> XB;
811  bits<4> XMSK;
812  bits<4> YMSK;
813  bits<4> PMSK;
814
815  let Pattern = pattern;
816
817  // The prefix.
818  let Inst{6-7} = 3;
819  let Inst{8-11} = 9;
820  let Inst{12-15} = 0;
821  let Inst{16-19} = PMSK;
822  let Inst{20-23} = 0;
823  let Inst{24-27} = XMSK;
824  let Inst{28-31} = YMSK;
825
826  // The instruction.
827  let Inst{38-40} = AT;
828  let Inst{41-42} = 0;
829  let Inst{43-47} = XA{4-0};
830  let Inst{48-52} = XB{4-0};
831  let Inst{53-60} = xo;
832  let Inst{61} = XA{5};
833  let Inst{62} = XB{5};
834  let Inst{63} = 0;
835}
836
837def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
838def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
839def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">;
840def MMA : Predicate<"Subtarget->hasMMA()">;
841
842def RCCp {
843  dag AToVSRC = (COPY_TO_REGCLASS $XA, VSRC);
844  dag BToVSRC = (COPY_TO_REGCLASS $XB, VSRC);
845}
846
847let Predicates = [PrefixInstrs] in {
848  let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
849    defm PADDI8 :
850      MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA, s34imm:$SI),
851                              (ins immZero:$RA, s34imm_pcrel:$SI),
852                              "paddi $RT, $RA, $SI", IIC_LdStLFD>;
853    let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
854      def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
855                                    (ins s34imm:$SI),
856                                    "pli $RT, $SI", IIC_IntSimple, []>;
857    }
858  }
859  defm PADDI :
860    MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc:$RA, s34imm:$SI),
861                            (ins immZero:$RA, s34imm_pcrel:$SI),
862                            "paddi $RT, $RA, $SI", IIC_LdStLFD>;
863  let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
864    def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
865                                 (ins s34imm:$SI),
866                                 "pli $RT, $SI", IIC_IntSimple, []>;
867  }
868
869  let mayLoad = 1, mayStore = 0 in {
870    defm PLXV :
871      8LS_DForm_R_SI34_XT6_RA5_p<25, (outs vsrc:$XT), (ins memri34:$D_RA),
872                                 (ins memri34_pcrel:$D_RA), "plxv $XT, $D_RA",
873                                 IIC_LdStLFD>;
874    defm PLFS :
875      MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$FRT), (ins memri34:$D_RA),
876                                  (ins memri34_pcrel:$D_RA), "plfs $FRT, $D_RA",
877                                  IIC_LdStLFD>;
878    defm PLFD :
879      MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$FRT), (ins memri34:$D_RA),
880                                  (ins  memri34_pcrel:$D_RA), "plfd $FRT, $D_RA",
881                                  IIC_LdStLFD>;
882    defm PLXSSP :
883      8LS_DForm_R_SI34_RTA5_p<43, (outs vfrc:$VRT), (ins memri34:$D_RA),
884                              (ins memri34_pcrel:$D_RA), "plxssp $VRT, $D_RA",
885                              IIC_LdStLFD>;
886    defm PLXSD :
887      8LS_DForm_R_SI34_RTA5_p<42, (outs vfrc:$VRT), (ins memri34:$D_RA),
888                              (ins memri34_pcrel:$D_RA), "plxsd $VRT, $D_RA",
889                              IIC_LdStLFD>;
890    let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
891      defm PLBZ8 :
892        MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RT), (ins memri34:$D_RA),
893                                    (ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA",
894                                    IIC_LdStLFD>;
895      defm PLHZ8 :
896        MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RT), (ins memri34:$D_RA),
897                                    (ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA",
898                                    IIC_LdStLFD>;
899      defm PLHA8 :
900        MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RT), (ins memri34:$D_RA),
901                                    (ins memri34_pcrel:$D_RA), "plha $RT, $D_RA",
902                                    IIC_LdStLFD>;
903      defm PLWA8 :
904        8LS_DForm_R_SI34_RTA5_p<41, (outs g8rc:$RT), (ins memri34:$D_RA),
905                                (ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA",
906                                IIC_LdStLFD>;
907      defm PLWZ8 :
908        MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RT), (ins memri34:$D_RA),
909                                    (ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA",
910                                    IIC_LdStLFD>;
911    }
912    defm PLBZ :
913      MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RT), (ins memri34:$D_RA),
914                                  (ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA",
915                                  IIC_LdStLFD>;
916    defm PLHZ :
917      MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RT), (ins memri34:$D_RA),
918                                  (ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA",
919                                  IIC_LdStLFD>;
920    defm PLHA :
921      MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RT), (ins memri34:$D_RA),
922                                  (ins memri34_pcrel:$D_RA), "plha $RT, $D_RA",
923                                  IIC_LdStLFD>;
924    defm PLWZ :
925      MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RT), (ins memri34:$D_RA),
926                                  (ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA",
927                                  IIC_LdStLFD>;
928    defm PLWA :
929      8LS_DForm_R_SI34_RTA5_p<41, (outs gprc:$RT), (ins memri34:$D_RA),
930                              (ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA",
931                              IIC_LdStLFD>;
932    defm PLD :
933      8LS_DForm_R_SI34_RTA5_p<57, (outs g8rc:$RT), (ins memri34:$D_RA),
934                              (ins memri34_pcrel:$D_RA), "pld $RT, $D_RA",
935                              IIC_LdStLFD>;
936  }
937
938  let mayStore = 1, mayLoad = 0 in {
939    defm PSTXV :
940      8LS_DForm_R_SI34_XT6_RA5_p<27, (outs), (ins vsrc:$XS, memri34:$D_RA),
941                                 (ins vsrc:$XS, memri34_pcrel:$D_RA),
942                                 "pstxv $XS, $D_RA", IIC_LdStLFD>;
943    defm PSTFS :
944      MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$FRS, memri34:$D_RA),
945                                  (ins f4rc:$FRS, memri34_pcrel:$D_RA),
946                                  "pstfs $FRS, $D_RA", IIC_LdStLFD>;
947    defm PSTFD :
948      MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$FRS, memri34:$D_RA),
949                                  (ins f8rc:$FRS, memri34_pcrel:$D_RA),
950                                  "pstfd $FRS, $D_RA", IIC_LdStLFD>;
951    defm PSTXSSP :
952      8LS_DForm_R_SI34_RTA5_p<47, (outs), (ins vfrc:$VRS, memri34:$D_RA),
953                              (ins vfrc:$VRS, memri34_pcrel:$D_RA),
954                              "pstxssp $VRS, $D_RA", IIC_LdStLFD>;
955    defm PSTXSD :
956      8LS_DForm_R_SI34_RTA5_p<46, (outs), (ins vfrc:$VRS, memri34:$D_RA),
957                              (ins vfrc:$VRS, memri34_pcrel:$D_RA),
958                              "pstxsd $VRS, $D_RA", IIC_LdStLFD>;
959    let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
960      defm PSTB8 :
961        MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RS, memri34:$D_RA),
962                                    (ins g8rc:$RS, memri34_pcrel:$D_RA),
963                                    "pstb $RS, $D_RA", IIC_LdStLFD>;
964      defm PSTH8 :
965        MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RS, memri34:$D_RA),
966                                    (ins g8rc:$RS, memri34_pcrel:$D_RA),
967                                    "psth $RS, $D_RA", IIC_LdStLFD>;
968      defm PSTW8 :
969        MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RS, memri34:$D_RA),
970                                    (ins g8rc:$RS, memri34_pcrel:$D_RA),
971                                    "pstw $RS, $D_RA", IIC_LdStLFD>;
972    }
973    defm PSTB :
974      MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RS, memri34:$D_RA),
975                                  (ins gprc:$RS, memri34_pcrel:$D_RA),
976                                  "pstb $RS, $D_RA", IIC_LdStLFD>;
977    defm PSTH :
978      MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RS, memri34:$D_RA),
979                                  (ins gprc:$RS, memri34_pcrel:$D_RA),
980                                  "psth $RS, $D_RA", IIC_LdStLFD>;
981    defm PSTW :
982      MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RS, memri34:$D_RA),
983                                  (ins gprc:$RS, memri34_pcrel:$D_RA),
984                                  "pstw $RS, $D_RA", IIC_LdStLFD>;
985    defm PSTD :
986      8LS_DForm_R_SI34_RTA5_p<61, (outs), (ins g8rc:$RS, memri34:$D_RA),
987                              (ins g8rc:$RS, memri34_pcrel:$D_RA),
988                              "pstd $RS, $D_RA", IIC_LdStLFD>;
989  }
990}
991
992// Multiclass definitions for MMA accumulator instructions.
993// ----------------------------------------------------------------------------
994
995// Defines 2 unmasked instructions where the xo field for acc/non-acc version
996// is even/odd.
997multiclass ACC_UM_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
998                       string asmstr> {
999  let Predicates = [MMA] in {
1000  def NAME :
1001    XX3Form_AT3_XAB6<opcode, !or(xo, 0x01), (outs acc:$AT), IOL,
1002                     !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,
1003    RegConstraint<"@earlyclobber $AT">;
1004  def PP :
1005    XX3Form_AT3_XAB6<opcode, xo, (outs acc:$AT), !con((ins acc:$ATi), IOL),
1006                     !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
1007    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1008  }
1009}
1010
1011// Defines 4 instructions, masked/unmasked with masks 8, 4, 4 bits.
1012// The XO field for acc/non-acc version is even/odd.
1013multiclass ACC_UM_M844_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
1014                            string asmstr> {
1015  defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
1016  let Predicates = [MMA, PrefixInstrs] in {
1017  def PM#NAME :
1018    MMIRR_XX3Form_XY4P8_XAB6<
1019      opcode, !or(xo, 0x01), (outs acc:$AT),
1020      !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u8imm:$PMSK)),
1021      !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
1022      IIC_VecFP, []>,
1023    RegConstraint<"@earlyclobber $AT">;
1024  def PM#NAME#PP :
1025    MMIRR_XX3Form_XY4P8_XAB6<
1026      opcode, xo, (outs acc:$AT),
1027      !con((ins acc:$ATi),
1028           !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u8imm:$PMSK))),
1029      !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
1030      IIC_VecFP, []>,
1031    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1032  }
1033}
1034
1035// Defines 4 instructions, masked/unmasked with masks 4, 4, 4 bits.
1036// The XO field for acc/non-acc version is even/odd.
1037multiclass ACC_UM_M444_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
1038                            string asmstr> {
1039  defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
1040  let Predicates = [MMA, PrefixInstrs] in {
1041  def PM#NAME :
1042    MMIRR_XX3Form_XYP4_XAB6<
1043      opcode, !or(xo, 0x01), (outs acc:$AT),
1044      !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK)),
1045      !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
1046      IIC_VecFP, []>,
1047    RegConstraint<"@earlyclobber $AT">;
1048  def PM#NAME#PP :
1049    MMIRR_XX3Form_XYP4_XAB6<
1050      opcode, xo, (outs acc:$AT),
1051      !con((ins acc:$ATi),
1052           !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK))),
1053      !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
1054      IIC_VecFP, []>,
1055    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1056  }
1057}
1058
1059// Defines 4 instructions, masked/unmasked with masks 2, 4, 4 bits.
1060// The XO field for acc/non-acc version is even/odd.
1061multiclass ACC_UM_M244_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
1062                            string asmstr> {
1063  defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
1064  let Predicates = [MMA, PrefixInstrs] in {
1065  def PM#NAME :
1066    MMIRR_XX3Form_XY4P2_XAB6<
1067      opcode, !or(xo, 0x01), (outs acc:$AT),
1068      !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)),
1069      !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
1070      IIC_VecFP, []>,
1071    RegConstraint<"@earlyclobber $AT">;
1072  def PM#NAME#PP :
1073    MMIRR_XX3Form_XY4P2_XAB6<
1074      opcode, xo, (outs acc:$AT),
1075      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
1076      !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
1077      IIC_VecFP, []>,
1078    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1079  }
1080}
1081
1082// Defines 4 instructions, masked/unmasked with masks 2, 4, 4 bits.
1083// Upper nibble of XO field for acc/non-acc version is 0x4/0x6.
1084multiclass ACC_UM_M244_XO46<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
1085                            string asmstr> {
1086  let Predicates = [MMA] in {
1087  def NAME :
1088    XX3Form_AT3_XAB6<opcode, xo, (outs acc:$AT), IOL,
1089                     !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,
1090    RegConstraint<"@earlyclobber $AT">;
1091  def PP :
1092    XX3Form_AT3_XAB6<
1093      opcode, !or(xo, 0x20), (outs acc:$AT), !con((ins acc:$ATi), IOL),
1094      !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
1095    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1096  }
1097  let Predicates = [MMA, PrefixInstrs] in {
1098  def PM#NAME :
1099    MMIRR_XX3Form_XY4P2_XAB6<
1100      opcode, xo, (outs acc:$AT),
1101      !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)),
1102      !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
1103      IIC_VecFP, []>,
1104    RegConstraint<"@earlyclobber $AT">;
1105  def PM#NAME#PP :
1106    MMIRR_XX3Form_XY4P2_XAB6<
1107      opcode, !or(xo, 0x20), (outs acc:$AT),
1108      !con((ins acc:$ATi),
1109           !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
1110      !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
1111      IIC_VecFP, []>,
1112    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1113  }
1114}
1115
1116// Defines 10 instructions, operand negating, unmasked, masked with 2, 4, 4
1117// bits. Upper nibble are masked with 0x8, 0x4, 0xC for negating operands.
1118multiclass ACC_NEG_UM_M244_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
1119                                  string asmbase, string asmstr> {
1120  defm NAME : ACC_UM_M244_XOEO<opcode, xo, IOL, asmbase, asmstr>;
1121  let Predicates = [MMA] in {
1122  def PN : XX3Form_AT3_XAB6<
1123             opcode, !or(xo, 0x80), (outs acc:$AT), !con((ins acc:$ATi), IOL),
1124             !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
1125           RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1126  def NP : XX3Form_AT3_XAB6<
1127             opcode, !or(xo, 0x40), (outs acc:$AT), !con((ins acc:$ATi), IOL),
1128             !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,
1129           RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1130  def NN : XX3Form_AT3_XAB6<
1131             opcode, !or(xo, 0xC0), (outs acc:$AT), !con((ins acc:$ATi), IOL),
1132             !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,
1133           RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1134  }
1135  let Predicates = [MMA, PrefixInstrs] in {
1136  def PM#NAME#PN :
1137    MMIRR_XX3Form_XY4P2_XAB6<
1138      opcode, !or(xo, 0x80), (outs acc:$AT),
1139      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
1140      !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK, $PMSK"),
1141      IIC_VecFP, []>,
1142    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1143  def PM#NAME#NP :
1144    MMIRR_XX3Form_XY4P2_XAB6<
1145      opcode, !or(xo, 0x40), (outs acc:$AT),
1146      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
1147      !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK, $PMSK"),
1148      IIC_VecFP, []>,
1149    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1150  def PM#NAME#NN :
1151    MMIRR_XX3Form_XY4P2_XAB6<
1152      opcode, !or(xo, 0xC0), (outs acc:$AT),
1153      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
1154      !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK, $PMSK"),
1155      IIC_VecFP, []>,
1156    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1157  }
1158}
1159
1160// Defines 5 instructions, unmasked, operand negating.
1161// Upper nibble are masked with 0x8, 0x4, 0xC for negating operands.
1162multiclass ACC_NEG_UM_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
1163                             string asmbase, string asmstr> {
1164  defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
1165  let Predicates = [MMA] in {
1166  def PN : XX3Form_AT3_XAB6<opcode, !or(xo, 0x80), (outs acc:$AT),
1167                            !con((ins acc:$ATi), IOL),
1168                            !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
1169           RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1170  def NP : XX3Form_AT3_XAB6<opcode, !or(xo, 0x40), (outs acc:$AT),
1171                            !con((ins acc:$ATi), IOL),
1172                            !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,
1173           RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1174  def NN : XX3Form_AT3_XAB6<opcode, !or(xo, 0xC0), (outs acc:$AT),
1175                            !con((ins acc:$ATi), IOL),
1176                            !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,
1177           RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1178  }
1179}
1180
1181// Defines 10 instructions, operand negating, unmasked, masked with 4, 4 bits.
1182// Upper nibble are masked with 0x8, 0x4, 0xC for negating operands.
1183multiclass ACC_NEG_UM_M44_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
1184                                 string asmbase, string asmstr> {
1185  defm NAME : ACC_NEG_UM_XOM84C<opcode, xo, IOL, asmbase, asmstr>;
1186  let Predicates = [MMA, PrefixInstrs] in {
1187  def PM#NAME :
1188    MMIRR_XX3Form_XY4_XAB6<
1189      opcode, !or(xo, 0x01), (outs acc:$AT),
1190      !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK)),
1191      !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK"),
1192      IIC_VecFP, []>,
1193    RegConstraint<"@earlyclobber $AT">;
1194  def PM#NAME#PP :
1195    MMIRR_XX3Form_XY4_XAB6<
1196      opcode, xo, (outs acc:$AT),
1197      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
1198      !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"),
1199      IIC_VecFP, []>,
1200    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1201  def PM#NAME#PN :
1202    MMIRR_XX3Form_XY4_XAB6<
1203      opcode, !or(xo, 0x80), (outs acc:$AT),
1204      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
1205      !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"),
1206      IIC_VecFP, []>,
1207    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1208  def PM#NAME#NP :
1209    MMIRR_XX3Form_XY4_XAB6<
1210      opcode, !or(xo, 0x40), (outs acc:$AT),
1211      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
1212      !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"),
1213      IIC_VecFP, []>,
1214    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1215  def PM#NAME#NN :
1216    MMIRR_XX3Form_XY4_XAB6<
1217      opcode, !or(xo, 0xC0), (outs acc:$AT),
1218      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
1219      !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"),
1220      IIC_VecFP, []>,
1221    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1222  }
1223}
1224
1225// Defines 10 instructions, operand negating, unmasked, masked with 4, 2 bits.
1226// Upper nibble are masked with 0x8, 0x4, 0xC for negating operands.
1227multiclass ACC_NEG_UM_M42_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
1228                                 string asmbase, string asmstr> {
1229  defm NAME : ACC_NEG_UM_XOM84C<opcode, xo, IOL, asmbase, asmstr>;
1230  let Predicates = [MMA, PrefixInstrs] in {
1231  def PM#NAME :
1232    MMIRR_XX3Form_X4Y2_XAB6<
1233      opcode, !or(xo, 0x01), (outs acc:$AT),
1234      !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK)),
1235      !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK"),
1236      IIC_VecFP, []>,
1237    RegConstraint<"@earlyclobber $AT">;
1238  def PM#NAME#PP :
1239    MMIRR_XX3Form_X4Y2_XAB6<
1240      opcode, xo, (outs acc:$AT),
1241      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
1242      !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"),
1243      IIC_VecFP, []>,
1244    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1245  def PM#NAME#PN :
1246    MMIRR_XX3Form_X4Y2_XAB6<
1247      opcode, !or(xo, 0x80), (outs acc:$AT),
1248      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
1249      !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"),
1250      IIC_VecFP, []>,
1251    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1252  def PM#NAME#NP :
1253    MMIRR_XX3Form_X4Y2_XAB6<
1254      opcode, !or(xo, 0x40), (outs acc:$AT),
1255      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
1256      !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"),
1257      IIC_VecFP, []>,
1258    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1259  def PM#NAME#NN :
1260    MMIRR_XX3Form_X4Y2_XAB6<
1261      opcode, !or(xo, 0xC0), (outs acc:$AT),
1262      !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
1263      !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"),
1264      IIC_VecFP, []>,
1265    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1266  }
1267}
1268
1269// End of class definitions.
1270//-----------------------------------------------------------------------------
1271
1272let Predicates = [MMA] in {
1273  def XXMFACC :
1274    XForm_AT3<31, 0, 177, (outs acc:$ASo), (ins acc:$AS), "xxmfacc $AS",
1275              IIC_VecGeneral,
1276              [(set v512i1:$ASo, (int_ppc_mma_xxmfacc v512i1:$AS))]>,
1277              RegConstraint<"$ASo = $AS">, NoEncode<"$ASo">;
1278  def XXMTACC :
1279    XForm_AT3<31, 1, 177, (outs acc:$AT), (ins acc:$ATi), "xxmtacc $AT",
1280              IIC_VecGeneral,
1281              [(set v512i1:$AT, (int_ppc_mma_xxmtacc v512i1:$ATi))]>,
1282              RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1283  def KILL_PAIR : PPCPostRAExpPseudo<(outs vsrprc:$XTp), (ins vsrprc:$XSp),
1284                                      "#KILL_PAIR", []>,
1285                                      RegConstraint<"$XTp = $XSp">;
1286  def BUILD_UACC : PPCPostRAExpPseudo<(outs acc:$AT), (ins uacc:$AS),
1287                                      "#BUILD_UACC $AT, $AS", []>;
1288  // We define XXSETACCZ as rematerializable to undo CSE of that intrinsic in
1289  // the backend. We avoid CSE here because it generates a copy of the acc
1290  // register and this copy is more expensive than calling the intrinsic again.
1291  let isAsCheapAsAMove = 1, isReMaterializable = 1 in {
1292    def XXSETACCZ :
1293      XForm_AT3<31, 3, 177, (outs acc:$AT), (ins), "xxsetaccz $AT", IIC_VecGeneral,
1294                [(set v512i1:$AT, (int_ppc_mma_xxsetaccz))]>;
1295  }
1296  def XVI8GER4SPP :
1297    XX3Form_AT3_XAB6<59, 99, (outs acc:$AT), (ins acc:$ATi, vsrc:$XA, vsrc:$XB),
1298                     "xvi8ger4spp $AT, $XA, $XB", IIC_VecGeneral, []>,
1299    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1300  let mayStore = 1 in {
1301    def SPILL_ACC: PPCEmitTimePseudo<(outs), (ins acc:$AT, memrix16:$dst),
1302                                     "#SPILL_ACC", []>;
1303    def SPILL_UACC: PPCEmitTimePseudo<(outs), (ins uacc:$AT, memrix16:$dst),
1304                                     "#SPILL_UACC", []>;
1305  }
1306  let mayLoad = 1, hasSideEffects = 0 in {
1307    def RESTORE_ACC: PPCEmitTimePseudo<(outs acc:$AT), (ins memrix16:$src),
1308                                       "#RESTORE_ACC", []>;
1309    def RESTORE_UACC: PPCEmitTimePseudo<(outs uacc:$AT), (ins memrix16:$src),
1310                                       "#RESTORE_UACC", []>;
1311  }
1312}
1313
1314let Predicates = [MMA, PrefixInstrs] in {
1315  def PMXVI8GER4SPP :
1316    MMIRR_XX3Form_XYP4_XAB6<59, 99, (outs acc:$AT),
1317                            (ins acc:$ATi, vsrc:$XA,vsrc:$XB, u4imm:$XMSK,
1318                             u4imm:$YMSK, u4imm:$PMSK),
1319                            "pmxvi8ger4spp $AT, $XA, $XB, $XMSK, $YMSK, $PMSK",
1320                            IIC_VecGeneral, []>,
1321    RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
1322}
1323
1324// MMA accumulating/non-accumulating instructions.
1325//------------------------------------------------------------------------------
1326
1327// XVBF16GER2, XVBF16GER2PP, XVBF16GER2PN, XVBF16GER2NP, XVBF16GER2NN
1328// PMXVBF16GER2, PMXVBF16GER2PP, PMXVBF16GER2PN, PMXVBF16GER2NP, PMXVBF16GER2NN
1329defm XVBF16GER2 : ACC_NEG_UM_M244_XOM84C<59, 50, (ins vsrc:$XA, vsrc:$XB),
1330                                         "xvbf16ger2", "$AT, $XA, $XB">;
1331
1332// XVI4GER8, XVI4GER8PP, PMXVI4GER8,  PMXVI4GER8PP
1333defm XVI4GER8 : ACC_UM_M844_XOEO<59, 34, (ins vsrc:$XA, vsrc:$XB),
1334                                 "xvi4ger8", "$AT, $XA, $XB">;
1335
1336// XVI8GER4, XVI8GER4PP, PMXVI8GER4, PMXVI8GER4PP
1337defm XVI8GER4 : ACC_UM_M444_XOEO<59, 2, (ins vsrc:$XA, vsrc:$XB),
1338                                 "xvi8ger4", "$AT, $XA, $XB">;
1339
1340// XVI16GER2, XVI16GER2PP, PMXVI16GER2, PMXVI16GER2PP
1341defm XVI16GER2 : ACC_UM_M244_XO46<59, 75, (ins vsrc:$XA, vsrc:$XB),
1342                                  "xvi16ger2", "$AT, $XA, $XB">;
1343
1344// XVI16GER2S, XVI16GER2SPP, PMXVI16GER2S, PMXVI16GER2SPP
1345defm XVI16GER2S : ACC_UM_M244_XOEO<59, 42, (ins vsrc:$XA, vsrc:$XB),
1346                                   "xvi16ger2s", "$AT, $XA, $XB">;
1347
1348// XVF16GER2, XVF16GER2PP, XVF16GER2PN, XVF16GER2NP, XVF16GER2NN
1349// PMXVF16GER2, PMXVF16GER2PP, PMXVF16GER2PN, PMXVF16GER2NP, PMXVF16GER2NN
1350defm XVF16GER2 : ACC_NEG_UM_M244_XOM84C<59, 18, (ins vsrc:$XA, vsrc:$XB),
1351                                        "xvf16ger2", "$AT, $XA, $XB">;
1352
1353// XVF32GER, XVF32GERPP, XVF32GERPN, XVF32GERNP, XVF32GERPP
1354// PMXVF32GER, PMXVF32GERPP, PMXVF32GERPN, PMXVF32GERNP, PMXVF32GERPP
1355defm XVF32GER : ACC_NEG_UM_M44_XOM84C<59, 26, (ins vsrc:$XA, vsrc:$XB),
1356                                      "xvf32ger", "$AT, $XA, $XB">;
1357
1358// XVF64GER, XVF64GERPP, XVF64GERPN, XVF64GERNP, XVF64GERNN
1359// PMXVF64GER, PMXVF64GERPP, PMXVF64GERPN, PMXVF64GERNP, PMXVF64GERNN
1360defm XVF64GER : ACC_NEG_UM_M42_XOM84C<59, 58, (ins vsrpevenrc:$XA, vsrc:$XB),
1361                                      "xvf64ger", "$AT, $XA, $XB">;
1362//------------------------------------------------------------------------------
1363
1364// MMA Intrinsics
1365let Predicates = [MMA] in {
1366  def : Pat<(v512i1 (int_ppc_mma_xvi4ger8 v16i8:$XA, v16i8:$XB)),
1367            (XVI4GER8 RCCp.AToVSRC, RCCp.BToVSRC)>;
1368  def : Pat<(v512i1 (int_ppc_mma_xvi4ger8pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1369            (XVI4GER8PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1370
1371  def : Pat<(v512i1 (int_ppc_mma_xvi8ger4 v16i8:$XA, v16i8:$XB)),
1372            (XVI8GER4 RCCp.AToVSRC, RCCp.BToVSRC)>;
1373  def : Pat<(v512i1 (int_ppc_mma_xvi8ger4pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1374            (XVI8GER4PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1375
1376  def : Pat<(v512i1 (int_ppc_mma_xvi16ger2s v16i8:$XA, v16i8:$XB)),
1377            (XVI16GER2S RCCp.AToVSRC, RCCp.BToVSRC)>;
1378  def : Pat<(v512i1 (int_ppc_mma_xvi16ger2spp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1379            (XVI16GER2SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1380
1381  def : Pat<(v512i1 (int_ppc_mma_xvf16ger2 v16i8:$XA, v16i8:$XB)),
1382            (XVF16GER2 RCCp.AToVSRC, RCCp.BToVSRC)>;
1383  def : Pat<(v512i1 (int_ppc_mma_xvf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1384            (XVF16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1385  def : Pat<(v512i1 (int_ppc_mma_xvf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1386            (XVF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1387  def : Pat<(v512i1 (int_ppc_mma_xvf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1388            (XVF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1389  def : Pat<(v512i1 (int_ppc_mma_xvf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1390            (XVF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1391
1392  def : Pat<(v512i1 (int_ppc_mma_xvf32ger v16i8:$XA, v16i8:$XB)),
1393            (XVF32GER RCCp.AToVSRC, RCCp.BToVSRC)>;
1394  def : Pat<(v512i1 (int_ppc_mma_xvf32gerpp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1395            (XVF32GERPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1396  def : Pat<(v512i1 (int_ppc_mma_xvf32gerpn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1397            (XVF32GERPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1398  def : Pat<(v512i1 (int_ppc_mma_xvf32gernp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1399            (XVF32GERNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1400  def : Pat<(v512i1 (int_ppc_mma_xvf32gernn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1401            (XVF32GERNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1402  def : Pat<(v512i1 (int_ppc_mma_xvf64ger v256i1:$XA, v16i8:$XB)),
1403            (XVF64GER $XA, RCCp.BToVSRC)>;
1404  def : Pat<(v512i1 (int_ppc_mma_xvf64gerpp v512i1:$ATi, v256i1:$XA, v16i8:$XB)),
1405            (XVF64GERPP $ATi, $XA, RCCp.BToVSRC)>;
1406  def : Pat<(v512i1 (int_ppc_mma_xvf64gerpn v512i1:$ATi, v256i1:$XA, v16i8:$XB)),
1407            (XVF64GERPN $ATi, $XA, RCCp.BToVSRC)>;
1408  def : Pat<(v512i1 (int_ppc_mma_xvf64gernp v512i1:$ATi, v256i1:$XA, v16i8:$XB)),
1409            (XVF64GERNP $ATi, $XA, RCCp.BToVSRC)>;
1410  def : Pat<(v512i1 (int_ppc_mma_xvf64gernn v512i1:$ATi, v256i1:$XA, v16i8:$XB)),
1411            (XVF64GERNN $ATi, $XA, RCCp.BToVSRC)>;
1412
1413  def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2 v16i8:$XA, v16i8:$XB)),
1414            (XVBF16GER2 RCCp.AToVSRC, RCCp.BToVSRC)>;
1415  def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1416            (XVBF16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1417  def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1418            (XVBF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1419  def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1420            (XVBF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1421  def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1422            (XVBF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1423  def : Pat<(v512i1 (int_ppc_mma_xvi16ger2 v16i8:$XA, v16i8:$XB)),
1424            (XVI16GER2 RCCp.AToVSRC, RCCp.BToVSRC)>;
1425  def : Pat<(v512i1 (int_ppc_mma_xvi16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1426            (XVI16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1427  def : Pat<(v512i1 (int_ppc_mma_xvi8ger4spp v512i1:$ATi, v16i8:$XA, v16i8:$XB)),
1428            (XVI8GER4SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>;
1429}
1430
1431// MMA Intrinsics
1432let Predicates = [MMA, PrefixInstrs] in {
1433  def : Pat<(v512i1 (int_ppc_mma_pmxvi4ger8 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
1434                                            Msk4Imm:$YMSK, Msk8Imm:$PMSK)),
1435            (PMXVI4GER8 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1436                        Msk4Imm:$YMSK, Msk8Imm:$PMSK)>;
1437  def : Pat<(v512i1 (int_ppc_mma_pmxvi4ger8pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1438                                              Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1439                                              Msk8Imm:$PMSK)),
1440            (PMXVI4GER8PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1441                          Msk4Imm:$YMSK, Msk8Imm:$PMSK)>;
1442
1443  def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
1444                                            Msk4Imm:$YMSK, Msk4Imm:$PMSK)),
1445            (PMXVI8GER4 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1446                        Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
1447  def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1448                                              Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1449                                              Msk4Imm:$PMSK)),
1450            (PMXVI8GER4PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1451                          Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
1452
1453  def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2s v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
1454                                              Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
1455            (PMXVI16GER2S RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1456                          Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1457  def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2spp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1458                                                Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1459                                                Msk2Imm:$PMSK)),
1460            (PMXVI16GER2SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1461                            Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1462  def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
1463                                             Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
1464            (PMXVF16GER2 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1465                         Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1466  def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1467                                               Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1468                                               Msk2Imm:$PMSK)),
1469            (PMXVF16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1470                           Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1471  def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1472                                               Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1473                                               Msk2Imm:$PMSK)),
1474            (PMXVF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1475                           Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1476  def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1477                                               Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1478                                               Msk2Imm:$PMSK)),
1479            (PMXVF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1480                           Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1481  def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1482                                               Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1483                                               Msk2Imm:$PMSK)),
1484            (PMXVF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1485                           Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1486  def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1487                                               Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1488                                               Msk2Imm:$PMSK)),
1489            (PMXVF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1490                           Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1491  def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1492                                               Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1493                                               Msk2Imm:$PMSK)),
1494            (PMXVF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1495                           Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1496
1497  def : Pat<(v512i1 (int_ppc_mma_pmxvf32ger v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
1498                                            Msk4Imm:$YMSK)),
1499            (PMXVF32GER RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1500                        Msk4Imm:$YMSK)>;
1501  def : Pat<(v512i1 (int_ppc_mma_pmxvf32gerpp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1502                                              Msk4Imm:$XMSK, Msk4Imm:$YMSK)),
1503            (PMXVF32GERPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1504                          Msk4Imm:$YMSK)>;
1505  def : Pat<(v512i1 (int_ppc_mma_pmxvf32gerpn v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1506                                              Msk4Imm:$XMSK, Msk4Imm:$YMSK)),
1507            (PMXVF32GERPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1508                          Msk4Imm:$YMSK)>;
1509  def : Pat<(v512i1 (int_ppc_mma_pmxvf32gernp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1510                                              Msk4Imm:$XMSK, Msk4Imm:$YMSK)),
1511            (PMXVF32GERNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1512                          Msk4Imm:$YMSK)>;
1513  def : Pat<(v512i1 (int_ppc_mma_pmxvf32gernn v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1514                                              Msk4Imm:$XMSK, Msk4Imm:$YMSK)),
1515            (PMXVF32GERNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1516                          Msk4Imm:$YMSK)>;
1517
1518  def : Pat<(v512i1 (int_ppc_mma_pmxvf64ger v256i1:$XA, v16i8:$XB, Msk4Imm:$XMSK,
1519                                            Msk2Imm:$YMSK)),
1520            (PMXVF64GER $XA, RCCp.BToVSRC, Msk4Imm:$XMSK, Msk2Imm:$YMSK)>;
1521  def : Pat<(v512i1 (int_ppc_mma_pmxvf64gerpp v512i1:$ATi, v256i1:$XA, v16i8:$XB,
1522                                              Msk4Imm:$XMSK, Msk2Imm:$YMSK)),
1523            (PMXVF64GERPP $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK,
1524                          Msk2Imm:$YMSK)>;
1525  def : Pat<(v512i1 (int_ppc_mma_pmxvf64gerpn v512i1:$ATi, v256i1:$XA, v16i8:$XB,
1526                                              Msk4Imm:$XMSK, Msk2Imm:$YMSK)),
1527            (PMXVF64GERPN $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK,
1528                          Msk2Imm:$YMSK)>;
1529  def : Pat<(v512i1 (int_ppc_mma_pmxvf64gernp v512i1:$ATi, v256i1:$XA, v16i8:$XB,
1530                                              Msk4Imm:$XMSK, Msk2Imm:$YMSK)),
1531            (PMXVF64GERNP $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK,
1532                          Msk2Imm:$YMSK)>;
1533  def : Pat<(v512i1 (int_ppc_mma_pmxvf64gernn v512i1:$ATi, v256i1:$XA, v16i8:$XB,
1534                                              Msk4Imm:$XMSK, Msk2Imm:$YMSK)),
1535            (PMXVF64GERNN $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK,
1536                          Msk2Imm:$YMSK)>;
1537
1538  def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
1539                                              Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
1540            (PMXVBF16GER2 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1541                          Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1542  def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1543                                                Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1544                                                Msk2Imm:$PMSK)),
1545            (PMXVBF16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1546                            Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1547  def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1548                                                Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1549                                                Msk2Imm:$PMSK)),
1550            (PMXVBF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1551                            Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1552  def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1553                                                Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1554                                                Msk2Imm:$PMSK)),
1555            (PMXVBF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1556                            Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1557  def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1558                                                Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1559                                                Msk2Imm:$PMSK)),
1560            (PMXVBF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1561                            Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1562  def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK,
1563                                             Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
1564            (PMXVI16GER2 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1565                         Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1566  def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4spp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1567                                               Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1568                                               Msk2Imm:$PMSK)),
1569            (PMXVI8GER4SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1570                           Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1571  def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB,
1572                                               Msk4Imm:$XMSK, Msk4Imm:$YMSK,
1573                                               Msk2Imm:$PMSK)),
1574            (PMXVI16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK,
1575                           Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
1576}
1577
1578def Concats {
1579  dag VecsToVecPair0 =
1580    (v256i1 (INSERT_SUBREG
1581      (INSERT_SUBREG (IMPLICIT_DEF), $vs0, sub_vsx1),
1582      $vs1, sub_vsx0));
1583  dag VecsToVecPair1 =
1584    (v256i1 (INSERT_SUBREG
1585      (INSERT_SUBREG (IMPLICIT_DEF), $vs2, sub_vsx1),
1586      $vs3, sub_vsx0));
1587  dag VecsToVecQuad =
1588    (BUILD_UACC (INSERT_SUBREG
1589                  (INSERT_SUBREG (v512i1 (IMPLICIT_DEF)),
1590                                 (KILL_PAIR VecsToVecPair0), sub_pair0),
1591                  (KILL_PAIR VecsToVecPair1), sub_pair1));
1592}
1593
1594def Extracts {
1595  dag Pair0 = (v256i1 (EXTRACT_SUBREG $v, sub_pair0));
1596  dag Pair1 = (v256i1 (EXTRACT_SUBREG $v, sub_pair1));
1597  dag Vec0 = (v4i32 (EXTRACT_SUBREG Pair0, sub_vsx0));
1598  dag Vec1 = (v4i32 (EXTRACT_SUBREG Pair0, sub_vsx1));
1599  dag Vec2 = (v4i32 (EXTRACT_SUBREG Pair1, sub_vsx0));
1600  dag Vec3 = (v4i32 (EXTRACT_SUBREG Pair1, sub_vsx1));
1601}
1602
1603let Predicates = [MMA] in {
1604  def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
1605            (XXMTACC Concats.VecsToVecQuad)>;
1606  def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0,
1607                                              v16i8:$vs3, v16i8:$vs2)),
1608            (XXMTACC Concats.VecsToVecQuad)>;
1609  def : Pat<(v512i1 (PPCxxmfacc v512i1:$AS)), (XXMFACC acc:$AS)>;
1610  def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, 0)),
1611            Extracts.Vec0>;
1612  def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, 1)),
1613            Extracts.Vec1>;
1614  def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, 2)),
1615            Extracts.Vec2>;
1616  def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, 3)),
1617            Extracts.Vec3>;
1618}
1619
1620let Predicates = [PairedVectorMemops] in {
1621  def : Pat<(v256i1 (PPCPairBuild v4i32:$vs1, v4i32:$vs0)),
1622            Concats.VecsToVecPair0>;
1623  def : Pat<(v256i1 (int_ppc_vsx_assemble_pair v16i8:$vs1, v16i8:$vs0)),
1624            Concats.VecsToVecPair0>;
1625  def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 0)),
1626            (v4i32 (EXTRACT_SUBREG $v, sub_vsx0))>;
1627  def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, 1)),
1628            (v4i32 (EXTRACT_SUBREG $v, sub_vsx1))>;
1629}
1630
1631let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops] in {
1632  def LXVP : DQForm_XTp5_RA17_MEM<6, 0, (outs vsrprc:$XTp),
1633                                  (ins memrix16:$DQ_RA), "lxvp $XTp, $DQ_RA",
1634                                  IIC_LdStLFD, []>;
1635  def LXVPX : XForm_XTp5_XAB5<31, 333, (outs vsrprc:$XTp), (ins memrr:$src),
1636                              "lxvpx $XTp, $src", IIC_LdStLFD,
1637                              []>;
1638}
1639
1640let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops] in {
1641  def STXVP : DQForm_XTp5_RA17_MEM<6, 1, (outs), (ins vsrprc:$XTp,
1642                                   memrix16:$DQ_RA), "stxvp $XTp, $DQ_RA",
1643                                   IIC_LdStLFD, []>;
1644  def STXVPX : XForm_XTp5_XAB5<31, 461, (outs), (ins vsrprc:$XTp, memrr:$dst),
1645                               "stxvpx $XTp, $dst", IIC_LdStLFD,
1646                               []>;
1647}
1648
1649let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs] in {
1650  defm PLXVP :
1651    8LS_DForm_R_XTp5_SI34_MEM_p<58, (outs vsrprc:$XTp), (ins memri34:$D_RA),
1652                                (ins memri34_pcrel:$D_RA), "plxvp $XTp, $D_RA",
1653                                IIC_LdStLFD>;
1654}
1655
1656let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs] in {
1657  defm PSTXVP :
1658    8LS_DForm_R_XTp5_SI34_MEM_p<62, (outs), (ins vsrprc:$XTp, memri34:$D_RA),
1659                                (ins vsrprc:$XTp, memri34_pcrel:$D_RA),
1660                                "pstxvp $XTp, $D_RA", IIC_LdStLFD>;
1661}
1662
1663let Predicates = [PairedVectorMemops] in {
1664  // Intrinsics for Paired Vector Loads.
1665  def : Pat<(v256i1 (int_ppc_vsx_lxvp DQForm:$src)), (LXVP memrix16:$src)>;
1666  def : Pat<(v256i1 (int_ppc_vsx_lxvp XForm:$src)), (LXVPX XForm:$src)>;
1667  let Predicates = [PairedVectorMemops, PrefixInstrs] in {
1668    def : Pat<(v256i1 (int_ppc_vsx_lxvp PDForm:$src)), (PLXVP memri34:$src)>;
1669  }
1670  // Intrinsics for Paired Vector Stores.
1671  def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, DQForm:$dst),
1672            (STXVP $XSp, memrix16:$dst)>;
1673  def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, XForm:$dst),
1674            (STXVPX $XSp, XForm:$dst)>;
1675  let Predicates = [PairedVectorMemops, PrefixInstrs] in {
1676    def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, PDForm:$dst),
1677              (PSTXVP $XSp, memri34:$dst)>;
1678  }
1679}
1680
1681let Predicates = [PCRelativeMemops] in {
1682  // Load i32
1683  def : Pat<(i32 (zextloadi1  (PPCmatpcreladdr PCRelForm:$ga))),
1684            (PLBZpc $ga, 0)>;
1685  def : Pat<(i32 (extloadi1  (PPCmatpcreladdr PCRelForm:$ga))),
1686            (PLBZpc $ga, 0)>;
1687  def : Pat<(i32 (zextloadi8  (PPCmatpcreladdr PCRelForm:$ga))),
1688            (PLBZpc $ga, 0)>;
1689  def : Pat<(i32 (extloadi8   (PPCmatpcreladdr PCRelForm:$ga))),
1690            (PLBZpc $ga, 0)>;
1691  def : Pat<(i32 (sextloadi16 (PPCmatpcreladdr PCRelForm:$ga))),
1692            (PLHApc $ga, 0)>;
1693  def : Pat<(i32 (zextloadi16 (PPCmatpcreladdr PCRelForm:$ga))),
1694            (PLHZpc $ga, 0)>;
1695  def : Pat<(i32 (extloadi16 (PPCmatpcreladdr PCRelForm:$ga))),
1696            (PLHZpc $ga, 0)>;
1697  def : Pat<(i32 (load (PPCmatpcreladdr PCRelForm:$ga))), (PLWZpc $ga, 0)>;
1698
1699  // Store i32
1700  def : Pat<(truncstorei8 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1701            (PSTBpc $RS, $ga, 0)>;
1702  def : Pat<(truncstorei16 i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1703            (PSTHpc $RS, $ga, 0)>;
1704  def : Pat<(store i32:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1705            (PSTWpc $RS, $ga, 0)>;
1706
1707  // Load i64
1708  def : Pat<(i64 (zextloadi1  (PPCmatpcreladdr PCRelForm:$ga))),
1709            (PLBZ8pc $ga, 0)>;
1710  def : Pat<(i64 (extloadi1  (PPCmatpcreladdr PCRelForm:$ga))),
1711            (PLBZ8pc $ga, 0)>;
1712  def : Pat<(i64 (zextloadi8  (PPCmatpcreladdr PCRelForm:$ga))),
1713            (PLBZ8pc $ga, 0)>;
1714  def : Pat<(i64 (extloadi8   (PPCmatpcreladdr PCRelForm:$ga))),
1715            (PLBZ8pc $ga, 0)>;
1716  def : Pat<(i64 (sextloadi16 (PPCmatpcreladdr PCRelForm:$ga))),
1717            (PLHA8pc $ga, 0)>;
1718  def : Pat<(i64 (zextloadi16 (PPCmatpcreladdr PCRelForm:$ga))),
1719            (PLHZ8pc $ga, 0)>;
1720  def : Pat<(i64 (extloadi16 (PPCmatpcreladdr PCRelForm:$ga))),
1721            (PLHZ8pc $ga, 0)>;
1722  def : Pat<(i64 (zextloadi32 (PPCmatpcreladdr PCRelForm:$ga))),
1723            (PLWZ8pc $ga, 0)>;
1724  def : Pat<(i64 (sextloadi32 (PPCmatpcreladdr PCRelForm:$ga))),
1725            (PLWA8pc $ga, 0)>;
1726  def : Pat<(i64 (extloadi32 (PPCmatpcreladdr PCRelForm:$ga))),
1727            (PLWZ8pc $ga, 0)>;
1728  def : Pat<(i64 (load (PPCmatpcreladdr PCRelForm:$ga))), (PLDpc $ga, 0)>;
1729
1730  // Store i64
1731  def : Pat<(truncstorei8 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1732            (PSTB8pc $RS, $ga, 0)>;
1733  def : Pat<(truncstorei16 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1734            (PSTH8pc $RS, $ga, 0)>;
1735  def : Pat<(truncstorei32 i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1736            (PSTW8pc $RS, $ga, 0)>;
1737  def : Pat<(store i64:$RS, (PPCmatpcreladdr PCRelForm:$ga)),
1738            (PSTDpc $RS, $ga, 0)>;
1739
1740  // Load f32
1741  def : Pat<(f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFSpc $addr, 0)>;
1742
1743  // Store f32
1744  def : Pat<(store f32:$FRS, (PPCmatpcreladdr PCRelForm:$ga)),
1745            (PSTFSpc $FRS, $ga, 0)>;
1746
1747  // Load f64
1748  def : Pat<(f64 (extloadf32 (PPCmatpcreladdr PCRelForm:$addr))),
1749            (COPY_TO_REGCLASS (PLFSpc $addr, 0), VSFRC)>;
1750  def : Pat<(f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLFDpc $addr, 0)>;
1751
1752  // Store f64
1753  def : Pat<(store f64:$FRS, (PPCmatpcreladdr PCRelForm:$ga)),
1754            (PSTFDpc $FRS, $ga, 0)>;
1755
1756  // Load f128
1757  def : Pat<(f128 (load (PPCmatpcreladdr PCRelForm:$addr))),
1758            (COPY_TO_REGCLASS (PLXVpc $addr, 0), VRRC)>;
1759
1760  // Store f128
1761  def : Pat<(store f128:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1762            (PSTXVpc (COPY_TO_REGCLASS $XS, VSRC), $ga, 0)>;
1763
1764  // Load v4i32
1765  def : Pat<(v4i32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;
1766
1767  // Store v4i32
1768  def : Pat<(store v4i32:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1769            (PSTXVpc $XS, $ga, 0)>;
1770
1771  // Load v2i64
1772  def : Pat<(v2i64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;
1773
1774  // Store v2i64
1775  def : Pat<(store v2i64:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1776            (PSTXVpc $XS, $ga, 0)>;
1777
1778  // Load v4f32
1779  def : Pat<(v4f32 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;
1780
1781  // Store v4f32
1782  def : Pat<(store v4f32:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1783            (PSTXVpc $XS, $ga, 0)>;
1784
1785  // Load v2f64
1786  def : Pat<(v2f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;
1787
1788  // Store v2f64
1789  def : Pat<(store v2f64:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1790            (PSTXVpc $XS, $ga, 0)>;
1791
1792  // Atomic Load
1793  def : Pat<(atomic_load_8 (PPCmatpcreladdr PCRelForm:$ga)),
1794            (PLBZpc $ga, 0)>;
1795  def : Pat<(atomic_load_16 (PPCmatpcreladdr PCRelForm:$ga)),
1796            (PLHZpc $ga, 0)>;
1797  def : Pat<(atomic_load_32 (PPCmatpcreladdr PCRelForm:$ga)),
1798            (PLWZpc $ga, 0)>;
1799  def : Pat<(atomic_load_64 (PPCmatpcreladdr PCRelForm:$ga)),
1800            (PLDpc $ga, 0)>;
1801
1802  // Atomic Store
1803  def : Pat<(atomic_store_8 (PPCmatpcreladdr PCRelForm:$ga), i32:$RS),
1804            (PSTBpc $RS, $ga, 0)>;
1805  def : Pat<(atomic_store_16 (PPCmatpcreladdr PCRelForm:$ga), i32:$RS),
1806            (PSTHpc $RS, $ga, 0)>;
1807  def : Pat<(atomic_store_32 (PPCmatpcreladdr PCRelForm:$ga), i32:$RS),
1808            (PSTWpc $RS, $ga, 0)>;
1809  def : Pat<(atomic_store_8 (PPCmatpcreladdr PCRelForm:$ga), i64:$RS),
1810            (PSTB8pc $RS, $ga, 0)>;
1811  def : Pat<(atomic_store_16 (PPCmatpcreladdr PCRelForm:$ga), i64:$RS),
1812            (PSTH8pc $RS, $ga, 0)>;
1813  def : Pat<(atomic_store_32 (PPCmatpcreladdr PCRelForm:$ga), i64:$RS),
1814            (PSTW8pc $RS, $ga, 0)>;
1815  def : Pat<(atomic_store_64 (PPCmatpcreladdr PCRelForm:$ga), i64:$RS),
1816            (PSTDpc $RS, $ga, 0)>;
1817
1818  // Special Cases For PPCstore_scal_int_from_vsr
1819  def : Pat<(PPCstore_scal_int_from_vsr
1820              (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)),
1821              (PPCmatpcreladdr PCRelForm:$dst), 8),
1822            (PSTXSDpc (XSCVDPSXDS f64:$src), $dst, 0)>;
1823  def : Pat<(PPCstore_scal_int_from_vsr
1824              (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)),
1825              (PPCmatpcreladdr PCRelForm:$dst), 8),
1826            (PSTXSDpc (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC), $dst, 0)>;
1827
1828  def : Pat<(PPCstore_scal_int_from_vsr
1829              (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)),
1830              (PPCmatpcreladdr PCRelForm:$dst), 8),
1831            (PSTXSDpc (XSCVDPUXDS f64:$src), $dst, 0)>;
1832  def : Pat<(PPCstore_scal_int_from_vsr
1833              (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)),
1834              (PPCmatpcreladdr PCRelForm:$dst), 8),
1835            (PSTXSDpc (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC), $dst, 0)>;
1836
1837  def : Pat<(v4f32 (PPCldvsxlh (PPCmatpcreladdr PCRelForm:$addr))),
1838            (SUBREG_TO_REG (i64 1), (PLFDpc $addr, 0), sub_64)>;
1839
1840  // If the PPCmatpcreladdr node is not caught by any other pattern it should be
1841  // caught here and turned into a paddi instruction to materialize the address.
1842  def : Pat<(PPCmatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>;
1843  // PPCtlsdynamatpcreladdr node is used for TLS dynamic models to materialize
1844  // tls global address with paddi instruction.
1845  def : Pat<(PPCtlsdynamatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>;
1846  // PPCtlslocalexecmataddr node is used for TLS local exec models to
1847  // materialize tls global address with paddi instruction.
1848  def : Pat<(PPCaddTls i64:$in, (PPCtlslocalexecmataddr tglobaltlsaddr:$addr)),
1849            (PADDI8 $in, $addr)>;
1850}
1851
1852let Predicates = [PrefixInstrs] in {
1853  def XXPERMX :
1854    8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1855                            vsrc:$XC, u3imm:$UIM),
1856                            "xxpermx $XT, $XA, $XB, $XC, $UIM",
1857                            IIC_VecPerm, []>;
1858  def XXBLENDVB :
1859    8RR_XX4Form_XTABC6<33, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1860                       vsrc:$XC), "xxblendvb $XT, $XA, $XB, $XC",
1861                       IIC_VecGeneral, []>;
1862  def XXBLENDVH :
1863    8RR_XX4Form_XTABC6<33, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1864                       vsrc:$XC), "xxblendvh $XT, $XA, $XB, $XC",
1865                       IIC_VecGeneral, []>;
1866  def XXBLENDVW :
1867    8RR_XX4Form_XTABC6<33, 2, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1868                       vsrc:$XC), "xxblendvw $XT, $XA, $XB, $XC",
1869                       IIC_VecGeneral, []>;
1870  def XXBLENDVD :
1871    8RR_XX4Form_XTABC6<33, 3, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1872                       vsrc:$XC), "xxblendvd $XT, $XA, $XB, $XC",
1873                       IIC_VecGeneral, []>;
1874}
1875
1876// XXSPLTIW/DP/32DX need extra flags to make sure the compiler does not attempt
1877// to spill part of the instruction when the values are similar.
1878let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, Predicates = [PrefixInstrs] in {
1879  def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT),
1880                                     (ins i32imm:$IMM32),
1881                                     "xxspltiw $XT, $IMM32", IIC_VecGeneral,
1882                                     []>;
1883  def XXSPLTIDP : 8RR_DForm_IMM32_XT6<32, 2, (outs vsrc:$XT),
1884                                      (ins i32imm:$IMM32),
1885                                      "xxspltidp $XT, $IMM32", IIC_VecGeneral,
1886                                      [(set v2f64:$XT,
1887                                            (PPCxxspltidp i32:$IMM32))]>;
1888  def XXSPLTI32DX :
1889      8RR_DForm_IMM32_XT6_IX<32, 0, (outs vsrc:$XT),
1890                             (ins vsrc:$XTi, u1imm:$IX, i32imm:$IMM32),
1891                             "xxsplti32dx $XT, $IX, $IMM32", IIC_VecGeneral,
1892                             [(set v2i64:$XT,
1893                                   (PPCxxsplti32dx v2i64:$XTi, i32:$IX,
1894                                                   i32:$IMM32))]>,
1895                             RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
1896}
1897
1898let Predicates = [IsISA3_1] in {
1899  def SETBC : XForm_XT5_BI5<31, 384, (outs gprc:$RT), (ins crbitrc:$BI),
1900                            "setbc $RT, $BI", IIC_IntCompare, []>;
1901  def SETBCR : XForm_XT5_BI5<31, 416, (outs gprc:$RT), (ins crbitrc:$BI),
1902                             "setbcr $RT, $BI", IIC_IntCompare, []>;
1903  def SETNBC : XForm_XT5_BI5<31, 448, (outs gprc:$RT), (ins crbitrc:$BI),
1904                             "setnbc $RT, $BI", IIC_IntCompare, []>;
1905  def SETNBCR : XForm_XT5_BI5<31, 480, (outs gprc:$RT), (ins crbitrc:$BI),
1906                              "setnbcr $RT, $BI", IIC_IntCompare, []>;
1907
1908  let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
1909    def SETBC8 : XForm_XT5_BI5<31, 384, (outs g8rc:$RT), (ins crbitrc:$BI),
1910                               "setbc $RT, $BI", IIC_IntCompare, []>;
1911    def SETBCR8 : XForm_XT5_BI5<31, 416, (outs g8rc:$RT), (ins crbitrc:$BI),
1912                                "setbcr $RT, $BI", IIC_IntCompare, []>;
1913    def SETNBC8 : XForm_XT5_BI5<31, 448, (outs g8rc:$RT), (ins crbitrc:$BI),
1914                                "setnbc $RT, $BI", IIC_IntCompare, []>;
1915    def SETNBCR8 : XForm_XT5_BI5<31, 480, (outs g8rc:$RT), (ins crbitrc:$BI),
1916                                 "setnbcr $RT, $BI", IIC_IntCompare, []>;
1917  }
1918
1919  def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT),
1920                                (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
1921                                "vsldbi $VRT, $VRA, $VRB, $SH",
1922                                IIC_VecGeneral,
1923                                [(set v16i8:$VRT,
1924                                      (int_ppc_altivec_vsldbi v16i8:$VRA,
1925                                                              v16i8:$VRB,
1926                                                              timm:$SH))]>;
1927  def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT),
1928                                (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
1929                                "vsrdbi $VRT, $VRA, $VRB, $SH",
1930                                IIC_VecGeneral,
1931                                [(set v16i8:$VRT,
1932                                      (int_ppc_altivec_vsrdbi v16i8:$VRA,
1933                                                              v16i8:$VRB,
1934                                                              timm:$SH))]>;
1935  defm VSTRIBR : VXForm_VTB5_RCr<13, 1, (outs vrrc:$vT), (ins vrrc:$vB),
1936                                 "vstribr", "$vT, $vB", IIC_VecGeneral,
1937				 [(set v16i8:$vT,
1938                                       (int_ppc_altivec_vstribr v16i8:$vB))]>;
1939  defm VSTRIBL : VXForm_VTB5_RCr<13, 0, (outs vrrc:$vT), (ins vrrc:$vB),
1940                                 "vstribl", "$vT, $vB", IIC_VecGeneral,
1941                                 [(set v16i8:$vT,
1942                                       (int_ppc_altivec_vstribl v16i8:$vB))]>;
1943  defm VSTRIHR : VXForm_VTB5_RCr<13, 3, (outs vrrc:$vT), (ins vrrc:$vB),
1944                                 "vstrihr", "$vT, $vB", IIC_VecGeneral,
1945                                 [(set v8i16:$vT,
1946                                       (int_ppc_altivec_vstrihr v8i16:$vB))]>;
1947  defm VSTRIHL : VXForm_VTB5_RCr<13, 2, (outs vrrc:$vT), (ins vrrc:$vB),
1948                                 "vstrihl", "$vT, $vB", IIC_VecGeneral,
1949                                 [(set v8i16:$vT,
1950                                       (int_ppc_altivec_vstrihl v8i16:$vB))]>;
1951  def VINSW :
1952    VXForm_1<207, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, gprc:$rB),
1953             "vinsw $vD, $rB, $UIM", IIC_VecGeneral,
1954             [(set v4i32:$vD,
1955                   (int_ppc_altivec_vinsw v4i32:$vDi, i32:$rB, timm:$UIM))]>,
1956             RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
1957  def VINSD :
1958    VXForm_1<463, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, g8rc:$rB),
1959             "vinsd $vD, $rB, $UIM", IIC_VecGeneral,
1960             [(set v2i64:$vD,
1961                   (int_ppc_altivec_vinsd v2i64:$vDi, i64:$rB, timm:$UIM))]>,
1962             RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
1963  def VINSBVLX :
1964    VXForm_VTB5_RA5_ins<15, "vinsbvlx",
1965                        [(set v16i8:$vD,
1966                              (int_ppc_altivec_vinsbvlx v16i8:$vDi, i32:$rA,
1967                                                        v16i8:$vB))]>;
1968  def VINSBVRX :
1969    VXForm_VTB5_RA5_ins<271, "vinsbvrx",
1970                        [(set v16i8:$vD,
1971                              (int_ppc_altivec_vinsbvrx v16i8:$vDi, i32:$rA,
1972                                                        v16i8:$vB))]>;
1973  def VINSHVLX :
1974    VXForm_VTB5_RA5_ins<79, "vinshvlx",
1975                        [(set v8i16:$vD,
1976                              (int_ppc_altivec_vinshvlx v8i16:$vDi, i32:$rA,
1977                                                        v8i16:$vB))]>;
1978  def VINSHVRX :
1979    VXForm_VTB5_RA5_ins<335, "vinshvrx",
1980                        [(set v8i16:$vD,
1981                              (int_ppc_altivec_vinshvrx v8i16:$vDi, i32:$rA,
1982                                                        v8i16:$vB))]>;
1983  def VINSWVLX :
1984    VXForm_VTB5_RA5_ins<143, "vinswvlx",
1985                        [(set v4i32:$vD,
1986                              (int_ppc_altivec_vinswvlx v4i32:$vDi, i32:$rA,
1987                                                        v4i32:$vB))]>;
1988  def VINSWVRX :
1989    VXForm_VTB5_RA5_ins<399, "vinswvrx",
1990                        [(set v4i32:$vD,
1991                              (int_ppc_altivec_vinswvrx v4i32:$vDi, i32:$rA,
1992                                                        v4i32:$vB))]>;
1993  def VINSBLX :
1994    VXForm_VRT5_RAB5_ins<527, "vinsblx",
1995                         [(set v16i8:$vD,
1996                               (int_ppc_altivec_vinsblx v16i8:$vDi, i32:$rA,
1997                                                        i32:$rB))]>;
1998  def VINSBRX :
1999    VXForm_VRT5_RAB5_ins<783, "vinsbrx",
2000                         [(set v16i8:$vD,
2001                               (int_ppc_altivec_vinsbrx v16i8:$vDi, i32:$rA,
2002                                                        i32:$rB))]>;
2003  def VINSHLX :
2004    VXForm_VRT5_RAB5_ins<591, "vinshlx",
2005                         [(set v8i16:$vD,
2006                               (int_ppc_altivec_vinshlx v8i16:$vDi, i32:$rA,
2007                                                        i32:$rB))]>;
2008  def VINSHRX :
2009    VXForm_VRT5_RAB5_ins<847, "vinshrx",
2010                         [(set v8i16:$vD,
2011                               (int_ppc_altivec_vinshrx v8i16:$vDi, i32:$rA,
2012                                                        i32:$rB))]>;
2013  def VINSWLX :
2014    VXForm_VRT5_RAB5_ins<655, "vinswlx",
2015                         [(set v4i32:$vD,
2016                               (int_ppc_altivec_vinswlx v4i32:$vDi, i32:$rA,
2017                                                        i32:$rB))]>;
2018  def VINSWRX :
2019    VXForm_VRT5_RAB5_ins<911, "vinswrx",
2020                         [(set v4i32:$vD,
2021                               (int_ppc_altivec_vinswrx v4i32:$vDi, i32:$rA,
2022                                                        i32:$rB))]>;
2023  def VINSDLX :
2024    VXForm_1<719, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB),
2025             "vinsdlx $vD, $rA, $rB", IIC_VecGeneral,
2026              [(set v2i64:$vD,
2027                    (int_ppc_altivec_vinsdlx v2i64:$vDi, i64:$rA, i64:$rB))]>,
2028              RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
2029  def VINSDRX :
2030    VXForm_1<975, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB),
2031             "vinsdrx $vD, $rA, $rB", IIC_VecGeneral,
2032              [(set v2i64:$vD,
2033                    (int_ppc_altivec_vinsdrx v2i64:$vDi, i64:$rA, i64:$rB))]>,
2034              RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
2035  def VEXTRACTBM : VXForm_RD5_XO5_RS5<1602, 8, (outs gprc:$rD), (ins vrrc:$vB),
2036                                      "vextractbm $rD, $vB", IIC_VecGeneral,
2037                                      [(set i32:$rD,
2038                                      (int_ppc_altivec_vextractbm v16i8:$vB))]>;
2039  def VEXTRACTHM : VXForm_RD5_XO5_RS5<1602, 9, (outs gprc:$rD), (ins vrrc:$vB),
2040                                      "vextracthm $rD, $vB", IIC_VecGeneral,
2041                                      [(set i32:$rD,
2042                                      (int_ppc_altivec_vextracthm v8i16:$vB))]>;
2043  def VEXTRACTWM : VXForm_RD5_XO5_RS5<1602, 10, (outs gprc:$rD), (ins vrrc:$vB),
2044                                      "vextractwm $rD, $vB", IIC_VecGeneral,
2045                                      [(set i32:$rD,
2046                                      (int_ppc_altivec_vextractwm v4i32:$vB))]>;
2047  def VEXTRACTDM : VXForm_RD5_XO5_RS5<1602, 11, (outs gprc:$rD), (ins vrrc:$vB),
2048                                      "vextractdm $rD, $vB", IIC_VecGeneral,
2049                                      [(set i32:$rD,
2050                                      (int_ppc_altivec_vextractdm v2i64:$vB))]>;
2051  def VEXTRACTQM : VXForm_RD5_XO5_RS5<1602, 12, (outs gprc:$rD), (ins vrrc:$vB),
2052                                      "vextractqm $rD, $vB", IIC_VecGeneral,
2053                                      [(set i32:$rD,
2054                                      (int_ppc_altivec_vextractqm v1i128:$vB))]>;
2055  def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$vD), (ins vrrc:$vB),
2056                                     "vexpandbm $vD, $vB", IIC_VecGeneral,
2057                                     [(set v16i8:$vD, (int_ppc_altivec_vexpandbm
2058                                           v16i8:$vB))]>;
2059  def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$vD), (ins vrrc:$vB),
2060                                     "vexpandhm $vD, $vB", IIC_VecGeneral,
2061                                     [(set v8i16:$vD, (int_ppc_altivec_vexpandhm
2062                                           v8i16:$vB))]>;
2063  def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$vD), (ins vrrc:$vB),
2064                                     "vexpandwm $vD, $vB", IIC_VecGeneral,
2065                                     [(set v4i32:$vD, (int_ppc_altivec_vexpandwm
2066                                           v4i32:$vB))]>;
2067  def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$vD), (ins vrrc:$vB),
2068                                     "vexpanddm $vD, $vB", IIC_VecGeneral,
2069                                     [(set v2i64:$vD, (int_ppc_altivec_vexpanddm
2070                                           v2i64:$vB))]>;
2071  def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$vD), (ins vrrc:$vB),
2072                                     "vexpandqm $vD, $vB", IIC_VecGeneral,
2073                                     [(set v1i128:$vD, (int_ppc_altivec_vexpandqm
2074                                           v1i128:$vB))]>;
2075  def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$vD), (ins g8rc:$rB),
2076                                   "mtvsrbm $vD, $rB", IIC_VecGeneral,
2077                                   [(set v16i8:$vD,
2078                                         (int_ppc_altivec_mtvsrbm i64:$rB))]>;
2079  def MTVSRHM : VXForm_RD5_XO5_RS5<1602, 17, (outs vrrc:$vD), (ins g8rc:$rB),
2080                                   "mtvsrhm $vD, $rB", IIC_VecGeneral,
2081                                   [(set v8i16:$vD,
2082                                         (int_ppc_altivec_mtvsrhm i64:$rB))]>;
2083  def MTVSRWM : VXForm_RD5_XO5_RS5<1602, 18, (outs vrrc:$vD), (ins g8rc:$rB),
2084                                   "mtvsrwm $vD, $rB", IIC_VecGeneral,
2085                                   [(set v4i32:$vD,
2086                                         (int_ppc_altivec_mtvsrwm i64:$rB))]>;
2087  def MTVSRDM : VXForm_RD5_XO5_RS5<1602, 19, (outs vrrc:$vD), (ins g8rc:$rB),
2088                                   "mtvsrdm $vD, $rB", IIC_VecGeneral,
2089                                   [(set v2i64:$vD,
2090                                         (int_ppc_altivec_mtvsrdm i64:$rB))]>;
2091  def MTVSRQM : VXForm_RD5_XO5_RS5<1602, 20, (outs vrrc:$vD), (ins g8rc:$rB),
2092                                   "mtvsrqm $vD, $rB", IIC_VecGeneral,
2093                                   [(set v1i128:$vD,
2094                                         (int_ppc_altivec_mtvsrqm i64:$rB))]>;
2095  def MTVSRBMI : DXForm<4, 10, (outs vrrc:$vD), (ins u16imm64:$D),
2096                        "mtvsrbmi $vD, $D", IIC_VecGeneral,
2097                        [(set v16i8:$vD,
2098                              (int_ppc_altivec_mtvsrbm imm:$D))]>;
2099  def VCNTMBB : VXForm_RD5_MP_VB5<1602, 12, (outs g8rc:$rD),
2100                                  (ins vrrc:$vB, u1imm:$MP),
2101                                  "vcntmbb $rD, $vB, $MP", IIC_VecGeneral,
2102                                  [(set i64:$rD, (int_ppc_altivec_vcntmbb
2103                                        v16i8:$vB, timm:$MP))]>;
2104  def VCNTMBH : VXForm_RD5_MP_VB5<1602, 13, (outs g8rc:$rD),
2105                                  (ins vrrc:$vB, u1imm:$MP),
2106                                  "vcntmbh $rD, $vB, $MP", IIC_VecGeneral,
2107                                  [(set i64:$rD, (int_ppc_altivec_vcntmbh
2108                                        v8i16:$vB, timm:$MP))]>;
2109  def VCNTMBW : VXForm_RD5_MP_VB5<1602, 14, (outs g8rc:$rD),
2110                                  (ins vrrc:$vB, u1imm:$MP),
2111                                  "vcntmbw $rD, $vB, $MP", IIC_VecGeneral,
2112                                  [(set i64:$rD, (int_ppc_altivec_vcntmbw
2113                                        v4i32:$vB, timm:$MP))]>;
2114  def VCNTMBD : VXForm_RD5_MP_VB5<1602, 15, (outs g8rc:$rD),
2115                                  (ins vrrc:$vB, u1imm:$MP),
2116                                  "vcntmbd $rD, $vB, $MP", IIC_VecGeneral,
2117                                  [(set i64:$rD, (int_ppc_altivec_vcntmbd
2118                                        v2i64:$vB, timm:$MP))]>;
2119  def VEXTDUBVLX : VAForm_1a<24, (outs vrrc:$vD),
2120                             (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
2121                             "vextdubvlx $vD, $vA, $vB, $rC",
2122                             IIC_VecGeneral,
2123                             [(set v2i64:$vD,
2124                                   (int_ppc_altivec_vextdubvlx v16i8:$vA,
2125                                                               v16i8:$vB,
2126                                                               i32:$rC))]>;
2127  def VEXTDUBVRX : VAForm_1a<25, (outs vrrc:$vD),
2128                             (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
2129                             "vextdubvrx $vD, $vA, $vB, $rC",
2130                             IIC_VecGeneral,
2131                             [(set v2i64:$vD,
2132                                   (int_ppc_altivec_vextdubvrx v16i8:$vA,
2133                                                               v16i8:$vB,
2134                                                               i32:$rC))]>;
2135  def VEXTDUHVLX : VAForm_1a<26, (outs vrrc:$vD),
2136                             (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
2137                             "vextduhvlx $vD, $vA, $vB, $rC",
2138                             IIC_VecGeneral,
2139                             [(set v2i64:$vD,
2140                                   (int_ppc_altivec_vextduhvlx v8i16:$vA,
2141                                                               v8i16:$vB,
2142                                                               i32:$rC))]>;
2143  def VEXTDUHVRX : VAForm_1a<27, (outs vrrc:$vD),
2144                             (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
2145                             "vextduhvrx $vD, $vA, $vB, $rC",
2146                             IIC_VecGeneral,
2147                             [(set v2i64:$vD,
2148                                   (int_ppc_altivec_vextduhvrx v8i16:$vA,
2149                                                               v8i16:$vB,
2150                                                               i32:$rC))]>;
2151  def VEXTDUWVLX : VAForm_1a<28, (outs vrrc:$vD),
2152                             (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
2153                             "vextduwvlx $vD, $vA, $vB, $rC",
2154                             IIC_VecGeneral,
2155                             [(set v2i64:$vD,
2156                                   (int_ppc_altivec_vextduwvlx v4i32:$vA,
2157                                                               v4i32:$vB,
2158                                                               i32:$rC))]>;
2159  def VEXTDUWVRX : VAForm_1a<29, (outs vrrc:$vD),
2160                             (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
2161                             "vextduwvrx $vD, $vA, $vB, $rC",
2162                             IIC_VecGeneral,
2163                             [(set v2i64:$vD,
2164                                   (int_ppc_altivec_vextduwvrx v4i32:$vA,
2165                                                               v4i32:$vB,
2166                                                               i32:$rC))]>;
2167  def VEXTDDVLX : VAForm_1a<30, (outs vrrc:$vD),
2168                            (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
2169                            "vextddvlx $vD, $vA, $vB, $rC",
2170                            IIC_VecGeneral,
2171                            [(set v2i64:$vD,
2172                                  (int_ppc_altivec_vextddvlx v2i64:$vA,
2173                                                             v2i64:$vB,
2174                                                             i32:$rC))]>;
2175  def VEXTDDVRX : VAForm_1a<31, (outs vrrc:$vD),
2176                            (ins vrrc:$vA, vrrc:$vB, gprc:$rC),
2177                            "vextddvrx $vD, $vA, $vB, $rC",
2178                            IIC_VecGeneral,
2179                            [(set v2i64:$vD,
2180                                  (int_ppc_altivec_vextddvrx v2i64:$vA,
2181                                                             v2i64:$vB,
2182                                                             i32:$rC))]>;
2183   def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2184                         "vpdepd $vD, $vA, $vB", IIC_VecGeneral,
2185                         [(set v2i64:$vD,
2186                         (int_ppc_altivec_vpdepd v2i64:$vA, v2i64:$vB))]>;
2187   def VPEXTD : VXForm_1<1421, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2188                         "vpextd $vD, $vA, $vB", IIC_VecGeneral,
2189                         [(set v2i64:$vD,
2190                         (int_ppc_altivec_vpextd v2i64:$vA, v2i64:$vB))]>;
2191   def PDEPD : XForm_6<31, 156, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
2192                       "pdepd $rA, $rS, $rB", IIC_IntGeneral,
2193                       [(set i64:$rA, (int_ppc_pdepd i64:$rS, i64:$rB))]>;
2194   def PEXTD : XForm_6<31, 188, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
2195                       "pextd $rA, $rS, $rB", IIC_IntGeneral,
2196                       [(set i64:$rA, (int_ppc_pextd i64:$rS, i64:$rB))]>;
2197   def VCFUGED : VXForm_1<1357, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2198                          "vcfuged $vD, $vA, $vB", IIC_VecGeneral,
2199                          [(set v2i64:$vD,
2200                          (int_ppc_altivec_vcfuged v2i64:$vA, v2i64:$vB))]>;
2201   def VGNB : VXForm_RD5_N3_VB5<1228, (outs g8rc:$rD), (ins vrrc:$vB, u3imm:$N),
2202                                "vgnb $rD, $vB, $N", IIC_VecGeneral,
2203                                [(set i64:$rD,
2204                                (int_ppc_altivec_vgnb v1i128:$vB, timm:$N))]>;
2205   def CFUGED : XForm_6<31, 220, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
2206                        "cfuged $rA, $rS, $rB", IIC_IntGeneral,
2207                        [(set i64:$rA, (int_ppc_cfuged i64:$rS, i64:$rB))]>;
2208   def XXEVAL :
2209     8RR_XX4Form_IMM8_XTAB6<34, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
2210                            vsrc:$XC, u8imm:$IMM),
2211                            "xxeval $XT, $XA, $XB, $XC, $IMM", IIC_VecGeneral,
2212                            [(set v2i64:$XT, (int_ppc_vsx_xxeval v2i64:$XA,
2213                                  v2i64:$XB, v2i64:$XC, timm:$IMM))]>;
2214   def VCLZDM : VXForm_1<1924, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2215                         "vclzdm $vD, $vA, $vB", IIC_VecGeneral,
2216                         [(set v2i64:$vD,
2217                         (int_ppc_altivec_vclzdm v2i64:$vA, v2i64:$vB))]>;
2218   def VCTZDM : VXForm_1<1988, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2219                         "vctzdm $vD, $vA, $vB", IIC_VecGeneral,
2220                         [(set v2i64:$vD,
2221                         (int_ppc_altivec_vctzdm v2i64:$vA, v2i64:$vB))]>;
2222   def CNTLZDM : XForm_6<31, 59, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
2223                         "cntlzdm $rA, $rS, $rB", IIC_IntGeneral,
2224                         [(set i64:$rA,
2225                         (int_ppc_cntlzdm i64:$rS, i64:$rB))]>;
2226   def CNTTZDM : XForm_6<31, 571, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
2227                         "cnttzdm $rA, $rS, $rB", IIC_IntGeneral,
2228                         [(set i64:$rA,
2229                         (int_ppc_cnttzdm i64:$rS, i64:$rB))]>;
2230   def XXGENPCVBM :
2231     XForm_XT6_IMM5_VB5<60, 916, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
2232                        "xxgenpcvbm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
2233   def XXGENPCVHM :
2234     XForm_XT6_IMM5_VB5<60, 917, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
2235                        "xxgenpcvhm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
2236   def XXGENPCVWM :
2237     XForm_XT6_IMM5_VB5<60, 948, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
2238                        "xxgenpcvwm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
2239   def XXGENPCVDM :
2240     XForm_XT6_IMM5_VB5<60, 949, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
2241                        "xxgenpcvdm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
2242   def VCLRLB : VXForm_1<397, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
2243                         "vclrlb $vD, $vA, $rB", IIC_VecGeneral,
2244                         [(set v16i8:$vD,
2245                               (int_ppc_altivec_vclrlb v16i8:$vA, i32:$rB))]>;
2246   def VCLRRB : VXForm_1<461, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
2247                         "vclrrb $vD, $vA, $rB", IIC_VecGeneral,
2248                         [(set v16i8:$vD,
2249                               (int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
2250  def VMULLD : VXForm_1<457, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2251                        "vmulld $vD, $vA, $vB", IIC_VecGeneral,
2252                        [(set v2i64:$vD, (mul v2i64:$vA, v2i64:$vB))]>;
2253  def VMULHSW : VXForm_1<905, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2254                         "vmulhsw $vD, $vA, $vB", IIC_VecGeneral,
2255                         [(set v4i32:$vD, (mulhs v4i32:$vA, v4i32:$vB))]>;
2256  def VMULHUW : VXForm_1<649, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2257                         "vmulhuw $vD, $vA, $vB", IIC_VecGeneral,
2258                         [(set v4i32:$vD, (mulhu v4i32:$vA, v4i32:$vB))]>;
2259  def VMULHSD : VXForm_1<969, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2260                         "vmulhsd $vD, $vA, $vB", IIC_VecGeneral,
2261                         [(set v2i64:$vD, (mulhs v2i64:$vA, v2i64:$vB))]>;
2262  def VMULHUD : VXForm_1<713, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2263                         "vmulhud $vD, $vA, $vB", IIC_VecGeneral,
2264                         [(set v2i64:$vD, (mulhu v2i64:$vA, v2i64:$vB))]>;
2265  def VMODSW : VXForm_1<1931, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2266                        "vmodsw $vD, $vA, $vB", IIC_VecGeneral,
2267                        [(set v4i32:$vD, (srem v4i32:$vA, v4i32:$vB))]>;
2268  def VMODUW : VXForm_1<1675, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2269                        "vmoduw $vD, $vA, $vB", IIC_VecGeneral,
2270                        [(set v4i32:$vD, (urem v4i32:$vA, v4i32:$vB))]>;
2271  def VMODSD : VXForm_1<1995, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2272                        "vmodsd $vD, $vA, $vB", IIC_VecGeneral,
2273                        [(set v2i64:$vD, (srem v2i64:$vA, v2i64:$vB))]>;
2274  def VMODUD : VXForm_1<1739, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2275                        "vmodud $vD, $vA, $vB", IIC_VecGeneral,
2276                        [(set v2i64:$vD, (urem v2i64:$vA, v2i64:$vB))]>;
2277  def VDIVSW : VXForm_1<395, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2278                        "vdivsw $vD, $vA, $vB", IIC_VecGeneral,
2279                        [(set v4i32:$vD, (sdiv v4i32:$vA, v4i32:$vB))]>;
2280  def VDIVUW : VXForm_1<139, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2281                        "vdivuw $vD, $vA, $vB", IIC_VecGeneral,
2282                        [(set v4i32:$vD, (udiv v4i32:$vA, v4i32:$vB))]>;
2283  def VDIVSD : VXForm_1<459, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2284                        "vdivsd $vD, $vA, $vB", IIC_VecGeneral,
2285                        [(set v2i64:$vD, (sdiv v2i64:$vA, v2i64:$vB))]>;
2286  def VDIVUD : VXForm_1<203, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2287                        "vdivud $vD, $vA, $vB", IIC_VecGeneral,
2288                        [(set v2i64:$vD, (udiv v2i64:$vA, v2i64:$vB))]>;
2289  def VDIVESW : VXForm_1<907, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2290                         "vdivesw $vD, $vA, $vB", IIC_VecGeneral,
2291                         [(set v4i32:$vD, (int_ppc_altivec_vdivesw v4i32:$vA,
2292                               v4i32:$vB))]>;
2293  def VDIVEUW : VXForm_1<651, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2294                         "vdiveuw $vD, $vA, $vB", IIC_VecGeneral,
2295                         [(set v4i32:$vD, (int_ppc_altivec_vdiveuw v4i32:$vA,
2296                               v4i32:$vB))]>;
2297  def VDIVESD : VXForm_1<971, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2298                         "vdivesd $vD, $vA, $vB", IIC_VecGeneral,
2299                         [(set v2i64:$vD, (int_ppc_altivec_vdivesd v2i64:$vA,
2300                               v2i64:$vB))]>;
2301  def VDIVEUD : VXForm_1<715, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2302                         "vdiveud $vD, $vA, $vB", IIC_VecGeneral,
2303                         [(set v2i64:$vD, (int_ppc_altivec_vdiveud v2i64:$vA,
2304                               v2i64:$vB))]>;
2305  def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB),
2306                                    "xvtlsbb $BF, $XB", IIC_VecGeneral, []>;
2307
2308  // The XFormMemOp flag for the following 8 instructions is set on
2309  // the instruction format.
2310  let mayLoad = 1, mayStore = 0 in {
2311    def LXVRBX : X_XT6_RA5_RB5<31, 13, "lxvrbx", vsrc, []>;
2312    def LXVRHX : X_XT6_RA5_RB5<31, 45, "lxvrhx", vsrc, []>;
2313    def LXVRWX : X_XT6_RA5_RB5<31, 77, "lxvrwx", vsrc, []>;
2314    def LXVRDX : X_XT6_RA5_RB5<31, 109, "lxvrdx", vsrc, []>;
2315  }
2316
2317  let mayLoad = 0, mayStore = 1 in {
2318    def STXVRBX : X_XS6_RA5_RB5<31, 141, "stxvrbx", vsrc, []>;
2319    def STXVRHX : X_XS6_RA5_RB5<31, 173, "stxvrhx", vsrc, []>;
2320    def STXVRWX : X_XS6_RA5_RB5<31, 205, "stxvrwx", vsrc, []>;
2321    def STXVRDX : X_XS6_RA5_RB5<31, 237, "stxvrdx", vsrc, []>;
2322  }
2323
2324  def VMULESD : VXForm_1<968, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2325                         "vmulesd $vD, $vA, $vB", IIC_VecGeneral,
2326                         [(set v1i128:$vD, (int_ppc_altivec_vmulesd v2i64:$vA,
2327                               v2i64:$vB))]>;
2328  def VMULEUD : VXForm_1<712, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2329                         "vmuleud $vD, $vA, $vB", IIC_VecGeneral,
2330                         [(set v1i128:$vD, (int_ppc_altivec_vmuleud v2i64:$vA,
2331                               v2i64:$vB))]>;
2332  def VMULOSD : VXForm_1<456, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2333                         "vmulosd $vD, $vA, $vB", IIC_VecGeneral,
2334                         [(set v1i128:$vD, (int_ppc_altivec_vmulosd v2i64:$vA,
2335                               v2i64:$vB))]>;
2336  def VMULOUD : VXForm_1<200, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2337                         "vmuloud $vD, $vA, $vB", IIC_VecGeneral,
2338                         [(set v1i128:$vD, (int_ppc_altivec_vmuloud v2i64:$vA,
2339                               v2i64:$vB))]>;
2340  def VMSUMCUD : VAForm_1a<23, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
2341                           "vmsumcud $vD, $vA, $vB, $vC", IIC_VecGeneral,
2342                           [(set v1i128:$vD, (int_ppc_altivec_vmsumcud
2343                                 v2i64:$vA, v2i64:$vB, v1i128:$vC))]>;
2344  def VDIVSQ : VXForm_1<267, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2345                        "vdivsq $vD, $vA, $vB", IIC_VecGeneral,
2346                        [(set v1i128:$vD, (sdiv v1i128:$vA, v1i128:$vB))]>;
2347  def VDIVUQ : VXForm_1<11, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2348                        "vdivuq $vD, $vA, $vB", IIC_VecGeneral,
2349                        [(set v1i128:$vD, (udiv v1i128:$vA, v1i128:$vB))]>;
2350  def VDIVESQ : VXForm_1<779, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2351                         "vdivesq $vD, $vA, $vB", IIC_VecGeneral,
2352                         [(set v1i128:$vD, (int_ppc_altivec_vdivesq v1i128:$vA,
2353			       v1i128:$vB))]>;
2354  def VDIVEUQ : VXForm_1<523, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2355                         "vdiveuq $vD, $vA, $vB", IIC_VecGeneral,
2356                         [(set v1i128:$vD, (int_ppc_altivec_vdiveuq v1i128:$vA,
2357			       v1i128:$vB))]>;
2358  def VCMPEQUQ : VCMP <455, "vcmpequq $vD, $vA, $vB" , v1i128>;
2359  def VCMPGTSQ : VCMP <903, "vcmpgtsq $vD, $vA, $vB" , v1i128>;
2360  def VCMPGTUQ : VCMP <647, "vcmpgtuq $vD, $vA, $vB" , v1i128>;
2361  def VCMPEQUQ_rec : VCMP_rec <455, "vcmpequq. $vD, $vA, $vB" , v1i128>;
2362  def VCMPGTSQ_rec : VCMP_rec <903, "vcmpgtsq. $vD, $vA, $vB" , v1i128>;
2363  def VCMPGTUQ_rec : VCMP_rec <647, "vcmpgtuq. $vD, $vA, $vB" , v1i128>;
2364  def VMODSQ : VXForm_1<1803, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2365                        "vmodsq $vD, $vA, $vB", IIC_VecGeneral,
2366                        [(set v1i128:$vD, (srem v1i128:$vA, v1i128:$vB))]>;
2367  def VMODUQ : VXForm_1<1547, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
2368                        "vmoduq $vD, $vA, $vB", IIC_VecGeneral,
2369                        [(set v1i128:$vD, (urem v1i128:$vA, v1i128:$vB))]>;
2370  def VEXTSD2Q : VXForm_RD5_XO5_RS5<1538, 27, (outs vrrc:$vD), (ins vrrc:$vB),
2371                               "vextsd2q $vD, $vB", IIC_VecGeneral,
2372                               [(set v1i128:$vD, (int_ppc_altivec_vextsd2q v2i64:$vB))]>;
2373  def VCMPUQ : VXForm_BF3_VAB5<257, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB),
2374                               "vcmpuq $BF, $vA, $vB", IIC_VecGeneral, []>;
2375  def VCMPSQ : VXForm_BF3_VAB5<321, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB),
2376                               "vcmpsq $BF, $vA, $vB", IIC_VecGeneral, []>;
2377  def VRLQNM : VX1_VT5_VA5_VB5<325, "vrlqnm",
2378                               [(set v1i128:$vD,
2379                                   (int_ppc_altivec_vrlqnm v1i128:$vA,
2380                                                           v1i128:$vB))]>;
2381  def VRLQMI : VXForm_1<69, (outs vrrc:$vD),
2382                        (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi),
2383                        "vrlqmi $vD, $vA, $vB", IIC_VecFP,
2384                        [(set v1i128:$vD,
2385                          (int_ppc_altivec_vrlqmi v1i128:$vA, v1i128:$vB,
2386                                                  v1i128:$vDi))]>,
2387                        RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
2388  def VSLQ : VX1_VT5_VA5_VB5<261, "vslq", []>;
2389  def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>;
2390  def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>;
2391  def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>;
2392  def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>;
2393  def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>;
2394  def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>;
2395  def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>;
2396}
2397
2398let Predicates = [IsISA3_1, HasVSX] in {
2399  def XVCVSPBF16 : XX2_XT6_XO5_XB6<60, 17, 475, "xvcvspbf16", vsrc, []>;
2400  def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>;
2401  def XSMAXCQP : X_VT5_VA5_VB5<63, 676, "xsmaxcqp",
2402                               [(set f128:$vT, (PPCxsmaxc f128:$vA, f128:$vB))]>;
2403  def XSMINCQP : X_VT5_VA5_VB5<63, 740, "xsmincqp",
2404                               [(set f128:$vT, (PPCxsminc f128:$vA, f128:$vB))]>;
2405}
2406
2407// Multiclass defining patterns for Set Boolean Extension Reverse Instructions.
2408// This is analogous to the CRNotPat multiclass but specifically for Power10
2409// and newer subtargets since the extended forms use Set Boolean instructions.
2410// The first two anonymous patterns defined are actually a duplicate of those
2411// in CRNotPat, but it is preferable to define both multiclasses as complete
2412// ones rather than pulling that small common section out.
2413multiclass P10ReverseSetBool<dag pattern, dag result> {
2414  def : Pat<pattern, (crnot result)>;
2415  def : Pat<(not pattern), result>;
2416
2417  def : Pat<(i32 (zext pattern)),
2418            (SETBCR result)>;
2419  def : Pat<(i64 (zext pattern)),
2420            (SETBCR8 result)>;
2421
2422  def : Pat<(i32 (sext pattern)),
2423            (SETNBCR result)>;
2424  def : Pat<(i64 (sext pattern)),
2425            (SETNBCR8 result)>;
2426
2427  def : Pat<(i32 (anyext pattern)),
2428            (SETBCR result)>;
2429  def : Pat<(i64 (anyext pattern)),
2430            (SETBCR8 result)>;
2431}
2432
2433multiclass IntSetP10RevSetBool<SDNode SetCC, ValueType Ty, PatLeaf ZExtTy,
2434                               ImmLeaf SExtTy, I Cmpi, I Cmpli,
2435                               I Cmp, I Cmpl> {
2436  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
2437                           (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_lt)>;
2438  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
2439                           (EXTRACT_SUBREG (Cmp $s1, $s2), sub_lt)>;
2440  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
2441                           (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_gt)>;
2442  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
2443                           (EXTRACT_SUBREG (Cmp $s1, $s2), sub_gt)>;
2444  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
2445                           (EXTRACT_SUBREG (Cmp $s1, $s2), sub_eq)>;
2446
2447  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETUGE)),
2448                           (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_lt)>;
2449  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETGE)),
2450                           (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_lt)>;
2451  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETULE)),
2452                           (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_gt)>;
2453  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETLE)),
2454                           (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_gt)>;
2455  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETNE)),
2456                           (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_eq)>;
2457  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETNE)),
2458                           (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_eq)>;
2459}
2460
2461multiclass FSetP10RevSetBool<SDNode SetCC, ValueType Ty, I FCmp> {
2462  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
2463                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;
2464  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
2465                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;
2466  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
2467                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;
2468  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
2469                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;
2470  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)),
2471                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;
2472  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
2473                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;
2474  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)),
2475                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>;
2476}
2477
2478let Predicates = [IsISA3_1] in {
2479  def : Pat<(i32 (zext i1:$in)),
2480            (SETBC $in)>;
2481  def : Pat<(i64 (zext i1:$in)),
2482            (SETBC8 $in)>;
2483  def : Pat<(i32 (sext i1:$in)),
2484            (SETNBC $in)>;
2485  def : Pat<(i64 (sext i1:$in)),
2486            (SETNBC8 $in)>;
2487  def : Pat<(i32 (anyext i1:$in)),
2488            (SETBC $in)>;
2489  def : Pat<(i64 (anyext i1:$in)),
2490            (SETBC8 $in)>;
2491
2492  // Instantiation of the set boolean reverse patterns for 32-bit integers.
2493  defm : IntSetP10RevSetBool<setcc, i32, immZExt16, imm32SExt16,
2494                             CMPWI, CMPLWI, CMPW, CMPLW>;
2495  defm : P10ReverseSetBool<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
2496                           (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2497                                           (LO16 imm:$imm)), sub_eq)>;
2498
2499  // Instantiation of the set boolean reverse patterns for 64-bit integers.
2500  defm : IntSetP10RevSetBool<setcc, i64, immZExt16, imm64SExt16,
2501                             CMPDI, CMPLDI, CMPD, CMPLD>;
2502  defm : P10ReverseSetBool<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
2503                           (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
2504                                           (LO16 imm:$imm)), sub_eq)>;
2505}
2506
2507// Instantiation of the set boolean reverse patterns for f32, f64, f128.
2508let Predicates = [IsISA3_1, HasFPU] in {
2509  defm : FSetP10RevSetBool<setcc, f32, FCMPUS>;
2510  defm : FSetP10RevSetBool<setcc, f64, FCMPUD>;
2511  defm : FSetP10RevSetBool<setcc, f128, XSCMPUQP>;
2512}
2513
2514//---------------------------- Anonymous Patterns ----------------------------//
2515let Predicates = [IsISA3_1] in {
2516  // Exploit the vector multiply high instructions using intrinsics.
2517  def : Pat<(v4i32 (int_ppc_altivec_vmulhsw v4i32:$vA, v4i32:$vB)),
2518            (v4i32 (VMULHSW $vA, $vB))>;
2519  def : Pat<(v4i32 (int_ppc_altivec_vmulhuw v4i32:$vA, v4i32:$vB)),
2520            (v4i32 (VMULHUW $vA, $vB))>;
2521  def : Pat<(v2i64 (int_ppc_altivec_vmulhsd v2i64:$vA, v2i64:$vB)),
2522            (v2i64 (VMULHSD $vA, $vB))>;
2523  def : Pat<(v2i64 (int_ppc_altivec_vmulhud v2i64:$vA, v2i64:$vB)),
2524            (v2i64 (VMULHUD $vA, $vB))>;
2525  def : Pat<(v16i8 (int_ppc_vsx_xxgenpcvbm v16i8:$VRB, imm:$IMM)),
2526            (v16i8 (COPY_TO_REGCLASS (XXGENPCVBM $VRB, imm:$IMM), VRRC))>;
2527  def : Pat<(v8i16 (int_ppc_vsx_xxgenpcvhm v8i16:$VRB, imm:$IMM)),
2528            (v8i16 (COPY_TO_REGCLASS (XXGENPCVHM $VRB, imm:$IMM), VRRC))>;
2529  def : Pat<(v4i32 (int_ppc_vsx_xxgenpcvwm v4i32:$VRB, imm:$IMM)),
2530            (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>;
2531  def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)),
2532            (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>;
2533  def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 1)),
2534            (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>;
2535  def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)),
2536            (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
2537
2538  def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 8)),
2539             (v1i128 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VRRC))>;
2540  def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 16)),
2541             (v1i128 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VRRC))>;
2542  def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 32)),
2543             (v1i128 (COPY_TO_REGCLASS (LXVRWX ForceXForm:$src), VRRC))>;
2544  def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 64)),
2545             (v1i128 (COPY_TO_REGCLASS (LXVRDX ForceXForm:$src), VRRC))>;
2546
2547  def : Pat<(v1i128 (rotl v1i128:$vA, v1i128:$vB)),
2548            (v1i128 (VRLQ v1i128:$vA, v1i128:$vB))>;
2549
2550  def : Pat <(v2i64 (PPCxxsplti32dx v2i64:$XT, i32:$XI, i32:$IMM32)),
2551             (v2i64 (XXSPLTI32DX v2i64:$XT, i32:$XI, i32:$IMM32))>;
2552}
2553
2554let Predicates = [IsISA3_1, HasVSX] in {
2555  def : Pat<(v16i8 (int_ppc_vsx_xvcvspbf16 v16i8:$XA)),
2556            (COPY_TO_REGCLASS (XVCVSPBF16 RCCp.AToVSRC), VRRC)>;
2557  def : Pat<(v16i8 (int_ppc_vsx_xvcvbf16spn v16i8:$XA)),
2558            (COPY_TO_REGCLASS (XVCVBF16SPN RCCp.AToVSRC), VRRC)>;
2559}
2560
2561let AddedComplexity = 400, Predicates = [IsISA3_1, IsLittleEndian] in {
2562  // Store element 0 of a VSX register to memory
2563  def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$src, 0)), ForceXForm:$dst),
2564            (STXVRBX (COPY_TO_REGCLASS v16i8:$src, VSRC), ForceXForm:$dst)>;
2565  def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$src, 0)), ForceXForm:$dst),
2566            (STXVRHX (COPY_TO_REGCLASS v8i16:$src, VSRC), ForceXForm:$dst)>;
2567  def : Pat<(store (i32 (extractelt v4i32:$src, 0)), ForceXForm:$dst),
2568            (STXVRWX $src, ForceXForm:$dst)>;
2569  def : Pat<(store (f32 (extractelt v4f32:$src, 0)), ForceXForm:$dst),
2570            (STXVRWX $src, ForceXForm:$dst)>;
2571  def : Pat<(store (i64 (extractelt v2i64:$src, 0)), ForceXForm:$dst),
2572            (STXVRDX $src, ForceXForm:$dst)>;
2573  def : Pat<(store (f64 (extractelt v2f64:$src, 0)), ForceXForm:$dst),
2574            (STXVRDX $src, ForceXForm:$dst)>;
2575  // Load element 0 of a VSX register to memory
2576  def : Pat<(v8i16 (scalar_to_vector (i32 (extloadi16 ForceXForm:$src)))),
2577            (v8i16 (COPY_TO_REGCLASS (LXVRHX ForceXForm:$src), VSRC))>;
2578  def : Pat<(v16i8 (scalar_to_vector (i32 (extloadi8 ForceXForm:$src)))),
2579            (v16i8 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VSRC))>;
2580 }
2581
2582// FIXME: The swap is overkill when the shift amount is a constant.
2583// We should just fix the constant in the DAG.
2584let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in {
2585  def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)),
2586            (v1i128 (VSLQ v1i128:$VRA,
2587                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2588                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2589  def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)),
2590            (v1i128 (VSLQ v1i128:$VRA,
2591                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2592                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2593  def : Pat<(v1i128 (srl v1i128:$VRA, v1i128:$VRB)),
2594            (v1i128 (VSRQ v1i128:$VRA,
2595                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2596                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2597  def : Pat<(v1i128 (PPCsrl v1i128:$VRA, v1i128:$VRB)),
2598            (v1i128 (VSRQ v1i128:$VRA,
2599                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2600                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2601  def : Pat<(v1i128 (sra v1i128:$VRA, v1i128:$VRB)),
2602            (v1i128 (VSRAQ v1i128:$VRA,
2603                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2604                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2605  def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)),
2606            (v1i128 (VSRAQ v1i128:$VRA,
2607                     (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC),
2608                               (COPY_TO_REGCLASS $VRB, VSRC), 2)))>;
2609}
2610
2611class xxevalPattern <dag pattern, bits<8> imm> :
2612  Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)> {}
2613
2614let AddedComplexity = 400, Predicates = [PrefixInstrs] in {
2615 def : Pat<(v4i32 (build_vector i32immNonAllOneNonZero:$A,
2616                                i32immNonAllOneNonZero:$A,
2617                                i32immNonAllOneNonZero:$A,
2618                                i32immNonAllOneNonZero:$A)),
2619           (v4i32 (XXSPLTIW imm:$A))>;
2620 def : Pat<(f32 nzFPImmAsi32:$A),
2621           (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)),
2622                             VSFRC)>;
2623 def : Pat<(f64 nzFPImmAsi32:$A),
2624           (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)),
2625                             VSFRC)>;
2626
2627// To replace constant pool with XXSPLTI32DX for scalars.
2628def : Pat<(f32 nzFPImmAsi64:$A),
2629          (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX(IMPLICIT_DEF), 0,
2630                                        (getFPAs64BitIntHi $A)),
2631                                        1, (getFPAs64BitIntLo $A)),
2632                            VSSRC)>;
2633
2634def : Pat<(f64 nzFPImmAsi64:$A),
2635          (COPY_TO_REGCLASS (XXSPLTI32DX (XXSPLTI32DX (IMPLICIT_DEF), 0,
2636                                        (getFPAs64BitIntHi $A)),
2637                                        1, (getFPAs64BitIntLo $A)),
2638                            VSFRC)>;
2639
2640  // Anonymous patterns for XXEVAL
2641  // AND
2642  // and(A, B, C)
2643  def : xxevalPattern<(and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 1>;
2644  // and(A, xor(B, C))
2645  def : xxevalPattern<(and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 6>;
2646  // and(A, or(B, C))
2647  def : xxevalPattern<(and v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 7>;
2648  // and(A, nor(B, C))
2649  def : xxevalPattern<(and v4i32:$vA, (vnot (or v4i32:$vB, v4i32:$vC))), 8>;
2650  // and(A, eqv(B, C))
2651  def : xxevalPattern<(and v4i32:$vA, (vnot (xor v4i32:$vB, v4i32:$vC))), 9>;
2652  // and(A, nand(B, C))
2653  def : xxevalPattern<(and v4i32:$vA, (vnot (and v4i32:$vB, v4i32:$vC))), 14>;
2654
2655  // NAND
2656  // nand(A, B, C)
2657  def : xxevalPattern<(vnot (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))),
2658                       !sub(255, 1)>;
2659  // nand(A, xor(B, C))
2660  def : xxevalPattern<(vnot (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))),
2661                       !sub(255, 6)>;
2662  // nand(A, or(B, C))
2663  def : xxevalPattern<(vnot (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))),
2664                       !sub(255, 7)>;
2665  // nand(A, nor(B, C))
2666  def : xxevalPattern<(or (vnot v4i32:$vA), (or v4i32:$vB, v4i32:$vC)),
2667                       !sub(255, 8)>;
2668  // nand(A, eqv(B, C))
2669  def : xxevalPattern<(or (vnot v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)),
2670                       !sub(255, 9)>;
2671  // nand(A, nand(B, C))
2672  def : xxevalPattern<(or (vnot v4i32:$vA), (and v4i32:$vB, v4i32:$vC)),
2673                       !sub(255, 14)>;
2674
2675  // Anonymous patterns to select prefixed VSX loads and stores.
2676  // Load / Store f128
2677  def : Pat<(f128 (load PDForm:$src)),
2678            (COPY_TO_REGCLASS (PLXV memri34:$src), VRRC)>;
2679  def : Pat<(store f128:$XS, PDForm:$dst),
2680            (PSTXV (COPY_TO_REGCLASS $XS, VSRC), memri34:$dst)>;
2681
2682  // Load / Store v4i32
2683  def : Pat<(v4i32 (load PDForm:$src)), (PLXV memri34:$src)>;
2684  def : Pat<(store v4i32:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;
2685
2686  // Load / Store v2i64
2687  def : Pat<(v2i64 (load PDForm:$src)), (PLXV memri34:$src)>;
2688  def : Pat<(store v2i64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;
2689
2690  // Load / Store v4f32
2691  def : Pat<(v4f32 (load PDForm:$src)), (PLXV memri34:$src)>;
2692  def : Pat<(store v4f32:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;
2693
2694  // Load / Store v2f64
2695  def : Pat<(v2f64 (load PDForm:$src)), (PLXV memri34:$src)>;
2696  def : Pat<(store v2f64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;
2697
2698  // Cases For PPCstore_scal_int_from_vsr
2699  def : Pat<(PPCstore_scal_int_from_vsr
2700            (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), PDForm:$dst, 8),
2701            (PSTXSD (XSCVDPUXDS f64:$src), PDForm:$dst)>;
2702  def : Pat<(PPCstore_scal_int_from_vsr
2703            (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), PDForm:$dst, 8),
2704            (PSTXSD (XSCVDPSXDS f64:$src), PDForm:$dst)>;
2705  def : Pat<(PPCstore_scal_int_from_vsr
2706            (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), PDForm:$dst, 8),
2707            (PSTXSD (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC),
2708                     PDForm:$dst)>;
2709  def : Pat<(PPCstore_scal_int_from_vsr
2710            (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), PDForm:$dst, 8),
2711            (PSTXSD (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC),
2712                     PDForm:$dst)>;
2713}
2714
2715let Predicates = [PrefixInstrs] in {
2716  def : Pat<(i32 imm34:$imm), (PLI (getImmAs64BitInt imm:$imm))>;
2717  def : Pat<(i64 imm34:$imm), (PLI8 (getImmAs64BitInt imm:$imm))>;
2718  def : Pat<(v16i8 (int_ppc_vsx_xxpermx v16i8:$A, v16i8:$B, v16i8:$C, timm:$D)),
2719            (COPY_TO_REGCLASS (XXPERMX (COPY_TO_REGCLASS $A, VSRC),
2720                                       (COPY_TO_REGCLASS $B, VSRC),
2721                                       (COPY_TO_REGCLASS $C, VSRC), $D), VSRC)>;
2722  def : Pat<(v16i8 (int_ppc_vsx_xxblendvb v16i8:$A, v16i8:$B, v16i8:$C)),
2723            (COPY_TO_REGCLASS
2724                   (XXBLENDVB (COPY_TO_REGCLASS $A, VSRC),
2725                              (COPY_TO_REGCLASS $B, VSRC),
2726                              (COPY_TO_REGCLASS $C, VSRC)), VSRC)>;
2727  def : Pat<(v8i16 (int_ppc_vsx_xxblendvh v8i16:$A, v8i16:$B, v8i16:$C)),
2728            (COPY_TO_REGCLASS
2729                   (XXBLENDVH (COPY_TO_REGCLASS $A, VSRC),
2730                              (COPY_TO_REGCLASS $B, VSRC),
2731                              (COPY_TO_REGCLASS $C, VSRC)), VSRC)>;
2732  def : Pat<(int_ppc_vsx_xxblendvw v4i32:$A, v4i32:$B, v4i32:$C),
2733            (XXBLENDVW $A, $B, $C)>;
2734  def : Pat<(int_ppc_vsx_xxblendvd v2i64:$A, v2i64:$B, v2i64:$C),
2735            (XXBLENDVD $A, $B, $C)>;
2736
2737  // Anonymous patterns to select prefixed loads and stores.
2738  // Load i32
2739  def : Pat<(i32 (extloadi1 PDForm:$src)), (PLBZ memri34:$src)>;
2740  def : Pat<(i32 (zextloadi1 PDForm:$src)), (PLBZ memri34:$src)>;
2741  def : Pat<(i32 (extloadi8 PDForm:$src)), (PLBZ memri34:$src)>;
2742  def : Pat<(i32 (zextloadi8 PDForm:$src)), (PLBZ memri34:$src)>;
2743  def : Pat<(i32 (extloadi16 PDForm:$src)), (PLHZ memri34:$src)>;
2744  def : Pat<(i32 (zextloadi16 PDForm:$src)), (PLHZ memri34:$src)>;
2745  def : Pat<(i32 (sextloadi16 PDForm:$src)), (PLHA memri34:$src)>;
2746  def : Pat<(i32 (load PDForm:$src)), (PLWZ memri34:$src)>;
2747
2748  // Store i32
2749  def : Pat<(truncstorei8 i32:$rS, PDForm:$dst), (PSTB gprc:$rS, memri34:$dst)>;
2750  def : Pat<(truncstorei16 i32:$rS, PDForm:$dst), (PSTH gprc:$rS, memri34:$dst)>;
2751  def : Pat<(store i32:$rS, PDForm:$dst), (PSTW gprc:$rS, memri34:$dst)>;
2752
2753  // Load i64
2754  def : Pat<(i64 (extloadi1 PDForm:$src)), (PLBZ8 memri34:$src)>;
2755  def : Pat<(i64 (zextloadi1 PDForm:$src)), (PLBZ8 memri34:$src)>;
2756  def : Pat<(i64 (extloadi8 PDForm:$src)), (PLBZ8 memri34:$src)>;
2757  def : Pat<(i64 (zextloadi8 PDForm:$src)), (PLBZ8 memri34:$src)>;
2758  def : Pat<(i64 (extloadi16 PDForm:$src)), (PLHZ8 memri34:$src)>;
2759  def : Pat<(i64 (zextloadi16 PDForm:$src)), (PLHZ8 memri34:$src)>;
2760  def : Pat<(i64 (sextloadi16 PDForm:$src)), (PLHA8 memri34:$src)>;
2761  def : Pat<(i64 (extloadi32 PDForm:$src)), (PLWZ8 memri34:$src)>;
2762  def : Pat<(i64 (zextloadi32 PDForm:$src)), (PLWZ8 memri34:$src)>;
2763  def : Pat<(i64 (sextloadi32 PDForm:$src)), (PLWA8 memri34:$src)>;
2764  def : Pat<(i64 (load PDForm:$src)), (PLD memri34:$src)>;
2765
2766  // Store i64
2767  def : Pat<(truncstorei8 i64:$rS, PDForm:$dst), (PSTB8 g8rc:$rS, memri34:$dst)>;
2768  def : Pat<(truncstorei16 i64:$rS, PDForm:$dst), (PSTH8 g8rc:$rS, memri34:$dst)>;
2769  def : Pat<(truncstorei32 i64:$rS, PDForm:$dst), (PSTW8 g8rc:$rS, memri34:$dst)>;
2770  def : Pat<(store i64:$rS, PDForm:$dst), (PSTD g8rc:$rS, memri34:$dst)>;
2771
2772  // Load / Store f32
2773  def : Pat<(f32 (load PDForm:$src)), (PLFS memri34:$src)>;
2774  def : Pat<(store f32:$FRS, PDForm:$dst), (PSTFS $FRS, memri34:$dst)>;
2775
2776  // Load / Store f64
2777  def : Pat<(f64 (extloadf32 PDForm:$src)),
2778            (COPY_TO_REGCLASS (PLFS memri34:$src), VSFRC)>;
2779  def : Pat<(f64 (load PDForm:$src)), (PLFD memri34:$src)>;
2780  def : Pat<(store f64:$FRS, PDForm:$dst), (PSTFD $FRS, memri34:$dst)>;
2781
2782  // Atomic Load
2783  def : Pat<(atomic_load_8 PDForm:$src), (PLBZ memri34:$src)>;
2784  def : Pat<(atomic_load_16 PDForm:$src), (PLHZ memri34:$src)>;
2785  def : Pat<(atomic_load_32 PDForm:$src), (PLWZ memri34:$src)>;
2786  def : Pat<(atomic_load_64 PDForm:$src), (PLD memri34:$src)>;
2787
2788  // Atomic Store
2789  def : Pat<(atomic_store_8 PDForm:$dst, i32:$RS), (PSTB $RS, memri34:$dst)>;
2790  def : Pat<(atomic_store_16 PDForm:$dst, i32:$RS), (PSTH $RS, memri34:$dst)>;
2791  def : Pat<(atomic_store_32 PDForm:$dst, i32:$RS), (PSTW $RS, memri34:$dst)>;
2792  def : Pat<(atomic_store_64 PDForm:$dst, i64:$RS), (PSTD $RS, memri34:$dst)>;
2793
2794  // Prefixed fpext to v2f64
2795  def : Pat<(v4f32 (PPCldvsxlh PDForm:$src)),
2796            (SUBREG_TO_REG (i64 1), (PLFD PDForm:$src), sub_64)>;
2797}
2798
2799def InsertEltShift {
2800  dag Sub32 = (i32 (EXTRACT_SUBREG $rB, sub_32));
2801  dag Sub32Left1 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 1, 0, 30);
2802  dag Sub32Left2 = (RLWINM (EXTRACT_SUBREG $rB, sub_32), 2, 0, 29);
2803  dag Left1 = (RLWINM $rB, 1, 0, 30);
2804  dag Left2 = (RLWINM $rB, 2, 0, 29);
2805  dag Left3 = (RLWINM8 $rB, 3, 0, 28);
2806}
2807
2808let Predicates = [IsISA3_1, HasVSX, IsLittleEndian] in {
2809  // Indexed vector insert element
2810  def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i64:$rB)),
2811            (VINSBRX $vDi, InsertEltShift.Sub32, $rA)>;
2812  def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i64:$rB)),
2813            (VINSHRX $vDi, InsertEltShift.Sub32Left1, $rA)>;
2814  def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i64:$rB)),
2815            (VINSWRX $vDi, InsertEltShift.Sub32Left2, $rA)>;
2816  def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, i64:$rB)),
2817            (VINSDRX $vDi, InsertEltShift.Left3, $rA)>;
2818
2819  def : Pat<(v4f32 (insertelt v4f32:$vDi, f32:$rA, i64:$rB)),
2820            (VINSWVRX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>;
2821
2822  def : Pat<(v2f64 (insertelt v2f64:$vDi,  f64:$A, i64:$rB)),
2823            (VINSDRX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>;
2824  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load DSForm:$rA)), i64:$rB)),
2825            (VINSDRX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>;
2826  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load PDForm:$rA)), i64:$rB)),
2827            (VINSDRX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>;
2828  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load XForm:$rA)), i64:$rB)),
2829            (VINSDRX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>;
2830  let AddedComplexity = 400 in {
2831    // Immediate vector insert element
2832    foreach Idx = [0, 1, 2, 3] in {
2833      def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, Idx)),
2834                (VINSW $vDi, !mul(!sub(3, Idx), 4), $rA)>;
2835    }
2836    foreach i = [0, 1] in
2837     def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, (i64 i))),
2838               (VINSD $vDi, !mul(!sub(1, i), 8), $rA)>;
2839  }
2840}
2841
2842let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC32] in {
2843  // Indexed vector insert element
2844  def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i32:$rB)),
2845            (VINSBLX $vDi, $rB, $rA)>;
2846  def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i32:$rB)),
2847            (VINSHLX $vDi, InsertEltShift.Left1, $rA)>;
2848  def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i32:$rB)),
2849            (VINSWLX $vDi, InsertEltShift.Left2, $rA)>;
2850
2851  def : Pat<(v4f32 (insertelt v4f32:$vDi,  f32:$rA, i32:$rB)),
2852            (VINSWVLX $vDi, InsertEltShift.Left2, (XSCVDPSPN $rA))>;
2853}
2854
2855let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC64] in {
2856  // Indexed vector insert element
2857  def : Pat<(v16i8 (vector_insert v16i8:$vDi, i32:$rA, i64:$rB)),
2858            (VINSBLX $vDi, InsertEltShift.Sub32, $rA)>;
2859  def : Pat<(v8i16 (vector_insert v8i16:$vDi, i32:$rA, i64:$rB)),
2860            (VINSHLX $vDi, InsertEltShift.Sub32Left1, $rA)>;
2861  def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, i64:$rB)),
2862            (VINSWLX $vDi, InsertEltShift.Sub32Left2, $rA)>;
2863  def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, i64:$rB)),
2864            (VINSDLX $vDi, InsertEltShift.Left3, $rA)>;
2865
2866  def : Pat<(v4f32 (insertelt v4f32:$vDi,  f32:$rA, i64:$rB)),
2867            (VINSWVLX $vDi, InsertEltShift.Sub32Left2, (XSCVDPSPN $rA))>;
2868
2869  def : Pat<(v2f64 (insertelt v2f64:$vDi,  f64:$A, i64:$rB)),
2870            (VINSDLX $vDi, InsertEltShift.Left3, Bitcast.DblToLong)>;
2871  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load DSForm:$rA)), i64:$rB)),
2872            (VINSDLX $vDi, InsertEltShift.Left3, (LD memrix:$rA))>;
2873  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load PDForm:$rA)), i64:$rB)),
2874            (VINSDLX $vDi, InsertEltShift.Left3, (PLD memri34:$rA))>;
2875  def : Pat<(v2f64 (insertelt v2f64:$vDi, (f64 (load XForm:$rA)), i64:$rB)),
2876            (VINSDLX $vDi, InsertEltShift.Left3, (LDX memrr:$rA))>;
2877}
2878
2879let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX, IsBigEndian] in {
2880  // Immediate vector insert element
2881  foreach Ty = [i32, i64] in {
2882    foreach Idx = [0, 1, 2, 3] in {
2883      def : Pat<(v4i32 (insertelt v4i32:$vDi, i32:$rA, (Ty Idx))),
2884               (VINSW $vDi, !mul(Idx, 4), $rA)>;
2885    }
2886  }
2887
2888  foreach Idx = [0, 1] in
2889    def : Pat<(v2i64 (insertelt v2i64:$vDi, i64:$rA, Idx)),
2890              (VINSD $vDi, !mul(Idx, 8), $rA)>;
2891}
2892