1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the subset of the 32-bit PowerPC instruction set, as used
11// by the PowerPC instruction selector.
12//
13//===----------------------------------------------------------------------===//
14
15include "PPCInstrFormats.td"
16
17//===----------------------------------------------------------------------===//
18// PowerPC specific type constraints.
19//
20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21  SDTCisVT<0, f64>, SDTCisPtrTy<1>
22]>;
23def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24  SDTCisVT<0, f64>, SDTCisPtrTy<1>
25]>;
26
27def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28def SDT_PPCCallSeqEnd   : SDCallSeqEnd<[ SDTCisVT<0, i32>,
29                                         SDTCisVT<1, i32> ]>;
30def SDT_PPCvperm   : SDTypeProfile<1, 3, [
31  SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
32]>;
33
34def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>,
35  SDTCisVec<1>, SDTCisInt<2>
36]>;
37
38def SDT_PPCvcmp : SDTypeProfile<1, 3, [
39  SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
40]>;
41
42def SDT_PPCcondbr : SDTypeProfile<0, 3, [
43  SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
44]>;
45
46def SDT_PPClbrx : SDTypeProfile<1, 2, [
47  SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
48]>;
49def SDT_PPCstbrx : SDTypeProfile<0, 3, [
50  SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
51]>;
52
53def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
54  SDTCisPtrTy<0>, SDTCisVT<1, i32>
55]>;
56
57def tocentry32 : Operand<iPTR> {
58  let MIOperandInfo = (ops i32imm:$imm);
59}
60
61def SDT_PPCqvfperm   : SDTypeProfile<1, 3, [
62  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3>
63]>;
64def SDT_PPCqvgpci   : SDTypeProfile<1, 1, [
65  SDTCisVec<0>, SDTCisInt<1>
66]>;
67def SDT_PPCqvaligni   : SDTypeProfile<1, 3, [
68  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>
69]>;
70def SDT_PPCqvesplati   : SDTypeProfile<1, 2, [
71  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>
72]>;
73
74def SDT_PPCqbflt : SDTypeProfile<1, 1, [
75  SDTCisVec<0>, SDTCisVec<1>
76]>;
77
78def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [
79  SDTCisVec<0>, SDTCisPtrTy<1>
80]>;
81
82//===----------------------------------------------------------------------===//
83// PowerPC specific DAG Nodes.
84//
85
86def PPCfre    : SDNode<"PPCISD::FRE",     SDTFPUnaryOp, []>;
87def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
88
89def PPCfcfid  : SDNode<"PPCISD::FCFID",   SDTFPUnaryOp, []>;
90def PPCfcfidu : SDNode<"PPCISD::FCFIDU",  SDTFPUnaryOp, []>;
91def PPCfcfids : SDNode<"PPCISD::FCFIDS",  SDTFPRoundOp, []>;
92def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
93def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
94def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
95def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
96def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
97def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
98                       [SDNPHasChain, SDNPMayStore]>;
99def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
100                       [SDNPHasChain, SDNPMayLoad]>;
101def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
102                       [SDNPHasChain, SDNPMayLoad]>;
103
104// Extract FPSCR (not modeled at the DAG level).
105def PPCmffs   : SDNode<"PPCISD::MFFS",
106                       SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
107
108// Perform FADD in round-to-zero mode.
109def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
110
111
112def PPCfsel   : SDNode<"PPCISD::FSEL",
113   // Type constraint for fsel.
114   SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
115                        SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
116
117def PPChi       : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
118def PPClo       : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
119def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp,
120                         [SDNPMayLoad, SDNPMemOperand]>;
121def PPCvmaddfp  : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
122def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
123
124def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
125
126def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
127def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
128                            [SDNPMayLoad]>;
129def PPCaddTls     : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
130def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
131def PPCaddiTlsgdL   : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
132def PPCgetTlsAddr   : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
133def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR",
134                               SDTypeProfile<1, 3, [
135                                 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
136                                 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
137def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
138def PPCaddiTlsldL   : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
139def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
140def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR",
141                               SDTypeProfile<1, 3, [
142                                 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
143                                 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
144def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;
145def PPCaddiDtprelL   : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
146
147def PPCvperm    : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
148def PPCxxsplt    : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>;
149
150def PPCqvfperm   : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>;
151def PPCqvgpci    : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>;
152def PPCqvaligni  : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>;
153def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>;
154
155def PPCqbflt     : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>;
156
157def PPCqvlfsb    : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb,
158                          [SDNPHasChain, SDNPMayLoad]>;
159
160def PPCcmpb     : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>;
161
162// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
163// amounts.  These nodes are generated by the multi-precision shift code.
164def PPCsrl        : SDNode<"PPCISD::SRL"       , SDTIntShiftOp>;
165def PPCsra        : SDNode<"PPCISD::SRA"       , SDTIntShiftOp>;
166def PPCshl        : SDNode<"PPCISD::SHL"       , SDTIntShiftOp>;
167
168// These are target-independent nodes, but have target-specific formats.
169def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
170                           [SDNPHasChain, SDNPOutGlue]>;
171def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_PPCCallSeqEnd,
172                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
173
174def SDT_PPCCall   : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
175def PPCcall  : SDNode<"PPCISD::CALL", SDT_PPCCall,
176                      [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
177                       SDNPVariadic]>;
178def PPCcall_nop  : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
179                          [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
180                           SDNPVariadic]>;
181def PPCmtctr      : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
182                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
183def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
184                      [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
185                       SDNPVariadic]>;
186def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC",
187                               SDTypeProfile<0, 1, []>,
188                               [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
189                                SDNPVariadic]>;
190
191def retflag       : SDNode<"PPCISD::RET_FLAG", SDTNone,
192                           [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
193
194def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
195                        [SDNPHasChain,  SDNPOptInGlue, SDNPVariadic]>;
196
197def PPCeh_sjlj_setjmp  : SDNode<"PPCISD::EH_SJLJ_SETJMP",
198                                SDTypeProfile<1, 1, [SDTCisInt<0>,
199                                                     SDTCisPtrTy<1>]>,
200                                [SDNPHasChain, SDNPSideEffect]>;
201def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
202                                SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
203                                [SDNPHasChain, SDNPSideEffect]>;
204
205def SDT_PPCsc     : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
206def PPCsc         : SDNode<"PPCISD::SC", SDT_PPCsc,
207                           [SDNPHasChain, SDNPSideEffect]>;
208
209def PPCclrbhrb    : SDNode<"PPCISD::CLRBHRB", SDTNone,
210                           [SDNPHasChain, SDNPSideEffect]>;
211def PPCmfbhrbe    : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>;
212def PPCrfebb      : SDNode<"PPCISD::RFEBB", SDT_PPCsc,
213                           [SDNPHasChain, SDNPSideEffect]>;
214
215def PPCvcmp       : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
216def PPCvcmp_o     : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
217
218def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
219                           [SDNPHasChain, SDNPOptInGlue]>;
220
221def PPClbrx       : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
222                           [SDNPHasChain, SDNPMayLoad]>;
223def PPCstbrx      : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
224                           [SDNPHasChain, SDNPMayStore]>;
225
226// Instructions to set/unset CR bit 6 for SVR4 vararg calls
227def PPCcr6set   : SDNode<"PPCISD::CR6SET", SDTNone,
228                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
229def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
230                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
231
232// Instructions to support dynamic alloca.
233def SDTDynOp  : SDTypeProfile<1, 2, []>;
234def SDTDynAreaOp  : SDTypeProfile<1, 1, []>;
235def PPCdynalloc   : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
236def PPCdynareaoffset   : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>;
237
238//===----------------------------------------------------------------------===//
239// PowerPC specific transformation functions and pattern fragments.
240//
241
242def SHL32 : SDNodeXForm<imm, [{
243  // Transformation function: 31 - imm
244  return getI32Imm(31 - N->getZExtValue(), SDLoc(N));
245}]>;
246
247def SRL32 : SDNodeXForm<imm, [{
248  // Transformation function: 32 - imm
249  return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N))
250                           : getI32Imm(0, SDLoc(N));
251}]>;
252
253def LO16 : SDNodeXForm<imm, [{
254  // Transformation function: get the low 16 bits.
255  return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N));
256}]>;
257
258def HI16 : SDNodeXForm<imm, [{
259  // Transformation function: shift the immediate value down into the low bits.
260  return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N));
261}]>;
262
263def HA16 : SDNodeXForm<imm, [{
264  // Transformation function: shift the immediate value down into the low bits.
265  int Val = N->getZExtValue();
266  return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N));
267}]>;
268def MB : SDNodeXForm<imm, [{
269  // Transformation function: get the start bit of a mask
270  unsigned mb = 0, me;
271  (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
272  return getI32Imm(mb, SDLoc(N));
273}]>;
274
275def ME : SDNodeXForm<imm, [{
276  // Transformation function: get the end bit of a mask
277  unsigned mb, me = 0;
278  (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
279  return getI32Imm(me, SDLoc(N));
280}]>;
281def maskimm32 : PatLeaf<(imm), [{
282  // maskImm predicate - True if immediate is a run of ones.
283  unsigned mb, me;
284  if (N->getValueType(0) == MVT::i32)
285    return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
286  else
287    return false;
288}]>;
289
290def imm32SExt16  : Operand<i32>, ImmLeaf<i32, [{
291  // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
292  // sign extended field.  Used by instructions like 'addi'.
293  return (int32_t)Imm == (short)Imm;
294}]>;
295def imm64SExt16  : Operand<i64>, ImmLeaf<i64, [{
296  // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
297  // sign extended field.  Used by instructions like 'addi'.
298  return (int64_t)Imm == (short)Imm;
299}]>;
300def immZExt16  : PatLeaf<(imm), [{
301  // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
302  // field.  Used by instructions like 'ori'.
303  return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
304}], LO16>;
305
306// imm16Shifted* - These match immediates where the low 16-bits are zero.  There
307// are two forms: imm16ShiftedSExt and imm16ShiftedZExt.  These two forms are
308// identical in 32-bit mode, but in 64-bit mode, they return true if the
309// immediate fits into a sign/zero extended 32-bit immediate (with the low bits
310// clear).
311def imm16ShiftedZExt : PatLeaf<(imm), [{
312  // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
313  // immediate are set.  Used by instructions like 'xoris'.
314  return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
315}], HI16>;
316
317def imm16ShiftedSExt : PatLeaf<(imm), [{
318  // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
319  // immediate are set.  Used by instructions like 'addis'.  Identical to
320  // imm16ShiftedZExt in 32-bit mode.
321  if (N->getZExtValue() & 0xFFFF) return false;
322  if (N->getValueType(0) == MVT::i32)
323    return true;
324  // For 64-bit, make sure it is sext right.
325  return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
326}], HI16>;
327
328def imm64ZExt32  : Operand<i64>, ImmLeaf<i64, [{
329  // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
330  // zero extended field.
331  return isUInt<32>(Imm);
332}]>;
333
334// Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
335// restricted memrix (4-aligned) constants are alignment sensitive. If these
336// offsets are hidden behind TOC entries than the values of the lower-order
337// bits cannot be checked directly. As a result, we need to also incorporate
338// an alignment check into the relevant patterns.
339
340def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
341  return cast<LoadSDNode>(N)->getAlignment() >= 4;
342}]>;
343def aligned4store : PatFrag<(ops node:$val, node:$ptr),
344                            (store node:$val, node:$ptr), [{
345  return cast<StoreSDNode>(N)->getAlignment() >= 4;
346}]>;
347def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
348  return cast<LoadSDNode>(N)->getAlignment() >= 4;
349}]>;
350def aligned4pre_store : PatFrag<
351                          (ops node:$val, node:$base, node:$offset),
352                          (pre_store node:$val, node:$base, node:$offset), [{
353  return cast<StoreSDNode>(N)->getAlignment() >= 4;
354}]>;
355
356def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
357  return cast<LoadSDNode>(N)->getAlignment() < 4;
358}]>;
359def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
360                              (store node:$val, node:$ptr), [{
361  return cast<StoreSDNode>(N)->getAlignment() < 4;
362}]>;
363def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
364  return cast<LoadSDNode>(N)->getAlignment() < 4;
365}]>;
366
367//===----------------------------------------------------------------------===//
368// PowerPC Flag Definitions.
369
370class isPPC64 { bit PPC64 = 1; }
371class isDOT   { bit RC = 1; }
372
373class RegConstraint<string C> {
374  string Constraints = C;
375}
376class NoEncode<string E> {
377  string DisableEncoding = E;
378}
379
380
381//===----------------------------------------------------------------------===//
382// PowerPC Operand Definitions.
383
384// In the default PowerPC assembler syntax, registers are specified simply
385// by number, so they cannot be distinguished from immediate values (without
386// looking at the opcode).  This means that the default operand matching logic
387// for the asm parser does not work, and we need to specify custom matchers.
388// Since those can only be specified with RegisterOperand classes and not
389// directly on the RegisterClass, all instructions patterns used by the asm
390// parser need to use a RegisterOperand (instead of a RegisterClass) for
391// all their register operands.
392// For this purpose, we define one RegisterOperand for each RegisterClass,
393// using the same name as the class, just in lower case.
394
395def PPCRegGPRCAsmOperand : AsmOperandClass {
396  let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
397}
398def gprc : RegisterOperand<GPRC> {
399  let ParserMatchClass = PPCRegGPRCAsmOperand;
400}
401def PPCRegG8RCAsmOperand : AsmOperandClass {
402  let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
403}
404def g8rc : RegisterOperand<G8RC> {
405  let ParserMatchClass = PPCRegG8RCAsmOperand;
406}
407def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
408  let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
409}
410def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
411  let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
412}
413def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
414  let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
415}
416def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
417  let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
418}
419def PPCRegF8RCAsmOperand : AsmOperandClass {
420  let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
421}
422def f8rc : RegisterOperand<F8RC> {
423  let ParserMatchClass = PPCRegF8RCAsmOperand;
424}
425def PPCRegF4RCAsmOperand : AsmOperandClass {
426  let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
427}
428def f4rc : RegisterOperand<F4RC> {
429  let ParserMatchClass = PPCRegF4RCAsmOperand;
430}
431def PPCRegVRRCAsmOperand : AsmOperandClass {
432  let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
433}
434def vrrc : RegisterOperand<VRRC> {
435  let ParserMatchClass = PPCRegVRRCAsmOperand;
436}
437def PPCRegCRBITRCAsmOperand : AsmOperandClass {
438  let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
439}
440def crbitrc : RegisterOperand<CRBITRC> {
441  let ParserMatchClass = PPCRegCRBITRCAsmOperand;
442}
443def PPCRegCRRCAsmOperand : AsmOperandClass {
444  let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
445}
446def crrc : RegisterOperand<CRRC> {
447  let ParserMatchClass = PPCRegCRRCAsmOperand;
448}
449def crrc0 : RegisterOperand<CRRC0> {
450  let ParserMatchClass = PPCRegCRRCAsmOperand;
451}
452
453def PPCU1ImmAsmOperand : AsmOperandClass {
454  let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
455  let RenderMethod = "addImmOperands";
456}
457def u1imm   : Operand<i32> {
458  let PrintMethod = "printU1ImmOperand";
459  let ParserMatchClass = PPCU1ImmAsmOperand;
460}
461
462def PPCU2ImmAsmOperand : AsmOperandClass {
463  let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
464  let RenderMethod = "addImmOperands";
465}
466def u2imm   : Operand<i32> {
467  let PrintMethod = "printU2ImmOperand";
468  let ParserMatchClass = PPCU2ImmAsmOperand;
469}
470
471def PPCU3ImmAsmOperand : AsmOperandClass {
472  let Name = "U3Imm"; let PredicateMethod = "isU3Imm";
473  let RenderMethod = "addImmOperands";
474}
475def u3imm   : Operand<i32> {
476  let PrintMethod = "printU3ImmOperand";
477  let ParserMatchClass = PPCU3ImmAsmOperand;
478}
479
480def PPCU4ImmAsmOperand : AsmOperandClass {
481  let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
482  let RenderMethod = "addImmOperands";
483}
484def u4imm   : Operand<i32> {
485  let PrintMethod = "printU4ImmOperand";
486  let ParserMatchClass = PPCU4ImmAsmOperand;
487}
488def PPCS5ImmAsmOperand : AsmOperandClass {
489  let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
490  let RenderMethod = "addImmOperands";
491}
492def s5imm   : Operand<i32> {
493  let PrintMethod = "printS5ImmOperand";
494  let ParserMatchClass = PPCS5ImmAsmOperand;
495  let DecoderMethod = "decodeSImmOperand<5>";
496}
497def PPCU5ImmAsmOperand : AsmOperandClass {
498  let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
499  let RenderMethod = "addImmOperands";
500}
501def u5imm   : Operand<i32> {
502  let PrintMethod = "printU5ImmOperand";
503  let ParserMatchClass = PPCU5ImmAsmOperand;
504  let DecoderMethod = "decodeUImmOperand<5>";
505}
506def PPCU6ImmAsmOperand : AsmOperandClass {
507  let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
508  let RenderMethod = "addImmOperands";
509}
510def u6imm   : Operand<i32> {
511  let PrintMethod = "printU6ImmOperand";
512  let ParserMatchClass = PPCU6ImmAsmOperand;
513  let DecoderMethod = "decodeUImmOperand<6>";
514}
515def PPCU7ImmAsmOperand : AsmOperandClass {
516  let Name = "U7Imm"; let PredicateMethod = "isU7Imm";
517  let RenderMethod = "addImmOperands";
518}
519def u7imm   : Operand<i32> {
520  let PrintMethod = "printU7ImmOperand";
521  let ParserMatchClass = PPCU7ImmAsmOperand;
522  let DecoderMethod = "decodeUImmOperand<7>";
523}
524def PPCU8ImmAsmOperand : AsmOperandClass {
525  let Name = "U8Imm"; let PredicateMethod = "isU8Imm";
526  let RenderMethod = "addImmOperands";
527}
528def u8imm   : Operand<i32> {
529  let PrintMethod = "printU8ImmOperand";
530  let ParserMatchClass = PPCU8ImmAsmOperand;
531  let DecoderMethod = "decodeUImmOperand<8>";
532}
533def PPCU10ImmAsmOperand : AsmOperandClass {
534  let Name = "U10Imm"; let PredicateMethod = "isU10Imm";
535  let RenderMethod = "addImmOperands";
536}
537def u10imm  : Operand<i32> {
538  let PrintMethod = "printU10ImmOperand";
539  let ParserMatchClass = PPCU10ImmAsmOperand;
540  let DecoderMethod = "decodeUImmOperand<10>";
541}
542def PPCU12ImmAsmOperand : AsmOperandClass {
543  let Name = "U12Imm"; let PredicateMethod = "isU12Imm";
544  let RenderMethod = "addImmOperands";
545}
546def u12imm  : Operand<i32> {
547  let PrintMethod = "printU12ImmOperand";
548  let ParserMatchClass = PPCU12ImmAsmOperand;
549  let DecoderMethod = "decodeUImmOperand<12>";
550}
551def PPCS16ImmAsmOperand : AsmOperandClass {
552  let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
553  let RenderMethod = "addS16ImmOperands";
554}
555def s16imm  : Operand<i32> {
556  let PrintMethod = "printS16ImmOperand";
557  let EncoderMethod = "getImm16Encoding";
558  let ParserMatchClass = PPCS16ImmAsmOperand;
559  let DecoderMethod = "decodeSImmOperand<16>";
560}
561def PPCU16ImmAsmOperand : AsmOperandClass {
562  let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
563  let RenderMethod = "addU16ImmOperands";
564}
565def u16imm  : Operand<i32> {
566  let PrintMethod = "printU16ImmOperand";
567  let EncoderMethod = "getImm16Encoding";
568  let ParserMatchClass = PPCU16ImmAsmOperand;
569  let DecoderMethod = "decodeUImmOperand<16>";
570}
571def PPCS17ImmAsmOperand : AsmOperandClass {
572  let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
573  let RenderMethod = "addS16ImmOperands";
574}
575def s17imm  : Operand<i32> {
576  // This operand type is used for addis/lis to allow the assembler parser
577  // to accept immediates in the range -65536..65535 for compatibility with
578  // the GNU assembler.  The operand is treated as 16-bit otherwise.
579  let PrintMethod = "printS16ImmOperand";
580  let EncoderMethod = "getImm16Encoding";
581  let ParserMatchClass = PPCS17ImmAsmOperand;
582  let DecoderMethod = "decodeSImmOperand<16>";
583}
584def PPCDirectBrAsmOperand : AsmOperandClass {
585  let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
586  let RenderMethod = "addBranchTargetOperands";
587}
588def directbrtarget : Operand<OtherVT> {
589  let PrintMethod = "printBranchOperand";
590  let EncoderMethod = "getDirectBrEncoding";
591  let ParserMatchClass = PPCDirectBrAsmOperand;
592}
593def absdirectbrtarget : Operand<OtherVT> {
594  let PrintMethod = "printAbsBranchOperand";
595  let EncoderMethod = "getAbsDirectBrEncoding";
596  let ParserMatchClass = PPCDirectBrAsmOperand;
597}
598def PPCCondBrAsmOperand : AsmOperandClass {
599  let Name = "CondBr"; let PredicateMethod = "isCondBr";
600  let RenderMethod = "addBranchTargetOperands";
601}
602def condbrtarget : Operand<OtherVT> {
603  let PrintMethod = "printBranchOperand";
604  let EncoderMethod = "getCondBrEncoding";
605  let ParserMatchClass = PPCCondBrAsmOperand;
606}
607def abscondbrtarget : Operand<OtherVT> {
608  let PrintMethod = "printAbsBranchOperand";
609  let EncoderMethod = "getAbsCondBrEncoding";
610  let ParserMatchClass = PPCCondBrAsmOperand;
611}
612def calltarget : Operand<iPTR> {
613  let PrintMethod = "printBranchOperand";
614  let EncoderMethod = "getDirectBrEncoding";
615  let ParserMatchClass = PPCDirectBrAsmOperand;
616}
617def abscalltarget : Operand<iPTR> {
618  let PrintMethod = "printAbsBranchOperand";
619  let EncoderMethod = "getAbsDirectBrEncoding";
620  let ParserMatchClass = PPCDirectBrAsmOperand;
621}
622def PPCCRBitMaskOperand : AsmOperandClass {
623 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
624}
625def crbitm: Operand<i8> {
626  let PrintMethod = "printcrbitm";
627  let EncoderMethod = "get_crbitm_encoding";
628  let DecoderMethod = "decodeCRBitMOperand";
629  let ParserMatchClass = PPCCRBitMaskOperand;
630}
631// Address operands
632// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
633def PPCRegGxRCNoR0Operand : AsmOperandClass {
634  let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
635}
636def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
637  let ParserMatchClass = PPCRegGxRCNoR0Operand;
638}
639// A version of ptr_rc usable with the asm parser.
640def PPCRegGxRCOperand : AsmOperandClass {
641  let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
642}
643def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
644  let ParserMatchClass = PPCRegGxRCOperand;
645}
646
647def PPCDispRIOperand : AsmOperandClass {
648 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
649 let RenderMethod = "addS16ImmOperands";
650}
651def dispRI : Operand<iPTR> {
652  let ParserMatchClass = PPCDispRIOperand;
653}
654def PPCDispRIXOperand : AsmOperandClass {
655 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
656 let RenderMethod = "addImmOperands";
657}
658def dispRIX : Operand<iPTR> {
659  let ParserMatchClass = PPCDispRIXOperand;
660}
661def PPCDispRIX16Operand : AsmOperandClass {
662 let Name = "DispRIX16"; let PredicateMethod = "isS16ImmX16";
663 let RenderMethod = "addImmOperands";
664}
665def dispRIX16 : Operand<iPTR> {
666  let ParserMatchClass = PPCDispRIX16Operand;
667}
668def PPCDispSPE8Operand : AsmOperandClass {
669 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
670 let RenderMethod = "addImmOperands";
671}
672def dispSPE8 : Operand<iPTR> {
673  let ParserMatchClass = PPCDispSPE8Operand;
674}
675def PPCDispSPE4Operand : AsmOperandClass {
676 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
677 let RenderMethod = "addImmOperands";
678}
679def dispSPE4 : Operand<iPTR> {
680  let ParserMatchClass = PPCDispSPE4Operand;
681}
682def PPCDispSPE2Operand : AsmOperandClass {
683 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
684 let RenderMethod = "addImmOperands";
685}
686def dispSPE2 : Operand<iPTR> {
687  let ParserMatchClass = PPCDispSPE2Operand;
688}
689
690def memri : Operand<iPTR> {
691  let PrintMethod = "printMemRegImm";
692  let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
693  let EncoderMethod = "getMemRIEncoding";
694  let DecoderMethod = "decodeMemRIOperands";
695}
696def memrr : Operand<iPTR> {
697  let PrintMethod = "printMemRegReg";
698  let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
699}
700def memrix : Operand<iPTR> {   // memri where the imm is 4-aligned.
701  let PrintMethod = "printMemRegImm";
702  let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
703  let EncoderMethod = "getMemRIXEncoding";
704  let DecoderMethod = "decodeMemRIXOperands";
705}
706def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16:27}
707  let PrintMethod = "printMemRegImm";
708  let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg);
709  let EncoderMethod = "getMemRIX16Encoding";
710  let DecoderMethod = "decodeMemRIX16Operands";
711}
712def spe8dis : Operand<iPTR> {   // SPE displacement where the imm is 8-aligned.
713  let PrintMethod = "printMemRegImm";
714  let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
715  let EncoderMethod = "getSPE8DisEncoding";
716}
717def spe4dis : Operand<iPTR> {   // SPE displacement where the imm is 4-aligned.
718  let PrintMethod = "printMemRegImm";
719  let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
720  let EncoderMethod = "getSPE4DisEncoding";
721}
722def spe2dis : Operand<iPTR> {   // SPE displacement where the imm is 2-aligned.
723  let PrintMethod = "printMemRegImm";
724  let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
725  let EncoderMethod = "getSPE2DisEncoding";
726}
727
728// A single-register address. This is used with the SjLj
729// pseudo-instructions.
730def memr : Operand<iPTR> {
731  let MIOperandInfo = (ops ptr_rc:$ptrreg);
732}
733def PPCTLSRegOperand : AsmOperandClass {
734  let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
735  let RenderMethod = "addTLSRegOperands";
736}
737def tlsreg32 : Operand<i32> {
738  let EncoderMethod = "getTLSRegEncoding";
739  let ParserMatchClass = PPCTLSRegOperand;
740}
741def tlsgd32 : Operand<i32> {}
742def tlscall32 : Operand<i32> {
743  let PrintMethod = "printTLSCall";
744  let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
745  let EncoderMethod = "getTLSCallEncoding";
746}
747
748// PowerPC Predicate operand.
749def pred : Operand<OtherVT> {
750  let PrintMethod = "printPredicateOperand";
751  let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
752}
753
754// Define PowerPC specific addressing mode.
755def iaddr  : ComplexPattern<iPTR, 2, "SelectAddrImm",    [], []>;
756def xaddr  : ComplexPattern<iPTR, 2, "SelectAddrIdx",    [], []>;
757def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
758def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4",  [], []>; // "std"
759
760// The address in a single register. This is used with the SjLj
761// pseudo-instructions.
762def addr   : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
763
764/// This is just the offset part of iaddr, used for preinc.
765def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
766
767//===----------------------------------------------------------------------===//
768// PowerPC Instruction Predicate Definitions.
769def In32BitMode  : Predicate<"!PPCSubTarget->isPPC64()">;
770def In64BitMode  : Predicate<"PPCSubTarget->isPPC64()">;
771def IsBookE  : Predicate<"PPCSubTarget->isBookE()">;
772def IsNotBookE  : Predicate<"!PPCSubTarget->isBookE()">;
773def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
774def HasSYNC   : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
775def IsPPC4xx  : Predicate<"PPCSubTarget->isPPC4xx()">;
776def IsPPC6xx  : Predicate<"PPCSubTarget->isPPC6xx()">;
777def IsE500  : Predicate<"PPCSubTarget->isE500()">;
778def HasSPE  : Predicate<"PPCSubTarget->HasSPE()">;
779def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
780def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">;
781def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
782def NaNsFPMath   : Predicate<"!TM.Options.NoNaNsFPMath">;
783def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">;
784def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">;
785def IsISA3_0 : Predicate<"PPCSubTarget->isISA3_0()">;
786
787//===----------------------------------------------------------------------===//
788// PowerPC Multiclass Definitions.
789
790multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
791                    string asmbase, string asmstr, InstrItinClass itin,
792                    list<dag> pattern> {
793  let BaseName = asmbase in {
794    def NAME : XForm_6<opcode, xo, OOL, IOL,
795                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
796                       pattern>, RecFormRel;
797    let Defs = [CR0] in
798    def o    : XForm_6<opcode, xo, OOL, IOL,
799                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
800                       []>, isDOT, RecFormRel;
801  }
802}
803
804multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
805                     string asmbase, string asmstr, InstrItinClass itin,
806                     list<dag> pattern> {
807  let BaseName = asmbase in {
808    let Defs = [CARRY] in
809    def NAME : XForm_6<opcode, xo, OOL, IOL,
810                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
811                       pattern>, RecFormRel;
812    let Defs = [CARRY, CR0] in
813    def o    : XForm_6<opcode, xo, OOL, IOL,
814                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
815                       []>, isDOT, RecFormRel;
816  }
817}
818
819multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
820                      string asmbase, string asmstr, InstrItinClass itin,
821                      list<dag> pattern> {
822  let BaseName = asmbase in {
823    let Defs = [CARRY] in
824    def NAME : XForm_10<opcode, xo, OOL, IOL,
825                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
826                       pattern>, RecFormRel;
827    let Defs = [CARRY, CR0] in
828    def o    : XForm_10<opcode, xo, OOL, IOL,
829                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
830                       []>, isDOT, RecFormRel;
831  }
832}
833
834multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
835                    string asmbase, string asmstr, InstrItinClass itin,
836                    list<dag> pattern> {
837  let BaseName = asmbase in {
838    def NAME : XForm_11<opcode, xo, OOL, IOL,
839                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
840                       pattern>, RecFormRel;
841    let Defs = [CR0] in
842    def o    : XForm_11<opcode, xo, OOL, IOL,
843                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
844                       []>, isDOT, RecFormRel;
845  }
846}
847
848multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
849                    string asmbase, string asmstr, InstrItinClass itin,
850                    list<dag> pattern> {
851  let BaseName = asmbase in {
852    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
853                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
854                       pattern>, RecFormRel;
855    let Defs = [CR0] in
856    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
857                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
858                       []>, isDOT, RecFormRel;
859  }
860}
861
862// Multiclass for instructions for which the non record form is not cracked
863// and the record form is cracked (i.e. divw, mullw, etc.)
864multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
865                      string asmbase, string asmstr, InstrItinClass itin,
866                      list<dag> pattern> {
867  let BaseName = asmbase in {
868    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
869                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
870                       pattern>, RecFormRel;
871    let Defs = [CR0] in
872    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
873                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
874                       []>, isDOT, RecFormRel, PPC970_DGroup_First,
875                       PPC970_DGroup_Cracked;
876  }
877}
878
879multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
880                      string asmbase, string asmstr, InstrItinClass itin,
881                      list<dag> pattern> {
882  let BaseName = asmbase in {
883    let Defs = [CARRY] in
884    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
885                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
886                       pattern>, RecFormRel;
887    let Defs = [CARRY, CR0] in
888    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
889                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
890                       []>, isDOT, RecFormRel;
891  }
892}
893
894multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
895                    string asmbase, string asmstr, InstrItinClass itin,
896                    list<dag> pattern> {
897  let BaseName = asmbase in {
898    def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
899                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
900                       pattern>, RecFormRel;
901    let Defs = [CR0] in
902    def o    : XOForm_3<opcode, xo, oe, OOL, IOL,
903                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
904                       []>, isDOT, RecFormRel;
905  }
906}
907
908multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
909                      string asmbase, string asmstr, InstrItinClass itin,
910                      list<dag> pattern> {
911  let BaseName = asmbase in {
912    let Defs = [CARRY] in
913    def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
914                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
915                       pattern>, RecFormRel;
916    let Defs = [CARRY, CR0] in
917    def o    : XOForm_3<opcode, xo, oe, OOL, IOL,
918                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
919                       []>, isDOT, RecFormRel;
920  }
921}
922
923multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
924                    string asmbase, string asmstr, InstrItinClass itin,
925                    list<dag> pattern> {
926  let BaseName = asmbase in {
927    def NAME : MForm_2<opcode, OOL, IOL,
928                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
929                       pattern>, RecFormRel;
930    let Defs = [CR0] in
931    def o    : MForm_2<opcode, OOL, IOL,
932                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
933                       []>, isDOT, RecFormRel;
934  }
935}
936
937multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
938                    string asmbase, string asmstr, InstrItinClass itin,
939                    list<dag> pattern> {
940  let BaseName = asmbase in {
941    def NAME : MDForm_1<opcode, xo, OOL, IOL,
942                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
943                       pattern>, RecFormRel;
944    let Defs = [CR0] in
945    def o    : MDForm_1<opcode, xo, OOL, IOL,
946                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
947                       []>, isDOT, RecFormRel;
948  }
949}
950
951multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
952                     string asmbase, string asmstr, InstrItinClass itin,
953                     list<dag> pattern> {
954  let BaseName = asmbase in {
955    def NAME : MDSForm_1<opcode, xo, OOL, IOL,
956                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
957                        pattern>, RecFormRel;
958    let Defs = [CR0] in
959    def o    : MDSForm_1<opcode, xo, OOL, IOL,
960                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
961                        []>, isDOT, RecFormRel;
962  }
963}
964
965multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
966                      string asmbase, string asmstr, InstrItinClass itin,
967                      list<dag> pattern> {
968  let BaseName = asmbase in {
969    let Defs = [CARRY] in
970    def NAME : XSForm_1<opcode, xo, OOL, IOL,
971                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
972                       pattern>, RecFormRel;
973    let Defs = [CARRY, CR0] in
974    def o    : XSForm_1<opcode, xo, OOL, IOL,
975                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
976                       []>, isDOT, RecFormRel;
977  }
978}
979
980multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
981                    string asmbase, string asmstr, InstrItinClass itin,
982                    list<dag> pattern> {
983  let BaseName = asmbase in {
984    def NAME : XForm_26<opcode, xo, OOL, IOL,
985                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
986                       pattern>, RecFormRel;
987    let Defs = [CR1] in
988    def o    : XForm_26<opcode, xo, OOL, IOL,
989                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
990                       []>, isDOT, RecFormRel;
991  }
992}
993
994multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
995                    string asmbase, string asmstr, InstrItinClass itin,
996                    list<dag> pattern> {
997  let BaseName = asmbase in {
998    def NAME : XForm_28<opcode, xo, OOL, IOL,
999                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1000                       pattern>, RecFormRel;
1001    let Defs = [CR1] in
1002    def o    : XForm_28<opcode, xo, OOL, IOL,
1003                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1004                       []>, isDOT, RecFormRel;
1005  }
1006}
1007
1008multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
1009                    string asmbase, string asmstr, InstrItinClass itin,
1010                    list<dag> pattern> {
1011  let BaseName = asmbase in {
1012    def NAME : AForm_1<opcode, xo, OOL, IOL,
1013                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1014                       pattern>, RecFormRel;
1015    let Defs = [CR1] in
1016    def o    : AForm_1<opcode, xo, OOL, IOL,
1017                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1018                       []>, isDOT, RecFormRel;
1019  }
1020}
1021
1022multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
1023                    string asmbase, string asmstr, InstrItinClass itin,
1024                    list<dag> pattern> {
1025  let BaseName = asmbase in {
1026    def NAME : AForm_2<opcode, xo, OOL, IOL,
1027                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1028                       pattern>, RecFormRel;
1029    let Defs = [CR1] in
1030    def o    : AForm_2<opcode, xo, OOL, IOL,
1031                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1032                       []>, isDOT, RecFormRel;
1033  }
1034}
1035
1036multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
1037                    string asmbase, string asmstr, InstrItinClass itin,
1038                    list<dag> pattern> {
1039  let BaseName = asmbase in {
1040    def NAME : AForm_3<opcode, xo, OOL, IOL,
1041                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1042                       pattern>, RecFormRel;
1043    let Defs = [CR1] in
1044    def o    : AForm_3<opcode, xo, OOL, IOL,
1045                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1046                       []>, isDOT, RecFormRel;
1047  }
1048}
1049
1050//===----------------------------------------------------------------------===//
1051// PowerPC Instruction Definitions.
1052
1053// Pseudo-instructions:
1054
1055let hasCtrlDep = 1 in {
1056let Defs = [R1], Uses = [R1] in {
1057def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
1058                              [(callseq_start timm:$amt)]>;
1059def ADJCALLSTACKUP   : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
1060                              [(callseq_end timm:$amt1, timm:$amt2)]>;
1061}
1062
1063def UPDATE_VRSAVE    : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
1064                              "UPDATE_VRSAVE $rD, $rS", []>;
1065}
1066
1067let Defs = [R1], Uses = [R1] in
1068def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
1069                       [(set i32:$result,
1070                             (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
1071def DYNAREAOFFSET : Pseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET",
1072                       [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>;
1073
1074// SELECT_CC_* - Used to implement the SELECT_CC DAG operation.  Expanded after
1075// instruction selection into a branch sequence.
1076let usesCustomInserter = 1,    // Expanded after instruction selection.
1077    PPC970_Single = 1 in {
1078  // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
1079  // because either operand might become the first operand in an isel, and
1080  // that operand cannot be r0.
1081  def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
1082                              gprc_nor0:$T, gprc_nor0:$F,
1083                              i32imm:$BROPC), "#SELECT_CC_I4",
1084                              []>;
1085  def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
1086                              g8rc_nox0:$T, g8rc_nox0:$F,
1087                              i32imm:$BROPC), "#SELECT_CC_I8",
1088                              []>;
1089  def SELECT_CC_F4  : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1090                              i32imm:$BROPC), "#SELECT_CC_F4",
1091                              []>;
1092  def SELECT_CC_F8  : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
1093                              i32imm:$BROPC), "#SELECT_CC_F8",
1094                              []>;
1095  def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
1096                              i32imm:$BROPC), "#SELECT_CC_VRRC",
1097                              []>;
1098
1099  // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
1100  // register bit directly.
1101  def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
1102                          gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
1103                          [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
1104  def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
1105                          g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
1106                          [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
1107  def SELECT_F4  : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
1108                          f4rc:$T, f4rc:$F), "#SELECT_F4",
1109                          [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
1110  def SELECT_F8  : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
1111                          f8rc:$T, f8rc:$F), "#SELECT_F8",
1112                          [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
1113  def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
1114                          vrrc:$T, vrrc:$F), "#SELECT_VRRC",
1115                          [(set v4i32:$dst,
1116                                (select i1:$cond, v4i32:$T, v4i32:$F))]>;
1117}
1118
1119// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
1120// scavenge a register for it.
1121let mayStore = 1 in {
1122def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
1123                     "#SPILL_CR", []>;
1124def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1125                         "#SPILL_CRBIT", []>;
1126}
1127
1128// RESTORE_CR - Indicate that we're restoring the CR register (previously
1129// spilled), so we'll need to scavenge a register for it.
1130let mayLoad = 1 in {
1131def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1132                     "#RESTORE_CR", []>;
1133def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1134                           "#RESTORE_CRBIT", []>;
1135}
1136
1137let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1138  let isReturn = 1, Uses = [LR, RM] in
1139    def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1140                           [(retflag)]>, Requires<[In32BitMode]>;
1141  let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1142    def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1143                            []>;
1144
1145    let isCodeGenOnly = 1 in {
1146      def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1147                               "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1148                               []>;
1149
1150      def BCCTR :  XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1151                                "bcctr 12, $bi, 0", IIC_BrB, []>;
1152      def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1153                                "bcctr 4, $bi, 0", IIC_BrB, []>;
1154    }
1155  }
1156}
1157
1158let Defs = [LR] in
1159  def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1160                   PPC970_Unit_BRU;
1161let Defs = [LR] in
1162  def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1163                    PPC970_Unit_BRU;
1164
1165let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1166  let isBarrier = 1 in {
1167  def B   : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1168                  "b $dst", IIC_BrB,
1169                  [(br bb:$dst)]>;
1170  def BA  : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1171                  "ba $dst", IIC_BrB, []>;
1172  }
1173
1174  // BCC represents an arbitrary conditional branch on a predicate.
1175  // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1176  // a two-value operand where a dag node expects two operands. :(
1177  let isCodeGenOnly = 1 in {
1178    def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1179                    "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1180                    /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1181    def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1182                     "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1183
1184    let isReturn = 1, Uses = [LR, RM] in
1185    def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1186                           "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1187  }
1188
1189  let isCodeGenOnly = 1 in {
1190    let Pattern = [(brcond i1:$bi, bb:$dst)] in
1191    def BC  : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1192             "bc 12, $bi, $dst">;
1193
1194    let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1195    def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1196             "bc 4, $bi, $dst">;
1197
1198    let isReturn = 1, Uses = [LR, RM] in
1199    def BCLR  : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1200                             "bclr 12, $bi, 0", IIC_BrB, []>;
1201    def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1202                             "bclr 4, $bi, 0", IIC_BrB, []>;
1203  }
1204
1205  let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1206   def BDZLR  : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1207                             "bdzlr", IIC_BrB, []>;
1208   def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1209                             "bdnzlr", IIC_BrB, []>;
1210   def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1211                             "bdzlr+", IIC_BrB, []>;
1212   def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1213                             "bdnzlr+", IIC_BrB, []>;
1214   def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1215                             "bdzlr-", IIC_BrB, []>;
1216   def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1217                             "bdnzlr-", IIC_BrB, []>;
1218  }
1219
1220  let Defs = [CTR], Uses = [CTR] in {
1221    def BDZ  : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1222                       "bdz $dst">;
1223    def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1224                       "bdnz $dst">;
1225    def BDZA  : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1226                        "bdza $dst">;
1227    def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1228                        "bdnza $dst">;
1229    def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1230                       "bdz+ $dst">;
1231    def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1232                       "bdnz+ $dst">;
1233    def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1234                        "bdza+ $dst">;
1235    def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1236                        "bdnza+ $dst">;
1237    def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1238                       "bdz- $dst">;
1239    def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1240                       "bdnz- $dst">;
1241    def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1242                        "bdza- $dst">;
1243    def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1244                        "bdnza- $dst">;
1245  }
1246}
1247
1248// The unconditional BCL used by the SjLj setjmp code.
1249let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1250  let Defs = [LR], Uses = [RM] in {
1251    def BCLalways  : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1252                            "bcl 20, 31, $dst">;
1253  }
1254}
1255
1256let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1257  // Convenient aliases for call instructions
1258  let Uses = [RM] in {
1259    def BL  : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1260                    "bl $func", IIC_BrB, []>;  // See Pat patterns below.
1261    def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1262                    "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1263
1264    let isCodeGenOnly = 1 in {
1265      def BL_TLS  : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1266                          "bl $func", IIC_BrB, []>;
1267      def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1268                       "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1269      def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1270                        "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1271
1272      def BCL  : BForm_4<16, 12, 0, 1, (outs),
1273                         (ins crbitrc:$bi, condbrtarget:$dst),
1274                         "bcl 12, $bi, $dst">;
1275      def BCLn : BForm_4<16, 4, 0, 1, (outs),
1276                         (ins crbitrc:$bi, condbrtarget:$dst),
1277                         "bcl 4, $bi, $dst">;
1278    }
1279  }
1280  let Uses = [CTR, RM] in {
1281    def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1282                             "bctrl", IIC_BrB, [(PPCbctrl)]>,
1283                Requires<[In32BitMode]>;
1284
1285    let isCodeGenOnly = 1 in {
1286      def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1287                                "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1288                                []>;
1289
1290      def BCCTRL  : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1291                                 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1292      def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1293                                 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1294    }
1295  }
1296  let Uses = [LR, RM] in {
1297    def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1298                            "blrl", IIC_BrB, []>;
1299
1300    let isCodeGenOnly = 1 in {
1301      def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1302                              "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1303                              []>;
1304
1305      def BCLRL  : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1306                                "bclrl 12, $bi, 0", IIC_BrB, []>;
1307      def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1308                                "bclrl 4, $bi, 0", IIC_BrB, []>;
1309    }
1310  }
1311  let Defs = [CTR], Uses = [CTR, RM] in {
1312    def BDZL  : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1313                        "bdzl $dst">;
1314    def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1315                        "bdnzl $dst">;
1316    def BDZLA  : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1317                         "bdzla $dst">;
1318    def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1319                         "bdnzla $dst">;
1320    def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1321                        "bdzl+ $dst">;
1322    def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1323                        "bdnzl+ $dst">;
1324    def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1325                         "bdzla+ $dst">;
1326    def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1327                         "bdnzla+ $dst">;
1328    def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1329                        "bdzl- $dst">;
1330    def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1331                        "bdnzl- $dst">;
1332    def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1333                         "bdzla- $dst">;
1334    def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1335                         "bdnzla- $dst">;
1336  }
1337  let Defs = [CTR], Uses = [CTR, LR, RM] in {
1338    def BDZLRL  : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1339                               "bdzlrl", IIC_BrB, []>;
1340    def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1341                               "bdnzlrl", IIC_BrB, []>;
1342    def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1343                               "bdzlrl+", IIC_BrB, []>;
1344    def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1345                               "bdnzlrl+", IIC_BrB, []>;
1346    def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1347                               "bdzlrl-", IIC_BrB, []>;
1348    def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1349                               "bdnzlrl-", IIC_BrB, []>;
1350  }
1351}
1352
1353let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1354def TCRETURNdi :Pseudo< (outs),
1355                        (ins calltarget:$dst, i32imm:$offset),
1356                 "#TC_RETURNd $dst $offset",
1357                 []>;
1358
1359
1360let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1361def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1362                 "#TC_RETURNa $func $offset",
1363                 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1364
1365let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1366def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1367                 "#TC_RETURNr $dst $offset",
1368                 []>;
1369
1370
1371let isCodeGenOnly = 1 in {
1372
1373let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1374    isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM]  in
1375def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1376                            []>, Requires<[In32BitMode]>;
1377
1378let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1379    isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1380def TAILB   : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1381                  "b $dst", IIC_BrB,
1382                  []>;
1383
1384let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1385    isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1386def TAILBA   : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1387                  "ba $dst", IIC_BrB,
1388                  []>;
1389
1390}
1391
1392let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1393  let Defs = [CTR] in
1394  def EH_SjLj_SetJmp32  : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1395                            "#EH_SJLJ_SETJMP32",
1396                            [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1397                          Requires<[In32BitMode]>;
1398  let isTerminator = 1 in
1399  def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1400                            "#EH_SJLJ_LONGJMP32",
1401                            [(PPCeh_sjlj_longjmp addr:$buf)]>,
1402                          Requires<[In32BitMode]>;
1403}
1404
1405// This pseudo is never removed from the function, as it serves as
1406// a terminator.  Size is set to 0 to prevent the builtin assembler
1407// from emitting it.
1408let isBranch = 1, isTerminator = 1, Size = 0 in {
1409  def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1410                        "#EH_SjLj_Setup\t$dst", []>;
1411}
1412
1413// System call.
1414let PPC970_Unit = 7 in {
1415  def SC     : SCForm<17, 1, (outs), (ins i32imm:$lev),
1416                      "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1417}
1418
1419// Branch history rolling buffer.
1420def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB,
1421                      [(PPCclrbhrb)]>,
1422                      PPC970_DGroup_Single;
1423// The $dmy argument used for MFBHRBE is not needed; however, including
1424// it avoids automatic generation of PPCFastISel::fastEmit_i(), which
1425// interferes with necessary special handling (see PPCFastISel.cpp).
1426def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD),
1427                         (ins u10imm:$imm, u10imm:$dmy),
1428                         "mfbhrbe $rD, $imm", IIC_BrB,
1429                         [(set i32:$rD,
1430                               (PPCmfbhrbe imm:$imm, imm:$dmy))]>,
1431                         PPC970_DGroup_First;
1432
1433def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm",
1434                     IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>,
1435                     PPC970_DGroup_Single;
1436
1437// DCB* instructions.
1438def DCBA   : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1439                      IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1440                      PPC970_DGroup_Single;
1441def DCBF   : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1442                      IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1443                      PPC970_DGroup_Single;
1444def DCBI   : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1445                      IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1446                      PPC970_DGroup_Single;
1447def DCBST  : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1448                      IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1449                      PPC970_DGroup_Single;
1450def DCBZ   : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1451                      IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1452                      PPC970_DGroup_Single;
1453def DCBZL  : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1454                      IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1455                      PPC970_DGroup_Single;
1456
1457let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in {
1458def DCBT   : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst),
1459                      "dcbt $dst, $TH", IIC_LdStDCBF, []>,
1460                      PPC970_DGroup_Single;
1461def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst),
1462                      "dcbtst $dst, $TH", IIC_LdStDCBF, []>,
1463                      PPC970_DGroup_Single;
1464} // hasSideEffects = 0
1465
1466def ICBT  : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1467                       "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1468
1469def : Pat<(int_ppc_dcbt xoaddr:$dst),
1470          (DCBT 0, xoaddr:$dst)>;
1471def : Pat<(int_ppc_dcbtst xoaddr:$dst),
1472          (DCBTST 0, xoaddr:$dst)>;
1473
1474def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1475          (DCBT 0, xoaddr:$dst)>;   // data prefetch for loads
1476def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1477          (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores
1478def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1479          (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
1480
1481// Atomic operations
1482let usesCustomInserter = 1 in {
1483  let Defs = [CR0] in {
1484    def ATOMIC_LOAD_ADD_I8 : Pseudo<
1485      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1486      [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1487    def ATOMIC_LOAD_SUB_I8 : Pseudo<
1488      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1489      [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1490    def ATOMIC_LOAD_AND_I8 : Pseudo<
1491      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1492      [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1493    def ATOMIC_LOAD_OR_I8 : Pseudo<
1494      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1495      [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1496    def ATOMIC_LOAD_XOR_I8 : Pseudo<
1497      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1498      [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1499    def ATOMIC_LOAD_NAND_I8 : Pseudo<
1500      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1501      [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1502    def ATOMIC_LOAD_ADD_I16 : Pseudo<
1503      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1504      [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1505    def ATOMIC_LOAD_SUB_I16 : Pseudo<
1506      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1507      [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1508    def ATOMIC_LOAD_AND_I16 : Pseudo<
1509      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1510      [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1511    def ATOMIC_LOAD_OR_I16 : Pseudo<
1512      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1513      [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1514    def ATOMIC_LOAD_XOR_I16 : Pseudo<
1515      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1516      [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1517    def ATOMIC_LOAD_NAND_I16 : Pseudo<
1518      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1519      [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1520    def ATOMIC_LOAD_ADD_I32 : Pseudo<
1521      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1522      [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1523    def ATOMIC_LOAD_SUB_I32 : Pseudo<
1524      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1525      [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1526    def ATOMIC_LOAD_AND_I32 : Pseudo<
1527      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1528      [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1529    def ATOMIC_LOAD_OR_I32 : Pseudo<
1530      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1531      [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1532    def ATOMIC_LOAD_XOR_I32 : Pseudo<
1533      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1534      [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1535    def ATOMIC_LOAD_NAND_I32 : Pseudo<
1536      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1537      [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1538
1539    def ATOMIC_CMP_SWAP_I8 : Pseudo<
1540      (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1541      [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1542    def ATOMIC_CMP_SWAP_I16 : Pseudo<
1543      (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1544      [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1545    def ATOMIC_CMP_SWAP_I32 : Pseudo<
1546      (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1547      [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1548
1549    def ATOMIC_SWAP_I8 : Pseudo<
1550      (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1551      [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1552    def ATOMIC_SWAP_I16 : Pseudo<
1553      (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1554      [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1555    def ATOMIC_SWAP_I32 : Pseudo<
1556      (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1557      [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1558  }
1559}
1560
1561// Instructions to support atomic operations
1562let mayLoad = 1, hasSideEffects = 0 in {
1563def LBARX : XForm_1<31,  52, (outs gprc:$rD), (ins memrr:$src),
1564                    "lbarx $rD, $src", IIC_LdStLWARX, []>,
1565                    Requires<[HasPartwordAtomics]>;
1566
1567def LHARX : XForm_1<31,  116, (outs gprc:$rD), (ins memrr:$src),
1568                    "lharx $rD, $src", IIC_LdStLWARX, []>,
1569                    Requires<[HasPartwordAtomics]>;
1570
1571def LWARX : XForm_1<31,  20, (outs gprc:$rD), (ins memrr:$src),
1572                    "lwarx $rD, $src", IIC_LdStLWARX, []>;
1573
1574// Instructions to support lock versions of atomics
1575// (EH=1 - see Power ISA 2.07 Book II 4.4.2)
1576def LBARXL : XForm_1<31,  52, (outs gprc:$rD), (ins memrr:$src),
1577                     "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1578                     Requires<[HasPartwordAtomics]>;
1579
1580def LHARXL : XForm_1<31,  116, (outs gprc:$rD), (ins memrr:$src),
1581                     "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1582                     Requires<[HasPartwordAtomics]>;
1583
1584def LWARXL : XForm_1<31,  20, (outs gprc:$rD), (ins memrr:$src),
1585                     "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT;
1586
1587// The atomic instructions use the destination register as well as the next one
1588// or two registers in order (modulo 31).
1589let hasExtraSrcRegAllocReq = 1 in
1590def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC),
1591                         "lwat $rD, $rA, $FC", IIC_LdStLoad>,
1592           Requires<[IsISA3_0]>;
1593}
1594
1595let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in {
1596def STBCX : XForm_1<31, 694, (outs), (ins gprc:$rS, memrr:$dst),
1597                    "stbcx. $rS, $dst", IIC_LdStSTWCX, []>,
1598                    isDOT, Requires<[HasPartwordAtomics]>;
1599
1600def STHCX : XForm_1<31, 726, (outs), (ins gprc:$rS, memrr:$dst),
1601                    "sthcx. $rS, $dst", IIC_LdStSTWCX, []>,
1602                    isDOT, Requires<[HasPartwordAtomics]>;
1603
1604def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1605                    "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT;
1606}
1607
1608let mayStore = 1, hasSideEffects = 0 in
1609def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC),
1610                          "stwat $rS, $rA, $FC", IIC_LdStStore>,
1611            Requires<[IsISA3_0]>;
1612
1613let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1614def TRAP  : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1615
1616def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1617                     "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1618def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1619                 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1620def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1621                     "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1622def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1623                 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1624
1625//===----------------------------------------------------------------------===//
1626// PPC32 Load Instructions.
1627//
1628
1629// Unindexed (r+i) Loads.
1630let PPC970_Unit = 2 in {
1631def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1632                  "lbz $rD, $src", IIC_LdStLoad,
1633                  [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1634def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1635                  "lha $rD, $src", IIC_LdStLHA,
1636                  [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1637                  PPC970_DGroup_Cracked;
1638def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1639                  "lhz $rD, $src", IIC_LdStLoad,
1640                  [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1641def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1642                  "lwz $rD, $src", IIC_LdStLoad,
1643                  [(set i32:$rD, (load iaddr:$src))]>;
1644
1645def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1646                  "lfs $rD, $src", IIC_LdStLFD,
1647                  [(set f32:$rD, (load iaddr:$src))]>;
1648def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1649                  "lfd $rD, $src", IIC_LdStLFD,
1650                  [(set f64:$rD, (load iaddr:$src))]>;
1651
1652
1653// Unindexed (r+i) Loads with Update (preinc).
1654let mayLoad = 1, hasSideEffects = 0 in {
1655def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1656                   "lbzu $rD, $addr", IIC_LdStLoadUpd,
1657                   []>, RegConstraint<"$addr.reg = $ea_result">,
1658                   NoEncode<"$ea_result">;
1659
1660def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1661                   "lhau $rD, $addr", IIC_LdStLHAU,
1662                   []>, RegConstraint<"$addr.reg = $ea_result">,
1663                   NoEncode<"$ea_result">;
1664
1665def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1666                   "lhzu $rD, $addr", IIC_LdStLoadUpd,
1667                   []>, RegConstraint<"$addr.reg = $ea_result">,
1668                   NoEncode<"$ea_result">;
1669
1670def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1671                   "lwzu $rD, $addr", IIC_LdStLoadUpd,
1672                   []>, RegConstraint<"$addr.reg = $ea_result">,
1673                   NoEncode<"$ea_result">;
1674
1675def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1676                  "lfsu $rD, $addr", IIC_LdStLFDU,
1677                  []>, RegConstraint<"$addr.reg = $ea_result">,
1678                   NoEncode<"$ea_result">;
1679
1680def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1681                  "lfdu $rD, $addr", IIC_LdStLFDU,
1682                  []>, RegConstraint<"$addr.reg = $ea_result">,
1683                   NoEncode<"$ea_result">;
1684
1685
1686// Indexed (r+r) Loads with Update (preinc).
1687def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1688                   (ins memrr:$addr),
1689                   "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1690                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1691                   NoEncode<"$ea_result">;
1692
1693def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1694                   (ins memrr:$addr),
1695                   "lhaux $rD, $addr", IIC_LdStLHAUX,
1696                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1697                   NoEncode<"$ea_result">;
1698
1699def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1700                   (ins memrr:$addr),
1701                   "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1702                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1703                   NoEncode<"$ea_result">;
1704
1705def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1706                   (ins memrr:$addr),
1707                   "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1708                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1709                   NoEncode<"$ea_result">;
1710
1711def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1712                   (ins memrr:$addr),
1713                   "lfsux $rD, $addr", IIC_LdStLFDUX,
1714                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1715                   NoEncode<"$ea_result">;
1716
1717def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1718                   (ins memrr:$addr),
1719                   "lfdux $rD, $addr", IIC_LdStLFDUX,
1720                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1721                   NoEncode<"$ea_result">;
1722}
1723}
1724
1725// Indexed (r+r) Loads.
1726//
1727let PPC970_Unit = 2 in {
1728def LBZX : XForm_1<31,  87, (outs gprc:$rD), (ins memrr:$src),
1729                   "lbzx $rD, $src", IIC_LdStLoad,
1730                   [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1731def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1732                   "lhax $rD, $src", IIC_LdStLHA,
1733                   [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1734                   PPC970_DGroup_Cracked;
1735def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1736                   "lhzx $rD, $src", IIC_LdStLoad,
1737                   [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1738def LWZX : XForm_1<31,  23, (outs gprc:$rD), (ins memrr:$src),
1739                   "lwzx $rD, $src", IIC_LdStLoad,
1740                   [(set i32:$rD, (load xaddr:$src))]>;
1741
1742
1743def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1744                   "lhbrx $rD, $src", IIC_LdStLoad,
1745                   [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1746def LWBRX : XForm_1<31,  534, (outs gprc:$rD), (ins memrr:$src),
1747                   "lwbrx $rD, $src", IIC_LdStLoad,
1748                   [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1749
1750def LFSX   : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1751                      "lfsx $frD, $src", IIC_LdStLFD,
1752                      [(set f32:$frD, (load xaddr:$src))]>;
1753def LFDX   : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1754                      "lfdx $frD, $src", IIC_LdStLFD,
1755                      [(set f64:$frD, (load xaddr:$src))]>;
1756
1757def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1758                      "lfiwax $frD, $src", IIC_LdStLFD,
1759                      [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1760def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1761                      "lfiwzx $frD, $src", IIC_LdStLFD,
1762                      [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1763}
1764
1765// Load Multiple
1766def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1767                  "lmw $rD, $src", IIC_LdStLMW, []>;
1768
1769//===----------------------------------------------------------------------===//
1770// PPC32 Store Instructions.
1771//
1772
1773// Unindexed (r+i) Stores.
1774let PPC970_Unit = 2 in {
1775def STB  : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1776                   "stb $rS, $src", IIC_LdStStore,
1777                   [(truncstorei8 i32:$rS, iaddr:$src)]>;
1778def STH  : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1779                   "sth $rS, $src", IIC_LdStStore,
1780                   [(truncstorei16 i32:$rS, iaddr:$src)]>;
1781def STW  : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1782                   "stw $rS, $src", IIC_LdStStore,
1783                   [(store i32:$rS, iaddr:$src)]>;
1784def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1785                   "stfs $rS, $dst", IIC_LdStSTFD,
1786                   [(store f32:$rS, iaddr:$dst)]>;
1787def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1788                   "stfd $rS, $dst", IIC_LdStSTFD,
1789                   [(store f64:$rS, iaddr:$dst)]>;
1790}
1791
1792// Unindexed (r+i) Stores with Update (preinc).
1793let PPC970_Unit = 2, mayStore = 1 in {
1794def STBU  : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1795                    "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1796                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1797def STHU  : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1798                    "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1799                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1800def STWU  : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1801                    "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1802                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1803def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1804                    "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1805                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1806def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1807                    "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1808                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1809}
1810
1811// Patterns to match the pre-inc stores.  We can't put the patterns on
1812// the instruction definitions directly as ISel wants the address base
1813// and offset to be separate operands, not a single complex operand.
1814def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1815          (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1816def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1817          (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1818def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1819          (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1820def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1821          (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1822def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1823          (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1824
1825// Indexed (r+r) Stores.
1826let PPC970_Unit = 2 in {
1827def STBX  : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1828                   "stbx $rS, $dst", IIC_LdStStore,
1829                   [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1830                   PPC970_DGroup_Cracked;
1831def STHX  : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1832                   "sthx $rS, $dst", IIC_LdStStore,
1833                   [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1834                   PPC970_DGroup_Cracked;
1835def STWX  : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1836                   "stwx $rS, $dst", IIC_LdStStore,
1837                   [(store i32:$rS, xaddr:$dst)]>,
1838                   PPC970_DGroup_Cracked;
1839
1840def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1841                   "sthbrx $rS, $dst", IIC_LdStStore,
1842                   [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1843                   PPC970_DGroup_Cracked;
1844def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1845                   "stwbrx $rS, $dst", IIC_LdStStore,
1846                   [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1847                   PPC970_DGroup_Cracked;
1848
1849def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1850                     "stfiwx $frS, $dst", IIC_LdStSTFD,
1851                     [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1852
1853def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1854                     "stfsx $frS, $dst", IIC_LdStSTFD,
1855                     [(store f32:$frS, xaddr:$dst)]>;
1856def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1857                     "stfdx $frS, $dst", IIC_LdStSTFD,
1858                     [(store f64:$frS, xaddr:$dst)]>;
1859}
1860
1861// Indexed (r+r) Stores with Update (preinc).
1862let PPC970_Unit = 2, mayStore = 1 in {
1863def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1864                    "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1865                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1866                    PPC970_DGroup_Cracked;
1867def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1868                    "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1869                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1870                    PPC970_DGroup_Cracked;
1871def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1872                    "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1873                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1874                    PPC970_DGroup_Cracked;
1875def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1876                    "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1877                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1878                    PPC970_DGroup_Cracked;
1879def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1880                    "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1881                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1882                    PPC970_DGroup_Cracked;
1883}
1884
1885// Patterns to match the pre-inc stores.  We can't put the patterns on
1886// the instruction definitions directly as ISel wants the address base
1887// and offset to be separate operands, not a single complex operand.
1888def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1889          (STBUX $rS, $ptrreg, $ptroff)>;
1890def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1891          (STHUX $rS, $ptrreg, $ptroff)>;
1892def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1893          (STWUX $rS, $ptrreg, $ptroff)>;
1894def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1895          (STFSUX $rS, $ptrreg, $ptroff)>;
1896def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1897          (STFDUX $rS, $ptrreg, $ptroff)>;
1898
1899// Store Multiple
1900def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1901                   "stmw $rS, $dst", IIC_LdStLMW, []>;
1902
1903def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1904                        "sync $L", IIC_LdStSync, []>;
1905
1906let isCodeGenOnly = 1 in {
1907  def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1908                           "msync", IIC_LdStSync, []> {
1909    let L = 0;
1910  }
1911}
1912
1913def : Pat<(int_ppc_sync),   (SYNC 0)>, Requires<[HasSYNC]>;
1914def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
1915def : Pat<(int_ppc_sync),   (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1916def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1917
1918//===----------------------------------------------------------------------===//
1919// PPC32 Arithmetic Instructions.
1920//
1921
1922let PPC970_Unit = 1 in {  // FXU Operations.
1923def ADDI   : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1924                     "addi $rD, $rA, $imm", IIC_IntSimple,
1925                     [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1926let BaseName = "addic" in {
1927let Defs = [CARRY] in
1928def ADDIC  : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1929                     "addic $rD, $rA, $imm", IIC_IntGeneral,
1930                     [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1931                     RecFormRel, PPC970_DGroup_Cracked;
1932let Defs = [CARRY, CR0] in
1933def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1934                     "addic. $rD, $rA, $imm", IIC_IntGeneral,
1935                     []>, isDOT, RecFormRel;
1936}
1937def ADDIS  : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1938                     "addis $rD, $rA, $imm", IIC_IntSimple,
1939                     [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1940let isCodeGenOnly = 1 in
1941def LA     : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1942                     "la $rD, $sym($rA)", IIC_IntGeneral,
1943                     [(set i32:$rD, (add i32:$rA,
1944                                          (PPClo tglobaladdr:$sym, 0)))]>;
1945def MULLI  : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1946                     "mulli $rD, $rA, $imm", IIC_IntMulLI,
1947                     [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1948let Defs = [CARRY] in
1949def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1950                     "subfic $rD, $rA, $imm", IIC_IntGeneral,
1951                     [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1952
1953let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1954  def LI  : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1955                       "li $rD, $imm", IIC_IntSimple,
1956                       [(set i32:$rD, imm32SExt16:$imm)]>;
1957  def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1958                       "lis $rD, $imm", IIC_IntSimple,
1959                       [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1960}
1961}
1962
1963let PPC970_Unit = 1 in {  // FXU Operations.
1964let Defs = [CR0] in {
1965def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1966                    "andi. $dst, $src1, $src2", IIC_IntGeneral,
1967                    [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1968                    isDOT;
1969def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1970                    "andis. $dst, $src1, $src2", IIC_IntGeneral,
1971                    [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1972                    isDOT;
1973}
1974def ORI   : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1975                    "ori $dst, $src1, $src2", IIC_IntSimple,
1976                    [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1977def ORIS  : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1978                    "oris $dst, $src1, $src2", IIC_IntSimple,
1979                    [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1980def XORI  : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1981                    "xori $dst, $src1, $src2", IIC_IntSimple,
1982                    [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1983def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1984                    "xoris $dst, $src1, $src2", IIC_IntSimple,
1985                    [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1986
1987def NOP   : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1988                         []>;
1989let isCodeGenOnly = 1 in {
1990// The POWER6 and POWER7 have special group-terminating nops.
1991def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1992                                        "ori 1, 1, 0", IIC_IntSimple, []>;
1993def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1994                                        "ori 2, 2, 0", IIC_IntSimple, []>;
1995}
1996
1997let isCompare = 1, hasSideEffects = 0 in {
1998  def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1999                          "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
2000  def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
2001                           "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
2002  def CMPRB  : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF),
2003                                (ins u1imm:$L, g8rc:$rA, g8rc:$rB),
2004                                "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>,
2005               Requires<[IsISA3_0]>;
2006}
2007}
2008
2009let PPC970_Unit = 1, hasSideEffects = 0 in {  // FXU Operations.
2010let isCommutable = 1 in {
2011defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2012                     "nand", "$rA, $rS, $rB", IIC_IntSimple,
2013                     [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
2014defm AND  : XForm_6r<31,  28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2015                     "and", "$rA, $rS, $rB", IIC_IntSimple,
2016                     [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
2017} // isCommutable
2018defm ANDC : XForm_6r<31,  60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2019                     "andc", "$rA, $rS, $rB", IIC_IntSimple,
2020                     [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
2021let isCommutable = 1 in {
2022defm OR   : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2023                     "or", "$rA, $rS, $rB", IIC_IntSimple,
2024                     [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
2025defm NOR  : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2026                     "nor", "$rA, $rS, $rB", IIC_IntSimple,
2027                     [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
2028} // isCommutable
2029defm ORC  : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2030                     "orc", "$rA, $rS, $rB", IIC_IntSimple,
2031                     [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
2032let isCommutable = 1 in {
2033defm EQV  : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2034                     "eqv", "$rA, $rS, $rB", IIC_IntSimple,
2035                     [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
2036defm XOR  : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2037                     "xor", "$rA, $rS, $rB", IIC_IntSimple,
2038                     [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
2039} // isCommutable
2040defm SLW  : XForm_6r<31,  24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2041                     "slw", "$rA, $rS, $rB", IIC_IntGeneral,
2042                     [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
2043defm SRW  : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2044                     "srw", "$rA, $rS, $rB", IIC_IntGeneral,
2045                     [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
2046defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2047                      "sraw", "$rA, $rS, $rB", IIC_IntShift,
2048                      [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
2049}
2050
2051let PPC970_Unit = 1 in {  // FXU Operations.
2052let hasSideEffects = 0 in {
2053defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
2054                        "srawi", "$rA, $rS, $SH", IIC_IntShift,
2055                        [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
2056defm CNTLZW : XForm_11r<31,  26, (outs gprc:$rA), (ins gprc:$rS),
2057                        "cntlzw", "$rA, $rS", IIC_IntGeneral,
2058                        [(set i32:$rA, (ctlz i32:$rS))]>;
2059defm CNTTZW : XForm_11r<31, 538, (outs gprc:$rA), (ins gprc:$rS),
2060                        "cnttzw", "$rA, $rS", IIC_IntGeneral,
2061                        [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>;
2062defm EXTSB  : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
2063                        "extsb", "$rA, $rS", IIC_IntSimple,
2064                        [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
2065defm EXTSH  : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
2066                        "extsh", "$rA, $rS", IIC_IntSimple,
2067                        [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
2068
2069let isCommutable = 1 in
2070def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2071                   "cmpb $rA, $rS, $rB", IIC_IntGeneral,
2072                   [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>;
2073}
2074let isCompare = 1, hasSideEffects = 0 in {
2075  def CMPW   : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
2076                            "cmpw $crD, $rA, $rB", IIC_IntCompare>;
2077  def CMPLW  : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
2078                            "cmplw $crD, $rA, $rB", IIC_IntCompare>;
2079}
2080}
2081let PPC970_Unit = 3 in {  // FPU Operations.
2082//def FCMPO  : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
2083//                      "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
2084let isCompare = 1, hasSideEffects = 0 in {
2085  def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
2086                        "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
2087  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2088  def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
2089                        "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
2090}
2091
2092let Uses = [RM] in {
2093  let hasSideEffects = 0 in {
2094  defm FCTIW  : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
2095                          "fctiw", "$frD, $frB", IIC_FPGeneral,
2096                          []>;
2097  defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
2098                          "fctiwz", "$frD, $frB", IIC_FPGeneral,
2099                          [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
2100
2101  defm FRSP   : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
2102                          "frsp", "$frD, $frB", IIC_FPGeneral,
2103                          [(set f32:$frD, (fround f64:$frB))]>;
2104
2105  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2106  defm FRIND  : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
2107                          "frin", "$frD, $frB", IIC_FPGeneral,
2108                          [(set f64:$frD, (frnd f64:$frB))]>;
2109  defm FRINS  : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
2110                          "frin", "$frD, $frB", IIC_FPGeneral,
2111                          [(set f32:$frD, (frnd f32:$frB))]>;
2112  }
2113
2114  let hasSideEffects = 0 in {
2115  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2116  defm FRIPD  : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
2117                          "frip", "$frD, $frB", IIC_FPGeneral,
2118                          [(set f64:$frD, (fceil f64:$frB))]>;
2119  defm FRIPS  : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
2120                          "frip", "$frD, $frB", IIC_FPGeneral,
2121                          [(set f32:$frD, (fceil f32:$frB))]>;
2122  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2123  defm FRIZD  : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
2124                          "friz", "$frD, $frB", IIC_FPGeneral,
2125                          [(set f64:$frD, (ftrunc f64:$frB))]>;
2126  defm FRIZS  : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
2127                          "friz", "$frD, $frB", IIC_FPGeneral,
2128                          [(set f32:$frD, (ftrunc f32:$frB))]>;
2129  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2130  defm FRIMD  : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
2131                          "frim", "$frD, $frB", IIC_FPGeneral,
2132                          [(set f64:$frD, (ffloor f64:$frB))]>;
2133  defm FRIMS  : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
2134                          "frim", "$frD, $frB", IIC_FPGeneral,
2135                          [(set f32:$frD, (ffloor f32:$frB))]>;
2136
2137  defm FSQRT  : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
2138                          "fsqrt", "$frD, $frB", IIC_FPSqrtD,
2139                          [(set f64:$frD, (fsqrt f64:$frB))]>;
2140  defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
2141                          "fsqrts", "$frD, $frB", IIC_FPSqrtS,
2142                          [(set f32:$frD, (fsqrt f32:$frB))]>;
2143  }
2144  }
2145}
2146
2147/// Note that FMR is defined as pseudo-ops on the PPC970 because they are
2148/// often coalesced away and we don't want the dispatch group builder to think
2149/// that they will fill slots (which could cause the load of a LSU reject to
2150/// sneak into a d-group with a store).
2151let hasSideEffects = 0 in
2152defm FMR   : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
2153                       "fmr", "$frD, $frB", IIC_FPGeneral,
2154                       []>,  // (set f32:$frD, f32:$frB)
2155                       PPC970_Unit_Pseudo;
2156
2157let PPC970_Unit = 3, hasSideEffects = 0 in {  // FPU Operations.
2158// These are artificially split into two different forms, for 4/8 byte FP.
2159defm FABSS  : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
2160                        "fabs", "$frD, $frB", IIC_FPGeneral,
2161                        [(set f32:$frD, (fabs f32:$frB))]>;
2162let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2163defm FABSD  : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
2164                        "fabs", "$frD, $frB", IIC_FPGeneral,
2165                        [(set f64:$frD, (fabs f64:$frB))]>;
2166defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
2167                        "fnabs", "$frD, $frB", IIC_FPGeneral,
2168                        [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
2169let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2170defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
2171                        "fnabs", "$frD, $frB", IIC_FPGeneral,
2172                        [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
2173defm FNEGS  : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
2174                        "fneg", "$frD, $frB", IIC_FPGeneral,
2175                        [(set f32:$frD, (fneg f32:$frB))]>;
2176let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2177defm FNEGD  : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
2178                        "fneg", "$frD, $frB", IIC_FPGeneral,
2179                        [(set f64:$frD, (fneg f64:$frB))]>;
2180
2181defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
2182                        "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2183                        [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
2184let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2185defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
2186                        "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2187                        [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
2188
2189// Reciprocal estimates.
2190defm FRE      : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
2191                          "fre", "$frD, $frB", IIC_FPGeneral,
2192                          [(set f64:$frD, (PPCfre f64:$frB))]>;
2193defm FRES     : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
2194                          "fres", "$frD, $frB", IIC_FPGeneral,
2195                          [(set f32:$frD, (PPCfre f32:$frB))]>;
2196defm FRSQRTE  : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
2197                          "frsqrte", "$frD, $frB", IIC_FPGeneral,
2198                          [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
2199defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
2200                          "frsqrtes", "$frD, $frB", IIC_FPGeneral,
2201                          [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
2202}
2203
2204// XL-Form instructions.  condition register logical ops.
2205//
2206let hasSideEffects = 0 in
2207def MCRF   : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
2208                      "mcrf $BF, $BFA", IIC_BrMCR>,
2209             PPC970_DGroup_First, PPC970_Unit_CRU;
2210
2211// FIXME: According to the ISA (section 2.5.1 of version 2.06), the
2212// condition-register logical instructions have preferred forms. Specifically,
2213// it is preferred that the bit specified by the BT field be in the same
2214// condition register as that specified by the bit BB. We might want to account
2215// for this via hinting the register allocator and anti-dep breakers, or we
2216// could constrain the register class to force this constraint and then loosen
2217// it during register allocation via convertToThreeAddress or some similar
2218// mechanism.
2219
2220let isCommutable = 1 in {
2221def CRAND  : XLForm_1<19, 257, (outs crbitrc:$CRD),
2222                               (ins crbitrc:$CRA, crbitrc:$CRB),
2223                      "crand $CRD, $CRA, $CRB", IIC_BrCR,
2224                      [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2225
2226def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2227                               (ins crbitrc:$CRA, crbitrc:$CRB),
2228                      "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2229                      [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2230
2231def CROR   : XLForm_1<19, 449, (outs crbitrc:$CRD),
2232                               (ins crbitrc:$CRA, crbitrc:$CRB),
2233                      "cror $CRD, $CRA, $CRB", IIC_BrCR,
2234                      [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2235
2236def CRXOR  : XLForm_1<19, 193, (outs crbitrc:$CRD),
2237                               (ins crbitrc:$CRA, crbitrc:$CRB),
2238                      "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2239                      [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2240
2241def CRNOR  : XLForm_1<19, 33, (outs crbitrc:$CRD),
2242                              (ins crbitrc:$CRA, crbitrc:$CRB),
2243                      "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2244                      [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2245
2246def CREQV  : XLForm_1<19, 289, (outs crbitrc:$CRD),
2247                               (ins crbitrc:$CRA, crbitrc:$CRB),
2248                      "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2249                      [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2250} // isCommutable
2251
2252def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2253                               (ins crbitrc:$CRA, crbitrc:$CRB),
2254                      "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2255                      [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2256
2257def CRORC  : XLForm_1<19, 417, (outs crbitrc:$CRD),
2258                               (ins crbitrc:$CRA, crbitrc:$CRB),
2259                      "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2260                      [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2261
2262let isCodeGenOnly = 1 in {
2263def CRSET  : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2264              "creqv $dst, $dst, $dst", IIC_BrCR,
2265              [(set i1:$dst, 1)]>;
2266
2267def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2268              "crxor $dst, $dst, $dst", IIC_BrCR,
2269              [(set i1:$dst, 0)]>;
2270
2271let Defs = [CR1EQ], CRD = 6 in {
2272def CR6SET  : XLForm_1_ext<19, 289, (outs), (ins),
2273              "creqv 6, 6, 6", IIC_BrCR,
2274              [(PPCcr6set)]>;
2275
2276def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2277              "crxor 6, 6, 6", IIC_BrCR,
2278              [(PPCcr6unset)]>;
2279}
2280}
2281
2282// XFX-Form instructions.  Instructions that deal with SPRs.
2283//
2284
2285def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2286                      "mfspr $RT, $SPR", IIC_SprMFSPR>;
2287def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2288                      "mtspr $SPR, $RT", IIC_SprMTSPR>;
2289
2290def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2291                     "mftb $RT, $SPR", IIC_SprMFTB>;
2292
2293// A pseudo-instruction used to implement the read of the 64-bit cycle counter
2294// on a 32-bit target.
2295let hasSideEffects = 1, usesCustomInserter = 1 in
2296def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins),
2297                    "#ReadTB", []>;
2298
2299let Uses = [CTR] in {
2300def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2301                          "mfctr $rT", IIC_SprMFSPR>,
2302            PPC970_DGroup_First, PPC970_Unit_FXU;
2303}
2304let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2305def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2306                          "mtctr $rS", IIC_SprMTSPR>,
2307            PPC970_DGroup_First, PPC970_Unit_FXU;
2308}
2309let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2310let Pattern = [(int_ppc_mtctr i32:$rS)] in
2311def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2312                              "mtctr $rS", IIC_SprMTSPR>,
2313                PPC970_DGroup_First, PPC970_Unit_FXU;
2314}
2315
2316let Defs = [LR] in {
2317def MTLR  : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2318                          "mtlr $rS", IIC_SprMTSPR>,
2319            PPC970_DGroup_First, PPC970_Unit_FXU;
2320}
2321let Uses = [LR] in {
2322def MFLR  : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2323                          "mflr $rT", IIC_SprMFSPR>,
2324            PPC970_DGroup_First, PPC970_Unit_FXU;
2325}
2326
2327let isCodeGenOnly = 1 in {
2328  // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2329  // like a GPR on the PPC970.  As such, copies in and out have the same
2330  // performance characteristics as an OR instruction.
2331  def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2332                               "mtspr 256, $rS", IIC_IntGeneral>,
2333                 PPC970_DGroup_Single, PPC970_Unit_FXU;
2334  def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2335                               "mfspr $rT, 256", IIC_IntGeneral>,
2336                 PPC970_DGroup_First, PPC970_Unit_FXU;
2337
2338  def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2339                                (outs VRSAVERC:$reg), (ins gprc:$rS),
2340                                "mtspr 256, $rS", IIC_IntGeneral>,
2341                  PPC970_DGroup_Single, PPC970_Unit_FXU;
2342  def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2343                                (ins VRSAVERC:$reg),
2344                                "mfspr $rT, 256", IIC_IntGeneral>,
2345                  PPC970_DGroup_First, PPC970_Unit_FXU;
2346}
2347
2348// Aliases for mtvrsave/mfvrsave to mfspr/mtspr.
2349def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>;
2350def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>;
2351
2352// SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2353// so we'll need to scavenge a register for it.
2354let mayStore = 1 in
2355def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2356                     "#SPILL_VRSAVE", []>;
2357
2358// RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2359// spilled), so we'll need to scavenge a register for it.
2360let mayLoad = 1 in
2361def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2362                     "#RESTORE_VRSAVE", []>;
2363
2364let hasSideEffects = 0 in {
2365// mtocrf's input needs to be prepared by shifting by an amount dependent
2366// on the cr register selected. Thus, post-ra anti-dep breaking must not
2367// later change that register assignment.
2368let hasExtraDefRegAllocReq = 1 in {
2369def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2370                       "mtocrf $FXM, $ST", IIC_BrMCRX>,
2371            PPC970_DGroup_First, PPC970_Unit_CRU;
2372
2373// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that
2374// is dependent on the cr fields being set.
2375def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2376                      "mtcrf $FXM, $rS", IIC_BrMCRX>,
2377            PPC970_MicroCode, PPC970_Unit_CRU;
2378} // hasExtraDefRegAllocReq = 1
2379
2380// mfocrf's input needs to be prepared by shifting by an amount dependent
2381// on the cr register selected. Thus, post-ra anti-dep breaking must not
2382// later change that register assignment.
2383let hasExtraSrcRegAllocReq = 1 in {
2384def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2385                       "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2386            PPC970_DGroup_First, PPC970_Unit_CRU;
2387
2388// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that
2389// is dependent on the cr fields being copied.
2390def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2391                     "mfcr $rT", IIC_SprMFCR>,
2392                     PPC970_MicroCode, PPC970_Unit_CRU;
2393} // hasExtraSrcRegAllocReq = 1
2394
2395def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins),
2396                   "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>;
2397} // hasSideEffects = 0
2398
2399// Pseudo instruction to perform FADD in round-to-zero mode.
2400let usesCustomInserter = 1, Uses = [RM] in {
2401  def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2402                      [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2403}
2404
2405// The above pseudo gets expanded to make use of the following instructions
2406// to manipulate FPSCR.  Note that FPSCR is not modeled at the DAG level.
2407let Uses = [RM], Defs = [RM] in {
2408  def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2409                        "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2410               PPC970_DGroup_Single, PPC970_Unit_FPU;
2411  def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2412                        "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2413               PPC970_DGroup_Single, PPC970_Unit_FPU;
2414  let isCodeGenOnly = 1 in
2415  def MTFSFb  : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2416                        "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2417                PPC970_DGroup_Single, PPC970_Unit_FPU;
2418}
2419let Uses = [RM] in {
2420  def MFFS   : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2421                         "mffs $rT", IIC_IntMFFS,
2422                         [(set f64:$rT, (PPCmffs))]>,
2423               PPC970_DGroup_Single, PPC970_Unit_FPU;
2424
2425  let Defs = [CR1] in
2426  def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2427                      "mffs. $rT", IIC_IntMFFS, []>, isDOT;
2428}
2429
2430
2431let PPC970_Unit = 1, hasSideEffects = 0 in {  // FXU Operations.
2432// XO-Form instructions.  Arithmetic instructions that can set overflow bit
2433let isCommutable = 1 in
2434defm ADD4  : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2435                       "add", "$rT, $rA, $rB", IIC_IntSimple,
2436                       [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2437let isCodeGenOnly = 1 in
2438def ADD4TLS  : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2439                       "add $rT, $rA, $rB", IIC_IntSimple,
2440                       [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2441let isCommutable = 1 in
2442defm ADDC  : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2443                        "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2444                        [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2445                        PPC970_DGroup_Cracked;
2446
2447defm DIVW  : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2448                          "divw", "$rT, $rA, $rB", IIC_IntDivW,
2449                          [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>;
2450defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2451                          "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2452                          [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>;
2453def DIVWE : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2454                     "divwe $rT, $rA, $rB", IIC_IntDivW,
2455                     [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>,
2456                     Requires<[HasExtDiv]>;
2457let Defs = [CR0] in
2458def DIVWEo : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2459                      "divwe. $rT, $rA, $rB", IIC_IntDivW,
2460                      []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2461                      Requires<[HasExtDiv]>;
2462def DIVWEU : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2463                      "divweu $rT, $rA, $rB", IIC_IntDivW,
2464                      [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>,
2465                      Requires<[HasExtDiv]>;
2466let Defs = [CR0] in
2467def DIVWEUo : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2468                       "divweu. $rT, $rA, $rB", IIC_IntDivW,
2469                       []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2470                       Requires<[HasExtDiv]>;
2471let isCommutable = 1 in {
2472defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2473                       "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2474                       [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2475defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2476                       "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2477                       [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2478defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2479                       "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2480                       [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2481} // isCommutable
2482defm SUBF  : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2483                       "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2484                       [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2485defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2486                        "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2487                        [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2488                        PPC970_DGroup_Cracked;
2489defm NEG    : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2490                        "neg", "$rT, $rA", IIC_IntSimple,
2491                        [(set i32:$rT, (ineg i32:$rA))]>;
2492let Uses = [CARRY] in {
2493let isCommutable = 1 in
2494defm ADDE  : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2495                        "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2496                        [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2497defm ADDME  : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2498                         "addme", "$rT, $rA", IIC_IntGeneral,
2499                         [(set i32:$rT, (adde i32:$rA, -1))]>;
2500defm ADDZE  : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2501                         "addze", "$rT, $rA", IIC_IntGeneral,
2502                         [(set i32:$rT, (adde i32:$rA, 0))]>;
2503defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2504                        "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2505                        [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2506defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2507                         "subfme", "$rT, $rA", IIC_IntGeneral,
2508                         [(set i32:$rT, (sube -1, i32:$rA))]>;
2509defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2510                         "subfze", "$rT, $rA", IIC_IntGeneral,
2511                         [(set i32:$rT, (sube 0, i32:$rA))]>;
2512}
2513}
2514
2515// A-Form instructions.  Most of the instructions executed in the FPU are of
2516// this type.
2517//
2518let PPC970_Unit = 3, hasSideEffects = 0 in {  // FPU Operations.
2519let Uses = [RM] in {
2520let isCommutable = 1 in {
2521  defm FMADD : AForm_1r<63, 29,
2522                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2523                      "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2524                      [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2525  defm FMADDS : AForm_1r<59, 29,
2526                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2527                      "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2528                      [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2529  defm FMSUB : AForm_1r<63, 28,
2530                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2531                      "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2532                      [(set f64:$FRT,
2533                            (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2534  defm FMSUBS : AForm_1r<59, 28,
2535                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2536                      "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2537                      [(set f32:$FRT,
2538                            (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2539  defm FNMADD : AForm_1r<63, 31,
2540                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2541                      "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2542                      [(set f64:$FRT,
2543                            (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2544  defm FNMADDS : AForm_1r<59, 31,
2545                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2546                      "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2547                      [(set f32:$FRT,
2548                            (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2549  defm FNMSUB : AForm_1r<63, 30,
2550                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2551                      "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2552                      [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2553                                                 (fneg f64:$FRB))))]>;
2554  defm FNMSUBS : AForm_1r<59, 30,
2555                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2556                      "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2557                      [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2558                                                 (fneg f32:$FRB))))]>;
2559} // isCommutable
2560}
2561// FSEL is artificially split into 4 and 8-byte forms for the result.  To avoid
2562// having 4 of these, force the comparison to always be an 8-byte double (code
2563// should use an FMRSD if the input comparison value really wants to be a float)
2564// and 4/8 byte forms for the result and operand type..
2565let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2566defm FSELD : AForm_1r<63, 23,
2567                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2568                      "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2569                      [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2570defm FSELS : AForm_1r<63, 23,
2571                      (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2572                      "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2573                      [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2574let Uses = [RM] in {
2575  let isCommutable = 1 in {
2576  defm FADD  : AForm_2r<63, 21,
2577                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2578                        "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2579                        [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2580  defm FADDS : AForm_2r<59, 21,
2581                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2582                        "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2583                        [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2584  } // isCommutable
2585  defm FDIV  : AForm_2r<63, 18,
2586                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2587                        "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2588                        [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2589  defm FDIVS : AForm_2r<59, 18,
2590                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2591                        "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2592                        [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2593  let isCommutable = 1 in {
2594  defm FMUL  : AForm_3r<63, 25,
2595                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2596                        "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2597                        [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2598  defm FMULS : AForm_3r<59, 25,
2599                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2600                        "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2601                        [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2602  } // isCommutable
2603  defm FSUB  : AForm_2r<63, 20,
2604                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2605                        "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2606                        [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2607  defm FSUBS : AForm_2r<59, 20,
2608                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2609                        "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2610                        [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2611  }
2612}
2613
2614let hasSideEffects = 0 in {
2615let PPC970_Unit = 1 in {  // FXU Operations.
2616  let isSelect = 1 in
2617  def ISEL  : AForm_4<31, 15,
2618                     (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2619                     "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
2620                     []>;
2621}
2622
2623let PPC970_Unit = 1 in {  // FXU Operations.
2624// M-Form instructions.  rotate and mask instructions.
2625//
2626let isCommutable = 1 in {
2627// RLWIMI can be commuted if the rotate amount is zero.
2628defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2629                       (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2630                       u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2631                       IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2632                       RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2633}
2634let BaseName = "rlwinm" in {
2635def RLWINM : MForm_2<21,
2636                     (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2637                     "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2638                     []>, RecFormRel;
2639let Defs = [CR0] in
2640def RLWINMo : MForm_2<21,
2641                      (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2642                      "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2643                      []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2644}
2645defm RLWNM  : MForm_2r<23, (outs gprc:$rA),
2646                       (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2647                       "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2648                       []>;
2649}
2650} // hasSideEffects = 0
2651
2652//===----------------------------------------------------------------------===//
2653// PowerPC Instruction Patterns
2654//
2655
2656// Arbitrary immediate support.  Implement in terms of LIS/ORI.
2657def : Pat<(i32 imm:$imm),
2658          (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2659
2660// Implement the 'not' operation with the NOR instruction.
2661def i32not : OutPatFrag<(ops node:$in),
2662                        (NOR $in, $in)>;
2663def        : Pat<(not i32:$in),
2664                 (i32not $in)>;
2665
2666// ADD an arbitrary immediate.
2667def : Pat<(add i32:$in, imm:$imm),
2668          (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2669// OR an arbitrary immediate.
2670def : Pat<(or i32:$in, imm:$imm),
2671          (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2672// XOR an arbitrary immediate.
2673def : Pat<(xor i32:$in, imm:$imm),
2674          (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2675// SUBFIC
2676def : Pat<(sub imm32SExt16:$imm, i32:$in),
2677          (SUBFIC $in, imm:$imm)>;
2678
2679// SHL/SRL
2680def : Pat<(shl i32:$in, (i32 imm:$imm)),
2681          (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2682def : Pat<(srl i32:$in, (i32 imm:$imm)),
2683          (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2684
2685// ROTL
2686def : Pat<(rotl i32:$in, i32:$sh),
2687          (RLWNM $in, $sh, 0, 31)>;
2688def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2689          (RLWINM $in, imm:$imm, 0, 31)>;
2690
2691// RLWNM
2692def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2693          (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2694
2695// Calls
2696def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2697          (BL tglobaladdr:$dst)>;
2698def : Pat<(PPCcall (i32 texternalsym:$dst)),
2699          (BL texternalsym:$dst)>;
2700
2701def : Pat<(PPCtc_return (i32 tglobaladdr:$dst),  imm:$imm),
2702          (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2703
2704def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2705          (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2706
2707def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2708          (TCRETURNri CTRRC:$dst, imm:$imm)>;
2709
2710
2711
2712// Hi and Lo for Darwin Global Addresses.
2713def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2714def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2715def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2716def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2717def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2718def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2719def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2720def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2721def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2722          (ADDIS $in, tglobaltlsaddr:$g)>;
2723def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2724          (ADDI $in, tglobaltlsaddr:$g)>;
2725def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2726          (ADDIS $in, tglobaladdr:$g)>;
2727def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2728          (ADDIS $in, tconstpool:$g)>;
2729def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2730          (ADDIS $in, tjumptable:$g)>;
2731def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2732          (ADDIS $in, tblockaddress:$g)>;
2733
2734// Support for thread-local storage.
2735def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2736                [(set i32:$rD, (PPCppc32GOT))]>;
2737
2738// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2739// This uses two output registers, the first as the real output, the second as a
2740// temporary register, used internally in code generation.
2741def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2742                []>, NoEncode<"$rT">;
2743
2744def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2745                           "#LDgotTprelL32",
2746                           [(set i32:$rD,
2747                             (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2748def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2749          (ADD4TLS $in, tglobaltlsaddr:$g)>;
2750
2751def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2752                         "#ADDItlsgdL32",
2753                         [(set i32:$rD,
2754                           (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2755// LR is a true define, while the rest of the Defs are clobbers.  R3 is
2756// explicitly defined when this op is created, so not mentioned here.
2757let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2758    Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2759def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2760                          "GETtlsADDR32",
2761                          [(set i32:$rD,
2762                            (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2763// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded.  R3 and LR
2764// are true defines while the rest of the Defs are clobbers.
2765let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2766    Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2767def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD),
2768                              (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2769                              "#ADDItlsgdLADDR32",
2770                              [(set i32:$rD,
2771                                (PPCaddiTlsgdLAddr i32:$reg,
2772                                                   tglobaltlsaddr:$disp,
2773                                                   tglobaltlsaddr:$sym))]>;
2774def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2775                          "#ADDItlsldL32",
2776                          [(set i32:$rD,
2777                            (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2778// LR is a true define, while the rest of the Defs are clobbers.  R3 is
2779// explicitly defined when this op is created, so not mentioned here.
2780let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2781    Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2782def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2783                            "GETtlsldADDR32",
2784                            [(set i32:$rD,
2785                              (PPCgetTlsldAddr i32:$reg,
2786                                               tglobaltlsaddr:$sym))]>;
2787// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded.  R3 and LR
2788// are true defines while the rest of the Defs are clobbers.
2789let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2790    Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2791def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD),
2792                              (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2793                              "#ADDItlsldLADDR32",
2794                              [(set i32:$rD,
2795                                (PPCaddiTlsldLAddr i32:$reg,
2796                                                   tglobaltlsaddr:$disp,
2797                                                   tglobaltlsaddr:$sym))]>;
2798def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2799                           "#ADDIdtprelL32",
2800                           [(set i32:$rD,
2801                             (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2802def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2803                            "#ADDISdtprelHA32",
2804                            [(set i32:$rD,
2805                              (PPCaddisDtprelHA i32:$reg,
2806                                                tglobaltlsaddr:$disp))]>;
2807
2808// Support for Position-independent code
2809def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2810                   "#LWZtoc",
2811                   [(set i32:$rD,
2812                      (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2813// Get Global (GOT) Base Register offset, from the word immediately preceding
2814// the function label.
2815def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2816
2817
2818// Standard shifts.  These are represented separately from the real shifts above
2819// so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2820// amounts.
2821def : Pat<(sra i32:$rS, i32:$rB),
2822          (SRAW $rS, $rB)>;
2823def : Pat<(srl i32:$rS, i32:$rB),
2824          (SRW $rS, $rB)>;
2825def : Pat<(shl i32:$rS, i32:$rB),
2826          (SLW $rS, $rB)>;
2827
2828def : Pat<(zextloadi1 iaddr:$src),
2829          (LBZ iaddr:$src)>;
2830def : Pat<(zextloadi1 xaddr:$src),
2831          (LBZX xaddr:$src)>;
2832def : Pat<(extloadi1 iaddr:$src),
2833          (LBZ iaddr:$src)>;
2834def : Pat<(extloadi1 xaddr:$src),
2835          (LBZX xaddr:$src)>;
2836def : Pat<(extloadi8 iaddr:$src),
2837          (LBZ iaddr:$src)>;
2838def : Pat<(extloadi8 xaddr:$src),
2839          (LBZX xaddr:$src)>;
2840def : Pat<(extloadi16 iaddr:$src),
2841          (LHZ iaddr:$src)>;
2842def : Pat<(extloadi16 xaddr:$src),
2843          (LHZX xaddr:$src)>;
2844def : Pat<(f64 (extloadf32 iaddr:$src)),
2845          (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2846def : Pat<(f64 (extloadf32 xaddr:$src)),
2847          (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2848
2849def : Pat<(f64 (fextend f32:$src)),
2850          (COPY_TO_REGCLASS $src, F8RC)>;
2851
2852// Only seq_cst fences require the heavyweight sync (SYNC 0).
2853// All others can use the lightweight sync (SYNC 1).
2854// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
2855// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
2856// versions of Power.
2857def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2858def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2859def : Pat<(atomic_fence (imm),   (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
2860def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2861
2862// Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2863def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2864          (FNMSUB $A, $C, $B)>;
2865def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2866          (FNMSUB $A, $C, $B)>;
2867def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2868          (FNMSUBS $A, $C, $B)>;
2869def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2870          (FNMSUBS $A, $C, $B)>;
2871
2872// FCOPYSIGN's operand types need not agree.
2873def : Pat<(fcopysign f64:$frB, f32:$frA),
2874          (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2875def : Pat<(fcopysign f32:$frB, f64:$frA),
2876          (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2877
2878include "PPCInstrAltivec.td"
2879include "PPCInstrSPE.td"
2880include "PPCInstr64Bit.td"
2881include "PPCInstrVSX.td"
2882include "PPCInstrQPX.td"
2883include "PPCInstrHTM.td"
2884
2885def crnot : OutPatFrag<(ops node:$in),
2886                       (CRNOR $in, $in)>;
2887def       : Pat<(not i1:$in),
2888                (crnot $in)>;
2889
2890// Patterns for arithmetic i1 operations.
2891def : Pat<(add i1:$a, i1:$b),
2892          (CRXOR $a, $b)>;
2893def : Pat<(sub i1:$a, i1:$b),
2894          (CRXOR $a, $b)>;
2895def : Pat<(mul i1:$a, i1:$b),
2896          (CRAND $a, $b)>;
2897
2898// We're sometimes asked to materialize i1 -1, which is just 1 in this case
2899// (-1 is used to mean all bits set).
2900def : Pat<(i1 -1), (CRSET)>;
2901
2902// i1 extensions, implemented in terms of isel.
2903def : Pat<(i32 (zext i1:$in)),
2904          (SELECT_I4 $in, (LI 1), (LI 0))>;
2905def : Pat<(i32 (sext i1:$in)),
2906          (SELECT_I4 $in, (LI -1), (LI 0))>;
2907
2908def : Pat<(i64 (zext i1:$in)),
2909          (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2910def : Pat<(i64 (sext i1:$in)),
2911          (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2912
2913// FIXME: We should choose either a zext or a sext based on other constants
2914// already around.
2915def : Pat<(i32 (anyext i1:$in)),
2916          (SELECT_I4 $in, (LI 1), (LI 0))>;
2917def : Pat<(i64 (anyext i1:$in)),
2918          (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2919
2920// match setcc on i1 variables.
2921// CRANDC is:
2922//   1 1 : F
2923//   1 0 : T
2924//   0 1 : F
2925//   0 0 : F
2926//
2927// LT is:
2928//  -1 -1  : F
2929//  -1  0  : T
2930//   0 -1  : F
2931//   0  0  : F
2932//
2933// ULT is:
2934//   1 1 : F
2935//   1 0 : F
2936//   0 1 : T
2937//   0 0 : F
2938def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2939          (CRANDC $s1, $s2)>;
2940def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2941          (CRANDC $s2, $s1)>;
2942// CRORC is:
2943//   1 1 : T
2944//   1 0 : T
2945//   0 1 : F
2946//   0 0 : T
2947//
2948// LE is:
2949//  -1 -1 : T
2950//  -1  0 : T
2951//   0 -1 : F
2952//   0  0 : T
2953//
2954// ULE is:
2955//   1 1 : T
2956//   1 0 : F
2957//   0 1 : T
2958//   0 0 : T
2959def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2960          (CRORC $s1, $s2)>;
2961def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2962          (CRORC $s2, $s1)>;
2963
2964def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2965          (CREQV $s1, $s2)>;
2966
2967// GE is:
2968//  -1 -1 : T
2969//  -1  0 : F
2970//   0 -1 : T
2971//   0  0 : T
2972//
2973// UGE is:
2974//   1 1 : T
2975//   1 0 : T
2976//   0 1 : F
2977//   0 0 : T
2978def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2979          (CRORC $s2, $s1)>;
2980def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2981          (CRORC $s1, $s2)>;
2982
2983// GT is:
2984//  -1 -1 : F
2985//  -1  0 : F
2986//   0 -1 : T
2987//   0  0 : F
2988//
2989// UGT is:
2990//  1 1 : F
2991//  1 0 : T
2992//  0 1 : F
2993//  0 0 : F
2994def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2995          (CRANDC $s2, $s1)>;
2996def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2997          (CRANDC $s1, $s2)>;
2998
2999def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
3000          (CRXOR $s1, $s2)>;
3001
3002// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
3003// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3004// floating-point types.
3005
3006multiclass CRNotPat<dag pattern, dag result> {
3007  def : Pat<pattern, (crnot result)>;
3008  def : Pat<(not pattern), result>;
3009
3010  // We can also fold the crnot into an extension:
3011  def : Pat<(i32 (zext pattern)),
3012            (SELECT_I4 result, (LI 0), (LI 1))>;
3013  def : Pat<(i32 (sext pattern)),
3014            (SELECT_I4 result, (LI 0), (LI -1))>;
3015
3016  // We can also fold the crnot into an extension:
3017  def : Pat<(i64 (zext pattern)),
3018            (SELECT_I8 result, (LI8 0), (LI8 1))>;
3019  def : Pat<(i64 (sext pattern)),
3020            (SELECT_I8 result, (LI8 0), (LI8 -1))>;
3021
3022  // FIXME: We should choose either a zext or a sext based on other constants
3023  // already around.
3024  def : Pat<(i32 (anyext pattern)),
3025            (SELECT_I4 result, (LI 0), (LI 1))>;
3026
3027  def : Pat<(i64 (anyext pattern)),
3028            (SELECT_I8 result, (LI8 0), (LI8 1))>;
3029}
3030
3031// FIXME: Because of what seems like a bug in TableGen's type-inference code,
3032// we need to write imm:$imm in the output patterns below, not just $imm, or
3033// else the resulting matcher will not correctly add the immediate operand
3034// (making it a register operand instead).
3035
3036// extended SETCC.
3037multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
3038                       OutPatFrag rfrag, OutPatFrag rfrag8> {
3039  def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
3040            (rfrag $s1)>;
3041  def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
3042            (rfrag8 $s1)>;
3043  def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
3044            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
3045  def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
3046            (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
3047
3048  def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
3049            (rfrag $s1)>;
3050  def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
3051            (rfrag8 $s1)>;
3052  def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
3053            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
3054  def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
3055            (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
3056}
3057
3058// Note that we do all inversions below with i(32|64)not, instead of using
3059// (xori x, 1) because on the A2 nor has single-cycle latency while xori
3060// has 2-cycle latency.
3061
3062defm : ExtSetCCPat<SETEQ,
3063                   PatFrag<(ops node:$in, node:$cc),
3064                           (setcc $in, 0, $cc)>,
3065                   OutPatFrag<(ops node:$in),
3066                              (RLWINM (CNTLZW $in), 27, 31, 31)>,
3067                   OutPatFrag<(ops node:$in),
3068                              (RLDICL (CNTLZD $in), 58, 63)> >;
3069
3070defm : ExtSetCCPat<SETNE,
3071                   PatFrag<(ops node:$in, node:$cc),
3072                           (setcc $in, 0, $cc)>,
3073                   OutPatFrag<(ops node:$in),
3074                              (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
3075                   OutPatFrag<(ops node:$in),
3076                              (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
3077
3078defm : ExtSetCCPat<SETLT,
3079                   PatFrag<(ops node:$in, node:$cc),
3080                           (setcc $in, 0, $cc)>,
3081                   OutPatFrag<(ops node:$in),
3082                              (RLWINM $in, 1, 31, 31)>,
3083                   OutPatFrag<(ops node:$in),
3084                              (RLDICL $in, 1, 63)> >;
3085
3086defm : ExtSetCCPat<SETGE,
3087                   PatFrag<(ops node:$in, node:$cc),
3088                           (setcc $in, 0, $cc)>,
3089                   OutPatFrag<(ops node:$in),
3090                              (RLWINM (i32not $in), 1, 31, 31)>,
3091                   OutPatFrag<(ops node:$in),
3092                              (RLDICL (i64not $in), 1, 63)> >;
3093
3094defm : ExtSetCCPat<SETGT,
3095                   PatFrag<(ops node:$in, node:$cc),
3096                           (setcc $in, 0, $cc)>,
3097                   OutPatFrag<(ops node:$in),
3098                              (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
3099                   OutPatFrag<(ops node:$in),
3100                              (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
3101
3102defm : ExtSetCCPat<SETLE,
3103                   PatFrag<(ops node:$in, node:$cc),
3104                           (setcc $in, 0, $cc)>,
3105                   OutPatFrag<(ops node:$in),
3106                              (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
3107                   OutPatFrag<(ops node:$in),
3108                              (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
3109
3110defm : ExtSetCCPat<SETLT,
3111                   PatFrag<(ops node:$in, node:$cc),
3112                           (setcc $in, -1, $cc)>,
3113                   OutPatFrag<(ops node:$in),
3114                              (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
3115                   OutPatFrag<(ops node:$in),
3116                              (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3117
3118defm : ExtSetCCPat<SETGE,
3119                   PatFrag<(ops node:$in, node:$cc),
3120                           (setcc $in, -1, $cc)>,
3121                   OutPatFrag<(ops node:$in),
3122                              (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
3123                   OutPatFrag<(ops node:$in),
3124                              (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3125
3126defm : ExtSetCCPat<SETGT,
3127                   PatFrag<(ops node:$in, node:$cc),
3128                           (setcc $in, -1, $cc)>,
3129                   OutPatFrag<(ops node:$in),
3130                              (RLWINM (i32not $in), 1, 31, 31)>,
3131                   OutPatFrag<(ops node:$in),
3132                              (RLDICL (i64not $in), 1, 63)> >;
3133
3134defm : ExtSetCCPat<SETLE,
3135                   PatFrag<(ops node:$in, node:$cc),
3136                           (setcc $in, -1, $cc)>,
3137                   OutPatFrag<(ops node:$in),
3138                              (RLWINM $in, 1, 31, 31)>,
3139                   OutPatFrag<(ops node:$in),
3140                              (RLDICL $in, 1, 63)> >;
3141
3142// SETCC for i32.
3143def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
3144          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3145def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
3146          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3147def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
3148          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3149def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
3150          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3151def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
3152          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3153def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
3154          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3155
3156// For non-equality comparisons, the default code would materialize the
3157// constant, then compare against it, like this:
3158//   lis r2, 4660
3159//   ori r2, r2, 22136
3160//   cmpw cr0, r3, r2
3161//   beq cr0,L6
3162// Since we are just comparing for equality, we can emit this instead:
3163//   xoris r0,r3,0x1234
3164//   cmplwi cr0,r0,0x5678
3165//   beq cr0,L6
3166
3167def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
3168          (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3169                                  (LO16 imm:$imm)), sub_eq)>;
3170
3171defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
3172                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3173defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
3174                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3175defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
3176                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3177defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
3178                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3179defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
3180                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3181defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
3182                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3183
3184defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
3185                (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3186                                        (LO16 imm:$imm)), sub_eq)>;
3187
3188def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
3189          (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3190def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
3191          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3192def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
3193          (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3194def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
3195          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3196def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
3197          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3198
3199defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
3200                (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3201defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
3202                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3203defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
3204                (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3205defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
3206                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3207defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
3208                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3209
3210// SETCC for i64.
3211def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
3212          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3213def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
3214          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3215def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
3216          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3217def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
3218          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3219def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
3220          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3221def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
3222          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3223
3224// For non-equality comparisons, the default code would materialize the
3225// constant, then compare against it, like this:
3226//   lis r2, 4660
3227//   ori r2, r2, 22136
3228//   cmpd cr0, r3, r2
3229//   beq cr0,L6
3230// Since we are just comparing for equality, we can emit this instead:
3231//   xoris r0,r3,0x1234
3232//   cmpldi cr0,r0,0x5678
3233//   beq cr0,L6
3234
3235def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
3236          (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3237                                  (LO16 imm:$imm)), sub_eq)>;
3238
3239defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3240                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3241defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
3242                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3243defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
3244                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3245defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
3246                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3247defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
3248                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3249defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
3250                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3251
3252defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
3253                (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3254                                        (LO16 imm:$imm)), sub_eq)>;
3255
3256def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
3257          (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3258def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3259          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3260def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3261          (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3262def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
3263          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3264def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
3265          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3266
3267defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3268                (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3269defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
3270                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3271defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
3272                (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3273defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
3274                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3275defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
3276                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3277
3278// SETCC for f32.
3279def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
3280          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3281def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
3282          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3283def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
3284          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3285def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
3286          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3287def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
3288          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3289def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
3290          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3291def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
3292          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3293
3294defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3295                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3296defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
3297                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3298defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
3299                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3300defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
3301                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3302defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
3303                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3304defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
3305                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3306defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
3307                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3308
3309// SETCC for f64.
3310def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
3311          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3312def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
3313          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3314def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
3315          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3316def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
3317          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3318def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
3319          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3320def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
3321          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3322def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
3323          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3324
3325defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3326                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3327defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
3328                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3329defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
3330                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3331defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
3332                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3333defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
3334                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3335defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
3336                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3337defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
3338                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3339
3340// match select on i1 variables:
3341def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
3342          (CROR (CRAND        $cond , $tval),
3343                (CRAND (crnot $cond), $fval))>;
3344
3345// match selectcc on i1 variables:
3346//   select (lhs == rhs), tval, fval is:
3347//   ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
3348def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
3349           (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3350                 (CRAND (CRORC  $rhs, $lhs), $fval))>;
3351def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)),
3352           (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3353                 (CRAND (CRORC  $lhs, $rhs), $fval))>;
3354def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
3355           (CROR (CRAND (CRORC  $lhs, $rhs), $tval),
3356                 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3357def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)),
3358           (CROR (CRAND (CRORC  $rhs, $lhs), $tval),
3359                 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3360def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
3361           (CROR (CRAND (CREQV $lhs, $rhs), $tval),
3362                 (CRAND (CRXOR $lhs, $rhs), $fval))>;
3363def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
3364           (CROR (CRAND (CRORC  $rhs, $lhs), $tval),
3365                 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3366def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)),
3367           (CROR (CRAND (CRORC  $lhs, $rhs), $tval),
3368                 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3369def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
3370           (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3371                 (CRAND (CRORC  $lhs, $rhs), $fval))>;
3372def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)),
3373           (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3374                 (CRAND (CRORC  $rhs, $lhs), $fval))>;
3375def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
3376           (CROR (CRAND (CREQV $lhs, $rhs), $fval),
3377                 (CRAND (CRXOR $lhs, $rhs), $tval))>;
3378
3379// match selectcc on i1 variables with non-i1 output.
3380def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3381          (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3382def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)),
3383          (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3384def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3385          (SELECT_I4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3386def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)),
3387          (SELECT_I4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3388def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3389          (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3390def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3391          (SELECT_I4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3392def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)),
3393          (SELECT_I4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3394def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3395          (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3396def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)),
3397          (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3398def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3399          (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3400
3401def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3402          (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3403def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)),
3404          (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3405def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3406          (SELECT_I8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3407def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)),
3408          (SELECT_I8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3409def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3410          (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3411def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3412          (SELECT_I8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3413def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)),
3414          (SELECT_I8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3415def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3416          (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3417def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)),
3418          (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3419def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3420          (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3421
3422def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3423          (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3424def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
3425          (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3426def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3427          (SELECT_F4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3428def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),
3429          (SELECT_F4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3430def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3431          (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3432def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3433          (SELECT_F4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3434def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
3435          (SELECT_F4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3436def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3437          (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3438def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
3439          (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3440def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3441          (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3442
3443def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3444          (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3445def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
3446          (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3447def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3448          (SELECT_F8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3449def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)),
3450          (SELECT_F8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3451def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3452          (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3453def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3454          (SELECT_F8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3455def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
3456          (SELECT_F8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3457def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3458          (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3459def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
3460          (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3461def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3462          (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3463
3464def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3465          (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3466def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)),
3467          (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3468def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3469          (SELECT_VRRC (CRORC  $lhs, $rhs), $tval, $fval)>;
3470def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)),
3471          (SELECT_VRRC (CRORC  $rhs, $lhs), $tval, $fval)>;
3472def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3473          (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3474def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3475          (SELECT_VRRC (CRORC  $rhs, $lhs), $tval, $fval)>;
3476def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)),
3477          (SELECT_VRRC (CRORC  $lhs, $rhs), $tval, $fval)>;
3478def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3479          (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3480def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)),
3481          (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3482def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3483          (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3484
3485let usesCustomInserter = 1 in {
3486def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3487                             "#ANDIo_1_EQ_BIT",
3488                             [(set i1:$dst, (trunc (not i32:$in)))]>;
3489def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3490                             "#ANDIo_1_GT_BIT",
3491                             [(set i1:$dst, (trunc i32:$in))]>;
3492
3493def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3494                              "#ANDIo_1_EQ_BIT8",
3495                              [(set i1:$dst, (trunc (not i64:$in)))]>;
3496def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3497                              "#ANDIo_1_GT_BIT8",
3498                              [(set i1:$dst, (trunc i64:$in))]>;
3499}
3500
3501def : Pat<(i1 (not (trunc i32:$in))),
3502           (ANDIo_1_EQ_BIT $in)>;
3503def : Pat<(i1 (not (trunc i64:$in))),
3504           (ANDIo_1_EQ_BIT8 $in)>;
3505
3506//===----------------------------------------------------------------------===//
3507// PowerPC Instructions used for assembler/disassembler only
3508//
3509
3510// FIXME: For B=0 or B > 8, the registers following RT are used.
3511// WARNING: Do not add patterns for this instruction without fixing this.
3512def LSWI  : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3513                            "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3514
3515// FIXME: For B=0 or B > 8, the registers following RT are used.
3516// WARNING: Do not add patterns for this instruction without fixing this.
3517def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3518                            "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3519
3520def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3521                         "isync", IIC_SprISYNC, []>;
3522
3523def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3524                    "icbi $src", IIC_LdStICBI, []>;
3525
3526// We used to have EIEIO as value but E[0-9A-Z] is a reserved name
3527def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3528                           "eieio", IIC_LdStLoad, []>;
3529
3530def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3531                         "wait $L", IIC_LdStLoad, []>;
3532
3533def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3534                         "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3535
3536def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3537            "mtsr $SR, $RS", IIC_SprMTSR>;
3538
3539def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3540            "mfsr $RS, $SR", IIC_SprMFSR>;
3541
3542def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3543            "mtsrin $RS, $RB", IIC_SprMTSR>;
3544
3545def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3546            "mfsrin $RS, $RB", IIC_SprMFSR>;
3547
3548def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3549                    "mtmsr $RS, $L", IIC_SprMTMSR>;
3550
3551def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3552                    "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3553  let L = 0;
3554}
3555
3556def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3557              Requires<[IsBookE]> {
3558  bits<1> E;
3559
3560  let Inst{16} = E;
3561  let Inst{21-30} = 163;
3562}
3563
3564def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3565               "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3566def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3567               "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3568
3569def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3570def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3571def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3572def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3573
3574def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3575                  "mfmsr $RT", IIC_SprMFMSR, []>;
3576
3577def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3578                    "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3579
3580def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
3581                     "mcrfs $BF, $BFA", IIC_BrMCR>;
3582
3583def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3584                      "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
3585
3586def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3587                       "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
3588
3589def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
3590def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
3591
3592def MTFSF : XFLForm_1<63, 711, (outs),
3593                      (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3594                      "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
3595def MTFSFo : XFLForm_1<63, 711, (outs),
3596                       (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3597                       "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
3598
3599def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3600def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3601
3602def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3603                        "slbie $RB", IIC_SprSLBIE, []>;
3604
3605def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3606                    "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3607
3608def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3609                       "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3610
3611def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3612
3613def TLBIA : XForm_0<31, 370, (outs), (ins),
3614                        "tlbia", IIC_SprTLBIA, []>;
3615
3616def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3617                        "tlbsync", IIC_SprTLBSYNC, []>;
3618
3619def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3620                          "tlbiel $RB", IIC_SprTLBIEL, []>;
3621
3622def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3623                          "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3624def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3625                          "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3626
3627def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3628                          "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3629
3630def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3631                IIC_LdStLoad>, Requires<[IsBookE]>;
3632
3633def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3634                IIC_LdStLoad>, Requires<[IsBookE]>;
3635
3636def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3637                           "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3638
3639def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3640                           "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3641
3642def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3643               "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3644
3645def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3646               "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3647
3648def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3649                             "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3650                             Requires<[IsPPC4xx]>;
3651def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3652                              (ins gprc:$RST, gprc:$A, gprc:$B),
3653                              "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3654                              Requires<[IsPPC4xx]>, isDOT;
3655
3656def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3657
3658def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3659                  Requires<[IsBookE]>;
3660def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3661                   Requires<[IsBookE]>;
3662
3663def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3664                   Requires<[IsE500]>;
3665def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3666                    Requires<[IsE500]>;
3667
3668def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3669                      "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3670def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3671                      "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3672
3673def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
3674
3675def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3676                             "lbzcix $RST, $A, $B", IIC_LdStLoad, []>;
3677def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3678                             "lhzcix $RST, $A, $B", IIC_LdStLoad, []>;
3679def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3680                             "lwzcix $RST, $A, $B", IIC_LdStLoad, []>;
3681def LDCIX :  XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3682                             "ldcix $RST, $A, $B", IIC_LdStLoad, []>;
3683
3684def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3685                             "stbcix $RST, $A, $B", IIC_LdStLoad, []>;
3686def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3687                             "sthcix $RST, $A, $B", IIC_LdStLoad, []>;
3688def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3689                             "stwcix $RST, $A, $B", IIC_LdStLoad, []>;
3690def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3691                             "stdcix $RST, $A, $B", IIC_LdStLoad, []>;
3692
3693//===----------------------------------------------------------------------===//
3694// PowerPC Assembler Instruction Aliases
3695//
3696
3697// Pseudo-instructions for alternate assembly syntax (never used by codegen).
3698// These are aliases that require C++ handling to convert to the target
3699// instruction, while InstAliases can be handled directly by tblgen.
3700class PPCAsmPseudo<string asm, dag iops>
3701  : Instruction {
3702  let Namespace = "PPC";
3703  bit PPC64 = 0;  // Default value, override with isPPC64
3704
3705  let OutOperandList = (outs);
3706  let InOperandList = iops;
3707  let Pattern = [];
3708  let AsmString = asm;
3709  let isAsmParserOnly = 1;
3710  let isPseudo = 1;
3711}
3712
3713def : InstAlias<"sc", (SC 0)>;
3714
3715def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
3716def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>;
3717def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
3718def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
3719
3720def : InstAlias<"wait", (WAIT 0)>;
3721def : InstAlias<"waitrsv", (WAIT 1)>;
3722def : InstAlias<"waitimpl", (WAIT 2)>;
3723
3724def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3725
3726def DCBTx   : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>;
3727def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>;
3728
3729def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3730def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3731def DCBTT  : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>;
3732
3733def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3734def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3735def DCBTSTT  : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>;
3736
3737def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3738def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3739def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3740def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3741
3742def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3743def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3744
3745def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3746def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3747
3748def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3749def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3750
3751def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3752def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3753
3754def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3755def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3756
3757def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3758def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3759
3760def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3761def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3762
3763def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3764def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3765
3766def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3767def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3768
3769def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3770def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3771
3772def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3773def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3774
3775def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3776def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3777
3778def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3779def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3780
3781def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3782def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3783
3784def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3785def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3786def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3787
3788def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3789def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3790
3791def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3792def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3793def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3794def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3795
3796def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3797
3798def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3799def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3800
3801def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3802def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3803
3804def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3805
3806foreach BATR = 0-3 in {
3807    def : InstAlias<"mtdbatu "#BATR#", $Rx",
3808                    (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3809                    Requires<[IsPPC6xx]>;
3810    def : InstAlias<"mfdbatu $Rx, "#BATR,
3811                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3812                    Requires<[IsPPC6xx]>;
3813    def : InstAlias<"mtdbatl "#BATR#", $Rx",
3814                    (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3815                    Requires<[IsPPC6xx]>;
3816    def : InstAlias<"mfdbatl $Rx, "#BATR,
3817                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3818                    Requires<[IsPPC6xx]>;
3819    def : InstAlias<"mtibatu "#BATR#", $Rx",
3820                    (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3821                    Requires<[IsPPC6xx]>;
3822    def : InstAlias<"mfibatu $Rx, "#BATR,
3823                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3824                    Requires<[IsPPC6xx]>;
3825    def : InstAlias<"mtibatl "#BATR#", $Rx",
3826                    (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3827                    Requires<[IsPPC6xx]>;
3828    def : InstAlias<"mfibatl $Rx, "#BATR,
3829                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3830                    Requires<[IsPPC6xx]>;
3831}
3832
3833foreach BR = 0-7 in {
3834    def : InstAlias<"mfbr"#BR#" $Rx",
3835                    (MFDCR gprc:$Rx, !add(BR, 0x80))>,
3836                    Requires<[IsPPC4xx]>;
3837    def : InstAlias<"mtbr"#BR#" $Rx",
3838                    (MTDCR gprc:$Rx, !add(BR, 0x80))>,
3839                    Requires<[IsPPC4xx]>;
3840}
3841
3842def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3843def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
3844
3845def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3846def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
3847
3848def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3849def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
3850
3851def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3852def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
3853
3854def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
3855def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
3856
3857def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3858def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
3859
3860def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3861
3862def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3863                        (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3864def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3865                         (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3866def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3867                         (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3868def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3869                          (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3870
3871def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3872def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3873def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3874def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3875
3876def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3877def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3878
3879def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
3880def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
3881
3882foreach SPRG = 0-3 in {
3883  def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
3884  def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
3885  def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3886  def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3887}
3888foreach SPRG = 4-7 in {
3889  def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
3890                  Requires<[IsBookE]>;
3891  def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
3892                  Requires<[IsBookE]>;
3893  def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3894                  Requires<[IsBookE]>;
3895  def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3896                  Requires<[IsBookE]>;
3897}
3898
3899def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3900
3901def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3902def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3903
3904def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3905
3906def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3907def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3908
3909def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3910def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3911def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3912def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3913
3914def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3915
3916def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
3917                Requires<[IsPPC4xx]>;
3918def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
3919                Requires<[IsPPC4xx]>;
3920def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
3921                Requires<[IsPPC4xx]>;
3922def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
3923                Requires<[IsPPC4xx]>;
3924
3925def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3926                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3927def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3928                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3929def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3930                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3931def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3932                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3933def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3934                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3935def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3936                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3937def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3938                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3939def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3940                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3941def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3942                          (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3943def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3944                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3945def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3946                        (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3947def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3948                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3949def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3950                        (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3951def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3952                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3953def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3954                          (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3955def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3956                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3957def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3958                            (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3959def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3960                             (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3961
3962def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3963def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3964def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3965def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3966def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3967def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3968
3969def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
3970def : InstAlias<"cntlzw. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>;
3971// The POWER variant
3972def : MnemonicAlias<"cntlz",  "cntlzw">;
3973def : MnemonicAlias<"cntlz.", "cntlzw.">;
3974
3975def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3976                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3977def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3978                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3979def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3980                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3981def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3982                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3983def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3984                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3985def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3986                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3987def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3988                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3989def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3990                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3991def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3992                        (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3993def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3994                         (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3995def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3996                        (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3997def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3998                         (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3999def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
4000                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4001def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
4002                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4003def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
4004                            (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
4005def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
4006                             (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
4007
4008def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
4009def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
4010def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
4011def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
4012def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
4013def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
4014
4015def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b",
4016                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4017def RLWINMobm : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b",
4018                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4019def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b",
4020                           (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4021def RLWIMIobm : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b",
4022                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4023def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b",
4024                          (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4025def RLWNMobm : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b",
4026                           (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4027
4028// These generic branch instruction forms are used for the assembler parser only.
4029// Defs and Uses are conservative, since we don't know the BO value.
4030let PPC970_Unit = 7 in {
4031  let Defs = [CTR], Uses = [CTR, RM] in {
4032    def gBC : BForm_3<16, 0, 0, (outs),
4033                      (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
4034                      "bc $bo, $bi, $dst">;
4035    def gBCA : BForm_3<16, 1, 0, (outs),
4036                       (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
4037                       "bca $bo, $bi, $dst">;
4038  }
4039  let Defs = [LR, CTR], Uses = [CTR, RM] in {
4040    def gBCL : BForm_3<16, 0, 1, (outs),
4041                       (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
4042                       "bcl $bo, $bi, $dst">;
4043    def gBCLA : BForm_3<16, 1, 1, (outs),
4044                        (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
4045                        "bcla $bo, $bi, $dst">;
4046  }
4047  let Defs = [CTR], Uses = [CTR, LR, RM] in
4048    def gBCLR : XLForm_2<19, 16, 0, (outs),
4049                         (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4050                         "bclr $bo, $bi, $bh", IIC_BrB, []>;
4051  let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
4052    def gBCLRL : XLForm_2<19, 16, 1, (outs),
4053                          (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4054                          "bclrl $bo, $bi, $bh", IIC_BrB, []>;
4055  let Defs = [CTR], Uses = [CTR, LR, RM] in
4056    def gBCCTR : XLForm_2<19, 528, 0, (outs),
4057                          (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4058                          "bcctr $bo, $bi, $bh", IIC_BrB, []>;
4059  let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
4060    def gBCCTRL : XLForm_2<19, 528, 1, (outs),
4061                           (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4062                           "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
4063}
4064def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
4065def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
4066def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
4067def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
4068
4069multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
4070  def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
4071  def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
4072  def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
4073  def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
4074  def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
4075  def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
4076}
4077multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
4078  : BranchSimpleMnemonic1<name, pm, bo> {
4079  def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
4080  def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
4081}
4082defm : BranchSimpleMnemonic2<"t", "", 12>;
4083defm : BranchSimpleMnemonic2<"f", "", 4>;
4084defm : BranchSimpleMnemonic2<"t", "-", 14>;
4085defm : BranchSimpleMnemonic2<"f", "-", 6>;
4086defm : BranchSimpleMnemonic2<"t", "+", 15>;
4087defm : BranchSimpleMnemonic2<"f", "+", 7>;
4088defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
4089defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
4090defm : BranchSimpleMnemonic1<"dzt", "", 10>;
4091defm : BranchSimpleMnemonic1<"dzf", "", 2>;
4092
4093multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
4094  def : InstAlias<"b"#name#pm#" $cc, $dst",
4095                  (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
4096  def : InstAlias<"b"#name#pm#" $dst",
4097                  (BCC bibo, CR0, condbrtarget:$dst)>;
4098
4099  def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
4100                  (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
4101  def : InstAlias<"b"#name#"a"#pm#" $dst",
4102                  (BCCA bibo, CR0, abscondbrtarget:$dst)>;
4103
4104  def : InstAlias<"b"#name#"lr"#pm#" $cc",
4105                  (BCCLR bibo, crrc:$cc)>;
4106  def : InstAlias<"b"#name#"lr"#pm,
4107                  (BCCLR bibo, CR0)>;
4108
4109  def : InstAlias<"b"#name#"ctr"#pm#" $cc",
4110                  (BCCCTR bibo, crrc:$cc)>;
4111  def : InstAlias<"b"#name#"ctr"#pm,
4112                  (BCCCTR bibo, CR0)>;
4113
4114  def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
4115                  (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
4116  def : InstAlias<"b"#name#"l"#pm#" $dst",
4117                  (BCCL bibo, CR0, condbrtarget:$dst)>;
4118
4119  def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
4120                  (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
4121  def : InstAlias<"b"#name#"la"#pm#" $dst",
4122                  (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
4123
4124  def : InstAlias<"b"#name#"lrl"#pm#" $cc",
4125                  (BCCLRL bibo, crrc:$cc)>;
4126  def : InstAlias<"b"#name#"lrl"#pm,
4127                  (BCCLRL bibo, CR0)>;
4128
4129  def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
4130                  (BCCCTRL bibo, crrc:$cc)>;
4131  def : InstAlias<"b"#name#"ctrl"#pm,
4132                  (BCCCTRL bibo, CR0)>;
4133}
4134multiclass BranchExtendedMnemonic<string name, int bibo> {
4135  defm : BranchExtendedMnemonicPM<name, "", bibo>;
4136  defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
4137  defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
4138}
4139defm : BranchExtendedMnemonic<"lt", 12>;
4140defm : BranchExtendedMnemonic<"gt", 44>;
4141defm : BranchExtendedMnemonic<"eq", 76>;
4142defm : BranchExtendedMnemonic<"un", 108>;
4143defm : BranchExtendedMnemonic<"so", 108>;
4144defm : BranchExtendedMnemonic<"ge", 4>;
4145defm : BranchExtendedMnemonic<"nl", 4>;
4146defm : BranchExtendedMnemonic<"le", 36>;
4147defm : BranchExtendedMnemonic<"ng", 36>;
4148defm : BranchExtendedMnemonic<"ne", 68>;
4149defm : BranchExtendedMnemonic<"nu", 100>;
4150defm : BranchExtendedMnemonic<"ns", 100>;
4151
4152def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
4153def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
4154def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
4155def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
4156def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
4157def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
4158def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
4159def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
4160
4161def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
4162def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
4163def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
4164def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
4165def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
4166def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
4167def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
4168def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
4169
4170multiclass TrapExtendedMnemonic<string name, int to> {
4171  def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
4172  def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
4173  def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
4174  def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
4175}
4176defm : TrapExtendedMnemonic<"lt", 16>;
4177defm : TrapExtendedMnemonic<"le", 20>;
4178defm : TrapExtendedMnemonic<"eq", 4>;
4179defm : TrapExtendedMnemonic<"ge", 12>;
4180defm : TrapExtendedMnemonic<"gt", 8>;
4181defm : TrapExtendedMnemonic<"nl", 12>;
4182defm : TrapExtendedMnemonic<"ne", 24>;
4183defm : TrapExtendedMnemonic<"ng", 20>;
4184defm : TrapExtendedMnemonic<"llt", 2>;
4185defm : TrapExtendedMnemonic<"lle", 6>;
4186defm : TrapExtendedMnemonic<"lge", 5>;
4187defm : TrapExtendedMnemonic<"lgt", 1>;
4188defm : TrapExtendedMnemonic<"lnl", 5>;
4189defm : TrapExtendedMnemonic<"lng", 6>;
4190defm : TrapExtendedMnemonic<"u", 31>;
4191
4192// Atomic loads
4193def : Pat<(atomic_load_8  iaddr:$src), (LBZ  memri:$src)>;
4194def : Pat<(atomic_load_16 iaddr:$src), (LHZ  memri:$src)>;
4195def : Pat<(atomic_load_32 iaddr:$src), (LWZ  memri:$src)>;
4196def : Pat<(atomic_load_8  xaddr:$src), (LBZX memrr:$src)>;
4197def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
4198def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
4199
4200// Atomic stores
4201def : Pat<(atomic_store_8  iaddr:$ptr, i32:$val), (STB  gprc:$val, memri:$ptr)>;
4202def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH  gprc:$val, memri:$ptr)>;
4203def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW  gprc:$val, memri:$ptr)>;
4204def : Pat<(atomic_store_8  xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
4205def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
4206def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;
4207
4208let Predicates = [IsISA3_0] in {
4209
4210// Copy-Paste Facility
4211// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to
4212// PASTE for naming consistency.
4213let mayLoad = 1 in
4214def CP_COPY   : X_L1_RA5_RB5<31, 774, "copy"  , gprc, IIC_LdStCOPY, []>;
4215
4216let mayStore = 1 in
4217def CP_PASTE  : X_L1_RA5_RB5<31, 902, "paste" , gprc, IIC_LdStPASTE, []>;
4218
4219let mayStore = 1, Defs = [CR0] in
4220def CP_PASTEo : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isDOT;
4221
4222def CP_COPYx  : PPCAsmPseudo<"copy $rA, $rB" , (ins gprc:$rA, gprc:$rB)>;
4223def CP_PASTEx : PPCAsmPseudo<"paste $rA, $rB", (ins gprc:$rA, gprc:$rB)>;
4224def CP_COPY_FIRST : PPCAsmPseudo<"copy_first $rA, $rB",
4225                                  (ins gprc:$rA, gprc:$rB)>;
4226def CP_PASTE_LAST : PPCAsmPseudo<"paste_last $rA, $rB",
4227                                  (ins gprc:$rA, gprc:$rB)>;
4228def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cp_abort", IIC_SprABORT, []>;
4229
4230// Message Synchronize
4231def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>;
4232
4233// Power-Saving Mode Instruction:
4234def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>;
4235
4236} // IsISA3_0
4237