1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the subset of the 32-bit PowerPC instruction set, as used
11// by the PowerPC instruction selector.
12//
13//===----------------------------------------------------------------------===//
14
15include "PPCInstrFormats.td"
16
17//===----------------------------------------------------------------------===//
18// PowerPC specific type constraints.
19//
20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21  SDTCisVT<0, f64>, SDTCisPtrTy<1>
22]>;
23def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24  SDTCisVT<0, f64>, SDTCisPtrTy<1>
25]>;
26def SDT_PPCLxsizx : SDTypeProfile<1, 2, [
27  SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
28]>;
29def SDT_PPCstxsix : SDTypeProfile<0, 3, [
30  SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
31]>;
32def SDT_PPCVexts  : SDTypeProfile<1, 2, [
33  SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2>
34]>;
35
36def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
37def SDT_PPCCallSeqEnd   : SDCallSeqEnd<[ SDTCisVT<0, i32>,
38                                         SDTCisVT<1, i32> ]>;
39def SDT_PPCvperm   : SDTypeProfile<1, 3, [
40  SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
41]>;
42
43def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>,
44  SDTCisVec<1>, SDTCisInt<2>
45]>;
46
47def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>,
48  SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3>
49]>;
50
51def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>,
52  SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3>
53]>;
54
55def SDT_PPCvcmp : SDTypeProfile<1, 3, [
56  SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
57]>;
58
59def SDT_PPCcondbr : SDTypeProfile<0, 3, [
60  SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
61]>;
62
63def SDT_PPClbrx : SDTypeProfile<1, 2, [
64  SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
65]>;
66def SDT_PPCstbrx : SDTypeProfile<0, 3, [
67  SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
68]>;
69
70def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
71  SDTCisPtrTy<0>, SDTCisVT<1, i32>
72]>;
73
74def tocentry32 : Operand<iPTR> {
75  let MIOperandInfo = (ops i32imm:$imm);
76}
77
78def SDT_PPCqvfperm   : SDTypeProfile<1, 3, [
79  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3>
80]>;
81def SDT_PPCqvgpci   : SDTypeProfile<1, 1, [
82  SDTCisVec<0>, SDTCisInt<1>
83]>;
84def SDT_PPCqvaligni   : SDTypeProfile<1, 3, [
85  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>
86]>;
87def SDT_PPCqvesplati   : SDTypeProfile<1, 2, [
88  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>
89]>;
90
91def SDT_PPCqbflt : SDTypeProfile<1, 1, [
92  SDTCisVec<0>, SDTCisVec<1>
93]>;
94
95def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [
96  SDTCisVec<0>, SDTCisPtrTy<1>
97]>;
98
99//===----------------------------------------------------------------------===//
100// PowerPC specific DAG Nodes.
101//
102
103def PPCfre    : SDNode<"PPCISD::FRE",     SDTFPUnaryOp, []>;
104def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
105
106def PPCfcfid  : SDNode<"PPCISD::FCFID",   SDTFPUnaryOp, []>;
107def PPCfcfidu : SDNode<"PPCISD::FCFIDU",  SDTFPUnaryOp, []>;
108def PPCfcfids : SDNode<"PPCISD::FCFIDS",  SDTFPRoundOp, []>;
109def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
110def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
111def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
112def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
113def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
114def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
115                       [SDNPHasChain, SDNPMayStore]>;
116def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
117                       [SDNPHasChain, SDNPMayLoad]>;
118def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
119                       [SDNPHasChain, SDNPMayLoad]>;
120def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx,
121                       [SDNPHasChain, SDNPMayLoad]>;
122def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix,
123                       [SDNPHasChain, SDNPMayStore]>;
124def PPCVexts  : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>;
125
126// Extract FPSCR (not modeled at the DAG level).
127def PPCmffs   : SDNode<"PPCISD::MFFS",
128                       SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
129
130// Perform FADD in round-to-zero mode.
131def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
132
133
134def PPCfsel   : SDNode<"PPCISD::FSEL",
135   // Type constraint for fsel.
136   SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
137                        SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
138
139def PPChi       : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
140def PPClo       : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
141def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp,
142                         [SDNPMayLoad, SDNPMemOperand]>;
143def PPCvmaddfp  : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
144def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
145
146def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
147
148def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
149def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
150                            [SDNPMayLoad]>;
151def PPCaddTls     : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
152def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
153def PPCaddiTlsgdL   : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
154def PPCgetTlsAddr   : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
155def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR",
156                               SDTypeProfile<1, 3, [
157                                 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
158                                 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
159def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
160def PPCaddiTlsldL   : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
161def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
162def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR",
163                               SDTypeProfile<1, 3, [
164                                 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
165                                 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
166def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;
167def PPCaddiDtprelL   : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
168
169def PPCvperm     : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
170def PPCxxsplt    : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>;
171def PPCxxinsert  : SDNode<"PPCISD::XXINSERT", SDT_PPCVecInsert, []>;
172def PPCvecshl    : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>;
173
174def PPCqvfperm   : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>;
175def PPCqvgpci    : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>;
176def PPCqvaligni  : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>;
177def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>;
178
179def PPCqbflt     : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>;
180
181def PPCqvlfsb    : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb,
182                          [SDNPHasChain, SDNPMayLoad]>;
183
184def PPCcmpb     : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>;
185
186// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
187// amounts.  These nodes are generated by the multi-precision shift code.
188def PPCsrl        : SDNode<"PPCISD::SRL"       , SDTIntShiftOp>;
189def PPCsra        : SDNode<"PPCISD::SRA"       , SDTIntShiftOp>;
190def PPCshl        : SDNode<"PPCISD::SHL"       , SDTIntShiftOp>;
191
192// These are target-independent nodes, but have target-specific formats.
193def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
194                           [SDNPHasChain, SDNPOutGlue]>;
195def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_PPCCallSeqEnd,
196                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
197
198def SDT_PPCCall   : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
199def PPCcall  : SDNode<"PPCISD::CALL", SDT_PPCCall,
200                      [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
201                       SDNPVariadic]>;
202def PPCcall_nop  : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
203                          [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
204                           SDNPVariadic]>;
205def PPCmtctr      : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
206                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
207def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
208                      [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
209                       SDNPVariadic]>;
210def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC",
211                               SDTypeProfile<0, 1, []>,
212                               [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
213                                SDNPVariadic]>;
214
215def retflag       : SDNode<"PPCISD::RET_FLAG", SDTNone,
216                           [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
217
218def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
219                        [SDNPHasChain,  SDNPOptInGlue, SDNPVariadic]>;
220
221def PPCeh_sjlj_setjmp  : SDNode<"PPCISD::EH_SJLJ_SETJMP",
222                                SDTypeProfile<1, 1, [SDTCisInt<0>,
223                                                     SDTCisPtrTy<1>]>,
224                                [SDNPHasChain, SDNPSideEffect]>;
225def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
226                                SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
227                                [SDNPHasChain, SDNPSideEffect]>;
228
229def SDT_PPCsc     : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
230def PPCsc         : SDNode<"PPCISD::SC", SDT_PPCsc,
231                           [SDNPHasChain, SDNPSideEffect]>;
232
233def PPCclrbhrb    : SDNode<"PPCISD::CLRBHRB", SDTNone,
234                           [SDNPHasChain, SDNPSideEffect]>;
235def PPCmfbhrbe    : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>;
236def PPCrfebb      : SDNode<"PPCISD::RFEBB", SDT_PPCsc,
237                           [SDNPHasChain, SDNPSideEffect]>;
238
239def PPCvcmp       : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
240def PPCvcmp_o     : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
241
242def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
243                           [SDNPHasChain, SDNPOptInGlue]>;
244
245def PPClbrx       : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
246                           [SDNPHasChain, SDNPMayLoad]>;
247def PPCstbrx      : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
248                           [SDNPHasChain, SDNPMayStore]>;
249
250// Instructions to set/unset CR bit 6 for SVR4 vararg calls
251def PPCcr6set   : SDNode<"PPCISD::CR6SET", SDTNone,
252                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
253def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
254                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
255
256// Instructions to support dynamic alloca.
257def SDTDynOp  : SDTypeProfile<1, 2, []>;
258def SDTDynAreaOp  : SDTypeProfile<1, 1, []>;
259def PPCdynalloc   : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
260def PPCdynareaoffset   : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>;
261
262//===----------------------------------------------------------------------===//
263// PowerPC specific transformation functions and pattern fragments.
264//
265
266def SHL32 : SDNodeXForm<imm, [{
267  // Transformation function: 31 - imm
268  return getI32Imm(31 - N->getZExtValue(), SDLoc(N));
269}]>;
270
271def SRL32 : SDNodeXForm<imm, [{
272  // Transformation function: 32 - imm
273  return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N))
274                           : getI32Imm(0, SDLoc(N));
275}]>;
276
277def LO16 : SDNodeXForm<imm, [{
278  // Transformation function: get the low 16 bits.
279  return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N));
280}]>;
281
282def HI16 : SDNodeXForm<imm, [{
283  // Transformation function: shift the immediate value down into the low bits.
284  return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N));
285}]>;
286
287def HA16 : SDNodeXForm<imm, [{
288  // Transformation function: shift the immediate value down into the low bits.
289  int Val = N->getZExtValue();
290  return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N));
291}]>;
292def MB : SDNodeXForm<imm, [{
293  // Transformation function: get the start bit of a mask
294  unsigned mb = 0, me;
295  (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
296  return getI32Imm(mb, SDLoc(N));
297}]>;
298
299def ME : SDNodeXForm<imm, [{
300  // Transformation function: get the end bit of a mask
301  unsigned mb, me = 0;
302  (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
303  return getI32Imm(me, SDLoc(N));
304}]>;
305def maskimm32 : PatLeaf<(imm), [{
306  // maskImm predicate - True if immediate is a run of ones.
307  unsigned mb, me;
308  if (N->getValueType(0) == MVT::i32)
309    return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
310  else
311    return false;
312}]>;
313
314def imm32SExt16  : Operand<i32>, ImmLeaf<i32, [{
315  // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
316  // sign extended field.  Used by instructions like 'addi'.
317  return (int32_t)Imm == (short)Imm;
318}]>;
319def imm64SExt16  : Operand<i64>, ImmLeaf<i64, [{
320  // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
321  // sign extended field.  Used by instructions like 'addi'.
322  return (int64_t)Imm == (short)Imm;
323}]>;
324def immZExt16  : PatLeaf<(imm), [{
325  // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
326  // field.  Used by instructions like 'ori'.
327  return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
328}], LO16>;
329def immSExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm); }]>;
330def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>;
331
332// imm16Shifted* - These match immediates where the low 16-bits are zero.  There
333// are two forms: imm16ShiftedSExt and imm16ShiftedZExt.  These two forms are
334// identical in 32-bit mode, but in 64-bit mode, they return true if the
335// immediate fits into a sign/zero extended 32-bit immediate (with the low bits
336// clear).
337def imm16ShiftedZExt : PatLeaf<(imm), [{
338  // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
339  // immediate are set.  Used by instructions like 'xoris'.
340  return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
341}], HI16>;
342
343def imm16ShiftedSExt : PatLeaf<(imm), [{
344  // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
345  // immediate are set.  Used by instructions like 'addis'.  Identical to
346  // imm16ShiftedZExt in 32-bit mode.
347  if (N->getZExtValue() & 0xFFFF) return false;
348  if (N->getValueType(0) == MVT::i32)
349    return true;
350  // For 64-bit, make sure it is sext right.
351  return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
352}], HI16>;
353
354def imm64ZExt32  : Operand<i64>, ImmLeaf<i64, [{
355  // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
356  // zero extended field.
357  return isUInt<32>(Imm);
358}]>;
359
360// Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
361// restricted memrix (4-aligned) constants are alignment sensitive. If these
362// offsets are hidden behind TOC entries than the values of the lower-order
363// bits cannot be checked directly. As a result, we need to also incorporate
364// an alignment check into the relevant patterns.
365
366def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
367  return cast<LoadSDNode>(N)->getAlignment() >= 4;
368}]>;
369def aligned4store : PatFrag<(ops node:$val, node:$ptr),
370                            (store node:$val, node:$ptr), [{
371  return cast<StoreSDNode>(N)->getAlignment() >= 4;
372}]>;
373def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
374  return cast<LoadSDNode>(N)->getAlignment() >= 4;
375}]>;
376def aligned4pre_store : PatFrag<
377                          (ops node:$val, node:$base, node:$offset),
378                          (pre_store node:$val, node:$base, node:$offset), [{
379  return cast<StoreSDNode>(N)->getAlignment() >= 4;
380}]>;
381
382def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
383  return cast<LoadSDNode>(N)->getAlignment() < 4;
384}]>;
385def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
386                              (store node:$val, node:$ptr), [{
387  return cast<StoreSDNode>(N)->getAlignment() < 4;
388}]>;
389def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
390  return cast<LoadSDNode>(N)->getAlignment() < 4;
391}]>;
392
393//===----------------------------------------------------------------------===//
394// PowerPC Flag Definitions.
395
396class isPPC64 { bit PPC64 = 1; }
397class isDOT   { bit RC = 1; }
398
399class RegConstraint<string C> {
400  string Constraints = C;
401}
402class NoEncode<string E> {
403  string DisableEncoding = E;
404}
405
406
407//===----------------------------------------------------------------------===//
408// PowerPC Operand Definitions.
409
410// In the default PowerPC assembler syntax, registers are specified simply
411// by number, so they cannot be distinguished from immediate values (without
412// looking at the opcode).  This means that the default operand matching logic
413// for the asm parser does not work, and we need to specify custom matchers.
414// Since those can only be specified with RegisterOperand classes and not
415// directly on the RegisterClass, all instructions patterns used by the asm
416// parser need to use a RegisterOperand (instead of a RegisterClass) for
417// all their register operands.
418// For this purpose, we define one RegisterOperand for each RegisterClass,
419// using the same name as the class, just in lower case.
420
421def PPCRegGPRCAsmOperand : AsmOperandClass {
422  let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
423}
424def gprc : RegisterOperand<GPRC> {
425  let ParserMatchClass = PPCRegGPRCAsmOperand;
426}
427def PPCRegG8RCAsmOperand : AsmOperandClass {
428  let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
429}
430def g8rc : RegisterOperand<G8RC> {
431  let ParserMatchClass = PPCRegG8RCAsmOperand;
432}
433def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
434  let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
435}
436def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
437  let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
438}
439def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
440  let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
441}
442def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
443  let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
444}
445def PPCRegF8RCAsmOperand : AsmOperandClass {
446  let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
447}
448def f8rc : RegisterOperand<F8RC> {
449  let ParserMatchClass = PPCRegF8RCAsmOperand;
450}
451def PPCRegF4RCAsmOperand : AsmOperandClass {
452  let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
453}
454def f4rc : RegisterOperand<F4RC> {
455  let ParserMatchClass = PPCRegF4RCAsmOperand;
456}
457def PPCRegVRRCAsmOperand : AsmOperandClass {
458  let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
459}
460def vrrc : RegisterOperand<VRRC> {
461  let ParserMatchClass = PPCRegVRRCAsmOperand;
462}
463def PPCRegVFRCAsmOperand : AsmOperandClass {
464  let Name = "RegVFRC"; let PredicateMethod = "isRegNumber";
465}
466def vfrc : RegisterOperand<VFRC> {
467  let ParserMatchClass = PPCRegVFRCAsmOperand;
468}
469def PPCRegCRBITRCAsmOperand : AsmOperandClass {
470  let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
471}
472def crbitrc : RegisterOperand<CRBITRC> {
473  let ParserMatchClass = PPCRegCRBITRCAsmOperand;
474}
475def PPCRegCRRCAsmOperand : AsmOperandClass {
476  let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
477}
478def crrc : RegisterOperand<CRRC> {
479  let ParserMatchClass = PPCRegCRRCAsmOperand;
480}
481def crrc0 : RegisterOperand<CRRC0> {
482  let ParserMatchClass = PPCRegCRRCAsmOperand;
483}
484
485def PPCU1ImmAsmOperand : AsmOperandClass {
486  let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
487  let RenderMethod = "addImmOperands";
488}
489def u1imm   : Operand<i32> {
490  let PrintMethod = "printU1ImmOperand";
491  let ParserMatchClass = PPCU1ImmAsmOperand;
492}
493
494def PPCU2ImmAsmOperand : AsmOperandClass {
495  let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
496  let RenderMethod = "addImmOperands";
497}
498def u2imm   : Operand<i32> {
499  let PrintMethod = "printU2ImmOperand";
500  let ParserMatchClass = PPCU2ImmAsmOperand;
501}
502
503def PPCATBitsAsHintAsmOperand : AsmOperandClass {
504  let Name = "ATBitsAsHint"; let PredicateMethod = "isATBitsAsHint";
505  let RenderMethod = "addImmOperands"; // Irrelevant, predicate always fails.
506}
507def atimm   : Operand<i32> {
508  let PrintMethod = "printATBitsAsHint";
509  let ParserMatchClass = PPCATBitsAsHintAsmOperand;
510}
511
512def PPCU3ImmAsmOperand : AsmOperandClass {
513  let Name = "U3Imm"; let PredicateMethod = "isU3Imm";
514  let RenderMethod = "addImmOperands";
515}
516def u3imm   : Operand<i32> {
517  let PrintMethod = "printU3ImmOperand";
518  let ParserMatchClass = PPCU3ImmAsmOperand;
519}
520
521def PPCU4ImmAsmOperand : AsmOperandClass {
522  let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
523  let RenderMethod = "addImmOperands";
524}
525def u4imm   : Operand<i32> {
526  let PrintMethod = "printU4ImmOperand";
527  let ParserMatchClass = PPCU4ImmAsmOperand;
528}
529def PPCS5ImmAsmOperand : AsmOperandClass {
530  let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
531  let RenderMethod = "addImmOperands";
532}
533def s5imm   : Operand<i32> {
534  let PrintMethod = "printS5ImmOperand";
535  let ParserMatchClass = PPCS5ImmAsmOperand;
536  let DecoderMethod = "decodeSImmOperand<5>";
537}
538def PPCU5ImmAsmOperand : AsmOperandClass {
539  let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
540  let RenderMethod = "addImmOperands";
541}
542def u5imm   : Operand<i32> {
543  let PrintMethod = "printU5ImmOperand";
544  let ParserMatchClass = PPCU5ImmAsmOperand;
545  let DecoderMethod = "decodeUImmOperand<5>";
546}
547def PPCU6ImmAsmOperand : AsmOperandClass {
548  let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
549  let RenderMethod = "addImmOperands";
550}
551def u6imm   : Operand<i32> {
552  let PrintMethod = "printU6ImmOperand";
553  let ParserMatchClass = PPCU6ImmAsmOperand;
554  let DecoderMethod = "decodeUImmOperand<6>";
555}
556def PPCU7ImmAsmOperand : AsmOperandClass {
557  let Name = "U7Imm"; let PredicateMethod = "isU7Imm";
558  let RenderMethod = "addImmOperands";
559}
560def u7imm   : Operand<i32> {
561  let PrintMethod = "printU7ImmOperand";
562  let ParserMatchClass = PPCU7ImmAsmOperand;
563  let DecoderMethod = "decodeUImmOperand<7>";
564}
565def PPCU8ImmAsmOperand : AsmOperandClass {
566  let Name = "U8Imm"; let PredicateMethod = "isU8Imm";
567  let RenderMethod = "addImmOperands";
568}
569def u8imm   : Operand<i32> {
570  let PrintMethod = "printU8ImmOperand";
571  let ParserMatchClass = PPCU8ImmAsmOperand;
572  let DecoderMethod = "decodeUImmOperand<8>";
573}
574def PPCU10ImmAsmOperand : AsmOperandClass {
575  let Name = "U10Imm"; let PredicateMethod = "isU10Imm";
576  let RenderMethod = "addImmOperands";
577}
578def u10imm  : Operand<i32> {
579  let PrintMethod = "printU10ImmOperand";
580  let ParserMatchClass = PPCU10ImmAsmOperand;
581  let DecoderMethod = "decodeUImmOperand<10>";
582}
583def PPCU12ImmAsmOperand : AsmOperandClass {
584  let Name = "U12Imm"; let PredicateMethod = "isU12Imm";
585  let RenderMethod = "addImmOperands";
586}
587def u12imm  : Operand<i32> {
588  let PrintMethod = "printU12ImmOperand";
589  let ParserMatchClass = PPCU12ImmAsmOperand;
590  let DecoderMethod = "decodeUImmOperand<12>";
591}
592def PPCS16ImmAsmOperand : AsmOperandClass {
593  let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
594  let RenderMethod = "addS16ImmOperands";
595}
596def s16imm  : Operand<i32> {
597  let PrintMethod = "printS16ImmOperand";
598  let EncoderMethod = "getImm16Encoding";
599  let ParserMatchClass = PPCS16ImmAsmOperand;
600  let DecoderMethod = "decodeSImmOperand<16>";
601}
602def PPCU16ImmAsmOperand : AsmOperandClass {
603  let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
604  let RenderMethod = "addU16ImmOperands";
605}
606def u16imm  : Operand<i32> {
607  let PrintMethod = "printU16ImmOperand";
608  let EncoderMethod = "getImm16Encoding";
609  let ParserMatchClass = PPCU16ImmAsmOperand;
610  let DecoderMethod = "decodeUImmOperand<16>";
611}
612def PPCS17ImmAsmOperand : AsmOperandClass {
613  let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
614  let RenderMethod = "addS16ImmOperands";
615}
616def s17imm  : Operand<i32> {
617  // This operand type is used for addis/lis to allow the assembler parser
618  // to accept immediates in the range -65536..65535 for compatibility with
619  // the GNU assembler.  The operand is treated as 16-bit otherwise.
620  let PrintMethod = "printS16ImmOperand";
621  let EncoderMethod = "getImm16Encoding";
622  let ParserMatchClass = PPCS17ImmAsmOperand;
623  let DecoderMethod = "decodeSImmOperand<16>";
624}
625
626def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
627
628def PPCDirectBrAsmOperand : AsmOperandClass {
629  let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
630  let RenderMethod = "addBranchTargetOperands";
631}
632def directbrtarget : Operand<OtherVT> {
633  let PrintMethod = "printBranchOperand";
634  let EncoderMethod = "getDirectBrEncoding";
635  let ParserMatchClass = PPCDirectBrAsmOperand;
636}
637def absdirectbrtarget : Operand<OtherVT> {
638  let PrintMethod = "printAbsBranchOperand";
639  let EncoderMethod = "getAbsDirectBrEncoding";
640  let ParserMatchClass = PPCDirectBrAsmOperand;
641}
642def PPCCondBrAsmOperand : AsmOperandClass {
643  let Name = "CondBr"; let PredicateMethod = "isCondBr";
644  let RenderMethod = "addBranchTargetOperands";
645}
646def condbrtarget : Operand<OtherVT> {
647  let PrintMethod = "printBranchOperand";
648  let EncoderMethod = "getCondBrEncoding";
649  let ParserMatchClass = PPCCondBrAsmOperand;
650}
651def abscondbrtarget : Operand<OtherVT> {
652  let PrintMethod = "printAbsBranchOperand";
653  let EncoderMethod = "getAbsCondBrEncoding";
654  let ParserMatchClass = PPCCondBrAsmOperand;
655}
656def calltarget : Operand<iPTR> {
657  let PrintMethod = "printBranchOperand";
658  let EncoderMethod = "getDirectBrEncoding";
659  let ParserMatchClass = PPCDirectBrAsmOperand;
660}
661def abscalltarget : Operand<iPTR> {
662  let PrintMethod = "printAbsBranchOperand";
663  let EncoderMethod = "getAbsDirectBrEncoding";
664  let ParserMatchClass = PPCDirectBrAsmOperand;
665}
666def PPCCRBitMaskOperand : AsmOperandClass {
667 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
668}
669def crbitm: Operand<i8> {
670  let PrintMethod = "printcrbitm";
671  let EncoderMethod = "get_crbitm_encoding";
672  let DecoderMethod = "decodeCRBitMOperand";
673  let ParserMatchClass = PPCCRBitMaskOperand;
674}
675// Address operands
676// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
677def PPCRegGxRCNoR0Operand : AsmOperandClass {
678  let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
679}
680def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
681  let ParserMatchClass = PPCRegGxRCNoR0Operand;
682}
683// A version of ptr_rc usable with the asm parser.
684def PPCRegGxRCOperand : AsmOperandClass {
685  let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
686}
687def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
688  let ParserMatchClass = PPCRegGxRCOperand;
689}
690
691def PPCDispRIOperand : AsmOperandClass {
692 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
693 let RenderMethod = "addS16ImmOperands";
694}
695def dispRI : Operand<iPTR> {
696  let ParserMatchClass = PPCDispRIOperand;
697}
698def PPCDispRIXOperand : AsmOperandClass {
699 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
700 let RenderMethod = "addImmOperands";
701}
702def dispRIX : Operand<iPTR> {
703  let ParserMatchClass = PPCDispRIXOperand;
704}
705def PPCDispRIX16Operand : AsmOperandClass {
706 let Name = "DispRIX16"; let PredicateMethod = "isS16ImmX16";
707 let RenderMethod = "addImmOperands";
708}
709def dispRIX16 : Operand<iPTR> {
710  let ParserMatchClass = PPCDispRIX16Operand;
711}
712def PPCDispSPE8Operand : AsmOperandClass {
713 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
714 let RenderMethod = "addImmOperands";
715}
716def dispSPE8 : Operand<iPTR> {
717  let ParserMatchClass = PPCDispSPE8Operand;
718}
719def PPCDispSPE4Operand : AsmOperandClass {
720 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
721 let RenderMethod = "addImmOperands";
722}
723def dispSPE4 : Operand<iPTR> {
724  let ParserMatchClass = PPCDispSPE4Operand;
725}
726def PPCDispSPE2Operand : AsmOperandClass {
727 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
728 let RenderMethod = "addImmOperands";
729}
730def dispSPE2 : Operand<iPTR> {
731  let ParserMatchClass = PPCDispSPE2Operand;
732}
733
734def memri : Operand<iPTR> {
735  let PrintMethod = "printMemRegImm";
736  let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
737  let EncoderMethod = "getMemRIEncoding";
738  let DecoderMethod = "decodeMemRIOperands";
739}
740def memrr : Operand<iPTR> {
741  let PrintMethod = "printMemRegReg";
742  let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
743}
744def memrix : Operand<iPTR> {   // memri where the imm is 4-aligned.
745  let PrintMethod = "printMemRegImm";
746  let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
747  let EncoderMethod = "getMemRIXEncoding";
748  let DecoderMethod = "decodeMemRIXOperands";
749}
750def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16:27}
751  let PrintMethod = "printMemRegImm";
752  let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg);
753  let EncoderMethod = "getMemRIX16Encoding";
754  let DecoderMethod = "decodeMemRIX16Operands";
755}
756def spe8dis : Operand<iPTR> {   // SPE displacement where the imm is 8-aligned.
757  let PrintMethod = "printMemRegImm";
758  let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
759  let EncoderMethod = "getSPE8DisEncoding";
760}
761def spe4dis : Operand<iPTR> {   // SPE displacement where the imm is 4-aligned.
762  let PrintMethod = "printMemRegImm";
763  let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
764  let EncoderMethod = "getSPE4DisEncoding";
765}
766def spe2dis : Operand<iPTR> {   // SPE displacement where the imm is 2-aligned.
767  let PrintMethod = "printMemRegImm";
768  let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
769  let EncoderMethod = "getSPE2DisEncoding";
770}
771
772// A single-register address. This is used with the SjLj
773// pseudo-instructions.
774def memr : Operand<iPTR> {
775  let MIOperandInfo = (ops ptr_rc:$ptrreg);
776}
777def PPCTLSRegOperand : AsmOperandClass {
778  let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
779  let RenderMethod = "addTLSRegOperands";
780}
781def tlsreg32 : Operand<i32> {
782  let EncoderMethod = "getTLSRegEncoding";
783  let ParserMatchClass = PPCTLSRegOperand;
784}
785def tlsgd32 : Operand<i32> {}
786def tlscall32 : Operand<i32> {
787  let PrintMethod = "printTLSCall";
788  let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
789  let EncoderMethod = "getTLSCallEncoding";
790}
791
792// PowerPC Predicate operand.
793def pred : Operand<OtherVT> {
794  let PrintMethod = "printPredicateOperand";
795  let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
796}
797
798// Define PowerPC specific addressing mode.
799def iaddr  : ComplexPattern<iPTR, 2, "SelectAddrImm",    [], []>;
800def xaddr  : ComplexPattern<iPTR, 2, "SelectAddrIdx",    [], []>;
801def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
802def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4",  [], []>; // "std"
803
804// The address in a single register. This is used with the SjLj
805// pseudo-instructions.
806def addr   : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
807
808/// This is just the offset part of iaddr, used for preinc.
809def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
810
811//===----------------------------------------------------------------------===//
812// PowerPC Instruction Predicate Definitions.
813def In32BitMode  : Predicate<"!PPCSubTarget->isPPC64()">;
814def In64BitMode  : Predicate<"PPCSubTarget->isPPC64()">;
815def IsBookE  : Predicate<"PPCSubTarget->isBookE()">;
816def IsNotBookE  : Predicate<"!PPCSubTarget->isBookE()">;
817def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
818def HasSYNC   : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
819def IsPPC4xx  : Predicate<"PPCSubTarget->isPPC4xx()">;
820def IsPPC6xx  : Predicate<"PPCSubTarget->isPPC6xx()">;
821def IsE500  : Predicate<"PPCSubTarget->isE500()">;
822def HasSPE  : Predicate<"PPCSubTarget->HasSPE()">;
823def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
824def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">;
825def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
826def NaNsFPMath   : Predicate<"!TM.Options.NoNaNsFPMath">;
827def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">;
828def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">;
829def IsISA3_0 : Predicate<"PPCSubTarget->isISA3_0()">;
830
831//===----------------------------------------------------------------------===//
832// PowerPC Multiclass Definitions.
833
834multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
835                    string asmbase, string asmstr, InstrItinClass itin,
836                    list<dag> pattern> {
837  let BaseName = asmbase in {
838    def NAME : XForm_6<opcode, xo, OOL, IOL,
839                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
840                       pattern>, RecFormRel;
841    let Defs = [CR0] in
842    def o    : XForm_6<opcode, xo, OOL, IOL,
843                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
844                       []>, isDOT, RecFormRel;
845  }
846}
847
848multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
849                     string asmbase, string asmstr, InstrItinClass itin,
850                     list<dag> pattern> {
851  let BaseName = asmbase in {
852    let Defs = [CARRY] in
853    def NAME : XForm_6<opcode, xo, OOL, IOL,
854                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
855                       pattern>, RecFormRel;
856    let Defs = [CARRY, CR0] in
857    def o    : XForm_6<opcode, xo, OOL, IOL,
858                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
859                       []>, isDOT, RecFormRel;
860  }
861}
862
863multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
864                      string asmbase, string asmstr, InstrItinClass itin,
865                      list<dag> pattern> {
866  let BaseName = asmbase in {
867    let Defs = [CARRY] in
868    def NAME : XForm_10<opcode, xo, OOL, IOL,
869                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
870                       pattern>, RecFormRel;
871    let Defs = [CARRY, CR0] in
872    def o    : XForm_10<opcode, xo, OOL, IOL,
873                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
874                       []>, isDOT, RecFormRel;
875  }
876}
877
878multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
879                    string asmbase, string asmstr, InstrItinClass itin,
880                    list<dag> pattern> {
881  let BaseName = asmbase in {
882    def NAME : XForm_11<opcode, xo, OOL, IOL,
883                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
884                       pattern>, RecFormRel;
885    let Defs = [CR0] in
886    def o    : XForm_11<opcode, xo, OOL, IOL,
887                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
888                       []>, isDOT, RecFormRel;
889  }
890}
891
892multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
893                    string asmbase, string asmstr, InstrItinClass itin,
894                    list<dag> pattern> {
895  let BaseName = asmbase in {
896    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
897                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
898                       pattern>, RecFormRel;
899    let Defs = [CR0] in
900    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
901                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
902                       []>, isDOT, RecFormRel;
903  }
904}
905
906// Multiclass for instructions for which the non record form is not cracked
907// and the record form is cracked (i.e. divw, mullw, etc.)
908multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
909                      string asmbase, string asmstr, InstrItinClass itin,
910                      list<dag> pattern> {
911  let BaseName = asmbase in {
912    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
913                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
914                       pattern>, RecFormRel;
915    let Defs = [CR0] in
916    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
917                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
918                       []>, isDOT, RecFormRel, PPC970_DGroup_First,
919                       PPC970_DGroup_Cracked;
920  }
921}
922
923multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
924                      string asmbase, string asmstr, InstrItinClass itin,
925                      list<dag> pattern> {
926  let BaseName = asmbase in {
927    let Defs = [CARRY] in
928    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
929                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
930                       pattern>, RecFormRel;
931    let Defs = [CARRY, CR0] in
932    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
933                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
934                       []>, isDOT, RecFormRel;
935  }
936}
937
938multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
939                    string asmbase, string asmstr, InstrItinClass itin,
940                    list<dag> pattern> {
941  let BaseName = asmbase in {
942    def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
943                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
944                       pattern>, RecFormRel;
945    let Defs = [CR0] in
946    def o    : XOForm_3<opcode, xo, oe, OOL, IOL,
947                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
948                       []>, isDOT, RecFormRel;
949  }
950}
951
952multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
953                      string asmbase, string asmstr, InstrItinClass itin,
954                      list<dag> pattern> {
955  let BaseName = asmbase in {
956    let Defs = [CARRY] in
957    def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
958                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
959                       pattern>, RecFormRel;
960    let Defs = [CARRY, CR0] in
961    def o    : XOForm_3<opcode, xo, oe, OOL, IOL,
962                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
963                       []>, isDOT, RecFormRel;
964  }
965}
966
967multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
968                    string asmbase, string asmstr, InstrItinClass itin,
969                    list<dag> pattern> {
970  let BaseName = asmbase in {
971    def NAME : MForm_2<opcode, OOL, IOL,
972                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
973                       pattern>, RecFormRel;
974    let Defs = [CR0] in
975    def o    : MForm_2<opcode, OOL, IOL,
976                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
977                       []>, isDOT, RecFormRel;
978  }
979}
980
981multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
982                    string asmbase, string asmstr, InstrItinClass itin,
983                    list<dag> pattern> {
984  let BaseName = asmbase in {
985    def NAME : MDForm_1<opcode, xo, OOL, IOL,
986                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
987                       pattern>, RecFormRel;
988    let Defs = [CR0] in
989    def o    : MDForm_1<opcode, xo, OOL, IOL,
990                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
991                       []>, isDOT, RecFormRel;
992  }
993}
994
995multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
996                     string asmbase, string asmstr, InstrItinClass itin,
997                     list<dag> pattern> {
998  let BaseName = asmbase in {
999    def NAME : MDSForm_1<opcode, xo, OOL, IOL,
1000                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1001                        pattern>, RecFormRel;
1002    let Defs = [CR0] in
1003    def o    : MDSForm_1<opcode, xo, OOL, IOL,
1004                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1005                        []>, isDOT, RecFormRel;
1006  }
1007}
1008
1009multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
1010                      string asmbase, string asmstr, InstrItinClass itin,
1011                      list<dag> pattern> {
1012  let BaseName = asmbase in {
1013    let Defs = [CARRY] in
1014    def NAME : XSForm_1<opcode, xo, OOL, IOL,
1015                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1016                       pattern>, RecFormRel;
1017    let Defs = [CARRY, CR0] in
1018    def o    : XSForm_1<opcode, xo, OOL, IOL,
1019                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1020                       []>, isDOT, RecFormRel;
1021  }
1022}
1023
1024multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
1025                    string asmbase, string asmstr, InstrItinClass itin,
1026                    list<dag> pattern> {
1027  let BaseName = asmbase in {
1028    def NAME : XForm_26<opcode, xo, OOL, IOL,
1029                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1030                       pattern>, RecFormRel;
1031    let Defs = [CR1] in
1032    def o    : XForm_26<opcode, xo, OOL, IOL,
1033                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1034                       []>, isDOT, RecFormRel;
1035  }
1036}
1037
1038multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
1039                    string asmbase, string asmstr, InstrItinClass itin,
1040                    list<dag> pattern> {
1041  let BaseName = asmbase in {
1042    def NAME : XForm_28<opcode, xo, OOL, IOL,
1043                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1044                       pattern>, RecFormRel;
1045    let Defs = [CR1] in
1046    def o    : XForm_28<opcode, xo, OOL, IOL,
1047                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1048                       []>, isDOT, RecFormRel;
1049  }
1050}
1051
1052multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
1053                    string asmbase, string asmstr, InstrItinClass itin,
1054                    list<dag> pattern> {
1055  let BaseName = asmbase in {
1056    def NAME : AForm_1<opcode, xo, OOL, IOL,
1057                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1058                       pattern>, RecFormRel;
1059    let Defs = [CR1] in
1060    def o    : AForm_1<opcode, xo, OOL, IOL,
1061                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1062                       []>, isDOT, RecFormRel;
1063  }
1064}
1065
1066multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
1067                    string asmbase, string asmstr, InstrItinClass itin,
1068                    list<dag> pattern> {
1069  let BaseName = asmbase in {
1070    def NAME : AForm_2<opcode, xo, OOL, IOL,
1071                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1072                       pattern>, RecFormRel;
1073    let Defs = [CR1] in
1074    def o    : AForm_2<opcode, xo, OOL, IOL,
1075                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1076                       []>, isDOT, RecFormRel;
1077  }
1078}
1079
1080multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
1081                    string asmbase, string asmstr, InstrItinClass itin,
1082                    list<dag> pattern> {
1083  let BaseName = asmbase in {
1084    def NAME : AForm_3<opcode, xo, OOL, IOL,
1085                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1086                       pattern>, RecFormRel;
1087    let Defs = [CR1] in
1088    def o    : AForm_3<opcode, xo, OOL, IOL,
1089                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1090                       []>, isDOT, RecFormRel;
1091  }
1092}
1093
1094//===----------------------------------------------------------------------===//
1095// PowerPC Instruction Definitions.
1096
1097// Pseudo-instructions:
1098
1099let hasCtrlDep = 1 in {
1100let Defs = [R1], Uses = [R1] in {
1101def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
1102                              [(callseq_start timm:$amt)]>;
1103def ADJCALLSTACKUP   : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
1104                              [(callseq_end timm:$amt1, timm:$amt2)]>;
1105}
1106
1107def UPDATE_VRSAVE    : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
1108                              "UPDATE_VRSAVE $rD, $rS", []>;
1109}
1110
1111let Defs = [R1], Uses = [R1] in
1112def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
1113                       [(set i32:$result,
1114                             (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
1115def DYNAREAOFFSET : Pseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET",
1116                       [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>;
1117
1118// SELECT_CC_* - Used to implement the SELECT_CC DAG operation.  Expanded after
1119// instruction selection into a branch sequence.
1120let usesCustomInserter = 1,    // Expanded after instruction selection.
1121    PPC970_Single = 1 in {
1122  // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
1123  // because either operand might become the first operand in an isel, and
1124  // that operand cannot be r0.
1125  def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
1126                              gprc_nor0:$T, gprc_nor0:$F,
1127                              i32imm:$BROPC), "#SELECT_CC_I4",
1128                              []>;
1129  def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
1130                              g8rc_nox0:$T, g8rc_nox0:$F,
1131                              i32imm:$BROPC), "#SELECT_CC_I8",
1132                              []>;
1133  def SELECT_CC_F4  : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1134                              i32imm:$BROPC), "#SELECT_CC_F4",
1135                              []>;
1136  def SELECT_CC_F8  : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
1137                              i32imm:$BROPC), "#SELECT_CC_F8",
1138                              []>;
1139  def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
1140                              i32imm:$BROPC), "#SELECT_CC_VRRC",
1141                              []>;
1142
1143  // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
1144  // register bit directly.
1145  def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
1146                          gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
1147                          [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
1148  def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
1149                          g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
1150                          [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
1151  def SELECT_F4  : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
1152                          f4rc:$T, f4rc:$F), "#SELECT_F4",
1153                          [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
1154  def SELECT_F8  : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
1155                          f8rc:$T, f8rc:$F), "#SELECT_F8",
1156                          [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
1157  def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
1158                          vrrc:$T, vrrc:$F), "#SELECT_VRRC",
1159                          [(set v4i32:$dst,
1160                                (select i1:$cond, v4i32:$T, v4i32:$F))]>;
1161}
1162
1163// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
1164// scavenge a register for it.
1165let mayStore = 1 in {
1166def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
1167                     "#SPILL_CR", []>;
1168def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1169                         "#SPILL_CRBIT", []>;
1170}
1171
1172// RESTORE_CR - Indicate that we're restoring the CR register (previously
1173// spilled), so we'll need to scavenge a register for it.
1174let mayLoad = 1 in {
1175def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1176                     "#RESTORE_CR", []>;
1177def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1178                           "#RESTORE_CRBIT", []>;
1179}
1180
1181let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1182  let isReturn = 1, Uses = [LR, RM] in
1183    def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1184                           [(retflag)]>, Requires<[In32BitMode]>;
1185  let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1186    def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1187                            []>;
1188
1189    let isCodeGenOnly = 1 in {
1190      def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1191                               "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1192                               []>;
1193
1194      def BCCTR :  XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1195                                "bcctr 12, $bi, 0", IIC_BrB, []>;
1196      def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1197                                "bcctr 4, $bi, 0", IIC_BrB, []>;
1198    }
1199  }
1200}
1201
1202let Defs = [LR] in
1203  def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1204                   PPC970_Unit_BRU;
1205let Defs = [LR] in
1206  def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1207                    PPC970_Unit_BRU;
1208
1209let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1210  let isBarrier = 1 in {
1211  def B   : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1212                  "b $dst", IIC_BrB,
1213                  [(br bb:$dst)]>;
1214  def BA  : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1215                  "ba $dst", IIC_BrB, []>;
1216  }
1217
1218  // BCC represents an arbitrary conditional branch on a predicate.
1219  // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1220  // a two-value operand where a dag node expects two operands. :(
1221  let isCodeGenOnly = 1 in {
1222    def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1223                    "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1224                    /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1225    def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1226                     "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1227
1228    let isReturn = 1, Uses = [LR, RM] in
1229    def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1230                           "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1231  }
1232
1233  let isCodeGenOnly = 1 in {
1234    let Pattern = [(brcond i1:$bi, bb:$dst)] in
1235    def BC  : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1236             "bc 12, $bi, $dst">;
1237
1238    let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1239    def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1240             "bc 4, $bi, $dst">;
1241
1242    let isReturn = 1, Uses = [LR, RM] in
1243    def BCLR  : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1244                             "bclr 12, $bi, 0", IIC_BrB, []>;
1245    def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1246                             "bclr 4, $bi, 0", IIC_BrB, []>;
1247  }
1248
1249  let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1250   def BDZLR  : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1251                             "bdzlr", IIC_BrB, []>;
1252   def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1253                             "bdnzlr", IIC_BrB, []>;
1254   def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1255                             "bdzlr+", IIC_BrB, []>;
1256   def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1257                             "bdnzlr+", IIC_BrB, []>;
1258   def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1259                             "bdzlr-", IIC_BrB, []>;
1260   def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1261                             "bdnzlr-", IIC_BrB, []>;
1262  }
1263
1264  let Defs = [CTR], Uses = [CTR] in {
1265    def BDZ  : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1266                       "bdz $dst">;
1267    def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1268                       "bdnz $dst">;
1269    def BDZA  : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1270                        "bdza $dst">;
1271    def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1272                        "bdnza $dst">;
1273    def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1274                       "bdz+ $dst">;
1275    def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1276                       "bdnz+ $dst">;
1277    def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1278                        "bdza+ $dst">;
1279    def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1280                        "bdnza+ $dst">;
1281    def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1282                       "bdz- $dst">;
1283    def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1284                       "bdnz- $dst">;
1285    def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1286                        "bdza- $dst">;
1287    def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1288                        "bdnza- $dst">;
1289  }
1290}
1291
1292// The unconditional BCL used by the SjLj setjmp code.
1293let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1294  let Defs = [LR], Uses = [RM] in {
1295    def BCLalways  : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1296                            "bcl 20, 31, $dst">;
1297  }
1298}
1299
1300let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1301  // Convenient aliases for call instructions
1302  let Uses = [RM] in {
1303    def BL  : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1304                    "bl $func", IIC_BrB, []>;  // See Pat patterns below.
1305    def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1306                    "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1307
1308    let isCodeGenOnly = 1 in {
1309      def BL_TLS  : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1310                          "bl $func", IIC_BrB, []>;
1311      def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1312                       "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1313      def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1314                        "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1315
1316      def BCL  : BForm_4<16, 12, 0, 1, (outs),
1317                         (ins crbitrc:$bi, condbrtarget:$dst),
1318                         "bcl 12, $bi, $dst">;
1319      def BCLn : BForm_4<16, 4, 0, 1, (outs),
1320                         (ins crbitrc:$bi, condbrtarget:$dst),
1321                         "bcl 4, $bi, $dst">;
1322    }
1323  }
1324  let Uses = [CTR, RM] in {
1325    def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1326                             "bctrl", IIC_BrB, [(PPCbctrl)]>,
1327                Requires<[In32BitMode]>;
1328
1329    let isCodeGenOnly = 1 in {
1330      def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1331                                "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1332                                []>;
1333
1334      def BCCTRL  : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1335                                 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1336      def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1337                                 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1338    }
1339  }
1340  let Uses = [LR, RM] in {
1341    def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1342                            "blrl", IIC_BrB, []>;
1343
1344    let isCodeGenOnly = 1 in {
1345      def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1346                              "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1347                              []>;
1348
1349      def BCLRL  : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1350                                "bclrl 12, $bi, 0", IIC_BrB, []>;
1351      def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1352                                "bclrl 4, $bi, 0", IIC_BrB, []>;
1353    }
1354  }
1355  let Defs = [CTR], Uses = [CTR, RM] in {
1356    def BDZL  : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1357                        "bdzl $dst">;
1358    def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1359                        "bdnzl $dst">;
1360    def BDZLA  : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1361                         "bdzla $dst">;
1362    def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1363                         "bdnzla $dst">;
1364    def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1365                        "bdzl+ $dst">;
1366    def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1367                        "bdnzl+ $dst">;
1368    def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1369                         "bdzla+ $dst">;
1370    def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1371                         "bdnzla+ $dst">;
1372    def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1373                        "bdzl- $dst">;
1374    def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1375                        "bdnzl- $dst">;
1376    def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1377                         "bdzla- $dst">;
1378    def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1379                         "bdnzla- $dst">;
1380  }
1381  let Defs = [CTR], Uses = [CTR, LR, RM] in {
1382    def BDZLRL  : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1383                               "bdzlrl", IIC_BrB, []>;
1384    def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1385                               "bdnzlrl", IIC_BrB, []>;
1386    def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1387                               "bdzlrl+", IIC_BrB, []>;
1388    def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1389                               "bdnzlrl+", IIC_BrB, []>;
1390    def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1391                               "bdzlrl-", IIC_BrB, []>;
1392    def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1393                               "bdnzlrl-", IIC_BrB, []>;
1394  }
1395}
1396
1397let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1398def TCRETURNdi :Pseudo< (outs),
1399                        (ins calltarget:$dst, i32imm:$offset),
1400                 "#TC_RETURNd $dst $offset",
1401                 []>;
1402
1403
1404let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1405def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1406                 "#TC_RETURNa $func $offset",
1407                 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1408
1409let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1410def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1411                 "#TC_RETURNr $dst $offset",
1412                 []>;
1413
1414
1415let isCodeGenOnly = 1 in {
1416
1417let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1418    isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM]  in
1419def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1420                            []>, Requires<[In32BitMode]>;
1421
1422let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1423    isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1424def TAILB   : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1425                  "b $dst", IIC_BrB,
1426                  []>;
1427
1428let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1429    isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1430def TAILBA   : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1431                  "ba $dst", IIC_BrB,
1432                  []>;
1433
1434}
1435
1436let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1437  let Defs = [CTR] in
1438  def EH_SjLj_SetJmp32  : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1439                            "#EH_SJLJ_SETJMP32",
1440                            [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1441                          Requires<[In32BitMode]>;
1442  let isTerminator = 1 in
1443  def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1444                            "#EH_SJLJ_LONGJMP32",
1445                            [(PPCeh_sjlj_longjmp addr:$buf)]>,
1446                          Requires<[In32BitMode]>;
1447}
1448
1449// This pseudo is never removed from the function, as it serves as
1450// a terminator.  Size is set to 0 to prevent the builtin assembler
1451// from emitting it.
1452let isBranch = 1, isTerminator = 1, Size = 0 in {
1453  def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1454                        "#EH_SjLj_Setup\t$dst", []>;
1455}
1456
1457// System call.
1458let PPC970_Unit = 7 in {
1459  def SC     : SCForm<17, 1, (outs), (ins i32imm:$lev),
1460                      "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1461}
1462
1463// Branch history rolling buffer.
1464def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB,
1465                      [(PPCclrbhrb)]>,
1466                      PPC970_DGroup_Single;
1467// The $dmy argument used for MFBHRBE is not needed; however, including
1468// it avoids automatic generation of PPCFastISel::fastEmit_i(), which
1469// interferes with necessary special handling (see PPCFastISel.cpp).
1470def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD),
1471                         (ins u10imm:$imm, u10imm:$dmy),
1472                         "mfbhrbe $rD, $imm", IIC_BrB,
1473                         [(set i32:$rD,
1474                               (PPCmfbhrbe imm:$imm, imm:$dmy))]>,
1475                         PPC970_DGroup_First;
1476
1477def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm",
1478                     IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>,
1479                     PPC970_DGroup_Single;
1480
1481// DCB* instructions.
1482def DCBA   : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1483                      IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1484                      PPC970_DGroup_Single;
1485def DCBI   : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1486                      IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1487                      PPC970_DGroup_Single;
1488def DCBST  : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1489                      IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1490                      PPC970_DGroup_Single;
1491def DCBZ   : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1492                      IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1493                      PPC970_DGroup_Single;
1494def DCBZL  : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1495                      IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1496                      PPC970_DGroup_Single;
1497
1498def DCBF   : DCB_Form_hint<86, (outs), (ins u5imm:$TH, memrr:$dst),
1499                      "dcbf $dst, $TH", IIC_LdStDCBF, []>,
1500                      PPC970_DGroup_Single;
1501
1502let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in {
1503def DCBT   : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst),
1504                      "dcbt $dst, $TH", IIC_LdStDCBF, []>,
1505                      PPC970_DGroup_Single;
1506def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst),
1507                      "dcbtst $dst, $TH", IIC_LdStDCBF, []>,
1508                      PPC970_DGroup_Single;
1509} // hasSideEffects = 0
1510
1511def ICBT  : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1512                       "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1513
1514def : Pat<(int_ppc_dcbt xoaddr:$dst),
1515          (DCBT 0, xoaddr:$dst)>;
1516def : Pat<(int_ppc_dcbtst xoaddr:$dst),
1517          (DCBTST 0, xoaddr:$dst)>;
1518def : Pat<(int_ppc_dcbf xoaddr:$dst),
1519          (DCBF 0, xoaddr:$dst)>;
1520
1521def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1522          (DCBT 0, xoaddr:$dst)>;   // data prefetch for loads
1523def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1524          (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores
1525def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1526          (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
1527
1528// Atomic operations
1529let usesCustomInserter = 1 in {
1530  let Defs = [CR0] in {
1531    def ATOMIC_LOAD_ADD_I8 : Pseudo<
1532      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1533      [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1534    def ATOMIC_LOAD_SUB_I8 : Pseudo<
1535      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1536      [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1537    def ATOMIC_LOAD_AND_I8 : Pseudo<
1538      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1539      [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1540    def ATOMIC_LOAD_OR_I8 : Pseudo<
1541      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1542      [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1543    def ATOMIC_LOAD_XOR_I8 : Pseudo<
1544      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1545      [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1546    def ATOMIC_LOAD_NAND_I8 : Pseudo<
1547      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1548      [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1549    def ATOMIC_LOAD_MIN_I8 : Pseudo<
1550      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8",
1551      [(set i32:$dst, (atomic_load_min_8 xoaddr:$ptr, i32:$incr))]>;
1552    def ATOMIC_LOAD_MAX_I8 : Pseudo<
1553      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8",
1554      [(set i32:$dst, (atomic_load_max_8 xoaddr:$ptr, i32:$incr))]>;
1555    def ATOMIC_LOAD_UMIN_I8 : Pseudo<
1556      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8",
1557      [(set i32:$dst, (atomic_load_umin_8 xoaddr:$ptr, i32:$incr))]>;
1558    def ATOMIC_LOAD_UMAX_I8 : Pseudo<
1559      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8",
1560      [(set i32:$dst, (atomic_load_umax_8 xoaddr:$ptr, i32:$incr))]>;
1561    def ATOMIC_LOAD_ADD_I16 : Pseudo<
1562      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1563      [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1564    def ATOMIC_LOAD_SUB_I16 : Pseudo<
1565      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1566      [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1567    def ATOMIC_LOAD_AND_I16 : Pseudo<
1568      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1569      [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1570    def ATOMIC_LOAD_OR_I16 : Pseudo<
1571      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1572      [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1573    def ATOMIC_LOAD_XOR_I16 : Pseudo<
1574      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1575      [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1576    def ATOMIC_LOAD_NAND_I16 : Pseudo<
1577      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1578      [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1579    def ATOMIC_LOAD_MIN_I16 : Pseudo<
1580      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16",
1581      [(set i32:$dst, (atomic_load_min_16 xoaddr:$ptr, i32:$incr))]>;
1582    def ATOMIC_LOAD_MAX_I16 : Pseudo<
1583      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16",
1584      [(set i32:$dst, (atomic_load_max_16 xoaddr:$ptr, i32:$incr))]>;
1585    def ATOMIC_LOAD_UMIN_I16 : Pseudo<
1586      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16",
1587      [(set i32:$dst, (atomic_load_umin_16 xoaddr:$ptr, i32:$incr))]>;
1588    def ATOMIC_LOAD_UMAX_I16 : Pseudo<
1589      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16",
1590      [(set i32:$dst, (atomic_load_umax_16 xoaddr:$ptr, i32:$incr))]>;
1591    def ATOMIC_LOAD_ADD_I32 : Pseudo<
1592      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1593      [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1594    def ATOMIC_LOAD_SUB_I32 : Pseudo<
1595      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1596      [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1597    def ATOMIC_LOAD_AND_I32 : Pseudo<
1598      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1599      [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1600    def ATOMIC_LOAD_OR_I32 : Pseudo<
1601      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1602      [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1603    def ATOMIC_LOAD_XOR_I32 : Pseudo<
1604      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1605      [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1606    def ATOMIC_LOAD_NAND_I32 : Pseudo<
1607      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1608      [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1609    def ATOMIC_LOAD_MIN_I32 : Pseudo<
1610      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32",
1611      [(set i32:$dst, (atomic_load_min_32 xoaddr:$ptr, i32:$incr))]>;
1612    def ATOMIC_LOAD_MAX_I32 : Pseudo<
1613      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32",
1614      [(set i32:$dst, (atomic_load_max_32 xoaddr:$ptr, i32:$incr))]>;
1615    def ATOMIC_LOAD_UMIN_I32 : Pseudo<
1616      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32",
1617      [(set i32:$dst, (atomic_load_umin_32 xoaddr:$ptr, i32:$incr))]>;
1618    def ATOMIC_LOAD_UMAX_I32 : Pseudo<
1619      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32",
1620      [(set i32:$dst, (atomic_load_umax_32 xoaddr:$ptr, i32:$incr))]>;
1621
1622    def ATOMIC_CMP_SWAP_I8 : Pseudo<
1623      (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1624      [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1625    def ATOMIC_CMP_SWAP_I16 : Pseudo<
1626      (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1627      [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1628    def ATOMIC_CMP_SWAP_I32 : Pseudo<
1629      (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1630      [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1631
1632    def ATOMIC_SWAP_I8 : Pseudo<
1633      (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1634      [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1635    def ATOMIC_SWAP_I16 : Pseudo<
1636      (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1637      [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1638    def ATOMIC_SWAP_I32 : Pseudo<
1639      (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1640      [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1641  }
1642}
1643
1644// Instructions to support atomic operations
1645let mayLoad = 1, hasSideEffects = 0 in {
1646def LBARX : XForm_1<31,  52, (outs gprc:$rD), (ins memrr:$src),
1647                    "lbarx $rD, $src", IIC_LdStLWARX, []>,
1648                    Requires<[HasPartwordAtomics]>;
1649
1650def LHARX : XForm_1<31,  116, (outs gprc:$rD), (ins memrr:$src),
1651                    "lharx $rD, $src", IIC_LdStLWARX, []>,
1652                    Requires<[HasPartwordAtomics]>;
1653
1654def LWARX : XForm_1<31,  20, (outs gprc:$rD), (ins memrr:$src),
1655                    "lwarx $rD, $src", IIC_LdStLWARX, []>;
1656
1657// Instructions to support lock versions of atomics
1658// (EH=1 - see Power ISA 2.07 Book II 4.4.2)
1659def LBARXL : XForm_1<31,  52, (outs gprc:$rD), (ins memrr:$src),
1660                     "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1661                     Requires<[HasPartwordAtomics]>;
1662
1663def LHARXL : XForm_1<31,  116, (outs gprc:$rD), (ins memrr:$src),
1664                     "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1665                     Requires<[HasPartwordAtomics]>;
1666
1667def LWARXL : XForm_1<31,  20, (outs gprc:$rD), (ins memrr:$src),
1668                     "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT;
1669
1670// The atomic instructions use the destination register as well as the next one
1671// or two registers in order (modulo 31).
1672let hasExtraSrcRegAllocReq = 1 in
1673def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC),
1674                         "lwat $rD, $rA, $FC", IIC_LdStLoad>,
1675           Requires<[IsISA3_0]>;
1676}
1677
1678let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in {
1679def STBCX : XForm_1<31, 694, (outs), (ins gprc:$rS, memrr:$dst),
1680                    "stbcx. $rS, $dst", IIC_LdStSTWCX, []>,
1681                    isDOT, Requires<[HasPartwordAtomics]>;
1682
1683def STHCX : XForm_1<31, 726, (outs), (ins gprc:$rS, memrr:$dst),
1684                    "sthcx. $rS, $dst", IIC_LdStSTWCX, []>,
1685                    isDOT, Requires<[HasPartwordAtomics]>;
1686
1687def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1688                    "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT;
1689}
1690
1691let mayStore = 1, hasSideEffects = 0 in
1692def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC),
1693                          "stwat $rS, $rA, $FC", IIC_LdStStore>,
1694            Requires<[IsISA3_0]>;
1695
1696let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1697def TRAP  : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1698
1699def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1700                     "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1701def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1702                 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1703def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1704                     "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1705def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1706                 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1707
1708//===----------------------------------------------------------------------===//
1709// PPC32 Load Instructions.
1710//
1711
1712// Unindexed (r+i) Loads.
1713let PPC970_Unit = 2 in {
1714def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1715                  "lbz $rD, $src", IIC_LdStLoad,
1716                  [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1717def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1718                  "lha $rD, $src", IIC_LdStLHA,
1719                  [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1720                  PPC970_DGroup_Cracked;
1721def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1722                  "lhz $rD, $src", IIC_LdStLoad,
1723                  [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1724def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1725                  "lwz $rD, $src", IIC_LdStLoad,
1726                  [(set i32:$rD, (load iaddr:$src))]>;
1727
1728def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1729                  "lfs $rD, $src", IIC_LdStLFD,
1730                  [(set f32:$rD, (load iaddr:$src))]>;
1731def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1732                  "lfd $rD, $src", IIC_LdStLFD,
1733                  [(set f64:$rD, (load iaddr:$src))]>;
1734
1735
1736// Unindexed (r+i) Loads with Update (preinc).
1737let mayLoad = 1, hasSideEffects = 0 in {
1738def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1739                   "lbzu $rD, $addr", IIC_LdStLoadUpd,
1740                   []>, RegConstraint<"$addr.reg = $ea_result">,
1741                   NoEncode<"$ea_result">;
1742
1743def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1744                   "lhau $rD, $addr", IIC_LdStLHAU,
1745                   []>, RegConstraint<"$addr.reg = $ea_result">,
1746                   NoEncode<"$ea_result">;
1747
1748def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1749                   "lhzu $rD, $addr", IIC_LdStLoadUpd,
1750                   []>, RegConstraint<"$addr.reg = $ea_result">,
1751                   NoEncode<"$ea_result">;
1752
1753def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1754                   "lwzu $rD, $addr", IIC_LdStLoadUpd,
1755                   []>, RegConstraint<"$addr.reg = $ea_result">,
1756                   NoEncode<"$ea_result">;
1757
1758def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1759                  "lfsu $rD, $addr", IIC_LdStLFDU,
1760                  []>, RegConstraint<"$addr.reg = $ea_result">,
1761                   NoEncode<"$ea_result">;
1762
1763def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1764                  "lfdu $rD, $addr", IIC_LdStLFDU,
1765                  []>, RegConstraint<"$addr.reg = $ea_result">,
1766                   NoEncode<"$ea_result">;
1767
1768
1769// Indexed (r+r) Loads with Update (preinc).
1770def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1771                   (ins memrr:$addr),
1772                   "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1773                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1774                   NoEncode<"$ea_result">;
1775
1776def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1777                   (ins memrr:$addr),
1778                   "lhaux $rD, $addr", IIC_LdStLHAUX,
1779                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1780                   NoEncode<"$ea_result">;
1781
1782def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1783                   (ins memrr:$addr),
1784                   "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1785                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1786                   NoEncode<"$ea_result">;
1787
1788def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1789                   (ins memrr:$addr),
1790                   "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1791                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1792                   NoEncode<"$ea_result">;
1793
1794def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1795                   (ins memrr:$addr),
1796                   "lfsux $rD, $addr", IIC_LdStLFDUX,
1797                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1798                   NoEncode<"$ea_result">;
1799
1800def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1801                   (ins memrr:$addr),
1802                   "lfdux $rD, $addr", IIC_LdStLFDUX,
1803                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1804                   NoEncode<"$ea_result">;
1805}
1806}
1807
1808// Indexed (r+r) Loads.
1809//
1810let PPC970_Unit = 2 in {
1811def LBZX : XForm_1<31,  87, (outs gprc:$rD), (ins memrr:$src),
1812                   "lbzx $rD, $src", IIC_LdStLoad,
1813                   [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1814def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1815                   "lhax $rD, $src", IIC_LdStLHA,
1816                   [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1817                   PPC970_DGroup_Cracked;
1818def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1819                   "lhzx $rD, $src", IIC_LdStLoad,
1820                   [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1821def LWZX : XForm_1<31,  23, (outs gprc:$rD), (ins memrr:$src),
1822                   "lwzx $rD, $src", IIC_LdStLoad,
1823                   [(set i32:$rD, (load xaddr:$src))]>;
1824
1825
1826def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1827                   "lhbrx $rD, $src", IIC_LdStLoad,
1828                   [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1829def LWBRX : XForm_1<31,  534, (outs gprc:$rD), (ins memrr:$src),
1830                   "lwbrx $rD, $src", IIC_LdStLoad,
1831                   [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1832
1833def LFSX   : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1834                      "lfsx $frD, $src", IIC_LdStLFD,
1835                      [(set f32:$frD, (load xaddr:$src))]>;
1836def LFDX   : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1837                      "lfdx $frD, $src", IIC_LdStLFD,
1838                      [(set f64:$frD, (load xaddr:$src))]>;
1839
1840def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1841                      "lfiwax $frD, $src", IIC_LdStLFD,
1842                      [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1843def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1844                      "lfiwzx $frD, $src", IIC_LdStLFD,
1845                      [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1846}
1847
1848// Load Multiple
1849def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1850                  "lmw $rD, $src", IIC_LdStLMW, []>;
1851
1852//===----------------------------------------------------------------------===//
1853// PPC32 Store Instructions.
1854//
1855
1856// Unindexed (r+i) Stores.
1857let PPC970_Unit = 2 in {
1858def STB  : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1859                   "stb $rS, $src", IIC_LdStStore,
1860                   [(truncstorei8 i32:$rS, iaddr:$src)]>;
1861def STH  : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1862                   "sth $rS, $src", IIC_LdStStore,
1863                   [(truncstorei16 i32:$rS, iaddr:$src)]>;
1864def STW  : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1865                   "stw $rS, $src", IIC_LdStStore,
1866                   [(store i32:$rS, iaddr:$src)]>;
1867def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1868                   "stfs $rS, $dst", IIC_LdStSTFD,
1869                   [(store f32:$rS, iaddr:$dst)]>;
1870def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1871                   "stfd $rS, $dst", IIC_LdStSTFD,
1872                   [(store f64:$rS, iaddr:$dst)]>;
1873}
1874
1875// Unindexed (r+i) Stores with Update (preinc).
1876let PPC970_Unit = 2, mayStore = 1 in {
1877def STBU  : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1878                    "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1879                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1880def STHU  : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1881                    "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1882                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1883def STWU  : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1884                    "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1885                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1886def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1887                    "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1888                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1889def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1890                    "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1891                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1892}
1893
1894// Patterns to match the pre-inc stores.  We can't put the patterns on
1895// the instruction definitions directly as ISel wants the address base
1896// and offset to be separate operands, not a single complex operand.
1897def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1898          (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1899def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1900          (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1901def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1902          (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1903def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1904          (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1905def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1906          (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1907
1908// Indexed (r+r) Stores.
1909let PPC970_Unit = 2 in {
1910def STBX  : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1911                   "stbx $rS, $dst", IIC_LdStStore,
1912                   [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1913                   PPC970_DGroup_Cracked;
1914def STHX  : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1915                   "sthx $rS, $dst", IIC_LdStStore,
1916                   [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1917                   PPC970_DGroup_Cracked;
1918def STWX  : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1919                   "stwx $rS, $dst", IIC_LdStStore,
1920                   [(store i32:$rS, xaddr:$dst)]>,
1921                   PPC970_DGroup_Cracked;
1922
1923def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1924                   "sthbrx $rS, $dst", IIC_LdStStore,
1925                   [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1926                   PPC970_DGroup_Cracked;
1927def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1928                   "stwbrx $rS, $dst", IIC_LdStStore,
1929                   [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1930                   PPC970_DGroup_Cracked;
1931
1932def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1933                     "stfiwx $frS, $dst", IIC_LdStSTFD,
1934                     [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1935
1936def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1937                     "stfsx $frS, $dst", IIC_LdStSTFD,
1938                     [(store f32:$frS, xaddr:$dst)]>;
1939def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1940                     "stfdx $frS, $dst", IIC_LdStSTFD,
1941                     [(store f64:$frS, xaddr:$dst)]>;
1942}
1943
1944// Indexed (r+r) Stores with Update (preinc).
1945let PPC970_Unit = 2, mayStore = 1 in {
1946def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1947                    "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1948                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1949                    PPC970_DGroup_Cracked;
1950def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1951                    "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1952                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1953                    PPC970_DGroup_Cracked;
1954def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1955                    "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1956                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1957                    PPC970_DGroup_Cracked;
1958def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1959                    "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1960                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1961                    PPC970_DGroup_Cracked;
1962def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1963                    "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1964                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1965                    PPC970_DGroup_Cracked;
1966}
1967
1968// Patterns to match the pre-inc stores.  We can't put the patterns on
1969// the instruction definitions directly as ISel wants the address base
1970// and offset to be separate operands, not a single complex operand.
1971def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1972          (STBUX $rS, $ptrreg, $ptroff)>;
1973def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1974          (STHUX $rS, $ptrreg, $ptroff)>;
1975def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1976          (STWUX $rS, $ptrreg, $ptroff)>;
1977def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1978          (STFSUX $rS, $ptrreg, $ptroff)>;
1979def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1980          (STFDUX $rS, $ptrreg, $ptroff)>;
1981
1982// Store Multiple
1983def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1984                   "stmw $rS, $dst", IIC_LdStLMW, []>;
1985
1986def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1987                        "sync $L", IIC_LdStSync, []>;
1988
1989let isCodeGenOnly = 1 in {
1990  def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1991                           "msync", IIC_LdStSync, []> {
1992    let L = 0;
1993  }
1994}
1995
1996def : Pat<(int_ppc_sync),   (SYNC 0)>, Requires<[HasSYNC]>;
1997def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
1998def : Pat<(int_ppc_sync),   (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1999def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2000
2001//===----------------------------------------------------------------------===//
2002// PPC32 Arithmetic Instructions.
2003//
2004
2005let PPC970_Unit = 1 in {  // FXU Operations.
2006def ADDI   : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
2007                     "addi $rD, $rA, $imm", IIC_IntSimple,
2008                     [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
2009let BaseName = "addic" in {
2010let Defs = [CARRY] in
2011def ADDIC  : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
2012                     "addic $rD, $rA, $imm", IIC_IntGeneral,
2013                     [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
2014                     RecFormRel, PPC970_DGroup_Cracked;
2015let Defs = [CARRY, CR0] in
2016def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
2017                     "addic. $rD, $rA, $imm", IIC_IntGeneral,
2018                     []>, isDOT, RecFormRel;
2019}
2020def ADDIS  : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
2021                     "addis $rD, $rA, $imm", IIC_IntSimple,
2022                     [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
2023let isCodeGenOnly = 1 in
2024def LA     : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
2025                     "la $rD, $sym($rA)", IIC_IntGeneral,
2026                     [(set i32:$rD, (add i32:$rA,
2027                                          (PPClo tglobaladdr:$sym, 0)))]>;
2028def MULLI  : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
2029                     "mulli $rD, $rA, $imm", IIC_IntMulLI,
2030                     [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
2031let Defs = [CARRY] in
2032def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
2033                     "subfic $rD, $rA, $imm", IIC_IntGeneral,
2034                     [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
2035
2036let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
2037  def LI  : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
2038                       "li $rD, $imm", IIC_IntSimple,
2039                       [(set i32:$rD, imm32SExt16:$imm)]>;
2040  def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
2041                       "lis $rD, $imm", IIC_IntSimple,
2042                       [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
2043}
2044}
2045
2046let PPC970_Unit = 1 in {  // FXU Operations.
2047let Defs = [CR0] in {
2048def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2049                    "andi. $dst, $src1, $src2", IIC_IntGeneral,
2050                    [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
2051                    isDOT;
2052def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2053                    "andis. $dst, $src1, $src2", IIC_IntGeneral,
2054                    [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
2055                    isDOT;
2056}
2057def ORI   : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2058                    "ori $dst, $src1, $src2", IIC_IntSimple,
2059                    [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
2060def ORIS  : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2061                    "oris $dst, $src1, $src2", IIC_IntSimple,
2062                    [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
2063def XORI  : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2064                    "xori $dst, $src1, $src2", IIC_IntSimple,
2065                    [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
2066def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2067                    "xoris $dst, $src1, $src2", IIC_IntSimple,
2068                    [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
2069
2070def NOP   : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
2071                         []>;
2072let isCodeGenOnly = 1 in {
2073// The POWER6 and POWER7 have special group-terminating nops.
2074def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
2075                                        "ori 1, 1, 0", IIC_IntSimple, []>;
2076def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
2077                                        "ori 2, 2, 0", IIC_IntSimple, []>;
2078}
2079
2080let isCompare = 1, hasSideEffects = 0 in {
2081  def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
2082                          "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
2083  def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
2084                           "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
2085  def CMPRB  : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF),
2086                                (ins u1imm:$L, g8rc:$rA, g8rc:$rB),
2087                                "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>,
2088               Requires<[IsISA3_0]>;
2089}
2090}
2091
2092let PPC970_Unit = 1, hasSideEffects = 0 in {  // FXU Operations.
2093let isCommutable = 1 in {
2094defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2095                     "nand", "$rA, $rS, $rB", IIC_IntSimple,
2096                     [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
2097defm AND  : XForm_6r<31,  28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2098                     "and", "$rA, $rS, $rB", IIC_IntSimple,
2099                     [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
2100} // isCommutable
2101defm ANDC : XForm_6r<31,  60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2102                     "andc", "$rA, $rS, $rB", IIC_IntSimple,
2103                     [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
2104let isCommutable = 1 in {
2105defm OR   : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2106                     "or", "$rA, $rS, $rB", IIC_IntSimple,
2107                     [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
2108defm NOR  : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2109                     "nor", "$rA, $rS, $rB", IIC_IntSimple,
2110                     [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
2111} // isCommutable
2112defm ORC  : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2113                     "orc", "$rA, $rS, $rB", IIC_IntSimple,
2114                     [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
2115let isCommutable = 1 in {
2116defm EQV  : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2117                     "eqv", "$rA, $rS, $rB", IIC_IntSimple,
2118                     [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
2119defm XOR  : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2120                     "xor", "$rA, $rS, $rB", IIC_IntSimple,
2121                     [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
2122} // isCommutable
2123defm SLW  : XForm_6r<31,  24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2124                     "slw", "$rA, $rS, $rB", IIC_IntGeneral,
2125                     [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
2126defm SRW  : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2127                     "srw", "$rA, $rS, $rB", IIC_IntGeneral,
2128                     [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
2129defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2130                      "sraw", "$rA, $rS, $rB", IIC_IntShift,
2131                      [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
2132}
2133
2134let PPC970_Unit = 1 in {  // FXU Operations.
2135let hasSideEffects = 0 in {
2136defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
2137                        "srawi", "$rA, $rS, $SH", IIC_IntShift,
2138                        [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
2139defm CNTLZW : XForm_11r<31,  26, (outs gprc:$rA), (ins gprc:$rS),
2140                        "cntlzw", "$rA, $rS", IIC_IntGeneral,
2141                        [(set i32:$rA, (ctlz i32:$rS))]>;
2142defm CNTTZW : XForm_11r<31, 538, (outs gprc:$rA), (ins gprc:$rS),
2143                        "cnttzw", "$rA, $rS", IIC_IntGeneral,
2144                        [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>;
2145defm EXTSB  : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
2146                        "extsb", "$rA, $rS", IIC_IntSimple,
2147                        [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
2148defm EXTSH  : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
2149                        "extsh", "$rA, $rS", IIC_IntSimple,
2150                        [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
2151
2152let isCommutable = 1 in
2153def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2154                   "cmpb $rA, $rS, $rB", IIC_IntGeneral,
2155                   [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>;
2156}
2157let isCompare = 1, hasSideEffects = 0 in {
2158  def CMPW   : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
2159                            "cmpw $crD, $rA, $rB", IIC_IntCompare>;
2160  def CMPLW  : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
2161                            "cmplw $crD, $rA, $rB", IIC_IntCompare>;
2162}
2163}
2164let PPC970_Unit = 3 in {  // FPU Operations.
2165//def FCMPO  : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
2166//                      "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
2167let isCompare = 1, hasSideEffects = 0 in {
2168  def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
2169                        "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
2170  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2171  def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
2172                        "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
2173}
2174
2175let Uses = [RM] in {
2176  let hasSideEffects = 0 in {
2177  defm FCTIW  : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
2178                          "fctiw", "$frD, $frB", IIC_FPGeneral,
2179                          []>;
2180  defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
2181                          "fctiwz", "$frD, $frB", IIC_FPGeneral,
2182                          [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
2183
2184  defm FRSP   : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
2185                          "frsp", "$frD, $frB", IIC_FPGeneral,
2186                          [(set f32:$frD, (fpround f64:$frB))]>;
2187
2188  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2189  defm FRIND  : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
2190                          "frin", "$frD, $frB", IIC_FPGeneral,
2191                          [(set f64:$frD, (fround f64:$frB))]>;
2192  defm FRINS  : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
2193                          "frin", "$frD, $frB", IIC_FPGeneral,
2194                          [(set f32:$frD, (fround f32:$frB))]>;
2195  }
2196
2197  let hasSideEffects = 0 in {
2198  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2199  defm FRIPD  : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
2200                          "frip", "$frD, $frB", IIC_FPGeneral,
2201                          [(set f64:$frD, (fceil f64:$frB))]>;
2202  defm FRIPS  : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
2203                          "frip", "$frD, $frB", IIC_FPGeneral,
2204                          [(set f32:$frD, (fceil f32:$frB))]>;
2205  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2206  defm FRIZD  : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
2207                          "friz", "$frD, $frB", IIC_FPGeneral,
2208                          [(set f64:$frD, (ftrunc f64:$frB))]>;
2209  defm FRIZS  : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
2210                          "friz", "$frD, $frB", IIC_FPGeneral,
2211                          [(set f32:$frD, (ftrunc f32:$frB))]>;
2212  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2213  defm FRIMD  : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
2214                          "frim", "$frD, $frB", IIC_FPGeneral,
2215                          [(set f64:$frD, (ffloor f64:$frB))]>;
2216  defm FRIMS  : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
2217                          "frim", "$frD, $frB", IIC_FPGeneral,
2218                          [(set f32:$frD, (ffloor f32:$frB))]>;
2219
2220  defm FSQRT  : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
2221                          "fsqrt", "$frD, $frB", IIC_FPSqrtD,
2222                          [(set f64:$frD, (fsqrt f64:$frB))]>;
2223  defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
2224                          "fsqrts", "$frD, $frB", IIC_FPSqrtS,
2225                          [(set f32:$frD, (fsqrt f32:$frB))]>;
2226  }
2227  }
2228}
2229
2230/// Note that FMR is defined as pseudo-ops on the PPC970 because they are
2231/// often coalesced away and we don't want the dispatch group builder to think
2232/// that they will fill slots (which could cause the load of a LSU reject to
2233/// sneak into a d-group with a store).
2234let hasSideEffects = 0 in
2235defm FMR   : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
2236                       "fmr", "$frD, $frB", IIC_FPGeneral,
2237                       []>,  // (set f32:$frD, f32:$frB)
2238                       PPC970_Unit_Pseudo;
2239
2240let PPC970_Unit = 3, hasSideEffects = 0 in {  // FPU Operations.
2241// These are artificially split into two different forms, for 4/8 byte FP.
2242defm FABSS  : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
2243                        "fabs", "$frD, $frB", IIC_FPGeneral,
2244                        [(set f32:$frD, (fabs f32:$frB))]>;
2245let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2246defm FABSD  : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
2247                        "fabs", "$frD, $frB", IIC_FPGeneral,
2248                        [(set f64:$frD, (fabs f64:$frB))]>;
2249defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
2250                        "fnabs", "$frD, $frB", IIC_FPGeneral,
2251                        [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
2252let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2253defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
2254                        "fnabs", "$frD, $frB", IIC_FPGeneral,
2255                        [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
2256defm FNEGS  : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
2257                        "fneg", "$frD, $frB", IIC_FPGeneral,
2258                        [(set f32:$frD, (fneg f32:$frB))]>;
2259let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2260defm FNEGD  : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
2261                        "fneg", "$frD, $frB", IIC_FPGeneral,
2262                        [(set f64:$frD, (fneg f64:$frB))]>;
2263
2264defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
2265                        "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2266                        [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
2267let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2268defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
2269                        "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2270                        [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
2271
2272// Reciprocal estimates.
2273defm FRE      : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
2274                          "fre", "$frD, $frB", IIC_FPGeneral,
2275                          [(set f64:$frD, (PPCfre f64:$frB))]>;
2276defm FRES     : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
2277                          "fres", "$frD, $frB", IIC_FPGeneral,
2278                          [(set f32:$frD, (PPCfre f32:$frB))]>;
2279defm FRSQRTE  : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
2280                          "frsqrte", "$frD, $frB", IIC_FPGeneral,
2281                          [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
2282defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
2283                          "frsqrtes", "$frD, $frB", IIC_FPGeneral,
2284                          [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
2285}
2286
2287// XL-Form instructions.  condition register logical ops.
2288//
2289let hasSideEffects = 0 in
2290def MCRF   : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
2291                      "mcrf $BF, $BFA", IIC_BrMCR>,
2292             PPC970_DGroup_First, PPC970_Unit_CRU;
2293
2294// FIXME: According to the ISA (section 2.5.1 of version 2.06), the
2295// condition-register logical instructions have preferred forms. Specifically,
2296// it is preferred that the bit specified by the BT field be in the same
2297// condition register as that specified by the bit BB. We might want to account
2298// for this via hinting the register allocator and anti-dep breakers, or we
2299// could constrain the register class to force this constraint and then loosen
2300// it during register allocation via convertToThreeAddress or some similar
2301// mechanism.
2302
2303let isCommutable = 1 in {
2304def CRAND  : XLForm_1<19, 257, (outs crbitrc:$CRD),
2305                               (ins crbitrc:$CRA, crbitrc:$CRB),
2306                      "crand $CRD, $CRA, $CRB", IIC_BrCR,
2307                      [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2308
2309def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2310                               (ins crbitrc:$CRA, crbitrc:$CRB),
2311                      "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2312                      [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2313
2314def CROR   : XLForm_1<19, 449, (outs crbitrc:$CRD),
2315                               (ins crbitrc:$CRA, crbitrc:$CRB),
2316                      "cror $CRD, $CRA, $CRB", IIC_BrCR,
2317                      [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2318
2319def CRXOR  : XLForm_1<19, 193, (outs crbitrc:$CRD),
2320                               (ins crbitrc:$CRA, crbitrc:$CRB),
2321                      "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2322                      [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2323
2324def CRNOR  : XLForm_1<19, 33, (outs crbitrc:$CRD),
2325                              (ins crbitrc:$CRA, crbitrc:$CRB),
2326                      "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2327                      [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2328
2329def CREQV  : XLForm_1<19, 289, (outs crbitrc:$CRD),
2330                               (ins crbitrc:$CRA, crbitrc:$CRB),
2331                      "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2332                      [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2333} // isCommutable
2334
2335def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2336                               (ins crbitrc:$CRA, crbitrc:$CRB),
2337                      "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2338                      [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2339
2340def CRORC  : XLForm_1<19, 417, (outs crbitrc:$CRD),
2341                               (ins crbitrc:$CRA, crbitrc:$CRB),
2342                      "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2343                      [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2344
2345let isCodeGenOnly = 1 in {
2346def CRSET  : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2347              "creqv $dst, $dst, $dst", IIC_BrCR,
2348              [(set i1:$dst, 1)]>;
2349
2350def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2351              "crxor $dst, $dst, $dst", IIC_BrCR,
2352              [(set i1:$dst, 0)]>;
2353
2354let Defs = [CR1EQ], CRD = 6 in {
2355def CR6SET  : XLForm_1_ext<19, 289, (outs), (ins),
2356              "creqv 6, 6, 6", IIC_BrCR,
2357              [(PPCcr6set)]>;
2358
2359def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2360              "crxor 6, 6, 6", IIC_BrCR,
2361              [(PPCcr6unset)]>;
2362}
2363}
2364
2365// XFX-Form instructions.  Instructions that deal with SPRs.
2366//
2367
2368def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2369                      "mfspr $RT, $SPR", IIC_SprMFSPR>;
2370def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2371                      "mtspr $SPR, $RT", IIC_SprMTSPR>;
2372
2373def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2374                     "mftb $RT, $SPR", IIC_SprMFTB>;
2375
2376// A pseudo-instruction used to implement the read of the 64-bit cycle counter
2377// on a 32-bit target.
2378let hasSideEffects = 1, usesCustomInserter = 1 in
2379def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins),
2380                    "#ReadTB", []>;
2381
2382let Uses = [CTR] in {
2383def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2384                          "mfctr $rT", IIC_SprMFSPR>,
2385            PPC970_DGroup_First, PPC970_Unit_FXU;
2386}
2387let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2388def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2389                          "mtctr $rS", IIC_SprMTSPR>,
2390            PPC970_DGroup_First, PPC970_Unit_FXU;
2391}
2392let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2393let Pattern = [(int_ppc_mtctr i32:$rS)] in
2394def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2395                              "mtctr $rS", IIC_SprMTSPR>,
2396                PPC970_DGroup_First, PPC970_Unit_FXU;
2397}
2398
2399let Defs = [LR] in {
2400def MTLR  : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2401                          "mtlr $rS", IIC_SprMTSPR>,
2402            PPC970_DGroup_First, PPC970_Unit_FXU;
2403}
2404let Uses = [LR] in {
2405def MFLR  : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2406                          "mflr $rT", IIC_SprMFSPR>,
2407            PPC970_DGroup_First, PPC970_Unit_FXU;
2408}
2409
2410let isCodeGenOnly = 1 in {
2411  // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2412  // like a GPR on the PPC970.  As such, copies in and out have the same
2413  // performance characteristics as an OR instruction.
2414  def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2415                               "mtspr 256, $rS", IIC_IntGeneral>,
2416                 PPC970_DGroup_Single, PPC970_Unit_FXU;
2417  def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2418                               "mfspr $rT, 256", IIC_IntGeneral>,
2419                 PPC970_DGroup_First, PPC970_Unit_FXU;
2420
2421  def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2422                                (outs VRSAVERC:$reg), (ins gprc:$rS),
2423                                "mtspr 256, $rS", IIC_IntGeneral>,
2424                  PPC970_DGroup_Single, PPC970_Unit_FXU;
2425  def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2426                                (ins VRSAVERC:$reg),
2427                                "mfspr $rT, 256", IIC_IntGeneral>,
2428                  PPC970_DGroup_First, PPC970_Unit_FXU;
2429}
2430
2431// Aliases for mtvrsave/mfvrsave to mfspr/mtspr.
2432def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>;
2433def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>;
2434
2435// SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2436// so we'll need to scavenge a register for it.
2437let mayStore = 1 in
2438def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2439                     "#SPILL_VRSAVE", []>;
2440
2441// RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2442// spilled), so we'll need to scavenge a register for it.
2443let mayLoad = 1 in
2444def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2445                     "#RESTORE_VRSAVE", []>;
2446
2447let hasSideEffects = 0 in {
2448// mtocrf's input needs to be prepared by shifting by an amount dependent
2449// on the cr register selected. Thus, post-ra anti-dep breaking must not
2450// later change that register assignment.
2451let hasExtraDefRegAllocReq = 1 in {
2452def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2453                       "mtocrf $FXM, $ST", IIC_BrMCRX>,
2454            PPC970_DGroup_First, PPC970_Unit_CRU;
2455
2456// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that
2457// is dependent on the cr fields being set.
2458def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2459                      "mtcrf $FXM, $rS", IIC_BrMCRX>,
2460            PPC970_MicroCode, PPC970_Unit_CRU;
2461} // hasExtraDefRegAllocReq = 1
2462
2463// mfocrf's input needs to be prepared by shifting by an amount dependent
2464// on the cr register selected. Thus, post-ra anti-dep breaking must not
2465// later change that register assignment.
2466let hasExtraSrcRegAllocReq = 1 in {
2467def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2468                       "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2469            PPC970_DGroup_First, PPC970_Unit_CRU;
2470
2471// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that
2472// is dependent on the cr fields being copied.
2473def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2474                     "mfcr $rT", IIC_SprMFCR>,
2475                     PPC970_MicroCode, PPC970_Unit_CRU;
2476} // hasExtraSrcRegAllocReq = 1
2477
2478def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins),
2479                   "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>;
2480} // hasSideEffects = 0
2481
2482// Pseudo instruction to perform FADD in round-to-zero mode.
2483let usesCustomInserter = 1, Uses = [RM] in {
2484  def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2485                      [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2486}
2487
2488// The above pseudo gets expanded to make use of the following instructions
2489// to manipulate FPSCR.  Note that FPSCR is not modeled at the DAG level.
2490let Uses = [RM], Defs = [RM] in {
2491  def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2492                        "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2493               PPC970_DGroup_Single, PPC970_Unit_FPU;
2494  def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2495                        "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2496               PPC970_DGroup_Single, PPC970_Unit_FPU;
2497  let isCodeGenOnly = 1 in
2498  def MTFSFb  : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2499                        "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2500                PPC970_DGroup_Single, PPC970_Unit_FPU;
2501}
2502let Uses = [RM] in {
2503  def MFFS   : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2504                         "mffs $rT", IIC_IntMFFS,
2505                         [(set f64:$rT, (PPCmffs))]>,
2506               PPC970_DGroup_Single, PPC970_Unit_FPU;
2507
2508  let Defs = [CR1] in
2509  def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2510                      "mffs. $rT", IIC_IntMFFS, []>, isDOT;
2511}
2512
2513
2514let PPC970_Unit = 1, hasSideEffects = 0 in {  // FXU Operations.
2515// XO-Form instructions.  Arithmetic instructions that can set overflow bit
2516let isCommutable = 1 in
2517defm ADD4  : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2518                       "add", "$rT, $rA, $rB", IIC_IntSimple,
2519                       [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2520let isCodeGenOnly = 1 in
2521def ADD4TLS  : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2522                       "add $rT, $rA, $rB", IIC_IntSimple,
2523                       [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2524let isCommutable = 1 in
2525defm ADDC  : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2526                        "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2527                        [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2528                        PPC970_DGroup_Cracked;
2529
2530defm DIVW  : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2531                          "divw", "$rT, $rA, $rB", IIC_IntDivW,
2532                          [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>;
2533defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2534                          "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2535                          [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>;
2536def DIVWE : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2537                     "divwe $rT, $rA, $rB", IIC_IntDivW,
2538                     [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>,
2539                     Requires<[HasExtDiv]>;
2540let Defs = [CR0] in
2541def DIVWEo : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2542                      "divwe. $rT, $rA, $rB", IIC_IntDivW,
2543                      []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2544                      Requires<[HasExtDiv]>;
2545def DIVWEU : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2546                      "divweu $rT, $rA, $rB", IIC_IntDivW,
2547                      [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>,
2548                      Requires<[HasExtDiv]>;
2549let Defs = [CR0] in
2550def DIVWEUo : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2551                       "divweu. $rT, $rA, $rB", IIC_IntDivW,
2552                       []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2553                       Requires<[HasExtDiv]>;
2554let isCommutable = 1 in {
2555defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2556                       "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2557                       [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2558defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2559                       "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2560                       [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2561defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2562                       "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2563                       [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2564} // isCommutable
2565defm SUBF  : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2566                       "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2567                       [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2568defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2569                        "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2570                        [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2571                        PPC970_DGroup_Cracked;
2572defm NEG    : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2573                        "neg", "$rT, $rA", IIC_IntSimple,
2574                        [(set i32:$rT, (ineg i32:$rA))]>;
2575let Uses = [CARRY] in {
2576let isCommutable = 1 in
2577defm ADDE  : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2578                        "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2579                        [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2580defm ADDME  : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2581                         "addme", "$rT, $rA", IIC_IntGeneral,
2582                         [(set i32:$rT, (adde i32:$rA, -1))]>;
2583defm ADDZE  : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2584                         "addze", "$rT, $rA", IIC_IntGeneral,
2585                         [(set i32:$rT, (adde i32:$rA, 0))]>;
2586defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2587                        "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2588                        [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2589defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2590                         "subfme", "$rT, $rA", IIC_IntGeneral,
2591                         [(set i32:$rT, (sube -1, i32:$rA))]>;
2592defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2593                         "subfze", "$rT, $rA", IIC_IntGeneral,
2594                         [(set i32:$rT, (sube 0, i32:$rA))]>;
2595}
2596}
2597
2598// A-Form instructions.  Most of the instructions executed in the FPU are of
2599// this type.
2600//
2601let PPC970_Unit = 3, hasSideEffects = 0 in {  // FPU Operations.
2602let Uses = [RM] in {
2603let isCommutable = 1 in {
2604  defm FMADD : AForm_1r<63, 29,
2605                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2606                      "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2607                      [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2608  defm FMADDS : AForm_1r<59, 29,
2609                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2610                      "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2611                      [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2612  defm FMSUB : AForm_1r<63, 28,
2613                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2614                      "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2615                      [(set f64:$FRT,
2616                            (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2617  defm FMSUBS : AForm_1r<59, 28,
2618                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2619                      "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2620                      [(set f32:$FRT,
2621                            (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2622  defm FNMADD : AForm_1r<63, 31,
2623                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2624                      "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2625                      [(set f64:$FRT,
2626                            (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2627  defm FNMADDS : AForm_1r<59, 31,
2628                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2629                      "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2630                      [(set f32:$FRT,
2631                            (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2632  defm FNMSUB : AForm_1r<63, 30,
2633                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2634                      "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2635                      [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2636                                                 (fneg f64:$FRB))))]>;
2637  defm FNMSUBS : AForm_1r<59, 30,
2638                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2639                      "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2640                      [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2641                                                 (fneg f32:$FRB))))]>;
2642} // isCommutable
2643}
2644// FSEL is artificially split into 4 and 8-byte forms for the result.  To avoid
2645// having 4 of these, force the comparison to always be an 8-byte double (code
2646// should use an FMRSD if the input comparison value really wants to be a float)
2647// and 4/8 byte forms for the result and operand type..
2648let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2649defm FSELD : AForm_1r<63, 23,
2650                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2651                      "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2652                      [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2653defm FSELS : AForm_1r<63, 23,
2654                      (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2655                      "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2656                      [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2657let Uses = [RM] in {
2658  let isCommutable = 1 in {
2659  defm FADD  : AForm_2r<63, 21,
2660                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2661                        "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2662                        [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2663  defm FADDS : AForm_2r<59, 21,
2664                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2665                        "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2666                        [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2667  } // isCommutable
2668  defm FDIV  : AForm_2r<63, 18,
2669                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2670                        "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2671                        [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2672  defm FDIVS : AForm_2r<59, 18,
2673                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2674                        "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2675                        [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2676  let isCommutable = 1 in {
2677  defm FMUL  : AForm_3r<63, 25,
2678                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2679                        "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2680                        [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2681  defm FMULS : AForm_3r<59, 25,
2682                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2683                        "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2684                        [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2685  } // isCommutable
2686  defm FSUB  : AForm_2r<63, 20,
2687                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2688                        "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2689                        [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2690  defm FSUBS : AForm_2r<59, 20,
2691                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2692                        "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2693                        [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2694  }
2695}
2696
2697let hasSideEffects = 0 in {
2698let PPC970_Unit = 1 in {  // FXU Operations.
2699  let isSelect = 1 in
2700  def ISEL  : AForm_4<31, 15,
2701                     (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2702                     "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
2703                     []>;
2704}
2705
2706let PPC970_Unit = 1 in {  // FXU Operations.
2707// M-Form instructions.  rotate and mask instructions.
2708//
2709let isCommutable = 1 in {
2710// RLWIMI can be commuted if the rotate amount is zero.
2711defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2712                       (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2713                       u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2714                       IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2715                       RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2716}
2717let BaseName = "rlwinm" in {
2718def RLWINM : MForm_2<21,
2719                     (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2720                     "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2721                     []>, RecFormRel;
2722let Defs = [CR0] in
2723def RLWINMo : MForm_2<21,
2724                      (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2725                      "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2726                      []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2727}
2728defm RLWNM  : MForm_2r<23, (outs gprc:$rA),
2729                       (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2730                       "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2731                       []>;
2732}
2733} // hasSideEffects = 0
2734
2735//===----------------------------------------------------------------------===//
2736// PowerPC Instruction Patterns
2737//
2738
2739// Arbitrary immediate support.  Implement in terms of LIS/ORI.
2740def : Pat<(i32 imm:$imm),
2741          (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2742
2743// Implement the 'not' operation with the NOR instruction.
2744def i32not : OutPatFrag<(ops node:$in),
2745                        (NOR $in, $in)>;
2746def        : Pat<(not i32:$in),
2747                 (i32not $in)>;
2748
2749// ADD an arbitrary immediate.
2750def : Pat<(add i32:$in, imm:$imm),
2751          (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2752// OR an arbitrary immediate.
2753def : Pat<(or i32:$in, imm:$imm),
2754          (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2755// XOR an arbitrary immediate.
2756def : Pat<(xor i32:$in, imm:$imm),
2757          (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2758// SUBFIC
2759def : Pat<(sub imm32SExt16:$imm, i32:$in),
2760          (SUBFIC $in, imm:$imm)>;
2761
2762// SHL/SRL
2763def : Pat<(shl i32:$in, (i32 imm:$imm)),
2764          (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2765def : Pat<(srl i32:$in, (i32 imm:$imm)),
2766          (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2767
2768// ROTL
2769def : Pat<(rotl i32:$in, i32:$sh),
2770          (RLWNM $in, $sh, 0, 31)>;
2771def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2772          (RLWINM $in, imm:$imm, 0, 31)>;
2773
2774// RLWNM
2775def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2776          (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2777
2778// Calls
2779def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2780          (BL tglobaladdr:$dst)>;
2781def : Pat<(PPCcall (i32 texternalsym:$dst)),
2782          (BL texternalsym:$dst)>;
2783
2784def : Pat<(PPCtc_return (i32 tglobaladdr:$dst),  imm:$imm),
2785          (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2786
2787def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2788          (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2789
2790def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2791          (TCRETURNri CTRRC:$dst, imm:$imm)>;
2792
2793
2794
2795// Hi and Lo for Darwin Global Addresses.
2796def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2797def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2798def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2799def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2800def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2801def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2802def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2803def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2804def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2805          (ADDIS $in, tglobaltlsaddr:$g)>;
2806def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2807          (ADDI $in, tglobaltlsaddr:$g)>;
2808def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2809          (ADDIS $in, tglobaladdr:$g)>;
2810def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2811          (ADDIS $in, tconstpool:$g)>;
2812def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2813          (ADDIS $in, tjumptable:$g)>;
2814def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2815          (ADDIS $in, tblockaddress:$g)>;
2816
2817// Support for thread-local storage.
2818def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2819                [(set i32:$rD, (PPCppc32GOT))]>;
2820
2821// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2822// This uses two output registers, the first as the real output, the second as a
2823// temporary register, used internally in code generation.
2824def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2825                []>, NoEncode<"$rT">;
2826
2827def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2828                           "#LDgotTprelL32",
2829                           [(set i32:$rD,
2830                             (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2831def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2832          (ADD4TLS $in, tglobaltlsaddr:$g)>;
2833
2834def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2835                         "#ADDItlsgdL32",
2836                         [(set i32:$rD,
2837                           (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2838// LR is a true define, while the rest of the Defs are clobbers.  R3 is
2839// explicitly defined when this op is created, so not mentioned here.
2840let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2841    Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2842def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2843                          "GETtlsADDR32",
2844                          [(set i32:$rD,
2845                            (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2846// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded.  R3 and LR
2847// are true defines while the rest of the Defs are clobbers.
2848let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2849    Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2850def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD),
2851                              (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2852                              "#ADDItlsgdLADDR32",
2853                              [(set i32:$rD,
2854                                (PPCaddiTlsgdLAddr i32:$reg,
2855                                                   tglobaltlsaddr:$disp,
2856                                                   tglobaltlsaddr:$sym))]>;
2857def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2858                          "#ADDItlsldL32",
2859                          [(set i32:$rD,
2860                            (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2861// LR is a true define, while the rest of the Defs are clobbers.  R3 is
2862// explicitly defined when this op is created, so not mentioned here.
2863let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2864    Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2865def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2866                            "GETtlsldADDR32",
2867                            [(set i32:$rD,
2868                              (PPCgetTlsldAddr i32:$reg,
2869                                               tglobaltlsaddr:$sym))]>;
2870// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded.  R3 and LR
2871// are true defines while the rest of the Defs are clobbers.
2872let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2873    Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2874def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD),
2875                              (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2876                              "#ADDItlsldLADDR32",
2877                              [(set i32:$rD,
2878                                (PPCaddiTlsldLAddr i32:$reg,
2879                                                   tglobaltlsaddr:$disp,
2880                                                   tglobaltlsaddr:$sym))]>;
2881def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2882                           "#ADDIdtprelL32",
2883                           [(set i32:$rD,
2884                             (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2885def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2886                            "#ADDISdtprelHA32",
2887                            [(set i32:$rD,
2888                              (PPCaddisDtprelHA i32:$reg,
2889                                                tglobaltlsaddr:$disp))]>;
2890
2891// Support for Position-independent code
2892def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2893                   "#LWZtoc",
2894                   [(set i32:$rD,
2895                      (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2896// Get Global (GOT) Base Register offset, from the word immediately preceding
2897// the function label.
2898def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2899
2900
2901// Standard shifts.  These are represented separately from the real shifts above
2902// so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2903// amounts.
2904def : Pat<(sra i32:$rS, i32:$rB),
2905          (SRAW $rS, $rB)>;
2906def : Pat<(srl i32:$rS, i32:$rB),
2907          (SRW $rS, $rB)>;
2908def : Pat<(shl i32:$rS, i32:$rB),
2909          (SLW $rS, $rB)>;
2910
2911def : Pat<(zextloadi1 iaddr:$src),
2912          (LBZ iaddr:$src)>;
2913def : Pat<(zextloadi1 xaddr:$src),
2914          (LBZX xaddr:$src)>;
2915def : Pat<(extloadi1 iaddr:$src),
2916          (LBZ iaddr:$src)>;
2917def : Pat<(extloadi1 xaddr:$src),
2918          (LBZX xaddr:$src)>;
2919def : Pat<(extloadi8 iaddr:$src),
2920          (LBZ iaddr:$src)>;
2921def : Pat<(extloadi8 xaddr:$src),
2922          (LBZX xaddr:$src)>;
2923def : Pat<(extloadi16 iaddr:$src),
2924          (LHZ iaddr:$src)>;
2925def : Pat<(extloadi16 xaddr:$src),
2926          (LHZX xaddr:$src)>;
2927def : Pat<(f64 (extloadf32 iaddr:$src)),
2928          (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2929def : Pat<(f64 (extloadf32 xaddr:$src)),
2930          (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2931
2932def : Pat<(f64 (fpextend f32:$src)),
2933          (COPY_TO_REGCLASS $src, F8RC)>;
2934
2935// Only seq_cst fences require the heavyweight sync (SYNC 0).
2936// All others can use the lightweight sync (SYNC 1).
2937// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
2938// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
2939// versions of Power.
2940def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2941def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2942def : Pat<(atomic_fence (imm),   (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
2943def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2944
2945// Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2946def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2947          (FNMSUB $A, $C, $B)>;
2948def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2949          (FNMSUB $A, $C, $B)>;
2950def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2951          (FNMSUBS $A, $C, $B)>;
2952def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2953          (FNMSUBS $A, $C, $B)>;
2954
2955// FCOPYSIGN's operand types need not agree.
2956def : Pat<(fcopysign f64:$frB, f32:$frA),
2957          (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2958def : Pat<(fcopysign f32:$frB, f64:$frA),
2959          (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2960
2961include "PPCInstrAltivec.td"
2962include "PPCInstrSPE.td"
2963include "PPCInstr64Bit.td"
2964include "PPCInstrVSX.td"
2965include "PPCInstrQPX.td"
2966include "PPCInstrHTM.td"
2967
2968def crnot : OutPatFrag<(ops node:$in),
2969                       (CRNOR $in, $in)>;
2970def       : Pat<(not i1:$in),
2971                (crnot $in)>;
2972
2973// Patterns for arithmetic i1 operations.
2974def : Pat<(add i1:$a, i1:$b),
2975          (CRXOR $a, $b)>;
2976def : Pat<(sub i1:$a, i1:$b),
2977          (CRXOR $a, $b)>;
2978def : Pat<(mul i1:$a, i1:$b),
2979          (CRAND $a, $b)>;
2980
2981// We're sometimes asked to materialize i1 -1, which is just 1 in this case
2982// (-1 is used to mean all bits set).
2983def : Pat<(i1 -1), (CRSET)>;
2984
2985// i1 extensions, implemented in terms of isel.
2986def : Pat<(i32 (zext i1:$in)),
2987          (SELECT_I4 $in, (LI 1), (LI 0))>;
2988def : Pat<(i32 (sext i1:$in)),
2989          (SELECT_I4 $in, (LI -1), (LI 0))>;
2990
2991def : Pat<(i64 (zext i1:$in)),
2992          (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2993def : Pat<(i64 (sext i1:$in)),
2994          (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2995
2996// FIXME: We should choose either a zext or a sext based on other constants
2997// already around.
2998def : Pat<(i32 (anyext i1:$in)),
2999          (SELECT_I4 $in, (LI 1), (LI 0))>;
3000def : Pat<(i64 (anyext i1:$in)),
3001          (SELECT_I8 $in, (LI8 1), (LI8 0))>;
3002
3003// match setcc on i1 variables.
3004// CRANDC is:
3005//   1 1 : F
3006//   1 0 : T
3007//   0 1 : F
3008//   0 0 : F
3009//
3010// LT is:
3011//  -1 -1  : F
3012//  -1  0  : T
3013//   0 -1  : F
3014//   0  0  : F
3015//
3016// ULT is:
3017//   1 1 : F
3018//   1 0 : F
3019//   0 1 : T
3020//   0 0 : F
3021def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
3022          (CRANDC $s1, $s2)>;
3023def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
3024          (CRANDC $s2, $s1)>;
3025// CRORC is:
3026//   1 1 : T
3027//   1 0 : T
3028//   0 1 : F
3029//   0 0 : T
3030//
3031// LE is:
3032//  -1 -1 : T
3033//  -1  0 : T
3034//   0 -1 : F
3035//   0  0 : T
3036//
3037// ULE is:
3038//   1 1 : T
3039//   1 0 : F
3040//   0 1 : T
3041//   0 0 : T
3042def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
3043          (CRORC $s1, $s2)>;
3044def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
3045          (CRORC $s2, $s1)>;
3046
3047def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
3048          (CREQV $s1, $s2)>;
3049
3050// GE is:
3051//  -1 -1 : T
3052//  -1  0 : F
3053//   0 -1 : T
3054//   0  0 : T
3055//
3056// UGE is:
3057//   1 1 : T
3058//   1 0 : T
3059//   0 1 : F
3060//   0 0 : T
3061def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
3062          (CRORC $s2, $s1)>;
3063def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
3064          (CRORC $s1, $s2)>;
3065
3066// GT is:
3067//  -1 -1 : F
3068//  -1  0 : F
3069//   0 -1 : T
3070//   0  0 : F
3071//
3072// UGT is:
3073//  1 1 : F
3074//  1 0 : T
3075//  0 1 : F
3076//  0 0 : F
3077def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
3078          (CRANDC $s2, $s1)>;
3079def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
3080          (CRANDC $s1, $s2)>;
3081
3082def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
3083          (CRXOR $s1, $s2)>;
3084
3085// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
3086// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3087// floating-point types.
3088
3089multiclass CRNotPat<dag pattern, dag result> {
3090  def : Pat<pattern, (crnot result)>;
3091  def : Pat<(not pattern), result>;
3092
3093  // We can also fold the crnot into an extension:
3094  def : Pat<(i32 (zext pattern)),
3095            (SELECT_I4 result, (LI 0), (LI 1))>;
3096  def : Pat<(i32 (sext pattern)),
3097            (SELECT_I4 result, (LI 0), (LI -1))>;
3098
3099  // We can also fold the crnot into an extension:
3100  def : Pat<(i64 (zext pattern)),
3101            (SELECT_I8 result, (LI8 0), (LI8 1))>;
3102  def : Pat<(i64 (sext pattern)),
3103            (SELECT_I8 result, (LI8 0), (LI8 -1))>;
3104
3105  // FIXME: We should choose either a zext or a sext based on other constants
3106  // already around.
3107  def : Pat<(i32 (anyext pattern)),
3108            (SELECT_I4 result, (LI 0), (LI 1))>;
3109
3110  def : Pat<(i64 (anyext pattern)),
3111            (SELECT_I8 result, (LI8 0), (LI8 1))>;
3112}
3113
3114// FIXME: Because of what seems like a bug in TableGen's type-inference code,
3115// we need to write imm:$imm in the output patterns below, not just $imm, or
3116// else the resulting matcher will not correctly add the immediate operand
3117// (making it a register operand instead).
3118
3119// extended SETCC.
3120multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
3121                       OutPatFrag rfrag, OutPatFrag rfrag8> {
3122  def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
3123            (rfrag $s1)>;
3124  def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
3125            (rfrag8 $s1)>;
3126  def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
3127            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
3128  def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
3129            (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
3130
3131  def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
3132            (rfrag $s1)>;
3133  def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
3134            (rfrag8 $s1)>;
3135  def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
3136            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
3137  def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
3138            (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
3139}
3140
3141// Note that we do all inversions below with i(32|64)not, instead of using
3142// (xori x, 1) because on the A2 nor has single-cycle latency while xori
3143// has 2-cycle latency.
3144
3145defm : ExtSetCCPat<SETEQ,
3146                   PatFrag<(ops node:$in, node:$cc),
3147                           (setcc $in, 0, $cc)>,
3148                   OutPatFrag<(ops node:$in),
3149                              (RLWINM (CNTLZW $in), 27, 31, 31)>,
3150                   OutPatFrag<(ops node:$in),
3151                              (RLDICL (CNTLZD $in), 58, 63)> >;
3152
3153defm : ExtSetCCPat<SETNE,
3154                   PatFrag<(ops node:$in, node:$cc),
3155                           (setcc $in, 0, $cc)>,
3156                   OutPatFrag<(ops node:$in),
3157                              (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
3158                   OutPatFrag<(ops node:$in),
3159                              (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
3160
3161defm : ExtSetCCPat<SETLT,
3162                   PatFrag<(ops node:$in, node:$cc),
3163                           (setcc $in, 0, $cc)>,
3164                   OutPatFrag<(ops node:$in),
3165                              (RLWINM $in, 1, 31, 31)>,
3166                   OutPatFrag<(ops node:$in),
3167                              (RLDICL $in, 1, 63)> >;
3168
3169defm : ExtSetCCPat<SETGE,
3170                   PatFrag<(ops node:$in, node:$cc),
3171                           (setcc $in, 0, $cc)>,
3172                   OutPatFrag<(ops node:$in),
3173                              (RLWINM (i32not $in), 1, 31, 31)>,
3174                   OutPatFrag<(ops node:$in),
3175                              (RLDICL (i64not $in), 1, 63)> >;
3176
3177defm : ExtSetCCPat<SETGT,
3178                   PatFrag<(ops node:$in, node:$cc),
3179                           (setcc $in, 0, $cc)>,
3180                   OutPatFrag<(ops node:$in),
3181                              (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
3182                   OutPatFrag<(ops node:$in),
3183                              (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
3184
3185defm : ExtSetCCPat<SETLE,
3186                   PatFrag<(ops node:$in, node:$cc),
3187                           (setcc $in, 0, $cc)>,
3188                   OutPatFrag<(ops node:$in),
3189                              (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
3190                   OutPatFrag<(ops node:$in),
3191                              (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
3192
3193defm : ExtSetCCPat<SETLT,
3194                   PatFrag<(ops node:$in, node:$cc),
3195                           (setcc $in, -1, $cc)>,
3196                   OutPatFrag<(ops node:$in),
3197                              (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
3198                   OutPatFrag<(ops node:$in),
3199                              (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3200
3201defm : ExtSetCCPat<SETGE,
3202                   PatFrag<(ops node:$in, node:$cc),
3203                           (setcc $in, -1, $cc)>,
3204                   OutPatFrag<(ops node:$in),
3205                              (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
3206                   OutPatFrag<(ops node:$in),
3207                              (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3208
3209defm : ExtSetCCPat<SETGT,
3210                   PatFrag<(ops node:$in, node:$cc),
3211                           (setcc $in, -1, $cc)>,
3212                   OutPatFrag<(ops node:$in),
3213                              (RLWINM (i32not $in), 1, 31, 31)>,
3214                   OutPatFrag<(ops node:$in),
3215                              (RLDICL (i64not $in), 1, 63)> >;
3216
3217defm : ExtSetCCPat<SETLE,
3218                   PatFrag<(ops node:$in, node:$cc),
3219                           (setcc $in, -1, $cc)>,
3220                   OutPatFrag<(ops node:$in),
3221                              (RLWINM $in, 1, 31, 31)>,
3222                   OutPatFrag<(ops node:$in),
3223                              (RLDICL $in, 1, 63)> >;
3224
3225// An extended SETCC with shift amount.
3226multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag,
3227                            OutPatFrag rfrag, OutPatFrag rfrag8> {
3228  def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
3229            (rfrag $s1, $sa)>;
3230  def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
3231            (rfrag8 $s1, $sa)>;
3232  def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
3233            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>;
3234  def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
3235            (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>;
3236
3237  def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
3238            (rfrag $s1, $sa)>;
3239  def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
3240            (rfrag8 $s1, $sa)>;
3241  def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
3242            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>;
3243  def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
3244            (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>;
3245}
3246
3247defm : ExtSetCCShiftPat<SETNE,
3248                        PatFrag<(ops node:$in, node:$sa, node:$cc),
3249                                (setcc (and $in, (shl 1, $sa)), 0, $cc)>,
3250                        OutPatFrag<(ops node:$in, node:$sa),
3251                                   (RLWNM $in, (SUBFIC $sa, 32), 31, 31)>,
3252                        OutPatFrag<(ops node:$in, node:$sa),
3253                                   (RLDCL $in, (SUBFIC $sa, 64), 63)> >;
3254
3255defm : ExtSetCCShiftPat<SETEQ,
3256                        PatFrag<(ops node:$in, node:$sa, node:$cc),
3257                                (setcc (and $in, (shl 1, $sa)), 0, $cc)>,
3258                        OutPatFrag<(ops node:$in, node:$sa),
3259                                   (RLWNM (i32not $in),
3260                                          (SUBFIC $sa, 32), 31, 31)>,
3261                        OutPatFrag<(ops node:$in, node:$sa),
3262                                   (RLDCL (i64not $in),
3263                                          (SUBFIC $sa, 64), 63)> >;
3264
3265// SETCC for i32.
3266def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
3267          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3268def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
3269          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3270def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
3271          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3272def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
3273          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3274def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
3275          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3276def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
3277          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3278
3279// For non-equality comparisons, the default code would materialize the
3280// constant, then compare against it, like this:
3281//   lis r2, 4660
3282//   ori r2, r2, 22136
3283//   cmpw cr0, r3, r2
3284//   beq cr0,L6
3285// Since we are just comparing for equality, we can emit this instead:
3286//   xoris r0,r3,0x1234
3287//   cmplwi cr0,r0,0x5678
3288//   beq cr0,L6
3289
3290def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
3291          (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3292                                  (LO16 imm:$imm)), sub_eq)>;
3293
3294defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
3295                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3296defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
3297                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3298defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
3299                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3300defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
3301                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3302defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
3303                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3304defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
3305                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3306
3307defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
3308                (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3309                                        (LO16 imm:$imm)), sub_eq)>;
3310
3311def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
3312          (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3313def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
3314          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3315def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
3316          (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3317def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
3318          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3319def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
3320          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3321
3322defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
3323                (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3324defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
3325                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3326defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
3327                (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3328defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
3329                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3330defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
3331                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3332
3333// SETCC for i64.
3334def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
3335          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3336def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
3337          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3338def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
3339          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3340def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
3341          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3342def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
3343          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3344def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
3345          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3346
3347// For non-equality comparisons, the default code would materialize the
3348// constant, then compare against it, like this:
3349//   lis r2, 4660
3350//   ori r2, r2, 22136
3351//   cmpd cr0, r3, r2
3352//   beq cr0,L6
3353// Since we are just comparing for equality, we can emit this instead:
3354//   xoris r0,r3,0x1234
3355//   cmpldi cr0,r0,0x5678
3356//   beq cr0,L6
3357
3358def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
3359          (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3360                                  (LO16 imm:$imm)), sub_eq)>;
3361
3362defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3363                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3364defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
3365                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3366defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
3367                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3368defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
3369                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3370defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
3371                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3372defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
3373                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3374
3375defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
3376                (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3377                                        (LO16 imm:$imm)), sub_eq)>;
3378
3379def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
3380          (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3381def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3382          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3383def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3384          (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3385def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
3386          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3387def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
3388          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3389
3390defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3391                (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3392defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
3393                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3394defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
3395                (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3396defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
3397                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3398defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
3399                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3400
3401// SETCC for f32.
3402def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
3403          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3404def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
3405          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3406def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
3407          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3408def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
3409          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3410def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
3411          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3412def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
3413          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3414def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
3415          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3416
3417defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3418                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3419defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
3420                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3421defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
3422                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3423defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
3424                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3425defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
3426                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3427defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
3428                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3429defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
3430                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3431
3432// SETCC for f64.
3433def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
3434          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3435def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
3436          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3437def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
3438          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3439def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
3440          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3441def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
3442          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3443def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
3444          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3445def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
3446          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3447
3448defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3449                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3450defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
3451                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3452defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
3453                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3454defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
3455                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3456defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
3457                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3458defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
3459                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3460defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
3461                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3462
3463// match select on i1 variables:
3464def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
3465          (CROR (CRAND        $cond , $tval),
3466                (CRAND (crnot $cond), $fval))>;
3467
3468// match selectcc on i1 variables:
3469//   select (lhs == rhs), tval, fval is:
3470//   ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
3471def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
3472           (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3473                 (CRAND (CRORC  $rhs, $lhs), $fval))>;
3474def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)),
3475           (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3476                 (CRAND (CRORC  $lhs, $rhs), $fval))>;
3477def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
3478           (CROR (CRAND (CRORC  $lhs, $rhs), $tval),
3479                 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3480def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)),
3481           (CROR (CRAND (CRORC  $rhs, $lhs), $tval),
3482                 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3483def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
3484           (CROR (CRAND (CREQV $lhs, $rhs), $tval),
3485                 (CRAND (CRXOR $lhs, $rhs), $fval))>;
3486def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
3487           (CROR (CRAND (CRORC  $rhs, $lhs), $tval),
3488                 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3489def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)),
3490           (CROR (CRAND (CRORC  $lhs, $rhs), $tval),
3491                 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3492def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
3493           (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3494                 (CRAND (CRORC  $lhs, $rhs), $fval))>;
3495def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)),
3496           (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3497                 (CRAND (CRORC  $rhs, $lhs), $fval))>;
3498def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
3499           (CROR (CRAND (CREQV $lhs, $rhs), $fval),
3500                 (CRAND (CRXOR $lhs, $rhs), $tval))>;
3501
3502// match selectcc on i1 variables with non-i1 output.
3503def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3504          (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3505def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)),
3506          (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3507def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3508          (SELECT_I4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3509def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)),
3510          (SELECT_I4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3511def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3512          (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3513def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3514          (SELECT_I4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3515def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)),
3516          (SELECT_I4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3517def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3518          (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3519def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)),
3520          (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3521def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3522          (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3523
3524def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3525          (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3526def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)),
3527          (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3528def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3529          (SELECT_I8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3530def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)),
3531          (SELECT_I8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3532def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3533          (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3534def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3535          (SELECT_I8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3536def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)),
3537          (SELECT_I8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3538def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3539          (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3540def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)),
3541          (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3542def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3543          (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3544
3545def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3546          (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3547def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
3548          (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3549def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3550          (SELECT_F4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3551def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),
3552          (SELECT_F4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3553def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3554          (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3555def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3556          (SELECT_F4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3557def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
3558          (SELECT_F4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3559def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3560          (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3561def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
3562          (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3563def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3564          (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3565
3566def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3567          (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3568def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
3569          (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3570def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3571          (SELECT_F8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3572def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)),
3573          (SELECT_F8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3574def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3575          (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3576def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3577          (SELECT_F8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3578def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
3579          (SELECT_F8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3580def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3581          (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3582def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
3583          (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3584def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3585          (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3586
3587def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3588          (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3589def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)),
3590          (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3591def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3592          (SELECT_VRRC (CRORC  $lhs, $rhs), $tval, $fval)>;
3593def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)),
3594          (SELECT_VRRC (CRORC  $rhs, $lhs), $tval, $fval)>;
3595def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3596          (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3597def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3598          (SELECT_VRRC (CRORC  $rhs, $lhs), $tval, $fval)>;
3599def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)),
3600          (SELECT_VRRC (CRORC  $lhs, $rhs), $tval, $fval)>;
3601def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3602          (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3603def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)),
3604          (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3605def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3606          (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3607
3608let usesCustomInserter = 1 in {
3609def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3610                             "#ANDIo_1_EQ_BIT",
3611                             [(set i1:$dst, (trunc (not i32:$in)))]>;
3612def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3613                             "#ANDIo_1_GT_BIT",
3614                             [(set i1:$dst, (trunc i32:$in))]>;
3615
3616def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3617                              "#ANDIo_1_EQ_BIT8",
3618                              [(set i1:$dst, (trunc (not i64:$in)))]>;
3619def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3620                              "#ANDIo_1_GT_BIT8",
3621                              [(set i1:$dst, (trunc i64:$in))]>;
3622}
3623
3624def : Pat<(i1 (not (trunc i32:$in))),
3625           (ANDIo_1_EQ_BIT $in)>;
3626def : Pat<(i1 (not (trunc i64:$in))),
3627           (ANDIo_1_EQ_BIT8 $in)>;
3628
3629//===----------------------------------------------------------------------===//
3630// PowerPC Instructions used for assembler/disassembler only
3631//
3632
3633// FIXME: For B=0 or B > 8, the registers following RT are used.
3634// WARNING: Do not add patterns for this instruction without fixing this.
3635def LSWI  : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3636                            "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3637
3638// FIXME: For B=0 or B > 8, the registers following RT are used.
3639// WARNING: Do not add patterns for this instruction without fixing this.
3640def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3641                            "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3642
3643def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3644                         "isync", IIC_SprISYNC, []>;
3645
3646def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3647                    "icbi $src", IIC_LdStICBI, []>;
3648
3649// We used to have EIEIO as value but E[0-9A-Z] is a reserved name
3650def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3651                           "eieio", IIC_LdStLoad, []>;
3652
3653def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3654                         "wait $L", IIC_LdStLoad, []>;
3655
3656def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3657                         "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3658
3659def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3660            "mtsr $SR, $RS", IIC_SprMTSR>;
3661
3662def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3663            "mfsr $RS, $SR", IIC_SprMFSR>;
3664
3665def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3666            "mtsrin $RS, $RB", IIC_SprMTSR>;
3667
3668def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3669            "mfsrin $RS, $RB", IIC_SprMFSR>;
3670
3671def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3672                    "mtmsr $RS, $L", IIC_SprMTMSR>;
3673
3674def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3675                    "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3676  let L = 0;
3677}
3678
3679def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3680              Requires<[IsBookE]> {
3681  bits<1> E;
3682
3683  let Inst{16} = E;
3684  let Inst{21-30} = 163;
3685}
3686
3687def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3688               "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3689def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3690               "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3691
3692def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3693def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3694def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3695def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3696
3697def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3698                  "mfmsr $RT", IIC_SprMFMSR, []>;
3699
3700def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3701                    "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3702
3703def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
3704                     "mcrfs $BF, $BFA", IIC_BrMCR>;
3705
3706def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3707                      "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
3708
3709def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3710                       "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
3711
3712def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
3713def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
3714
3715def MTFSF : XFLForm_1<63, 711, (outs),
3716                      (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3717                      "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
3718def MTFSFo : XFLForm_1<63, 711, (outs),
3719                       (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3720                       "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
3721
3722def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3723def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3724
3725def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3726                        "slbie $RB", IIC_SprSLBIE, []>;
3727
3728def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3729                    "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3730
3731def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3732                       "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3733
3734def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB),
3735                       "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>;
3736
3737def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3738
3739def TLBIA : XForm_0<31, 370, (outs), (ins),
3740                        "tlbia", IIC_SprTLBIA, []>;
3741
3742def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3743                        "tlbsync", IIC_SprTLBSYNC, []>;
3744
3745def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3746                          "tlbiel $RB", IIC_SprTLBIEL, []>;
3747
3748def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3749                          "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3750def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3751                          "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3752
3753def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3754                          "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3755
3756def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3757                IIC_LdStLoad>, Requires<[IsBookE]>;
3758
3759def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3760                IIC_LdStLoad>, Requires<[IsBookE]>;
3761
3762def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3763                           "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3764
3765def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3766                           "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3767
3768def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3769               "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3770
3771def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3772               "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3773
3774def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3775                             "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3776                             Requires<[IsPPC4xx]>;
3777def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3778                              (ins gprc:$RST, gprc:$A, gprc:$B),
3779                              "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3780                              Requires<[IsPPC4xx]>, isDOT;
3781
3782def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3783
3784def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3785                  Requires<[IsBookE]>;
3786def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3787                   Requires<[IsBookE]>;
3788
3789def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3790                   Requires<[IsE500]>;
3791def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3792                    Requires<[IsE500]>;
3793
3794def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3795                      "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3796def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3797                      "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3798
3799def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>;
3800def NAP   : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>;
3801
3802def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
3803
3804def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3805                             "lbzcix $RST, $A, $B", IIC_LdStLoad, []>;
3806def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3807                             "lhzcix $RST, $A, $B", IIC_LdStLoad, []>;
3808def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3809                             "lwzcix $RST, $A, $B", IIC_LdStLoad, []>;
3810def LDCIX :  XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3811                             "ldcix $RST, $A, $B", IIC_LdStLoad, []>;
3812
3813def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3814                             "stbcix $RST, $A, $B", IIC_LdStLoad, []>;
3815def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3816                             "sthcix $RST, $A, $B", IIC_LdStLoad, []>;
3817def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3818                             "stwcix $RST, $A, $B", IIC_LdStLoad, []>;
3819def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3820                             "stdcix $RST, $A, $B", IIC_LdStLoad, []>;
3821
3822//===----------------------------------------------------------------------===//
3823// PowerPC Assembler Instruction Aliases
3824//
3825
3826// Pseudo-instructions for alternate assembly syntax (never used by codegen).
3827// These are aliases that require C++ handling to convert to the target
3828// instruction, while InstAliases can be handled directly by tblgen.
3829class PPCAsmPseudo<string asm, dag iops>
3830  : Instruction {
3831  let Namespace = "PPC";
3832  bit PPC64 = 0;  // Default value, override with isPPC64
3833
3834  let OutOperandList = (outs);
3835  let InOperandList = iops;
3836  let Pattern = [];
3837  let AsmString = asm;
3838  let isAsmParserOnly = 1;
3839  let isPseudo = 1;
3840}
3841
3842def : InstAlias<"sc", (SC 0)>;
3843
3844def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
3845def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>;
3846def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
3847def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
3848
3849def : InstAlias<"wait", (WAIT 0)>;
3850def : InstAlias<"waitrsv", (WAIT 1)>;
3851def : InstAlias<"waitimpl", (WAIT 2)>;
3852
3853def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3854
3855def DCBTx   : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>;
3856def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>;
3857
3858def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3859def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3860def DCBTT  : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>;
3861
3862def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3863def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3864def DCBTSTT  : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>;
3865
3866def DCBFx  : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>;
3867def DCBFL  : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>;
3868def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>;
3869
3870def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3871def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3872def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3873def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3874
3875def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3876def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3877
3878def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3879def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3880
3881def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3882def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3883
3884def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3885def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3886
3887def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3888def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3889
3890def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3891def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3892
3893def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3894def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3895
3896def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3897def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3898
3899def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3900def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3901
3902def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3903def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3904
3905def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3906def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3907
3908def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3909def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3910
3911def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3912def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3913
3914def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3915def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3916
3917def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3918def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3919def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3920
3921def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3922def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3923
3924def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3925def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3926def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3927def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3928
3929def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3930
3931def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3932def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3933
3934def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3935def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3936
3937def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3938
3939foreach BATR = 0-3 in {
3940    def : InstAlias<"mtdbatu "#BATR#", $Rx",
3941                    (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3942                    Requires<[IsPPC6xx]>;
3943    def : InstAlias<"mfdbatu $Rx, "#BATR,
3944                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3945                    Requires<[IsPPC6xx]>;
3946    def : InstAlias<"mtdbatl "#BATR#", $Rx",
3947                    (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3948                    Requires<[IsPPC6xx]>;
3949    def : InstAlias<"mfdbatl $Rx, "#BATR,
3950                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3951                    Requires<[IsPPC6xx]>;
3952    def : InstAlias<"mtibatu "#BATR#", $Rx",
3953                    (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3954                    Requires<[IsPPC6xx]>;
3955    def : InstAlias<"mfibatu $Rx, "#BATR,
3956                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3957                    Requires<[IsPPC6xx]>;
3958    def : InstAlias<"mtibatl "#BATR#", $Rx",
3959                    (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3960                    Requires<[IsPPC6xx]>;
3961    def : InstAlias<"mfibatl $Rx, "#BATR,
3962                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3963                    Requires<[IsPPC6xx]>;
3964}
3965
3966foreach BR = 0-7 in {
3967    def : InstAlias<"mfbr"#BR#" $Rx",
3968                    (MFDCR gprc:$Rx, !add(BR, 0x80))>,
3969                    Requires<[IsPPC4xx]>;
3970    def : InstAlias<"mtbr"#BR#" $Rx",
3971                    (MTDCR gprc:$Rx, !add(BR, 0x80))>,
3972                    Requires<[IsPPC4xx]>;
3973}
3974
3975def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3976def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
3977
3978def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3979def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
3980
3981def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3982def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
3983
3984def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3985def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
3986
3987def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
3988def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
3989
3990def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3991def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
3992
3993def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3994
3995def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3996                        (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3997def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3998                         (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3999def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
4000                         (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
4001def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
4002                          (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
4003
4004def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
4005def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
4006def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
4007def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
4008
4009def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
4010def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
4011
4012def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
4013def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
4014
4015foreach SPRG = 0-3 in {
4016  def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
4017  def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
4018  def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
4019  def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
4020}
4021foreach SPRG = 4-7 in {
4022  def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
4023                  Requires<[IsBookE]>;
4024  def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
4025                  Requires<[IsBookE]>;
4026  def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
4027                  Requires<[IsBookE]>;
4028  def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
4029                  Requires<[IsBookE]>;
4030}
4031
4032def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
4033
4034def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
4035def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
4036
4037def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
4038
4039def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
4040def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
4041
4042def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
4043def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
4044def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
4045def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
4046
4047def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
4048
4049def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
4050                Requires<[IsPPC4xx]>;
4051def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
4052                Requires<[IsPPC4xx]>;
4053def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
4054                Requires<[IsPPC4xx]>;
4055def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
4056                Requires<[IsPPC4xx]>;
4057
4058def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
4059                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4060def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
4061                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4062def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
4063                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4064def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
4065                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4066def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
4067                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4068def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
4069                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4070def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
4071                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4072def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
4073                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4074def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
4075                          (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4076def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
4077                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4078def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
4079                        (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4080def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
4081                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4082def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
4083                        (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4084def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
4085                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4086def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
4087                          (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4088def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
4089                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4090def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
4091                            (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
4092def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
4093                             (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
4094
4095def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
4096def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
4097def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
4098def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
4099def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
4100def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
4101
4102def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
4103def : InstAlias<"cntlzw. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>;
4104// The POWER variant
4105def : MnemonicAlias<"cntlz",  "cntlzw">;
4106def : MnemonicAlias<"cntlz.", "cntlzw.">;
4107
4108def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
4109                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4110def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
4111                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4112def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
4113                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4114def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
4115                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4116def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
4117                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4118def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
4119                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4120def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
4121                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4122def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
4123                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4124def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
4125                        (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4126def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
4127                         (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4128def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
4129                        (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4130def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
4131                         (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4132def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
4133                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4134def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
4135                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4136def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
4137                            (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
4138def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
4139                             (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
4140
4141def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
4142def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
4143def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
4144def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
4145def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
4146def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
4147
4148def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b",
4149                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4150def RLWINMobm : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b",
4151                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4152def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b",
4153                           (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4154def RLWIMIobm : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b",
4155                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4156def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b",
4157                          (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4158def RLWNMobm : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b",
4159                           (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4160
4161// These generic branch instruction forms are used for the assembler parser only.
4162// Defs and Uses are conservative, since we don't know the BO value.
4163let PPC970_Unit = 7 in {
4164  let Defs = [CTR], Uses = [CTR, RM] in {
4165    def gBC : BForm_3<16, 0, 0, (outs),
4166                      (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
4167                      "bc $bo, $bi, $dst">;
4168    def gBCA : BForm_3<16, 1, 0, (outs),
4169                       (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
4170                       "bca $bo, $bi, $dst">;
4171    let isAsmParserOnly = 1 in {
4172      def gBCat : BForm_3_at<16, 0, 0, (outs),
4173                             (ins u5imm:$bo, atimm:$at, crbitrc:$bi,
4174                                  condbrtarget:$dst),
4175                                  "bc$at $bo, $bi, $dst">;
4176      def gBCAat : BForm_3_at<16, 1, 0, (outs),
4177                              (ins u5imm:$bo, atimm:$at, crbitrc:$bi,
4178                                   abscondbrtarget:$dst),
4179                                   "bca$at $bo, $bi, $dst">;
4180    } // isAsmParserOnly = 1
4181  }
4182  let Defs = [LR, CTR], Uses = [CTR, RM] in {
4183    def gBCL : BForm_3<16, 0, 1, (outs),
4184                       (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
4185                       "bcl $bo, $bi, $dst">;
4186    def gBCLA : BForm_3<16, 1, 1, (outs),
4187                        (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
4188                        "bcla $bo, $bi, $dst">;
4189    let isAsmParserOnly = 1 in {
4190      def gBCLat : BForm_3_at<16, 0, 1, (outs),
4191                         (ins u5imm:$bo, atimm:$at, crbitrc:$bi,
4192                              condbrtarget:$dst),
4193                              "bcl$at $bo, $bi, $dst">;
4194      def gBCLAat : BForm_3_at<16, 1, 1, (outs),
4195                          (ins u5imm:$bo, atimm:$at, crbitrc:$bi,
4196                               abscondbrtarget:$dst),
4197                               "bcla$at $bo, $bi, $dst">;
4198    } // // isAsmParserOnly = 1
4199  }
4200  let Defs = [CTR], Uses = [CTR, LR, RM] in
4201    def gBCLR : XLForm_2<19, 16, 0, (outs),
4202                         (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4203                         "bclr $bo, $bi, $bh", IIC_BrB, []>;
4204  let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
4205    def gBCLRL : XLForm_2<19, 16, 1, (outs),
4206                          (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4207                          "bclrl $bo, $bi, $bh", IIC_BrB, []>;
4208  let Defs = [CTR], Uses = [CTR, LR, RM] in
4209    def gBCCTR : XLForm_2<19, 528, 0, (outs),
4210                          (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4211                          "bcctr $bo, $bi, $bh", IIC_BrB, []>;
4212  let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
4213    def gBCCTRL : XLForm_2<19, 528, 1, (outs),
4214                           (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4215                           "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
4216}
4217
4218multiclass BranchSimpleMnemonicAT<string pm, int at> {
4219  def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi,
4220                                                    condbrtarget:$dst)>;
4221  def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi,
4222                                                      condbrtarget:$dst)>;
4223  def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi,
4224                                                      condbrtarget:$dst)>;
4225  def : InstAlias<"bcla"#pm#" $bo, $bi, $dst", (gBCLAat u5imm:$bo, at, crbitrc:$bi,
4226                                                        condbrtarget:$dst)>;
4227}
4228defm : BranchSimpleMnemonicAT<"+", 3>;
4229defm : BranchSimpleMnemonicAT<"-", 2>;
4230
4231def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
4232def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
4233def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
4234def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
4235
4236multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
4237  def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
4238  def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
4239  def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
4240  def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
4241  def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
4242  def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
4243}
4244multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
4245  : BranchSimpleMnemonic1<name, pm, bo> {
4246  def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
4247  def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
4248}
4249defm : BranchSimpleMnemonic2<"t", "", 12>;
4250defm : BranchSimpleMnemonic2<"f", "", 4>;
4251defm : BranchSimpleMnemonic2<"t", "-", 14>;
4252defm : BranchSimpleMnemonic2<"f", "-", 6>;
4253defm : BranchSimpleMnemonic2<"t", "+", 15>;
4254defm : BranchSimpleMnemonic2<"f", "+", 7>;
4255defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
4256defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
4257defm : BranchSimpleMnemonic1<"dzt", "", 10>;
4258defm : BranchSimpleMnemonic1<"dzf", "", 2>;
4259
4260multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
4261  def : InstAlias<"b"#name#pm#" $cc, $dst",
4262                  (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
4263  def : InstAlias<"b"#name#pm#" $dst",
4264                  (BCC bibo, CR0, condbrtarget:$dst)>;
4265
4266  def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
4267                  (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
4268  def : InstAlias<"b"#name#"a"#pm#" $dst",
4269                  (BCCA bibo, CR0, abscondbrtarget:$dst)>;
4270
4271  def : InstAlias<"b"#name#"lr"#pm#" $cc",
4272                  (BCCLR bibo, crrc:$cc)>;
4273  def : InstAlias<"b"#name#"lr"#pm,
4274                  (BCCLR bibo, CR0)>;
4275
4276  def : InstAlias<"b"#name#"ctr"#pm#" $cc",
4277                  (BCCCTR bibo, crrc:$cc)>;
4278  def : InstAlias<"b"#name#"ctr"#pm,
4279                  (BCCCTR bibo, CR0)>;
4280
4281  def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
4282                  (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
4283  def : InstAlias<"b"#name#"l"#pm#" $dst",
4284                  (BCCL bibo, CR0, condbrtarget:$dst)>;
4285
4286  def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
4287                  (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
4288  def : InstAlias<"b"#name#"la"#pm#" $dst",
4289                  (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
4290
4291  def : InstAlias<"b"#name#"lrl"#pm#" $cc",
4292                  (BCCLRL bibo, crrc:$cc)>;
4293  def : InstAlias<"b"#name#"lrl"#pm,
4294                  (BCCLRL bibo, CR0)>;
4295
4296  def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
4297                  (BCCCTRL bibo, crrc:$cc)>;
4298  def : InstAlias<"b"#name#"ctrl"#pm,
4299                  (BCCCTRL bibo, CR0)>;
4300}
4301multiclass BranchExtendedMnemonic<string name, int bibo> {
4302  defm : BranchExtendedMnemonicPM<name, "", bibo>;
4303  defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
4304  defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
4305}
4306defm : BranchExtendedMnemonic<"lt", 12>;
4307defm : BranchExtendedMnemonic<"gt", 44>;
4308defm : BranchExtendedMnemonic<"eq", 76>;
4309defm : BranchExtendedMnemonic<"un", 108>;
4310defm : BranchExtendedMnemonic<"so", 108>;
4311defm : BranchExtendedMnemonic<"ge", 4>;
4312defm : BranchExtendedMnemonic<"nl", 4>;
4313defm : BranchExtendedMnemonic<"le", 36>;
4314defm : BranchExtendedMnemonic<"ng", 36>;
4315defm : BranchExtendedMnemonic<"ne", 68>;
4316defm : BranchExtendedMnemonic<"nu", 100>;
4317defm : BranchExtendedMnemonic<"ns", 100>;
4318
4319def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
4320def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
4321def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
4322def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
4323def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
4324def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
4325def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
4326def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
4327
4328def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
4329def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
4330def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
4331def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
4332def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
4333def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
4334def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
4335def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
4336
4337multiclass TrapExtendedMnemonic<string name, int to> {
4338  def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
4339  def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
4340  def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
4341  def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
4342}
4343defm : TrapExtendedMnemonic<"lt", 16>;
4344defm : TrapExtendedMnemonic<"le", 20>;
4345defm : TrapExtendedMnemonic<"eq", 4>;
4346defm : TrapExtendedMnemonic<"ge", 12>;
4347defm : TrapExtendedMnemonic<"gt", 8>;
4348defm : TrapExtendedMnemonic<"nl", 12>;
4349defm : TrapExtendedMnemonic<"ne", 24>;
4350defm : TrapExtendedMnemonic<"ng", 20>;
4351defm : TrapExtendedMnemonic<"llt", 2>;
4352defm : TrapExtendedMnemonic<"lle", 6>;
4353defm : TrapExtendedMnemonic<"lge", 5>;
4354defm : TrapExtendedMnemonic<"lgt", 1>;
4355defm : TrapExtendedMnemonic<"lnl", 5>;
4356defm : TrapExtendedMnemonic<"lng", 6>;
4357defm : TrapExtendedMnemonic<"u", 31>;
4358
4359// Atomic loads
4360def : Pat<(atomic_load_8  iaddr:$src), (LBZ  memri:$src)>;
4361def : Pat<(atomic_load_16 iaddr:$src), (LHZ  memri:$src)>;
4362def : Pat<(atomic_load_32 iaddr:$src), (LWZ  memri:$src)>;
4363def : Pat<(atomic_load_8  xaddr:$src), (LBZX memrr:$src)>;
4364def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
4365def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
4366
4367// Atomic stores
4368def : Pat<(atomic_store_8  iaddr:$ptr, i32:$val), (STB  gprc:$val, memri:$ptr)>;
4369def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH  gprc:$val, memri:$ptr)>;
4370def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW  gprc:$val, memri:$ptr)>;
4371def : Pat<(atomic_store_8  xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
4372def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
4373def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;
4374
4375let Predicates = [IsISA3_0] in {
4376
4377// Copy-Paste Facility
4378// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to
4379// PASTE for naming consistency.
4380let mayLoad = 1 in
4381def CP_COPY   : X_L1_RA5_RB5<31, 774, "copy"  , gprc, IIC_LdStCOPY, []>;
4382
4383let mayStore = 1 in
4384def CP_PASTE  : X_L1_RA5_RB5<31, 902, "paste" , gprc, IIC_LdStPASTE, []>;
4385
4386let mayStore = 1, Defs = [CR0] in
4387def CP_PASTEo : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isDOT;
4388
4389def CP_COPYx  : PPCAsmPseudo<"copy $rA, $rB" , (ins gprc:$rA, gprc:$rB)>;
4390def CP_PASTEx : PPCAsmPseudo<"paste $rA, $rB", (ins gprc:$rA, gprc:$rB)>;
4391def CP_COPY_FIRST : PPCAsmPseudo<"copy_first $rA, $rB",
4392                                  (ins gprc:$rA, gprc:$rB)>;
4393def CP_PASTE_LAST : PPCAsmPseudo<"paste_last $rA, $rB",
4394                                  (ins gprc:$rA, gprc:$rB)>;
4395def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cp_abort", IIC_SprABORT, []>;
4396
4397// Message Synchronize
4398def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>;
4399
4400// Power-Saving Mode Instruction:
4401def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>;
4402
4403} // IsISA3_0
4404