1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the subset of the 32-bit PowerPC instruction set, as used
11// by the PowerPC instruction selector.
12//
13//===----------------------------------------------------------------------===//
14
15include "PPCInstrFormats.td"
16
17//===----------------------------------------------------------------------===//
18// PowerPC specific type constraints.
19//
20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21  SDTCisVT<0, f64>, SDTCisPtrTy<1>
22]>;
23def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24  SDTCisVT<0, f64>, SDTCisPtrTy<1>
25]>;
26def SDT_PPCLxsizx : SDTypeProfile<1, 2, [
27  SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
28]>;
29def SDT_PPCstxsix : SDTypeProfile<0, 3, [
30  SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
31]>;
32def SDT_PPCVexts  : SDTypeProfile<1, 2, [
33  SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2>
34]>;
35def SDT_PPCSExtVElems  : SDTypeProfile<1, 1, [
36  SDTCisVec<0>, SDTCisVec<1>
37]>;
38
39def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
40                                           SDTCisVT<1, i32> ]>;
41def SDT_PPCCallSeqEnd   : SDCallSeqEnd<[ SDTCisVT<0, i32>,
42                                         SDTCisVT<1, i32> ]>;
43def SDT_PPCvperm   : SDTypeProfile<1, 3, [
44  SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
45]>;
46
47def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>,
48  SDTCisVec<1>, SDTCisInt<2>
49]>;
50
51def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>,
52  SDTCisVec<1>, SDTCisVec<2>, SDTCisPtrTy<3>
53]>;
54
55def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>,
56  SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3>
57]>;
58
59def SDT_PPCVecReverse: SDTypeProfile<1, 1, [ SDTCisVec<0>,
60  SDTCisVec<1>
61]>;
62
63def SDT_PPCxxpermdi: SDTypeProfile<1, 3, [ SDTCisVec<0>,
64  SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3>
65]>;
66
67def SDT_PPCvcmp : SDTypeProfile<1, 3, [
68  SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
69]>;
70
71def SDT_PPCcondbr : SDTypeProfile<0, 3, [
72  SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
73]>;
74
75def SDT_PPClbrx : SDTypeProfile<1, 2, [
76  SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
77]>;
78def SDT_PPCstbrx : SDTypeProfile<0, 3, [
79  SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
80]>;
81
82def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
83  SDTCisPtrTy<0>, SDTCisVT<1, i32>
84]>;
85
86def tocentry32 : Operand<iPTR> {
87  let MIOperandInfo = (ops i32imm:$imm);
88}
89
90def SDT_PPCqvfperm   : SDTypeProfile<1, 3, [
91  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3>
92]>;
93def SDT_PPCqvgpci   : SDTypeProfile<1, 1, [
94  SDTCisVec<0>, SDTCisInt<1>
95]>;
96def SDT_PPCqvaligni   : SDTypeProfile<1, 3, [
97  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>
98]>;
99def SDT_PPCqvesplati   : SDTypeProfile<1, 2, [
100  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>
101]>;
102
103def SDT_PPCqbflt : SDTypeProfile<1, 1, [
104  SDTCisVec<0>, SDTCisVec<1>
105]>;
106
107def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [
108  SDTCisVec<0>, SDTCisPtrTy<1>
109]>;
110
111//===----------------------------------------------------------------------===//
112// PowerPC specific DAG Nodes.
113//
114
115def PPCfre    : SDNode<"PPCISD::FRE",     SDTFPUnaryOp, []>;
116def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
117
118def PPCfcfid  : SDNode<"PPCISD::FCFID",   SDTFPUnaryOp, []>;
119def PPCfcfidu : SDNode<"PPCISD::FCFIDU",  SDTFPUnaryOp, []>;
120def PPCfcfids : SDNode<"PPCISD::FCFIDS",  SDTFPRoundOp, []>;
121def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
122def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
123def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
124def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
125def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
126def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
127                       [SDNPHasChain, SDNPMayStore]>;
128def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
129                       [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
130def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
131                       [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
132def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx,
133                       [SDNPHasChain, SDNPMayLoad]>;
134def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix,
135                       [SDNPHasChain, SDNPMayStore]>;
136def PPCVexts  : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>;
137def PPCSExtVElems  : SDNode<"PPCISD::SExtVElems", SDT_PPCSExtVElems, []>;
138
139// Extract FPSCR (not modeled at the DAG level).
140def PPCmffs   : SDNode<"PPCISD::MFFS",
141                       SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
142
143// Perform FADD in round-to-zero mode.
144def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
145
146
147def PPCfsel   : SDNode<"PPCISD::FSEL",
148   // Type constraint for fsel.
149   SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
150                        SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
151
152def PPChi       : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
153def PPClo       : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
154def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp,
155                         [SDNPMayLoad, SDNPMemOperand]>;
156def PPCvmaddfp  : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
157def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
158
159def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
160
161def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
162def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
163                            [SDNPMayLoad]>;
164def PPCaddTls     : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
165def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
166def PPCaddiTlsgdL   : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
167def PPCgetTlsAddr   : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
168def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR",
169                               SDTypeProfile<1, 3, [
170                                 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
171                                 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
172def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
173def PPCaddiTlsldL   : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
174def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
175def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR",
176                               SDTypeProfile<1, 3, [
177                                 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
178                                 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
179def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;
180def PPCaddiDtprelL   : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
181
182def PPCvperm     : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
183def PPCxxsplt    : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>;
184def PPCvecinsert : SDNode<"PPCISD::VECINSERT", SDT_PPCVecInsert, []>;
185def PPCxxreverse : SDNode<"PPCISD::XXREVERSE", SDT_PPCVecReverse, []>;
186def PPCxxpermdi  : SDNode<"PPCISD::XXPERMDI", SDT_PPCxxpermdi, []>;
187def PPCvecshl    : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>;
188
189def PPCqvfperm   : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>;
190def PPCqvgpci    : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>;
191def PPCqvaligni  : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>;
192def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>;
193
194def PPCqbflt     : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>;
195
196def PPCqvlfsb    : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb,
197                          [SDNPHasChain, SDNPMayLoad]>;
198
199def PPCcmpb     : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>;
200
201// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
202// amounts.  These nodes are generated by the multi-precision shift code.
203def PPCsrl        : SDNode<"PPCISD::SRL"       , SDTIntShiftOp>;
204def PPCsra        : SDNode<"PPCISD::SRA"       , SDTIntShiftOp>;
205def PPCshl        : SDNode<"PPCISD::SHL"       , SDTIntShiftOp>;
206
207// These are target-independent nodes, but have target-specific formats.
208def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
209                           [SDNPHasChain, SDNPOutGlue]>;
210def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_PPCCallSeqEnd,
211                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
212
213def SDT_PPCCall   : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
214def PPCcall  : SDNode<"PPCISD::CALL", SDT_PPCCall,
215                      [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
216                       SDNPVariadic]>;
217def PPCcall_nop  : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
218                          [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
219                           SDNPVariadic]>;
220def PPCmtctr      : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
221                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
222def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
223                      [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
224                       SDNPVariadic]>;
225def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC",
226                               SDTypeProfile<0, 1, []>,
227                               [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
228                                SDNPVariadic]>;
229
230def retflag       : SDNode<"PPCISD::RET_FLAG", SDTNone,
231                           [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
232
233def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
234                        [SDNPHasChain,  SDNPOptInGlue, SDNPVariadic]>;
235
236def PPCeh_sjlj_setjmp  : SDNode<"PPCISD::EH_SJLJ_SETJMP",
237                                SDTypeProfile<1, 1, [SDTCisInt<0>,
238                                                     SDTCisPtrTy<1>]>,
239                                [SDNPHasChain, SDNPSideEffect]>;
240def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
241                                SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
242                                [SDNPHasChain, SDNPSideEffect]>;
243
244def SDT_PPCsc     : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
245def PPCsc         : SDNode<"PPCISD::SC", SDT_PPCsc,
246                           [SDNPHasChain, SDNPSideEffect]>;
247
248def PPCclrbhrb    : SDNode<"PPCISD::CLRBHRB", SDTNone,
249                           [SDNPHasChain, SDNPSideEffect]>;
250def PPCmfbhrbe    : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>;
251def PPCrfebb      : SDNode<"PPCISD::RFEBB", SDT_PPCsc,
252                           [SDNPHasChain, SDNPSideEffect]>;
253
254def PPCvcmp       : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
255def PPCvcmp_o     : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
256
257def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
258                           [SDNPHasChain, SDNPOptInGlue]>;
259
260def PPClbrx       : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
261                           [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
262def PPCstbrx      : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
263                           [SDNPHasChain, SDNPMayStore]>;
264
265// Instructions to set/unset CR bit 6 for SVR4 vararg calls
266def PPCcr6set   : SDNode<"PPCISD::CR6SET", SDTNone,
267                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
268def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
269                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
270
271// Instructions to support dynamic alloca.
272def SDTDynOp  : SDTypeProfile<1, 2, []>;
273def SDTDynAreaOp  : SDTypeProfile<1, 1, []>;
274def PPCdynalloc   : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
275def PPCdynareaoffset   : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>;
276
277//===----------------------------------------------------------------------===//
278// PowerPC specific transformation functions and pattern fragments.
279//
280
281def SHL32 : SDNodeXForm<imm, [{
282  // Transformation function: 31 - imm
283  return getI32Imm(31 - N->getZExtValue(), SDLoc(N));
284}]>;
285
286def SRL32 : SDNodeXForm<imm, [{
287  // Transformation function: 32 - imm
288  return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N))
289                           : getI32Imm(0, SDLoc(N));
290}]>;
291
292def LO16 : SDNodeXForm<imm, [{
293  // Transformation function: get the low 16 bits.
294  return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N));
295}]>;
296
297def HI16 : SDNodeXForm<imm, [{
298  // Transformation function: shift the immediate value down into the low bits.
299  return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N));
300}]>;
301
302def HA16 : SDNodeXForm<imm, [{
303  // Transformation function: shift the immediate value down into the low bits.
304  int Val = N->getZExtValue();
305  return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N));
306}]>;
307def MB : SDNodeXForm<imm, [{
308  // Transformation function: get the start bit of a mask
309  unsigned mb = 0, me;
310  (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
311  return getI32Imm(mb, SDLoc(N));
312}]>;
313
314def ME : SDNodeXForm<imm, [{
315  // Transformation function: get the end bit of a mask
316  unsigned mb, me = 0;
317  (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
318  return getI32Imm(me, SDLoc(N));
319}]>;
320def maskimm32 : PatLeaf<(imm), [{
321  // maskImm predicate - True if immediate is a run of ones.
322  unsigned mb, me;
323  if (N->getValueType(0) == MVT::i32)
324    return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
325  else
326    return false;
327}]>;
328
329def imm32SExt16  : Operand<i32>, ImmLeaf<i32, [{
330  // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
331  // sign extended field.  Used by instructions like 'addi'.
332  return (int32_t)Imm == (short)Imm;
333}]>;
334def imm64SExt16  : Operand<i64>, ImmLeaf<i64, [{
335  // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
336  // sign extended field.  Used by instructions like 'addi'.
337  return (int64_t)Imm == (short)Imm;
338}]>;
339def immZExt16  : PatLeaf<(imm), [{
340  // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
341  // field.  Used by instructions like 'ori'.
342  return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
343}], LO16>;
344def immAnyExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm) || isUInt<8>(Imm); }]>;
345def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>;
346
347// imm16Shifted* - These match immediates where the low 16-bits are zero.  There
348// are two forms: imm16ShiftedSExt and imm16ShiftedZExt.  These two forms are
349// identical in 32-bit mode, but in 64-bit mode, they return true if the
350// immediate fits into a sign/zero extended 32-bit immediate (with the low bits
351// clear).
352def imm16ShiftedZExt : PatLeaf<(imm), [{
353  // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
354  // immediate are set.  Used by instructions like 'xoris'.
355  return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
356}], HI16>;
357
358def imm16ShiftedSExt : PatLeaf<(imm), [{
359  // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
360  // immediate are set.  Used by instructions like 'addis'.  Identical to
361  // imm16ShiftedZExt in 32-bit mode.
362  if (N->getZExtValue() & 0xFFFF) return false;
363  if (N->getValueType(0) == MVT::i32)
364    return true;
365  // For 64-bit, make sure it is sext right.
366  return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
367}], HI16>;
368
369def imm64ZExt32  : Operand<i64>, ImmLeaf<i64, [{
370  // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
371  // zero extended field.
372  return isUInt<32>(Imm);
373}]>;
374
375// Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
376// restricted memrix (4-aligned) constants are alignment sensitive. If these
377// offsets are hidden behind TOC entries than the values of the lower-order
378// bits cannot be checked directly. As a result, we need to also incorporate
379// an alignment check into the relevant patterns.
380
381def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
382  return cast<LoadSDNode>(N)->getAlignment() >= 4;
383}]>;
384def aligned4store : PatFrag<(ops node:$val, node:$ptr),
385                            (store node:$val, node:$ptr), [{
386  return cast<StoreSDNode>(N)->getAlignment() >= 4;
387}]>;
388def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
389  return cast<LoadSDNode>(N)->getAlignment() >= 4;
390}]>;
391def aligned4pre_store : PatFrag<
392                          (ops node:$val, node:$base, node:$offset),
393                          (pre_store node:$val, node:$base, node:$offset), [{
394  return cast<StoreSDNode>(N)->getAlignment() >= 4;
395}]>;
396
397def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
398  return cast<LoadSDNode>(N)->getAlignment() < 4;
399}]>;
400def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
401                              (store node:$val, node:$ptr), [{
402  return cast<StoreSDNode>(N)->getAlignment() < 4;
403}]>;
404def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
405  return cast<LoadSDNode>(N)->getAlignment() < 4;
406}]>;
407
408// This is a somewhat weaker condition than actually checking for 16-byte
409// alignment. It is simply checking that the displacement can be represented
410// as an immediate that is a multiple of 16 (i.e. the requirements for DQ-Form
411// instructions).
412def quadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{
413  return isOffsetMultipleOf(N, 16);
414}]>;
415def quadwOffsetStore : PatFrag<(ops node:$val, node:$ptr),
416                               (store node:$val, node:$ptr), [{
417  return isOffsetMultipleOf(N, 16);
418}]>;
419def nonQuadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{
420  return !isOffsetMultipleOf(N, 16);
421}]>;
422def nonQuadwOffsetStore : PatFrag<(ops node:$val, node:$ptr),
423                                  (store node:$val, node:$ptr), [{
424  return !isOffsetMultipleOf(N, 16);
425}]>;
426
427//===----------------------------------------------------------------------===//
428// PowerPC Flag Definitions.
429
430class isPPC64 { bit PPC64 = 1; }
431class isDOT   { bit RC = 1; }
432
433class RegConstraint<string C> {
434  string Constraints = C;
435}
436class NoEncode<string E> {
437  string DisableEncoding = E;
438}
439
440
441//===----------------------------------------------------------------------===//
442// PowerPC Operand Definitions.
443
444// In the default PowerPC assembler syntax, registers are specified simply
445// by number, so they cannot be distinguished from immediate values (without
446// looking at the opcode).  This means that the default operand matching logic
447// for the asm parser does not work, and we need to specify custom matchers.
448// Since those can only be specified with RegisterOperand classes and not
449// directly on the RegisterClass, all instructions patterns used by the asm
450// parser need to use a RegisterOperand (instead of a RegisterClass) for
451// all their register operands.
452// For this purpose, we define one RegisterOperand for each RegisterClass,
453// using the same name as the class, just in lower case.
454
455def PPCRegGPRCAsmOperand : AsmOperandClass {
456  let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
457}
458def gprc : RegisterOperand<GPRC> {
459  let ParserMatchClass = PPCRegGPRCAsmOperand;
460}
461def PPCRegG8RCAsmOperand : AsmOperandClass {
462  let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
463}
464def g8rc : RegisterOperand<G8RC> {
465  let ParserMatchClass = PPCRegG8RCAsmOperand;
466}
467def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
468  let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
469}
470def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
471  let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
472}
473def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
474  let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
475}
476def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
477  let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
478}
479def PPCRegF8RCAsmOperand : AsmOperandClass {
480  let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
481}
482def f8rc : RegisterOperand<F8RC> {
483  let ParserMatchClass = PPCRegF8RCAsmOperand;
484}
485def PPCRegF4RCAsmOperand : AsmOperandClass {
486  let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
487}
488def f4rc : RegisterOperand<F4RC> {
489  let ParserMatchClass = PPCRegF4RCAsmOperand;
490}
491def PPCRegVRRCAsmOperand : AsmOperandClass {
492  let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
493}
494def vrrc : RegisterOperand<VRRC> {
495  let ParserMatchClass = PPCRegVRRCAsmOperand;
496}
497def PPCRegVFRCAsmOperand : AsmOperandClass {
498  let Name = "RegVFRC"; let PredicateMethod = "isRegNumber";
499}
500def vfrc : RegisterOperand<VFRC> {
501  let ParserMatchClass = PPCRegVFRCAsmOperand;
502}
503def PPCRegCRBITRCAsmOperand : AsmOperandClass {
504  let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
505}
506def crbitrc : RegisterOperand<CRBITRC> {
507  let ParserMatchClass = PPCRegCRBITRCAsmOperand;
508}
509def PPCRegCRRCAsmOperand : AsmOperandClass {
510  let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
511}
512def crrc : RegisterOperand<CRRC> {
513  let ParserMatchClass = PPCRegCRRCAsmOperand;
514}
515def crrc0 : RegisterOperand<CRRC0> {
516  let ParserMatchClass = PPCRegCRRCAsmOperand;
517}
518
519def PPCU1ImmAsmOperand : AsmOperandClass {
520  let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
521  let RenderMethod = "addImmOperands";
522}
523def u1imm   : Operand<i32> {
524  let PrintMethod = "printU1ImmOperand";
525  let ParserMatchClass = PPCU1ImmAsmOperand;
526}
527
528def PPCU2ImmAsmOperand : AsmOperandClass {
529  let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
530  let RenderMethod = "addImmOperands";
531}
532def u2imm   : Operand<i32> {
533  let PrintMethod = "printU2ImmOperand";
534  let ParserMatchClass = PPCU2ImmAsmOperand;
535}
536
537def PPCATBitsAsHintAsmOperand : AsmOperandClass {
538  let Name = "ATBitsAsHint"; let PredicateMethod = "isATBitsAsHint";
539  let RenderMethod = "addImmOperands"; // Irrelevant, predicate always fails.
540}
541def atimm   : Operand<i32> {
542  let PrintMethod = "printATBitsAsHint";
543  let ParserMatchClass = PPCATBitsAsHintAsmOperand;
544}
545
546def PPCU3ImmAsmOperand : AsmOperandClass {
547  let Name = "U3Imm"; let PredicateMethod = "isU3Imm";
548  let RenderMethod = "addImmOperands";
549}
550def u3imm   : Operand<i32> {
551  let PrintMethod = "printU3ImmOperand";
552  let ParserMatchClass = PPCU3ImmAsmOperand;
553}
554
555def PPCU4ImmAsmOperand : AsmOperandClass {
556  let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
557  let RenderMethod = "addImmOperands";
558}
559def u4imm   : Operand<i32> {
560  let PrintMethod = "printU4ImmOperand";
561  let ParserMatchClass = PPCU4ImmAsmOperand;
562}
563def PPCS5ImmAsmOperand : AsmOperandClass {
564  let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
565  let RenderMethod = "addImmOperands";
566}
567def s5imm   : Operand<i32> {
568  let PrintMethod = "printS5ImmOperand";
569  let ParserMatchClass = PPCS5ImmAsmOperand;
570  let DecoderMethod = "decodeSImmOperand<5>";
571}
572def PPCU5ImmAsmOperand : AsmOperandClass {
573  let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
574  let RenderMethod = "addImmOperands";
575}
576def u5imm   : Operand<i32> {
577  let PrintMethod = "printU5ImmOperand";
578  let ParserMatchClass = PPCU5ImmAsmOperand;
579  let DecoderMethod = "decodeUImmOperand<5>";
580}
581def PPCU6ImmAsmOperand : AsmOperandClass {
582  let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
583  let RenderMethod = "addImmOperands";
584}
585def u6imm   : Operand<i32> {
586  let PrintMethod = "printU6ImmOperand";
587  let ParserMatchClass = PPCU6ImmAsmOperand;
588  let DecoderMethod = "decodeUImmOperand<6>";
589}
590def PPCU7ImmAsmOperand : AsmOperandClass {
591  let Name = "U7Imm"; let PredicateMethod = "isU7Imm";
592  let RenderMethod = "addImmOperands";
593}
594def u7imm   : Operand<i32> {
595  let PrintMethod = "printU7ImmOperand";
596  let ParserMatchClass = PPCU7ImmAsmOperand;
597  let DecoderMethod = "decodeUImmOperand<7>";
598}
599def PPCU8ImmAsmOperand : AsmOperandClass {
600  let Name = "U8Imm"; let PredicateMethod = "isU8Imm";
601  let RenderMethod = "addImmOperands";
602}
603def u8imm   : Operand<i32> {
604  let PrintMethod = "printU8ImmOperand";
605  let ParserMatchClass = PPCU8ImmAsmOperand;
606  let DecoderMethod = "decodeUImmOperand<8>";
607}
608def PPCU10ImmAsmOperand : AsmOperandClass {
609  let Name = "U10Imm"; let PredicateMethod = "isU10Imm";
610  let RenderMethod = "addImmOperands";
611}
612def u10imm  : Operand<i32> {
613  let PrintMethod = "printU10ImmOperand";
614  let ParserMatchClass = PPCU10ImmAsmOperand;
615  let DecoderMethod = "decodeUImmOperand<10>";
616}
617def PPCU12ImmAsmOperand : AsmOperandClass {
618  let Name = "U12Imm"; let PredicateMethod = "isU12Imm";
619  let RenderMethod = "addImmOperands";
620}
621def u12imm  : Operand<i32> {
622  let PrintMethod = "printU12ImmOperand";
623  let ParserMatchClass = PPCU12ImmAsmOperand;
624  let DecoderMethod = "decodeUImmOperand<12>";
625}
626def PPCS16ImmAsmOperand : AsmOperandClass {
627  let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
628  let RenderMethod = "addS16ImmOperands";
629}
630def s16imm  : Operand<i32> {
631  let PrintMethod = "printS16ImmOperand";
632  let EncoderMethod = "getImm16Encoding";
633  let ParserMatchClass = PPCS16ImmAsmOperand;
634  let DecoderMethod = "decodeSImmOperand<16>";
635}
636def PPCU16ImmAsmOperand : AsmOperandClass {
637  let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
638  let RenderMethod = "addU16ImmOperands";
639}
640def u16imm  : Operand<i32> {
641  let PrintMethod = "printU16ImmOperand";
642  let EncoderMethod = "getImm16Encoding";
643  let ParserMatchClass = PPCU16ImmAsmOperand;
644  let DecoderMethod = "decodeUImmOperand<16>";
645}
646def PPCS17ImmAsmOperand : AsmOperandClass {
647  let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
648  let RenderMethod = "addS16ImmOperands";
649}
650def s17imm  : Operand<i32> {
651  // This operand type is used for addis/lis to allow the assembler parser
652  // to accept immediates in the range -65536..65535 for compatibility with
653  // the GNU assembler.  The operand is treated as 16-bit otherwise.
654  let PrintMethod = "printS16ImmOperand";
655  let EncoderMethod = "getImm16Encoding";
656  let ParserMatchClass = PPCS17ImmAsmOperand;
657  let DecoderMethod = "decodeSImmOperand<16>";
658}
659
660def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
661
662def PPCDirectBrAsmOperand : AsmOperandClass {
663  let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
664  let RenderMethod = "addBranchTargetOperands";
665}
666def directbrtarget : Operand<OtherVT> {
667  let PrintMethod = "printBranchOperand";
668  let EncoderMethod = "getDirectBrEncoding";
669  let ParserMatchClass = PPCDirectBrAsmOperand;
670}
671def absdirectbrtarget : Operand<OtherVT> {
672  let PrintMethod = "printAbsBranchOperand";
673  let EncoderMethod = "getAbsDirectBrEncoding";
674  let ParserMatchClass = PPCDirectBrAsmOperand;
675}
676def PPCCondBrAsmOperand : AsmOperandClass {
677  let Name = "CondBr"; let PredicateMethod = "isCondBr";
678  let RenderMethod = "addBranchTargetOperands";
679}
680def condbrtarget : Operand<OtherVT> {
681  let PrintMethod = "printBranchOperand";
682  let EncoderMethod = "getCondBrEncoding";
683  let ParserMatchClass = PPCCondBrAsmOperand;
684}
685def abscondbrtarget : Operand<OtherVT> {
686  let PrintMethod = "printAbsBranchOperand";
687  let EncoderMethod = "getAbsCondBrEncoding";
688  let ParserMatchClass = PPCCondBrAsmOperand;
689}
690def calltarget : Operand<iPTR> {
691  let PrintMethod = "printBranchOperand";
692  let EncoderMethod = "getDirectBrEncoding";
693  let ParserMatchClass = PPCDirectBrAsmOperand;
694}
695def abscalltarget : Operand<iPTR> {
696  let PrintMethod = "printAbsBranchOperand";
697  let EncoderMethod = "getAbsDirectBrEncoding";
698  let ParserMatchClass = PPCDirectBrAsmOperand;
699}
700def PPCCRBitMaskOperand : AsmOperandClass {
701 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
702}
703def crbitm: Operand<i8> {
704  let PrintMethod = "printcrbitm";
705  let EncoderMethod = "get_crbitm_encoding";
706  let DecoderMethod = "decodeCRBitMOperand";
707  let ParserMatchClass = PPCCRBitMaskOperand;
708}
709// Address operands
710// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
711def PPCRegGxRCNoR0Operand : AsmOperandClass {
712  let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
713}
714def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
715  let ParserMatchClass = PPCRegGxRCNoR0Operand;
716}
717// A version of ptr_rc usable with the asm parser.
718def PPCRegGxRCOperand : AsmOperandClass {
719  let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
720}
721def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
722  let ParserMatchClass = PPCRegGxRCOperand;
723}
724
725def PPCDispRIOperand : AsmOperandClass {
726 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
727 let RenderMethod = "addS16ImmOperands";
728}
729def dispRI : Operand<iPTR> {
730  let ParserMatchClass = PPCDispRIOperand;
731}
732def PPCDispRIXOperand : AsmOperandClass {
733 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
734 let RenderMethod = "addImmOperands";
735}
736def dispRIX : Operand<iPTR> {
737  let ParserMatchClass = PPCDispRIXOperand;
738}
739def PPCDispRIX16Operand : AsmOperandClass {
740 let Name = "DispRIX16"; let PredicateMethod = "isS16ImmX16";
741 let RenderMethod = "addImmOperands";
742}
743def dispRIX16 : Operand<iPTR> {
744  let ParserMatchClass = PPCDispRIX16Operand;
745}
746def PPCDispSPE8Operand : AsmOperandClass {
747 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
748 let RenderMethod = "addImmOperands";
749}
750def dispSPE8 : Operand<iPTR> {
751  let ParserMatchClass = PPCDispSPE8Operand;
752}
753def PPCDispSPE4Operand : AsmOperandClass {
754 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
755 let RenderMethod = "addImmOperands";
756}
757def dispSPE4 : Operand<iPTR> {
758  let ParserMatchClass = PPCDispSPE4Operand;
759}
760def PPCDispSPE2Operand : AsmOperandClass {
761 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
762 let RenderMethod = "addImmOperands";
763}
764def dispSPE2 : Operand<iPTR> {
765  let ParserMatchClass = PPCDispSPE2Operand;
766}
767
768def memri : Operand<iPTR> {
769  let PrintMethod = "printMemRegImm";
770  let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
771  let EncoderMethod = "getMemRIEncoding";
772  let DecoderMethod = "decodeMemRIOperands";
773}
774def memrr : Operand<iPTR> {
775  let PrintMethod = "printMemRegReg";
776  let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
777}
778def memrix : Operand<iPTR> {   // memri where the imm is 4-aligned.
779  let PrintMethod = "printMemRegImm";
780  let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
781  let EncoderMethod = "getMemRIXEncoding";
782  let DecoderMethod = "decodeMemRIXOperands";
783}
784def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16:27}
785  let PrintMethod = "printMemRegImm";
786  let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg);
787  let EncoderMethod = "getMemRIX16Encoding";
788  let DecoderMethod = "decodeMemRIX16Operands";
789}
790def spe8dis : Operand<iPTR> {   // SPE displacement where the imm is 8-aligned.
791  let PrintMethod = "printMemRegImm";
792  let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
793  let EncoderMethod = "getSPE8DisEncoding";
794}
795def spe4dis : Operand<iPTR> {   // SPE displacement where the imm is 4-aligned.
796  let PrintMethod = "printMemRegImm";
797  let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
798  let EncoderMethod = "getSPE4DisEncoding";
799}
800def spe2dis : Operand<iPTR> {   // SPE displacement where the imm is 2-aligned.
801  let PrintMethod = "printMemRegImm";
802  let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
803  let EncoderMethod = "getSPE2DisEncoding";
804}
805
806// A single-register address. This is used with the SjLj
807// pseudo-instructions which tranlates to LD/LWZ.  These instructions requires
808// G8RC_NOX0 registers.
809def memr : Operand<iPTR> {
810  let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg);
811}
812def PPCTLSRegOperand : AsmOperandClass {
813  let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
814  let RenderMethod = "addTLSRegOperands";
815}
816def tlsreg32 : Operand<i32> {
817  let EncoderMethod = "getTLSRegEncoding";
818  let ParserMatchClass = PPCTLSRegOperand;
819}
820def tlsgd32 : Operand<i32> {}
821def tlscall32 : Operand<i32> {
822  let PrintMethod = "printTLSCall";
823  let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
824  let EncoderMethod = "getTLSCallEncoding";
825}
826
827// PowerPC Predicate operand.
828def pred : Operand<OtherVT> {
829  let PrintMethod = "printPredicateOperand";
830  let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
831}
832
833// Define PowerPC specific addressing mode.
834def iaddr  : ComplexPattern<iPTR, 2, "SelectAddrImm",    [], []>;
835def xaddr  : ComplexPattern<iPTR, 2, "SelectAddrIdx",    [], []>;
836def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
837def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4",  [], []>;  // "std"
838def iqaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX16",  [], []>; // "stxv"
839
840// The address in a single register. This is used with the SjLj
841// pseudo-instructions.
842def addr   : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
843
844/// This is just the offset part of iaddr, used for preinc.
845def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
846
847//===----------------------------------------------------------------------===//
848// PowerPC Instruction Predicate Definitions.
849def In32BitMode  : Predicate<"!PPCSubTarget->isPPC64()">;
850def In64BitMode  : Predicate<"PPCSubTarget->isPPC64()">;
851def IsBookE  : Predicate<"PPCSubTarget->isBookE()">;
852def IsNotBookE  : Predicate<"!PPCSubTarget->isBookE()">;
853def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
854def HasSYNC   : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
855def IsPPC4xx  : Predicate<"PPCSubTarget->isPPC4xx()">;
856def IsPPC6xx  : Predicate<"PPCSubTarget->isPPC6xx()">;
857def IsE500  : Predicate<"PPCSubTarget->isE500()">;
858def HasSPE  : Predicate<"PPCSubTarget->HasSPE()">;
859def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
860def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">;
861def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
862def NaNsFPMath   : Predicate<"!TM.Options.NoNaNsFPMath">;
863def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">;
864def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">;
865def IsISA3_0 : Predicate<"PPCSubTarget->isISA3_0()">;
866
867//===----------------------------------------------------------------------===//
868// PowerPC Multiclass Definitions.
869
870multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
871                    string asmbase, string asmstr, InstrItinClass itin,
872                    list<dag> pattern> {
873  let BaseName = asmbase in {
874    def NAME : XForm_6<opcode, xo, OOL, IOL,
875                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
876                       pattern>, RecFormRel;
877    let Defs = [CR0] in
878    def o    : XForm_6<opcode, xo, OOL, IOL,
879                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
880                       []>, isDOT, RecFormRel;
881  }
882}
883
884multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
885                     string asmbase, string asmstr, InstrItinClass itin,
886                     list<dag> pattern> {
887  let BaseName = asmbase in {
888    let Defs = [CARRY] in
889    def NAME : XForm_6<opcode, xo, OOL, IOL,
890                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
891                       pattern>, RecFormRel;
892    let Defs = [CARRY, CR0] in
893    def o    : XForm_6<opcode, xo, OOL, IOL,
894                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
895                       []>, isDOT, RecFormRel;
896  }
897}
898
899multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
900                      string asmbase, string asmstr, InstrItinClass itin,
901                      list<dag> pattern> {
902  let BaseName = asmbase in {
903    let Defs = [CARRY] in
904    def NAME : XForm_10<opcode, xo, OOL, IOL,
905                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
906                       pattern>, RecFormRel;
907    let Defs = [CARRY, CR0] in
908    def o    : XForm_10<opcode, xo, OOL, IOL,
909                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
910                       []>, isDOT, RecFormRel;
911  }
912}
913
914multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
915                    string asmbase, string asmstr, InstrItinClass itin,
916                    list<dag> pattern> {
917  let BaseName = asmbase in {
918    def NAME : XForm_11<opcode, xo, OOL, IOL,
919                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
920                       pattern>, RecFormRel;
921    let Defs = [CR0] in
922    def o    : XForm_11<opcode, xo, OOL, IOL,
923                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
924                       []>, isDOT, RecFormRel;
925  }
926}
927
928multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
929                    string asmbase, string asmstr, InstrItinClass itin,
930                    list<dag> pattern> {
931  let BaseName = asmbase in {
932    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
933                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
934                       pattern>, RecFormRel;
935    let Defs = [CR0] in
936    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
937                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
938                       []>, isDOT, RecFormRel;
939  }
940}
941
942// Multiclass for instructions for which the non record form is not cracked
943// and the record form is cracked (i.e. divw, mullw, etc.)
944multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
945                      string asmbase, string asmstr, InstrItinClass itin,
946                      list<dag> pattern> {
947  let BaseName = asmbase in {
948    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
949                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
950                       pattern>, RecFormRel;
951    let Defs = [CR0] in
952    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
953                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
954                       []>, isDOT, RecFormRel, PPC970_DGroup_First,
955                       PPC970_DGroup_Cracked;
956  }
957}
958
959multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
960                      string asmbase, string asmstr, InstrItinClass itin,
961                      list<dag> pattern> {
962  let BaseName = asmbase in {
963    let Defs = [CARRY] in
964    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
965                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
966                       pattern>, RecFormRel;
967    let Defs = [CARRY, CR0] in
968    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
969                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
970                       []>, isDOT, RecFormRel;
971  }
972}
973
974multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
975                    string asmbase, string asmstr, InstrItinClass itin,
976                    list<dag> pattern> {
977  let BaseName = asmbase in {
978    def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
979                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
980                       pattern>, RecFormRel;
981    let Defs = [CR0] in
982    def o    : XOForm_3<opcode, xo, oe, OOL, IOL,
983                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
984                       []>, isDOT, RecFormRel;
985  }
986}
987
988multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
989                      string asmbase, string asmstr, InstrItinClass itin,
990                      list<dag> pattern> {
991  let BaseName = asmbase in {
992    let Defs = [CARRY] in
993    def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
994                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
995                       pattern>, RecFormRel;
996    let Defs = [CARRY, CR0] in
997    def o    : XOForm_3<opcode, xo, oe, OOL, IOL,
998                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
999                       []>, isDOT, RecFormRel;
1000  }
1001}
1002
1003multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
1004                    string asmbase, string asmstr, InstrItinClass itin,
1005                    list<dag> pattern> {
1006  let BaseName = asmbase in {
1007    def NAME : MForm_2<opcode, OOL, IOL,
1008                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1009                       pattern>, RecFormRel;
1010    let Defs = [CR0] in
1011    def o    : MForm_2<opcode, OOL, IOL,
1012                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1013                       []>, isDOT, RecFormRel;
1014  }
1015}
1016
1017multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
1018                    string asmbase, string asmstr, InstrItinClass itin,
1019                    list<dag> pattern> {
1020  let BaseName = asmbase in {
1021    def NAME : MDForm_1<opcode, xo, OOL, IOL,
1022                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1023                       pattern>, RecFormRel;
1024    let Defs = [CR0] in
1025    def o    : MDForm_1<opcode, xo, OOL, IOL,
1026                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1027                       []>, isDOT, RecFormRel;
1028  }
1029}
1030
1031multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
1032                     string asmbase, string asmstr, InstrItinClass itin,
1033                     list<dag> pattern> {
1034  let BaseName = asmbase in {
1035    def NAME : MDSForm_1<opcode, xo, OOL, IOL,
1036                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1037                        pattern>, RecFormRel;
1038    let Defs = [CR0] in
1039    def o    : MDSForm_1<opcode, xo, OOL, IOL,
1040                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1041                        []>, isDOT, RecFormRel;
1042  }
1043}
1044
1045multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
1046                      string asmbase, string asmstr, InstrItinClass itin,
1047                      list<dag> pattern> {
1048  let BaseName = asmbase in {
1049    let Defs = [CARRY] in
1050    def NAME : XSForm_1<opcode, xo, OOL, IOL,
1051                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1052                       pattern>, RecFormRel;
1053    let Defs = [CARRY, CR0] in
1054    def o    : XSForm_1<opcode, xo, OOL, IOL,
1055                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1056                       []>, isDOT, RecFormRel;
1057  }
1058}
1059
1060multiclass XSForm_1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
1061                    string asmbase, string asmstr, InstrItinClass itin,
1062                    list<dag> pattern> {
1063  let BaseName = asmbase in {
1064    def NAME : XSForm_1<opcode, xo, OOL, IOL,
1065                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1066                       pattern>, RecFormRel;
1067    let Defs = [CR0] in
1068    def o    : XSForm_1<opcode, xo, OOL, IOL,
1069                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1070                       []>, isDOT, RecFormRel;
1071  }
1072}
1073
1074multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
1075                    string asmbase, string asmstr, InstrItinClass itin,
1076                    list<dag> pattern> {
1077  let BaseName = asmbase in {
1078    def NAME : XForm_26<opcode, xo, OOL, IOL,
1079                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1080                       pattern>, RecFormRel;
1081    let Defs = [CR1] in
1082    def o    : XForm_26<opcode, xo, OOL, IOL,
1083                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1084                       []>, isDOT, RecFormRel;
1085  }
1086}
1087
1088multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
1089                    string asmbase, string asmstr, InstrItinClass itin,
1090                    list<dag> pattern> {
1091  let BaseName = asmbase in {
1092    def NAME : XForm_28<opcode, xo, OOL, IOL,
1093                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1094                       pattern>, RecFormRel;
1095    let Defs = [CR1] in
1096    def o    : XForm_28<opcode, xo, OOL, IOL,
1097                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1098                       []>, isDOT, RecFormRel;
1099  }
1100}
1101
1102multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
1103                    string asmbase, string asmstr, InstrItinClass itin,
1104                    list<dag> pattern> {
1105  let BaseName = asmbase in {
1106    def NAME : AForm_1<opcode, xo, OOL, IOL,
1107                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1108                       pattern>, RecFormRel;
1109    let Defs = [CR1] in
1110    def o    : AForm_1<opcode, xo, OOL, IOL,
1111                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1112                       []>, isDOT, RecFormRel;
1113  }
1114}
1115
1116multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
1117                    string asmbase, string asmstr, InstrItinClass itin,
1118                    list<dag> pattern> {
1119  let BaseName = asmbase in {
1120    def NAME : AForm_2<opcode, xo, OOL, IOL,
1121                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1122                       pattern>, RecFormRel;
1123    let Defs = [CR1] in
1124    def o    : AForm_2<opcode, xo, OOL, IOL,
1125                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1126                       []>, isDOT, RecFormRel;
1127  }
1128}
1129
1130multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
1131                    string asmbase, string asmstr, InstrItinClass itin,
1132                    list<dag> pattern> {
1133  let BaseName = asmbase in {
1134    def NAME : AForm_3<opcode, xo, OOL, IOL,
1135                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1136                       pattern>, RecFormRel;
1137    let Defs = [CR1] in
1138    def o    : AForm_3<opcode, xo, OOL, IOL,
1139                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1140                       []>, isDOT, RecFormRel;
1141  }
1142}
1143
1144//===----------------------------------------------------------------------===//
1145// PowerPC Instruction Definitions.
1146
1147// Pseudo-instructions:
1148
1149let hasCtrlDep = 1 in {
1150let Defs = [R1], Uses = [R1] in {
1151def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
1152                              "#ADJCALLSTACKDOWN $amt1 $amt2",
1153                              [(callseq_start timm:$amt1, timm:$amt2)]>;
1154def ADJCALLSTACKUP   : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
1155                              "#ADJCALLSTACKUP $amt1 $amt2",
1156                              [(callseq_end timm:$amt1, timm:$amt2)]>;
1157}
1158
1159def UPDATE_VRSAVE    : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
1160                              "UPDATE_VRSAVE $rD, $rS", []>;
1161}
1162
1163let Defs = [R1], Uses = [R1] in
1164def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
1165                       [(set i32:$result,
1166                             (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
1167def DYNAREAOFFSET : Pseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET",
1168                       [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>;
1169
1170// SELECT_CC_* - Used to implement the SELECT_CC DAG operation.  Expanded after
1171// instruction selection into a branch sequence.
1172let usesCustomInserter = 1,    // Expanded after instruction selection.
1173    PPC970_Single = 1 in {
1174  // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
1175  // because either operand might become the first operand in an isel, and
1176  // that operand cannot be r0.
1177  def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
1178                              gprc_nor0:$T, gprc_nor0:$F,
1179                              i32imm:$BROPC), "#SELECT_CC_I4",
1180                              []>;
1181  def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
1182                              g8rc_nox0:$T, g8rc_nox0:$F,
1183                              i32imm:$BROPC), "#SELECT_CC_I8",
1184                              []>;
1185  def SELECT_CC_F4  : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1186                              i32imm:$BROPC), "#SELECT_CC_F4",
1187                              []>;
1188  def SELECT_CC_F8  : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
1189                              i32imm:$BROPC), "#SELECT_CC_F8",
1190                              []>;
1191  def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
1192                              i32imm:$BROPC), "#SELECT_CC_VRRC",
1193                              []>;
1194
1195  // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
1196  // register bit directly.
1197  def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
1198                          gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
1199                          [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
1200  def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
1201                          g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
1202                          [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
1203  def SELECT_F4  : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
1204                          f4rc:$T, f4rc:$F), "#SELECT_F4",
1205                          [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
1206  def SELECT_F8  : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
1207                          f8rc:$T, f8rc:$F), "#SELECT_F8",
1208                          [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
1209  def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
1210                          vrrc:$T, vrrc:$F), "#SELECT_VRRC",
1211                          [(set v4i32:$dst,
1212                                (select i1:$cond, v4i32:$T, v4i32:$F))]>;
1213}
1214
1215// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
1216// scavenge a register for it.
1217let mayStore = 1 in {
1218def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
1219                     "#SPILL_CR", []>;
1220def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1221                         "#SPILL_CRBIT", []>;
1222}
1223
1224// RESTORE_CR - Indicate that we're restoring the CR register (previously
1225// spilled), so we'll need to scavenge a register for it.
1226let mayLoad = 1 in {
1227def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1228                     "#RESTORE_CR", []>;
1229def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1230                           "#RESTORE_CRBIT", []>;
1231}
1232
1233let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1234  let isReturn = 1, Uses = [LR, RM] in
1235    def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1236                           [(retflag)]>, Requires<[In32BitMode]>;
1237  let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1238    def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1239                            []>;
1240
1241    let isCodeGenOnly = 1 in {
1242      def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1243                               "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1244                               []>;
1245
1246      def BCCTR :  XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1247                                "bcctr 12, $bi, 0", IIC_BrB, []>;
1248      def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1249                                "bcctr 4, $bi, 0", IIC_BrB, []>;
1250    }
1251  }
1252}
1253
1254let Defs = [LR] in
1255  def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1256                   PPC970_Unit_BRU;
1257let Defs = [LR] in
1258  def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1259                    PPC970_Unit_BRU;
1260
1261let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1262  let isBarrier = 1 in {
1263  def B   : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1264                  "b $dst", IIC_BrB,
1265                  [(br bb:$dst)]>;
1266  def BA  : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1267                  "ba $dst", IIC_BrB, []>;
1268  }
1269
1270  // BCC represents an arbitrary conditional branch on a predicate.
1271  // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1272  // a two-value operand where a dag node expects two operands. :(
1273  let isCodeGenOnly = 1 in {
1274    class BCC_class : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1275                            "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1276                            /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1277    def BCC : BCC_class;
1278
1279    // The same as BCC, except that it's not a terminator. Used for introducing
1280    // control flow dependency without creating new blocks.
1281    let isTerminator = 0 in def CTRL_DEP : BCC_class;
1282
1283    def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1284                     "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1285
1286    let isReturn = 1, Uses = [LR, RM] in
1287    def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1288                           "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1289  }
1290
1291  let isCodeGenOnly = 1 in {
1292    let Pattern = [(brcond i1:$bi, bb:$dst)] in
1293    def BC  : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1294             "bc 12, $bi, $dst">;
1295
1296    let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1297    def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1298             "bc 4, $bi, $dst">;
1299
1300    let isReturn = 1, Uses = [LR, RM] in
1301    def BCLR  : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1302                             "bclr 12, $bi, 0", IIC_BrB, []>;
1303    def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1304                             "bclr 4, $bi, 0", IIC_BrB, []>;
1305  }
1306
1307  let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1308   def BDZLR  : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1309                             "bdzlr", IIC_BrB, []>;
1310   def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1311                             "bdnzlr", IIC_BrB, []>;
1312   def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1313                             "bdzlr+", IIC_BrB, []>;
1314   def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1315                             "bdnzlr+", IIC_BrB, []>;
1316   def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1317                             "bdzlr-", IIC_BrB, []>;
1318   def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1319                             "bdnzlr-", IIC_BrB, []>;
1320  }
1321
1322  let Defs = [CTR], Uses = [CTR] in {
1323    def BDZ  : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1324                       "bdz $dst">;
1325    def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1326                       "bdnz $dst">;
1327    def BDZA  : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1328                        "bdza $dst">;
1329    def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1330                        "bdnza $dst">;
1331    def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1332                       "bdz+ $dst">;
1333    def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1334                       "bdnz+ $dst">;
1335    def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1336                        "bdza+ $dst">;
1337    def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1338                        "bdnza+ $dst">;
1339    def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1340                       "bdz- $dst">;
1341    def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1342                       "bdnz- $dst">;
1343    def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1344                        "bdza- $dst">;
1345    def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1346                        "bdnza- $dst">;
1347  }
1348}
1349
1350// The unconditional BCL used by the SjLj setjmp code.
1351let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1352  let Defs = [LR], Uses = [RM] in {
1353    def BCLalways  : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1354                            "bcl 20, 31, $dst">;
1355  }
1356}
1357
1358let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1359  // Convenient aliases for call instructions
1360  let Uses = [RM] in {
1361    def BL  : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1362                    "bl $func", IIC_BrB, []>;  // See Pat patterns below.
1363    def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1364                    "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1365
1366    let isCodeGenOnly = 1 in {
1367      def BL_TLS  : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1368                          "bl $func", IIC_BrB, []>;
1369      def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1370                       "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1371      def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1372                        "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1373
1374      def BCL  : BForm_4<16, 12, 0, 1, (outs),
1375                         (ins crbitrc:$bi, condbrtarget:$dst),
1376                         "bcl 12, $bi, $dst">;
1377      def BCLn : BForm_4<16, 4, 0, 1, (outs),
1378                         (ins crbitrc:$bi, condbrtarget:$dst),
1379                         "bcl 4, $bi, $dst">;
1380    }
1381  }
1382  let Uses = [CTR, RM] in {
1383    def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1384                             "bctrl", IIC_BrB, [(PPCbctrl)]>,
1385                Requires<[In32BitMode]>;
1386
1387    let isCodeGenOnly = 1 in {
1388      def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1389                                "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1390                                []>;
1391
1392      def BCCTRL  : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1393                                 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1394      def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1395                                 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1396    }
1397  }
1398  let Uses = [LR, RM] in {
1399    def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1400                            "blrl", IIC_BrB, []>;
1401
1402    let isCodeGenOnly = 1 in {
1403      def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1404                              "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1405                              []>;
1406
1407      def BCLRL  : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1408                                "bclrl 12, $bi, 0", IIC_BrB, []>;
1409      def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1410                                "bclrl 4, $bi, 0", IIC_BrB, []>;
1411    }
1412  }
1413  let Defs = [CTR], Uses = [CTR, RM] in {
1414    def BDZL  : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1415                        "bdzl $dst">;
1416    def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1417                        "bdnzl $dst">;
1418    def BDZLA  : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1419                         "bdzla $dst">;
1420    def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1421                         "bdnzla $dst">;
1422    def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1423                        "bdzl+ $dst">;
1424    def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1425                        "bdnzl+ $dst">;
1426    def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1427                         "bdzla+ $dst">;
1428    def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1429                         "bdnzla+ $dst">;
1430    def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1431                        "bdzl- $dst">;
1432    def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1433                        "bdnzl- $dst">;
1434    def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1435                         "bdzla- $dst">;
1436    def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1437                         "bdnzla- $dst">;
1438  }
1439  let Defs = [CTR], Uses = [CTR, LR, RM] in {
1440    def BDZLRL  : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1441                               "bdzlrl", IIC_BrB, []>;
1442    def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1443                               "bdnzlrl", IIC_BrB, []>;
1444    def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1445                               "bdzlrl+", IIC_BrB, []>;
1446    def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1447                               "bdnzlrl+", IIC_BrB, []>;
1448    def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1449                               "bdzlrl-", IIC_BrB, []>;
1450    def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1451                               "bdnzlrl-", IIC_BrB, []>;
1452  }
1453}
1454
1455let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1456def TCRETURNdi :Pseudo< (outs),
1457                        (ins calltarget:$dst, i32imm:$offset),
1458                 "#TC_RETURNd $dst $offset",
1459                 []>;
1460
1461
1462let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1463def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1464                 "#TC_RETURNa $func $offset",
1465                 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1466
1467let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1468def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1469                 "#TC_RETURNr $dst $offset",
1470                 []>;
1471
1472
1473let isCodeGenOnly = 1 in {
1474
1475let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1476    isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM]  in
1477def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1478                            []>, Requires<[In32BitMode]>;
1479
1480let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1481    isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1482def TAILB   : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1483                  "b $dst", IIC_BrB,
1484                  []>;
1485
1486let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1487    isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1488def TAILBA   : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1489                  "ba $dst", IIC_BrB,
1490                  []>;
1491
1492}
1493
1494let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1495  let Defs = [CTR] in
1496  def EH_SjLj_SetJmp32  : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1497                            "#EH_SJLJ_SETJMP32",
1498                            [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1499                          Requires<[In32BitMode]>;
1500  let isTerminator = 1 in
1501  def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1502                            "#EH_SJLJ_LONGJMP32",
1503                            [(PPCeh_sjlj_longjmp addr:$buf)]>,
1504                          Requires<[In32BitMode]>;
1505}
1506
1507// This pseudo is never removed from the function, as it serves as
1508// a terminator.  Size is set to 0 to prevent the builtin assembler
1509// from emitting it.
1510let isBranch = 1, isTerminator = 1, Size = 0 in {
1511  def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1512                        "#EH_SjLj_Setup\t$dst", []>;
1513}
1514
1515// System call.
1516let PPC970_Unit = 7 in {
1517  def SC     : SCForm<17, 1, (outs), (ins i32imm:$lev),
1518                      "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1519}
1520
1521// Branch history rolling buffer.
1522def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB,
1523                      [(PPCclrbhrb)]>,
1524                      PPC970_DGroup_Single;
1525// The $dmy argument used for MFBHRBE is not needed; however, including
1526// it avoids automatic generation of PPCFastISel::fastEmit_i(), which
1527// interferes with necessary special handling (see PPCFastISel.cpp).
1528def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD),
1529                         (ins u10imm:$imm, u10imm:$dmy),
1530                         "mfbhrbe $rD, $imm", IIC_BrB,
1531                         [(set i32:$rD,
1532                               (PPCmfbhrbe imm:$imm, imm:$dmy))]>,
1533                         PPC970_DGroup_First;
1534
1535def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm",
1536                     IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>,
1537                     PPC970_DGroup_Single;
1538
1539// DCB* instructions.
1540def DCBA   : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1541                      IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1542                      PPC970_DGroup_Single;
1543def DCBI   : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1544                      IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1545                      PPC970_DGroup_Single;
1546def DCBST  : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1547                      IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1548                      PPC970_DGroup_Single;
1549def DCBZ   : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1550                      IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1551                      PPC970_DGroup_Single;
1552def DCBZL  : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1553                      IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1554                      PPC970_DGroup_Single;
1555
1556def DCBF   : DCB_Form_hint<86, (outs), (ins u5imm:$TH, memrr:$dst),
1557                      "dcbf $dst, $TH", IIC_LdStDCBF, []>,
1558                      PPC970_DGroup_Single;
1559
1560let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in {
1561def DCBT   : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst),
1562                      "dcbt $dst, $TH", IIC_LdStDCBF, []>,
1563                      PPC970_DGroup_Single;
1564def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst),
1565                      "dcbtst $dst, $TH", IIC_LdStDCBF, []>,
1566                      PPC970_DGroup_Single;
1567} // hasSideEffects = 0
1568
1569def ICBLC  : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, memrr:$src),
1570                       "icblc $CT, $src", IIC_LdStStore>, Requires<[HasICBT]>;
1571def ICBLQ  : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, memrr:$src),
1572                       "icblq. $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1573def ICBT  : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1574                       "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1575def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src),
1576                       "icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1577
1578def : Pat<(int_ppc_dcbt xoaddr:$dst),
1579          (DCBT 0, xoaddr:$dst)>;
1580def : Pat<(int_ppc_dcbtst xoaddr:$dst),
1581          (DCBTST 0, xoaddr:$dst)>;
1582def : Pat<(int_ppc_dcbf xoaddr:$dst),
1583          (DCBF 0, xoaddr:$dst)>;
1584
1585def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1586          (DCBT 0, xoaddr:$dst)>;   // data prefetch for loads
1587def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1588          (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores
1589def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1590          (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
1591
1592// Atomic operations
1593let usesCustomInserter = 1 in {
1594  let Defs = [CR0] in {
1595    def ATOMIC_LOAD_ADD_I8 : Pseudo<
1596      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1597      [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1598    def ATOMIC_LOAD_SUB_I8 : Pseudo<
1599      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1600      [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1601    def ATOMIC_LOAD_AND_I8 : Pseudo<
1602      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1603      [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1604    def ATOMIC_LOAD_OR_I8 : Pseudo<
1605      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1606      [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1607    def ATOMIC_LOAD_XOR_I8 : Pseudo<
1608      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1609      [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1610    def ATOMIC_LOAD_NAND_I8 : Pseudo<
1611      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1612      [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1613    def ATOMIC_LOAD_MIN_I8 : Pseudo<
1614      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8",
1615      [(set i32:$dst, (atomic_load_min_8 xoaddr:$ptr, i32:$incr))]>;
1616    def ATOMIC_LOAD_MAX_I8 : Pseudo<
1617      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8",
1618      [(set i32:$dst, (atomic_load_max_8 xoaddr:$ptr, i32:$incr))]>;
1619    def ATOMIC_LOAD_UMIN_I8 : Pseudo<
1620      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8",
1621      [(set i32:$dst, (atomic_load_umin_8 xoaddr:$ptr, i32:$incr))]>;
1622    def ATOMIC_LOAD_UMAX_I8 : Pseudo<
1623      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8",
1624      [(set i32:$dst, (atomic_load_umax_8 xoaddr:$ptr, i32:$incr))]>;
1625    def ATOMIC_LOAD_ADD_I16 : Pseudo<
1626      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1627      [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1628    def ATOMIC_LOAD_SUB_I16 : Pseudo<
1629      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1630      [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1631    def ATOMIC_LOAD_AND_I16 : Pseudo<
1632      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1633      [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1634    def ATOMIC_LOAD_OR_I16 : Pseudo<
1635      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1636      [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1637    def ATOMIC_LOAD_XOR_I16 : Pseudo<
1638      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1639      [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1640    def ATOMIC_LOAD_NAND_I16 : Pseudo<
1641      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1642      [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1643    def ATOMIC_LOAD_MIN_I16 : Pseudo<
1644      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16",
1645      [(set i32:$dst, (atomic_load_min_16 xoaddr:$ptr, i32:$incr))]>;
1646    def ATOMIC_LOAD_MAX_I16 : Pseudo<
1647      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16",
1648      [(set i32:$dst, (atomic_load_max_16 xoaddr:$ptr, i32:$incr))]>;
1649    def ATOMIC_LOAD_UMIN_I16 : Pseudo<
1650      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16",
1651      [(set i32:$dst, (atomic_load_umin_16 xoaddr:$ptr, i32:$incr))]>;
1652    def ATOMIC_LOAD_UMAX_I16 : Pseudo<
1653      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16",
1654      [(set i32:$dst, (atomic_load_umax_16 xoaddr:$ptr, i32:$incr))]>;
1655    def ATOMIC_LOAD_ADD_I32 : Pseudo<
1656      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1657      [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1658    def ATOMIC_LOAD_SUB_I32 : Pseudo<
1659      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1660      [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1661    def ATOMIC_LOAD_AND_I32 : Pseudo<
1662      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1663      [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1664    def ATOMIC_LOAD_OR_I32 : Pseudo<
1665      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1666      [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1667    def ATOMIC_LOAD_XOR_I32 : Pseudo<
1668      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1669      [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1670    def ATOMIC_LOAD_NAND_I32 : Pseudo<
1671      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1672      [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1673    def ATOMIC_LOAD_MIN_I32 : Pseudo<
1674      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32",
1675      [(set i32:$dst, (atomic_load_min_32 xoaddr:$ptr, i32:$incr))]>;
1676    def ATOMIC_LOAD_MAX_I32 : Pseudo<
1677      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32",
1678      [(set i32:$dst, (atomic_load_max_32 xoaddr:$ptr, i32:$incr))]>;
1679    def ATOMIC_LOAD_UMIN_I32 : Pseudo<
1680      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32",
1681      [(set i32:$dst, (atomic_load_umin_32 xoaddr:$ptr, i32:$incr))]>;
1682    def ATOMIC_LOAD_UMAX_I32 : Pseudo<
1683      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32",
1684      [(set i32:$dst, (atomic_load_umax_32 xoaddr:$ptr, i32:$incr))]>;
1685
1686    def ATOMIC_CMP_SWAP_I8 : Pseudo<
1687      (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1688      [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1689    def ATOMIC_CMP_SWAP_I16 : Pseudo<
1690      (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1691      [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1692    def ATOMIC_CMP_SWAP_I32 : Pseudo<
1693      (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1694      [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1695
1696    def ATOMIC_SWAP_I8 : Pseudo<
1697      (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1698      [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1699    def ATOMIC_SWAP_I16 : Pseudo<
1700      (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1701      [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1702    def ATOMIC_SWAP_I32 : Pseudo<
1703      (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1704      [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1705  }
1706}
1707
1708// Instructions to support atomic operations
1709let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {
1710def LBARX : XForm_1<31,  52, (outs gprc:$rD), (ins memrr:$src),
1711                    "lbarx $rD, $src", IIC_LdStLWARX, []>,
1712                    Requires<[HasPartwordAtomics]>;
1713
1714def LHARX : XForm_1<31,  116, (outs gprc:$rD), (ins memrr:$src),
1715                    "lharx $rD, $src", IIC_LdStLWARX, []>,
1716                    Requires<[HasPartwordAtomics]>;
1717
1718def LWARX : XForm_1<31,  20, (outs gprc:$rD), (ins memrr:$src),
1719                    "lwarx $rD, $src", IIC_LdStLWARX, []>;
1720
1721// Instructions to support lock versions of atomics
1722// (EH=1 - see Power ISA 2.07 Book II 4.4.2)
1723def LBARXL : XForm_1<31,  52, (outs gprc:$rD), (ins memrr:$src),
1724                     "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1725                     Requires<[HasPartwordAtomics]>;
1726
1727def LHARXL : XForm_1<31,  116, (outs gprc:$rD), (ins memrr:$src),
1728                     "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1729                     Requires<[HasPartwordAtomics]>;
1730
1731def LWARXL : XForm_1<31,  20, (outs gprc:$rD), (ins memrr:$src),
1732                     "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT;
1733
1734// The atomic instructions use the destination register as well as the next one
1735// or two registers in order (modulo 31).
1736let hasExtraSrcRegAllocReq = 1 in
1737def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC),
1738                         "lwat $rD, $rA, $FC", IIC_LdStLoad>,
1739           Requires<[IsISA3_0]>;
1740}
1741
1742let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in {
1743def STBCX : XForm_1<31, 694, (outs), (ins gprc:$rS, memrr:$dst),
1744                    "stbcx. $rS, $dst", IIC_LdStSTWCX, []>,
1745                    isDOT, Requires<[HasPartwordAtomics]>;
1746
1747def STHCX : XForm_1<31, 726, (outs), (ins gprc:$rS, memrr:$dst),
1748                    "sthcx. $rS, $dst", IIC_LdStSTWCX, []>,
1749                    isDOT, Requires<[HasPartwordAtomics]>;
1750
1751def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1752                    "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT;
1753}
1754
1755let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
1756def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC),
1757                          "stwat $rS, $rA, $FC", IIC_LdStStore>,
1758            Requires<[IsISA3_0]>;
1759
1760let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1761def TRAP  : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1762
1763def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1764                     "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1765def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1766                 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1767def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1768                     "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1769def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1770                 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1771
1772//===----------------------------------------------------------------------===//
1773// PPC32 Load Instructions.
1774//
1775
1776// Unindexed (r+i) Loads.
1777let PPC970_Unit = 2 in {
1778def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1779                  "lbz $rD, $src", IIC_LdStLoad,
1780                  [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1781def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1782                  "lha $rD, $src", IIC_LdStLHA,
1783                  [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1784                  PPC970_DGroup_Cracked;
1785def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1786                  "lhz $rD, $src", IIC_LdStLoad,
1787                  [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1788def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1789                  "lwz $rD, $src", IIC_LdStLoad,
1790                  [(set i32:$rD, (load iaddr:$src))]>;
1791
1792def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1793                  "lfs $rD, $src", IIC_LdStLFD,
1794                  [(set f32:$rD, (load iaddr:$src))]>;
1795def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1796                  "lfd $rD, $src", IIC_LdStLFD,
1797                  [(set f64:$rD, (load iaddr:$src))]>;
1798
1799
1800// Unindexed (r+i) Loads with Update (preinc).
1801let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {
1802def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1803                   "lbzu $rD, $addr", IIC_LdStLoadUpd,
1804                   []>, RegConstraint<"$addr.reg = $ea_result">,
1805                   NoEncode<"$ea_result">;
1806
1807def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1808                   "lhau $rD, $addr", IIC_LdStLHAU,
1809                   []>, RegConstraint<"$addr.reg = $ea_result">,
1810                   NoEncode<"$ea_result">;
1811
1812def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1813                   "lhzu $rD, $addr", IIC_LdStLoadUpd,
1814                   []>, RegConstraint<"$addr.reg = $ea_result">,
1815                   NoEncode<"$ea_result">;
1816
1817def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1818                   "lwzu $rD, $addr", IIC_LdStLoadUpd,
1819                   []>, RegConstraint<"$addr.reg = $ea_result">,
1820                   NoEncode<"$ea_result">;
1821
1822def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1823                  "lfsu $rD, $addr", IIC_LdStLFDU,
1824                  []>, RegConstraint<"$addr.reg = $ea_result">,
1825                   NoEncode<"$ea_result">;
1826
1827def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1828                  "lfdu $rD, $addr", IIC_LdStLFDU,
1829                  []>, RegConstraint<"$addr.reg = $ea_result">,
1830                   NoEncode<"$ea_result">;
1831
1832
1833// Indexed (r+r) Loads with Update (preinc).
1834def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1835                   (ins memrr:$addr),
1836                   "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1837                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1838                   NoEncode<"$ea_result">;
1839
1840def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1841                   (ins memrr:$addr),
1842                   "lhaux $rD, $addr", IIC_LdStLHAUX,
1843                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1844                   NoEncode<"$ea_result">;
1845
1846def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1847                   (ins memrr:$addr),
1848                   "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1849                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1850                   NoEncode<"$ea_result">;
1851
1852def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1853                   (ins memrr:$addr),
1854                   "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1855                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1856                   NoEncode<"$ea_result">;
1857
1858def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1859                   (ins memrr:$addr),
1860                   "lfsux $rD, $addr", IIC_LdStLFDUX,
1861                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1862                   NoEncode<"$ea_result">;
1863
1864def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1865                   (ins memrr:$addr),
1866                   "lfdux $rD, $addr", IIC_LdStLFDUX,
1867                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1868                   NoEncode<"$ea_result">;
1869}
1870}
1871
1872// Indexed (r+r) Loads.
1873//
1874let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in {
1875def LBZX : XForm_1<31,  87, (outs gprc:$rD), (ins memrr:$src),
1876                   "lbzx $rD, $src", IIC_LdStLoad,
1877                   [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1878def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1879                   "lhax $rD, $src", IIC_LdStLHA,
1880                   [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1881                   PPC970_DGroup_Cracked;
1882def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1883                   "lhzx $rD, $src", IIC_LdStLoad,
1884                   [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1885def LWZX : XForm_1<31,  23, (outs gprc:$rD), (ins memrr:$src),
1886                   "lwzx $rD, $src", IIC_LdStLoad,
1887                   [(set i32:$rD, (load xaddr:$src))]>;
1888def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1889                   "lhbrx $rD, $src", IIC_LdStLoad,
1890                   [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1891def LWBRX : XForm_1<31,  534, (outs gprc:$rD), (ins memrr:$src),
1892                   "lwbrx $rD, $src", IIC_LdStLoad,
1893                   [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1894
1895def LFSX   : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1896                      "lfsx $frD, $src", IIC_LdStLFD,
1897                      [(set f32:$frD, (load xaddr:$src))]>;
1898def LFDX   : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1899                      "lfdx $frD, $src", IIC_LdStLFD,
1900                      [(set f64:$frD, (load xaddr:$src))]>;
1901
1902def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1903                      "lfiwax $frD, $src", IIC_LdStLFD,
1904                      [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1905def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1906                      "lfiwzx $frD, $src", IIC_LdStLFD,
1907                      [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1908}
1909
1910// Load Multiple
1911def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1912                  "lmw $rD, $src", IIC_LdStLMW, []>;
1913
1914//===----------------------------------------------------------------------===//
1915// PPC32 Store Instructions.
1916//
1917
1918// Unindexed (r+i) Stores.
1919let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
1920def STB  : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1921                   "stb $rS, $src", IIC_LdStStore,
1922                   [(truncstorei8 i32:$rS, iaddr:$src)]>;
1923def STH  : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1924                   "sth $rS, $src", IIC_LdStStore,
1925                   [(truncstorei16 i32:$rS, iaddr:$src)]>;
1926def STW  : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1927                   "stw $rS, $src", IIC_LdStStore,
1928                   [(store i32:$rS, iaddr:$src)]>;
1929def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1930                   "stfs $rS, $dst", IIC_LdStSTFD,
1931                   [(store f32:$rS, iaddr:$dst)]>;
1932def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1933                   "stfd $rS, $dst", IIC_LdStSTFD,
1934                   [(store f64:$rS, iaddr:$dst)]>;
1935}
1936
1937// Unindexed (r+i) Stores with Update (preinc).
1938let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
1939def STBU  : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1940                    "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1941                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1942def STHU  : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1943                    "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1944                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1945def STWU  : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1946                    "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1947                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1948def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1949                    "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1950                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1951def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1952                    "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1953                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1954}
1955
1956// Patterns to match the pre-inc stores.  We can't put the patterns on
1957// the instruction definitions directly as ISel wants the address base
1958// and offset to be separate operands, not a single complex operand.
1959def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1960          (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1961def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1962          (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1963def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1964          (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1965def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1966          (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1967def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1968          (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1969
1970// Indexed (r+r) Stores.
1971let PPC970_Unit = 2 in {
1972def STBX  : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1973                   "stbx $rS, $dst", IIC_LdStStore,
1974                   [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1975                   PPC970_DGroup_Cracked;
1976def STHX  : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1977                   "sthx $rS, $dst", IIC_LdStStore,
1978                   [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1979                   PPC970_DGroup_Cracked;
1980def STWX  : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1981                   "stwx $rS, $dst", IIC_LdStStore,
1982                   [(store i32:$rS, xaddr:$dst)]>,
1983                   PPC970_DGroup_Cracked;
1984
1985def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1986                   "sthbrx $rS, $dst", IIC_LdStStore,
1987                   [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1988                   PPC970_DGroup_Cracked;
1989def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1990                   "stwbrx $rS, $dst", IIC_LdStStore,
1991                   [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1992                   PPC970_DGroup_Cracked;
1993
1994def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1995                     "stfiwx $frS, $dst", IIC_LdStSTFD,
1996                     [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1997
1998def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1999                     "stfsx $frS, $dst", IIC_LdStSTFD,
2000                     [(store f32:$frS, xaddr:$dst)]>;
2001def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
2002                     "stfdx $frS, $dst", IIC_LdStSTFD,
2003                     [(store f64:$frS, xaddr:$dst)]>;
2004}
2005
2006// Indexed (r+r) Stores with Update (preinc).
2007let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
2008def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
2009                    "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
2010                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
2011                    PPC970_DGroup_Cracked;
2012def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
2013                    "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
2014                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
2015                    PPC970_DGroup_Cracked;
2016def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
2017                    "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
2018                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
2019                    PPC970_DGroup_Cracked;
2020def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
2021                    "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
2022                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
2023                    PPC970_DGroup_Cracked;
2024def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
2025                    "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
2026                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
2027                    PPC970_DGroup_Cracked;
2028}
2029
2030// Patterns to match the pre-inc stores.  We can't put the patterns on
2031// the instruction definitions directly as ISel wants the address base
2032// and offset to be separate operands, not a single complex operand.
2033def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
2034          (STBUX $rS, $ptrreg, $ptroff)>;
2035def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
2036          (STHUX $rS, $ptrreg, $ptroff)>;
2037def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
2038          (STWUX $rS, $ptrreg, $ptroff)>;
2039def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
2040          (STFSUX $rS, $ptrreg, $ptroff)>;
2041def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
2042          (STFDUX $rS, $ptrreg, $ptroff)>;
2043
2044// Store Multiple
2045def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
2046                   "stmw $rS, $dst", IIC_LdStLMW, []>;
2047
2048def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
2049                        "sync $L", IIC_LdStSync, []>;
2050
2051let isCodeGenOnly = 1 in {
2052  def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
2053                           "msync", IIC_LdStSync, []> {
2054    let L = 0;
2055  }
2056}
2057
2058def : Pat<(int_ppc_sync),   (SYNC 0)>, Requires<[HasSYNC]>;
2059def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
2060def : Pat<(int_ppc_sync),   (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2061def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2062
2063//===----------------------------------------------------------------------===//
2064// PPC32 Arithmetic Instructions.
2065//
2066
2067let PPC970_Unit = 1 in {  // FXU Operations.
2068def ADDI   : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
2069                     "addi $rD, $rA, $imm", IIC_IntSimple,
2070                     [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
2071let BaseName = "addic" in {
2072let Defs = [CARRY] in
2073def ADDIC  : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
2074                     "addic $rD, $rA, $imm", IIC_IntGeneral,
2075                     [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
2076                     RecFormRel, PPC970_DGroup_Cracked;
2077let Defs = [CARRY, CR0] in
2078def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
2079                     "addic. $rD, $rA, $imm", IIC_IntGeneral,
2080                     []>, isDOT, RecFormRel;
2081}
2082def ADDIS  : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
2083                     "addis $rD, $rA, $imm", IIC_IntSimple,
2084                     [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
2085let isCodeGenOnly = 1 in
2086def LA     : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
2087                     "la $rD, $sym($rA)", IIC_IntGeneral,
2088                     [(set i32:$rD, (add i32:$rA,
2089                                          (PPClo tglobaladdr:$sym, 0)))]>;
2090def MULLI  : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
2091                     "mulli $rD, $rA, $imm", IIC_IntMulLI,
2092                     [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
2093let Defs = [CARRY] in
2094def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
2095                     "subfic $rD, $rA, $imm", IIC_IntGeneral,
2096                     [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
2097
2098let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
2099  def LI  : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
2100                       "li $rD, $imm", IIC_IntSimple,
2101                       [(set i32:$rD, imm32SExt16:$imm)]>;
2102  def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
2103                       "lis $rD, $imm", IIC_IntSimple,
2104                       [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
2105}
2106}
2107
2108let PPC970_Unit = 1 in {  // FXU Operations.
2109let Defs = [CR0] in {
2110def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2111                    "andi. $dst, $src1, $src2", IIC_IntGeneral,
2112                    [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
2113                    isDOT;
2114def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2115                    "andis. $dst, $src1, $src2", IIC_IntGeneral,
2116                    [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
2117                    isDOT;
2118}
2119def ORI   : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2120                    "ori $dst, $src1, $src2", IIC_IntSimple,
2121                    [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
2122def ORIS  : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2123                    "oris $dst, $src1, $src2", IIC_IntSimple,
2124                    [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
2125def XORI  : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2126                    "xori $dst, $src1, $src2", IIC_IntSimple,
2127                    [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
2128def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2129                    "xoris $dst, $src1, $src2", IIC_IntSimple,
2130                    [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
2131
2132def NOP   : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
2133                         []>;
2134let isCodeGenOnly = 1 in {
2135// The POWER6 and POWER7 have special group-terminating nops.
2136def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
2137                                        "ori 1, 1, 0", IIC_IntSimple, []>;
2138def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
2139                                        "ori 2, 2, 0", IIC_IntSimple, []>;
2140}
2141
2142let isCompare = 1, hasSideEffects = 0 in {
2143  def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
2144                          "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
2145  def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
2146                           "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
2147  def CMPRB  : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF),
2148                                (ins u1imm:$L, g8rc:$rA, g8rc:$rB),
2149                                "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>,
2150               Requires<[IsISA3_0]>;
2151}
2152}
2153
2154let PPC970_Unit = 1, hasSideEffects = 0 in {  // FXU Operations.
2155let isCommutable = 1 in {
2156defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2157                     "nand", "$rA, $rS, $rB", IIC_IntSimple,
2158                     [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
2159defm AND  : XForm_6r<31,  28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2160                     "and", "$rA, $rS, $rB", IIC_IntSimple,
2161                     [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
2162} // isCommutable
2163defm ANDC : XForm_6r<31,  60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2164                     "andc", "$rA, $rS, $rB", IIC_IntSimple,
2165                     [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
2166let isCommutable = 1 in {
2167defm OR   : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2168                     "or", "$rA, $rS, $rB", IIC_IntSimple,
2169                     [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
2170defm NOR  : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2171                     "nor", "$rA, $rS, $rB", IIC_IntSimple,
2172                     [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
2173} // isCommutable
2174defm ORC  : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2175                     "orc", "$rA, $rS, $rB", IIC_IntSimple,
2176                     [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
2177let isCommutable = 1 in {
2178defm EQV  : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2179                     "eqv", "$rA, $rS, $rB", IIC_IntSimple,
2180                     [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
2181defm XOR  : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2182                     "xor", "$rA, $rS, $rB", IIC_IntSimple,
2183                     [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
2184} // isCommutable
2185defm SLW  : XForm_6r<31,  24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2186                     "slw", "$rA, $rS, $rB", IIC_IntGeneral,
2187                     [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
2188defm SRW  : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2189                     "srw", "$rA, $rS, $rB", IIC_IntGeneral,
2190                     [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
2191defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2192                      "sraw", "$rA, $rS, $rB", IIC_IntShift,
2193                      [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
2194}
2195
2196let PPC970_Unit = 1 in {  // FXU Operations.
2197let hasSideEffects = 0 in {
2198defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
2199                        "srawi", "$rA, $rS, $SH", IIC_IntShift,
2200                        [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
2201defm CNTLZW : XForm_11r<31,  26, (outs gprc:$rA), (ins gprc:$rS),
2202                        "cntlzw", "$rA, $rS", IIC_IntGeneral,
2203                        [(set i32:$rA, (ctlz i32:$rS))]>;
2204defm CNTTZW : XForm_11r<31, 538, (outs gprc:$rA), (ins gprc:$rS),
2205                        "cnttzw", "$rA, $rS", IIC_IntGeneral,
2206                        [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>;
2207defm EXTSB  : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
2208                        "extsb", "$rA, $rS", IIC_IntSimple,
2209                        [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
2210defm EXTSH  : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
2211                        "extsh", "$rA, $rS", IIC_IntSimple,
2212                        [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
2213
2214let isCommutable = 1 in
2215def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2216                   "cmpb $rA, $rS, $rB", IIC_IntGeneral,
2217                   [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>;
2218}
2219let isCompare = 1, hasSideEffects = 0 in {
2220  def CMPW   : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
2221                            "cmpw $crD, $rA, $rB", IIC_IntCompare>;
2222  def CMPLW  : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
2223                            "cmplw $crD, $rA, $rB", IIC_IntCompare>;
2224}
2225}
2226let PPC970_Unit = 3 in {  // FPU Operations.
2227//def FCMPO  : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
2228//                      "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
2229let isCompare = 1, hasSideEffects = 0 in {
2230  def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
2231                        "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
2232  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2233  def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
2234                        "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
2235}
2236
2237def FTDIV: XForm_17<63, 128, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
2238                      "ftdiv $crD, $fA, $fB", IIC_FPCompare>;
2239def FTSQRT: XForm_17a<63, 160, (outs crrc:$crD), (ins f8rc:$fB),
2240                      "ftsqrt $crD, $fB", IIC_FPCompare>;
2241
2242let Uses = [RM] in {
2243  let hasSideEffects = 0 in {
2244  defm FCTIW  : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
2245                          "fctiw", "$frD, $frB", IIC_FPGeneral,
2246                          []>;
2247  defm FCTIWU  : XForm_26r<63, 142, (outs f8rc:$frD), (ins f8rc:$frB),
2248                          "fctiwu", "$frD, $frB", IIC_FPGeneral,
2249                          []>;
2250  defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
2251                          "fctiwz", "$frD, $frB", IIC_FPGeneral,
2252                          [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
2253
2254  defm FRSP   : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
2255                          "frsp", "$frD, $frB", IIC_FPGeneral,
2256                          [(set f32:$frD, (fpround f64:$frB))]>;
2257
2258  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2259  defm FRIND  : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
2260                          "frin", "$frD, $frB", IIC_FPGeneral,
2261                          [(set f64:$frD, (fround f64:$frB))]>;
2262  defm FRINS  : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
2263                          "frin", "$frD, $frB", IIC_FPGeneral,
2264                          [(set f32:$frD, (fround f32:$frB))]>;
2265  }
2266
2267  let hasSideEffects = 0 in {
2268  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2269  defm FRIPD  : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
2270                          "frip", "$frD, $frB", IIC_FPGeneral,
2271                          [(set f64:$frD, (fceil f64:$frB))]>;
2272  defm FRIPS  : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
2273                          "frip", "$frD, $frB", IIC_FPGeneral,
2274                          [(set f32:$frD, (fceil f32:$frB))]>;
2275  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2276  defm FRIZD  : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
2277                          "friz", "$frD, $frB", IIC_FPGeneral,
2278                          [(set f64:$frD, (ftrunc f64:$frB))]>;
2279  defm FRIZS  : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
2280                          "friz", "$frD, $frB", IIC_FPGeneral,
2281                          [(set f32:$frD, (ftrunc f32:$frB))]>;
2282  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2283  defm FRIMD  : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
2284                          "frim", "$frD, $frB", IIC_FPGeneral,
2285                          [(set f64:$frD, (ffloor f64:$frB))]>;
2286  defm FRIMS  : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
2287                          "frim", "$frD, $frB", IIC_FPGeneral,
2288                          [(set f32:$frD, (ffloor f32:$frB))]>;
2289
2290  defm FSQRT  : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
2291                          "fsqrt", "$frD, $frB", IIC_FPSqrtD,
2292                          [(set f64:$frD, (fsqrt f64:$frB))]>;
2293  defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
2294                          "fsqrts", "$frD, $frB", IIC_FPSqrtS,
2295                          [(set f32:$frD, (fsqrt f32:$frB))]>;
2296  }
2297  }
2298}
2299
2300/// Note that FMR is defined as pseudo-ops on the PPC970 because they are
2301/// often coalesced away and we don't want the dispatch group builder to think
2302/// that they will fill slots (which could cause the load of a LSU reject to
2303/// sneak into a d-group with a store).
2304let hasSideEffects = 0 in
2305defm FMR   : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
2306                       "fmr", "$frD, $frB", IIC_FPGeneral,
2307                       []>,  // (set f32:$frD, f32:$frB)
2308                       PPC970_Unit_Pseudo;
2309
2310let PPC970_Unit = 3, hasSideEffects = 0 in {  // FPU Operations.
2311// These are artificially split into two different forms, for 4/8 byte FP.
2312defm FABSS  : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
2313                        "fabs", "$frD, $frB", IIC_FPGeneral,
2314                        [(set f32:$frD, (fabs f32:$frB))]>;
2315let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2316defm FABSD  : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
2317                        "fabs", "$frD, $frB", IIC_FPGeneral,
2318                        [(set f64:$frD, (fabs f64:$frB))]>;
2319defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
2320                        "fnabs", "$frD, $frB", IIC_FPGeneral,
2321                        [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
2322let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2323defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
2324                        "fnabs", "$frD, $frB", IIC_FPGeneral,
2325                        [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
2326defm FNEGS  : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
2327                        "fneg", "$frD, $frB", IIC_FPGeneral,
2328                        [(set f32:$frD, (fneg f32:$frB))]>;
2329let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2330defm FNEGD  : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
2331                        "fneg", "$frD, $frB", IIC_FPGeneral,
2332                        [(set f64:$frD, (fneg f64:$frB))]>;
2333
2334defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
2335                        "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2336                        [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
2337let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2338defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
2339                        "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2340                        [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
2341
2342// Reciprocal estimates.
2343defm FRE      : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
2344                          "fre", "$frD, $frB", IIC_FPGeneral,
2345                          [(set f64:$frD, (PPCfre f64:$frB))]>;
2346defm FRES     : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
2347                          "fres", "$frD, $frB", IIC_FPGeneral,
2348                          [(set f32:$frD, (PPCfre f32:$frB))]>;
2349defm FRSQRTE  : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
2350                          "frsqrte", "$frD, $frB", IIC_FPGeneral,
2351                          [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
2352defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
2353                          "frsqrtes", "$frD, $frB", IIC_FPGeneral,
2354                          [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
2355}
2356
2357// XL-Form instructions.  condition register logical ops.
2358//
2359let hasSideEffects = 0 in
2360def MCRF   : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
2361                      "mcrf $BF, $BFA", IIC_BrMCR>,
2362             PPC970_DGroup_First, PPC970_Unit_CRU;
2363
2364// FIXME: According to the ISA (section 2.5.1 of version 2.06), the
2365// condition-register logical instructions have preferred forms. Specifically,
2366// it is preferred that the bit specified by the BT field be in the same
2367// condition register as that specified by the bit BB. We might want to account
2368// for this via hinting the register allocator and anti-dep breakers, or we
2369// could constrain the register class to force this constraint and then loosen
2370// it during register allocation via convertToThreeAddress or some similar
2371// mechanism.
2372
2373let isCommutable = 1 in {
2374def CRAND  : XLForm_1<19, 257, (outs crbitrc:$CRD),
2375                               (ins crbitrc:$CRA, crbitrc:$CRB),
2376                      "crand $CRD, $CRA, $CRB", IIC_BrCR,
2377                      [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2378
2379def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2380                               (ins crbitrc:$CRA, crbitrc:$CRB),
2381                      "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2382                      [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2383
2384def CROR   : XLForm_1<19, 449, (outs crbitrc:$CRD),
2385                               (ins crbitrc:$CRA, crbitrc:$CRB),
2386                      "cror $CRD, $CRA, $CRB", IIC_BrCR,
2387                      [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2388
2389def CRXOR  : XLForm_1<19, 193, (outs crbitrc:$CRD),
2390                               (ins crbitrc:$CRA, crbitrc:$CRB),
2391                      "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2392                      [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2393
2394def CRNOR  : XLForm_1<19, 33, (outs crbitrc:$CRD),
2395                              (ins crbitrc:$CRA, crbitrc:$CRB),
2396                      "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2397                      [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2398
2399def CREQV  : XLForm_1<19, 289, (outs crbitrc:$CRD),
2400                               (ins crbitrc:$CRA, crbitrc:$CRB),
2401                      "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2402                      [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2403} // isCommutable
2404
2405def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2406                               (ins crbitrc:$CRA, crbitrc:$CRB),
2407                      "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2408                      [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2409
2410def CRORC  : XLForm_1<19, 417, (outs crbitrc:$CRD),
2411                               (ins crbitrc:$CRA, crbitrc:$CRB),
2412                      "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2413                      [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2414
2415let isCodeGenOnly = 1 in {
2416def CRSET  : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2417              "creqv $dst, $dst, $dst", IIC_BrCR,
2418              [(set i1:$dst, 1)]>;
2419
2420def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2421              "crxor $dst, $dst, $dst", IIC_BrCR,
2422              [(set i1:$dst, 0)]>;
2423
2424let Defs = [CR1EQ], CRD = 6 in {
2425def CR6SET  : XLForm_1_ext<19, 289, (outs), (ins),
2426              "creqv 6, 6, 6", IIC_BrCR,
2427              [(PPCcr6set)]>;
2428
2429def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2430              "crxor 6, 6, 6", IIC_BrCR,
2431              [(PPCcr6unset)]>;
2432}
2433}
2434
2435// XFX-Form instructions.  Instructions that deal with SPRs.
2436//
2437
2438def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2439                      "mfspr $RT, $SPR", IIC_SprMFSPR>;
2440def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2441                      "mtspr $SPR, $RT", IIC_SprMTSPR>;
2442
2443def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2444                     "mftb $RT, $SPR", IIC_SprMFTB>;
2445
2446def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR),
2447                     "mfpmr $RT, $SPR", IIC_SprMFPMR>;
2448
2449def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT),
2450                     "mtpmr $SPR, $RT", IIC_SprMTPMR>;
2451
2452
2453// A pseudo-instruction used to implement the read of the 64-bit cycle counter
2454// on a 32-bit target.
2455let hasSideEffects = 1, usesCustomInserter = 1 in
2456def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins),
2457                    "#ReadTB", []>;
2458
2459let Uses = [CTR] in {
2460def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2461                          "mfctr $rT", IIC_SprMFSPR>,
2462            PPC970_DGroup_First, PPC970_Unit_FXU;
2463}
2464let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2465def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2466                          "mtctr $rS", IIC_SprMTSPR>,
2467            PPC970_DGroup_First, PPC970_Unit_FXU;
2468}
2469let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2470let Pattern = [(int_ppc_mtctr i32:$rS)] in
2471def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2472                              "mtctr $rS", IIC_SprMTSPR>,
2473                PPC970_DGroup_First, PPC970_Unit_FXU;
2474}
2475
2476let Defs = [LR] in {
2477def MTLR  : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2478                          "mtlr $rS", IIC_SprMTSPR>,
2479            PPC970_DGroup_First, PPC970_Unit_FXU;
2480}
2481let Uses = [LR] in {
2482def MFLR  : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2483                          "mflr $rT", IIC_SprMFSPR>,
2484            PPC970_DGroup_First, PPC970_Unit_FXU;
2485}
2486
2487let isCodeGenOnly = 1 in {
2488  // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2489  // like a GPR on the PPC970.  As such, copies in and out have the same
2490  // performance characteristics as an OR instruction.
2491  def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2492                               "mtspr 256, $rS", IIC_IntGeneral>,
2493                 PPC970_DGroup_Single, PPC970_Unit_FXU;
2494  def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2495                               "mfspr $rT, 256", IIC_IntGeneral>,
2496                 PPC970_DGroup_First, PPC970_Unit_FXU;
2497
2498  def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2499                                (outs VRSAVERC:$reg), (ins gprc:$rS),
2500                                "mtspr 256, $rS", IIC_IntGeneral>,
2501                  PPC970_DGroup_Single, PPC970_Unit_FXU;
2502  def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2503                                (ins VRSAVERC:$reg),
2504                                "mfspr $rT, 256", IIC_IntGeneral>,
2505                  PPC970_DGroup_First, PPC970_Unit_FXU;
2506}
2507
2508// Aliases for mtvrsave/mfvrsave to mfspr/mtspr.
2509def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>;
2510def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>;
2511
2512// SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2513// so we'll need to scavenge a register for it.
2514let mayStore = 1 in
2515def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2516                     "#SPILL_VRSAVE", []>;
2517
2518// RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2519// spilled), so we'll need to scavenge a register for it.
2520let mayLoad = 1 in
2521def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2522                     "#RESTORE_VRSAVE", []>;
2523
2524let hasSideEffects = 0 in {
2525// mtocrf's input needs to be prepared by shifting by an amount dependent
2526// on the cr register selected. Thus, post-ra anti-dep breaking must not
2527// later change that register assignment.
2528let hasExtraDefRegAllocReq = 1 in {
2529def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2530                       "mtocrf $FXM, $ST", IIC_BrMCRX>,
2531            PPC970_DGroup_First, PPC970_Unit_CRU;
2532
2533// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that
2534// is dependent on the cr fields being set.
2535def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2536                      "mtcrf $FXM, $rS", IIC_BrMCRX>,
2537            PPC970_MicroCode, PPC970_Unit_CRU;
2538} // hasExtraDefRegAllocReq = 1
2539
2540// mfocrf's input needs to be prepared by shifting by an amount dependent
2541// on the cr register selected. Thus, post-ra anti-dep breaking must not
2542// later change that register assignment.
2543let hasExtraSrcRegAllocReq = 1 in {
2544def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2545                       "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2546            PPC970_DGroup_First, PPC970_Unit_CRU;
2547
2548// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that
2549// is dependent on the cr fields being copied.
2550def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2551                     "mfcr $rT", IIC_SprMFCR>,
2552                     PPC970_MicroCode, PPC970_Unit_CRU;
2553} // hasExtraSrcRegAllocReq = 1
2554
2555def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins),
2556                   "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>;
2557} // hasSideEffects = 0
2558
2559// Pseudo instruction to perform FADD in round-to-zero mode.
2560let usesCustomInserter = 1, Uses = [RM] in {
2561  def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2562                      [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2563}
2564
2565// The above pseudo gets expanded to make use of the following instructions
2566// to manipulate FPSCR.  Note that FPSCR is not modeled at the DAG level.
2567let Uses = [RM], Defs = [RM] in {
2568  def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2569                        "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2570               PPC970_DGroup_Single, PPC970_Unit_FPU;
2571  def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2572                        "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2573               PPC970_DGroup_Single, PPC970_Unit_FPU;
2574  let isCodeGenOnly = 1 in
2575  def MTFSFb  : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2576                        "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2577                PPC970_DGroup_Single, PPC970_Unit_FPU;
2578}
2579let Uses = [RM] in {
2580  def MFFS   : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2581                         "mffs $rT", IIC_IntMFFS,
2582                         [(set f64:$rT, (PPCmffs))]>,
2583               PPC970_DGroup_Single, PPC970_Unit_FPU;
2584
2585  let Defs = [CR1] in
2586  def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2587                      "mffs. $rT", IIC_IntMFFS, []>, isDOT;
2588
2589  def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$rT), (ins),
2590                                  "mffsce $rT", IIC_IntMFFS, []>,
2591               PPC970_DGroup_Single, PPC970_Unit_FPU;
2592
2593  def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$rT),
2594                                         (ins f8rc:$FRB), "mffscdrn $rT, $FRB",
2595                                         IIC_IntMFFS, []>,
2596                 PPC970_DGroup_Single, PPC970_Unit_FPU;
2597
2598  def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$rT),
2599                                          (ins u3imm:$DRM),
2600                                          "mffscdrni $rT, $DRM",
2601                                          IIC_IntMFFS, []>,
2602                  PPC970_DGroup_Single, PPC970_Unit_FPU;
2603
2604  def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$rT),
2605                                        (ins f8rc:$FRB), "mffscrn $rT, $FRB",
2606                                        IIC_IntMFFS, []>,
2607                PPC970_DGroup_Single, PPC970_Unit_FPU;
2608
2609  def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$rT),
2610                                       (ins u2imm:$RM), "mffscrni $rT, $RM",
2611                                       IIC_IntMFFS, []>,
2612                 PPC970_DGroup_Single, PPC970_Unit_FPU;
2613
2614  def MFFSL  : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$rT), (ins),
2615                                  "mffsl $rT", IIC_IntMFFS, []>,
2616               PPC970_DGroup_Single, PPC970_Unit_FPU;
2617}
2618
2619let Predicates = [IsISA3_0] in {
2620def MODSW : XForm_8<31, 779, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2621                        "modsw $rT, $rA, $rB", IIC_IntDivW,
2622                        [(set i32:$rT, (srem i32:$rA, i32:$rB))]>;
2623def MODUW : XForm_8<31, 267, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2624                        "moduw $rT, $rA, $rB", IIC_IntDivW,
2625                        [(set i32:$rT, (urem i32:$rA, i32:$rB))]>;
2626}
2627
2628let PPC970_Unit = 1, hasSideEffects = 0 in {  // FXU Operations.
2629// XO-Form instructions.  Arithmetic instructions that can set overflow bit
2630let isCommutable = 1 in
2631defm ADD4  : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2632                       "add", "$rT, $rA, $rB", IIC_IntSimple,
2633                       [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2634let isCodeGenOnly = 1 in
2635def ADD4TLS  : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2636                       "add $rT, $rA, $rB", IIC_IntSimple,
2637                       [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2638let isCommutable = 1 in
2639defm ADDC  : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2640                        "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2641                        [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2642                        PPC970_DGroup_Cracked;
2643
2644defm DIVW  : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2645                          "divw", "$rT, $rA, $rB", IIC_IntDivW,
2646                          [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>;
2647defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2648                          "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2649                          [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>;
2650def DIVWE : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2651                     "divwe $rT, $rA, $rB", IIC_IntDivW,
2652                     [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>,
2653                     Requires<[HasExtDiv]>;
2654let Defs = [CR0] in
2655def DIVWEo : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2656                      "divwe. $rT, $rA, $rB", IIC_IntDivW,
2657                      []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2658                      Requires<[HasExtDiv]>;
2659def DIVWEU : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2660                      "divweu $rT, $rA, $rB", IIC_IntDivW,
2661                      [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>,
2662                      Requires<[HasExtDiv]>;
2663let Defs = [CR0] in
2664def DIVWEUo : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2665                       "divweu. $rT, $rA, $rB", IIC_IntDivW,
2666                       []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2667                       Requires<[HasExtDiv]>;
2668let isCommutable = 1 in {
2669defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2670                       "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2671                       [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2672defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2673                       "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2674                       [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2675defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2676                       "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2677                       [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2678} // isCommutable
2679defm SUBF  : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2680                       "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2681                       [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2682defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2683                        "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2684                        [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2685                        PPC970_DGroup_Cracked;
2686defm NEG    : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2687                        "neg", "$rT, $rA", IIC_IntSimple,
2688                        [(set i32:$rT, (ineg i32:$rA))]>;
2689let Uses = [CARRY] in {
2690let isCommutable = 1 in
2691defm ADDE  : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2692                        "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2693                        [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2694defm ADDME  : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2695                         "addme", "$rT, $rA", IIC_IntGeneral,
2696                         [(set i32:$rT, (adde i32:$rA, -1))]>;
2697defm ADDZE  : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2698                         "addze", "$rT, $rA", IIC_IntGeneral,
2699                         [(set i32:$rT, (adde i32:$rA, 0))]>;
2700defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2701                        "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2702                        [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2703defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2704                         "subfme", "$rT, $rA", IIC_IntGeneral,
2705                         [(set i32:$rT, (sube -1, i32:$rA))]>;
2706defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2707                         "subfze", "$rT, $rA", IIC_IntGeneral,
2708                         [(set i32:$rT, (sube 0, i32:$rA))]>;
2709}
2710}
2711
2712// A-Form instructions.  Most of the instructions executed in the FPU are of
2713// this type.
2714//
2715let PPC970_Unit = 3, hasSideEffects = 0 in {  // FPU Operations.
2716let Uses = [RM] in {
2717let isCommutable = 1 in {
2718  defm FMADD : AForm_1r<63, 29,
2719                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2720                      "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2721                      [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2722  defm FMADDS : AForm_1r<59, 29,
2723                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2724                      "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2725                      [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2726  defm FMSUB : AForm_1r<63, 28,
2727                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2728                      "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2729                      [(set f64:$FRT,
2730                            (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2731  defm FMSUBS : AForm_1r<59, 28,
2732                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2733                      "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2734                      [(set f32:$FRT,
2735                            (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2736  defm FNMADD : AForm_1r<63, 31,
2737                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2738                      "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2739                      [(set f64:$FRT,
2740                            (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2741  defm FNMADDS : AForm_1r<59, 31,
2742                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2743                      "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2744                      [(set f32:$FRT,
2745                            (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2746  defm FNMSUB : AForm_1r<63, 30,
2747                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2748                      "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2749                      [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2750                                                 (fneg f64:$FRB))))]>;
2751  defm FNMSUBS : AForm_1r<59, 30,
2752                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2753                      "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2754                      [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2755                                                 (fneg f32:$FRB))))]>;
2756} // isCommutable
2757}
2758// FSEL is artificially split into 4 and 8-byte forms for the result.  To avoid
2759// having 4 of these, force the comparison to always be an 8-byte double (code
2760// should use an FMRSD if the input comparison value really wants to be a float)
2761// and 4/8 byte forms for the result and operand type..
2762let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2763defm FSELD : AForm_1r<63, 23,
2764                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2765                      "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2766                      [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2767defm FSELS : AForm_1r<63, 23,
2768                      (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2769                      "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2770                      [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2771let Uses = [RM] in {
2772  let isCommutable = 1 in {
2773  defm FADD  : AForm_2r<63, 21,
2774                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2775                        "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2776                        [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2777  defm FADDS : AForm_2r<59, 21,
2778                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2779                        "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2780                        [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2781  } // isCommutable
2782  defm FDIV  : AForm_2r<63, 18,
2783                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2784                        "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2785                        [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2786  defm FDIVS : AForm_2r<59, 18,
2787                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2788                        "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2789                        [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2790  let isCommutable = 1 in {
2791  defm FMUL  : AForm_3r<63, 25,
2792                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2793                        "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2794                        [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2795  defm FMULS : AForm_3r<59, 25,
2796                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2797                        "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2798                        [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2799  } // isCommutable
2800  defm FSUB  : AForm_2r<63, 20,
2801                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2802                        "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2803                        [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2804  defm FSUBS : AForm_2r<59, 20,
2805                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2806                        "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2807                        [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2808  }
2809}
2810
2811let hasSideEffects = 0 in {
2812let PPC970_Unit = 1 in {  // FXU Operations.
2813  let isSelect = 1 in
2814  def ISEL  : AForm_4<31, 15,
2815                     (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2816                     "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
2817                     []>;
2818}
2819
2820let PPC970_Unit = 1 in {  // FXU Operations.
2821// M-Form instructions.  rotate and mask instructions.
2822//
2823let isCommutable = 1 in {
2824// RLWIMI can be commuted if the rotate amount is zero.
2825defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2826                       (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2827                       u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2828                       IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2829                       RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2830}
2831let BaseName = "rlwinm" in {
2832def RLWINM : MForm_2<21,
2833                     (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2834                     "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2835                     []>, RecFormRel;
2836let Defs = [CR0] in
2837def RLWINMo : MForm_2<21,
2838                      (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2839                      "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2840                      []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2841}
2842defm RLWNM  : MForm_2r<23, (outs gprc:$rA),
2843                       (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2844                       "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2845                       []>;
2846}
2847} // hasSideEffects = 0
2848
2849//===----------------------------------------------------------------------===//
2850// PowerPC Instruction Patterns
2851//
2852
2853// Arbitrary immediate support.  Implement in terms of LIS/ORI.
2854def : Pat<(i32 imm:$imm),
2855          (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2856
2857// Implement the 'not' operation with the NOR instruction.
2858def i32not : OutPatFrag<(ops node:$in),
2859                        (NOR $in, $in)>;
2860def        : Pat<(not i32:$in),
2861                 (i32not $in)>;
2862
2863// ADD an arbitrary immediate.
2864def : Pat<(add i32:$in, imm:$imm),
2865          (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2866// OR an arbitrary immediate.
2867def : Pat<(or i32:$in, imm:$imm),
2868          (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2869// XOR an arbitrary immediate.
2870def : Pat<(xor i32:$in, imm:$imm),
2871          (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2872// SUBFIC
2873def : Pat<(sub imm32SExt16:$imm, i32:$in),
2874          (SUBFIC $in, imm:$imm)>;
2875
2876// SHL/SRL
2877def : Pat<(shl i32:$in, (i32 imm:$imm)),
2878          (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2879def : Pat<(srl i32:$in, (i32 imm:$imm)),
2880          (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2881
2882// ROTL
2883def : Pat<(rotl i32:$in, i32:$sh),
2884          (RLWNM $in, $sh, 0, 31)>;
2885def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2886          (RLWINM $in, imm:$imm, 0, 31)>;
2887
2888// RLWNM
2889def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2890          (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2891
2892// Calls
2893def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2894          (BL tglobaladdr:$dst)>;
2895def : Pat<(PPCcall (i32 texternalsym:$dst)),
2896          (BL texternalsym:$dst)>;
2897
2898def : Pat<(PPCtc_return (i32 tglobaladdr:$dst),  imm:$imm),
2899          (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2900
2901def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2902          (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2903
2904def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2905          (TCRETURNri CTRRC:$dst, imm:$imm)>;
2906
2907
2908
2909// Hi and Lo for Darwin Global Addresses.
2910def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2911def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2912def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2913def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2914def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2915def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2916def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2917def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2918def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2919          (ADDIS $in, tglobaltlsaddr:$g)>;
2920def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2921          (ADDI $in, tglobaltlsaddr:$g)>;
2922def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2923          (ADDIS $in, tglobaladdr:$g)>;
2924def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2925          (ADDIS $in, tconstpool:$g)>;
2926def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2927          (ADDIS $in, tjumptable:$g)>;
2928def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2929          (ADDIS $in, tblockaddress:$g)>;
2930
2931// Support for thread-local storage.
2932def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2933                [(set i32:$rD, (PPCppc32GOT))]>;
2934
2935// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2936// This uses two output registers, the first as the real output, the second as a
2937// temporary register, used internally in code generation.
2938def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2939                []>, NoEncode<"$rT">;
2940
2941def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2942                           "#LDgotTprelL32",
2943                           [(set i32:$rD,
2944                             (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2945def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2946          (ADD4TLS $in, tglobaltlsaddr:$g)>;
2947
2948def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2949                         "#ADDItlsgdL32",
2950                         [(set i32:$rD,
2951                           (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2952// LR is a true define, while the rest of the Defs are clobbers.  R3 is
2953// explicitly defined when this op is created, so not mentioned here.
2954let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2955    Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2956def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2957                          "GETtlsADDR32",
2958                          [(set i32:$rD,
2959                            (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2960// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded.  R3 and LR
2961// are true defines while the rest of the Defs are clobbers.
2962let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2963    Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2964def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD),
2965                              (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2966                              "#ADDItlsgdLADDR32",
2967                              [(set i32:$rD,
2968                                (PPCaddiTlsgdLAddr i32:$reg,
2969                                                   tglobaltlsaddr:$disp,
2970                                                   tglobaltlsaddr:$sym))]>;
2971def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2972                          "#ADDItlsldL32",
2973                          [(set i32:$rD,
2974                            (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2975// LR is a true define, while the rest of the Defs are clobbers.  R3 is
2976// explicitly defined when this op is created, so not mentioned here.
2977let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2978    Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2979def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2980                            "GETtlsldADDR32",
2981                            [(set i32:$rD,
2982                              (PPCgetTlsldAddr i32:$reg,
2983                                               tglobaltlsaddr:$sym))]>;
2984// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded.  R3 and LR
2985// are true defines while the rest of the Defs are clobbers.
2986let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2987    Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2988def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD),
2989                              (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2990                              "#ADDItlsldLADDR32",
2991                              [(set i32:$rD,
2992                                (PPCaddiTlsldLAddr i32:$reg,
2993                                                   tglobaltlsaddr:$disp,
2994                                                   tglobaltlsaddr:$sym))]>;
2995def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2996                           "#ADDIdtprelL32",
2997                           [(set i32:$rD,
2998                             (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2999def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
3000                            "#ADDISdtprelHA32",
3001                            [(set i32:$rD,
3002                              (PPCaddisDtprelHA i32:$reg,
3003                                                tglobaltlsaddr:$disp))]>;
3004
3005// Support for Position-independent code
3006def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
3007                   "#LWZtoc",
3008                   [(set i32:$rD,
3009                      (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
3010// Get Global (GOT) Base Register offset, from the word immediately preceding
3011// the function label.
3012def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
3013
3014
3015// Standard shifts.  These are represented separately from the real shifts above
3016// so that we can distinguish between shifts that allow 5-bit and 6-bit shift
3017// amounts.
3018def : Pat<(sra i32:$rS, i32:$rB),
3019          (SRAW $rS, $rB)>;
3020def : Pat<(srl i32:$rS, i32:$rB),
3021          (SRW $rS, $rB)>;
3022def : Pat<(shl i32:$rS, i32:$rB),
3023          (SLW $rS, $rB)>;
3024
3025def : Pat<(zextloadi1 iaddr:$src),
3026          (LBZ iaddr:$src)>;
3027def : Pat<(zextloadi1 xaddr:$src),
3028          (LBZX xaddr:$src)>;
3029def : Pat<(extloadi1 iaddr:$src),
3030          (LBZ iaddr:$src)>;
3031def : Pat<(extloadi1 xaddr:$src),
3032          (LBZX xaddr:$src)>;
3033def : Pat<(extloadi8 iaddr:$src),
3034          (LBZ iaddr:$src)>;
3035def : Pat<(extloadi8 xaddr:$src),
3036          (LBZX xaddr:$src)>;
3037def : Pat<(extloadi16 iaddr:$src),
3038          (LHZ iaddr:$src)>;
3039def : Pat<(extloadi16 xaddr:$src),
3040          (LHZX xaddr:$src)>;
3041def : Pat<(f64 (extloadf32 iaddr:$src)),
3042          (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
3043def : Pat<(f64 (extloadf32 xaddr:$src)),
3044          (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
3045
3046def : Pat<(f64 (fpextend f32:$src)),
3047          (COPY_TO_REGCLASS $src, F8RC)>;
3048
3049// Only seq_cst fences require the heavyweight sync (SYNC 0).
3050// All others can use the lightweight sync (SYNC 1).
3051// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
3052// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
3053// versions of Power.
3054def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
3055def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
3056def : Pat<(atomic_fence (imm),   (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
3057def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
3058
3059// Additional FNMSUB patterns: -a*c + b == -(a*c - b)
3060def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
3061          (FNMSUB $A, $C, $B)>;
3062def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
3063          (FNMSUB $A, $C, $B)>;
3064def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
3065          (FNMSUBS $A, $C, $B)>;
3066def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
3067          (FNMSUBS $A, $C, $B)>;
3068
3069// FCOPYSIGN's operand types need not agree.
3070def : Pat<(fcopysign f64:$frB, f32:$frA),
3071          (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
3072def : Pat<(fcopysign f32:$frB, f64:$frA),
3073          (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
3074
3075include "PPCInstrAltivec.td"
3076include "PPCInstrSPE.td"
3077include "PPCInstr64Bit.td"
3078include "PPCInstrVSX.td"
3079include "PPCInstrQPX.td"
3080include "PPCInstrHTM.td"
3081
3082def crnot : OutPatFrag<(ops node:$in),
3083                       (CRNOR $in, $in)>;
3084def       : Pat<(not i1:$in),
3085                (crnot $in)>;
3086
3087// Patterns for arithmetic i1 operations.
3088def : Pat<(add i1:$a, i1:$b),
3089          (CRXOR $a, $b)>;
3090def : Pat<(sub i1:$a, i1:$b),
3091          (CRXOR $a, $b)>;
3092def : Pat<(mul i1:$a, i1:$b),
3093          (CRAND $a, $b)>;
3094
3095// We're sometimes asked to materialize i1 -1, which is just 1 in this case
3096// (-1 is used to mean all bits set).
3097def : Pat<(i1 -1), (CRSET)>;
3098
3099// i1 extensions, implemented in terms of isel.
3100def : Pat<(i32 (zext i1:$in)),
3101          (SELECT_I4 $in, (LI 1), (LI 0))>;
3102def : Pat<(i32 (sext i1:$in)),
3103          (SELECT_I4 $in, (LI -1), (LI 0))>;
3104
3105def : Pat<(i64 (zext i1:$in)),
3106          (SELECT_I8 $in, (LI8 1), (LI8 0))>;
3107def : Pat<(i64 (sext i1:$in)),
3108          (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
3109
3110// FIXME: We should choose either a zext or a sext based on other constants
3111// already around.
3112def : Pat<(i32 (anyext i1:$in)),
3113          (SELECT_I4 $in, (LI 1), (LI 0))>;
3114def : Pat<(i64 (anyext i1:$in)),
3115          (SELECT_I8 $in, (LI8 1), (LI8 0))>;
3116
3117// match setcc on i1 variables.
3118// CRANDC is:
3119//   1 1 : F
3120//   1 0 : T
3121//   0 1 : F
3122//   0 0 : F
3123//
3124// LT is:
3125//  -1 -1  : F
3126//  -1  0  : T
3127//   0 -1  : F
3128//   0  0  : F
3129//
3130// ULT is:
3131//   1 1 : F
3132//   1 0 : F
3133//   0 1 : T
3134//   0 0 : F
3135def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
3136          (CRANDC $s1, $s2)>;
3137def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
3138          (CRANDC $s2, $s1)>;
3139// CRORC is:
3140//   1 1 : T
3141//   1 0 : T
3142//   0 1 : F
3143//   0 0 : T
3144//
3145// LE is:
3146//  -1 -1 : T
3147//  -1  0 : T
3148//   0 -1 : F
3149//   0  0 : T
3150//
3151// ULE is:
3152//   1 1 : T
3153//   1 0 : F
3154//   0 1 : T
3155//   0 0 : T
3156def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
3157          (CRORC $s1, $s2)>;
3158def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
3159          (CRORC $s2, $s1)>;
3160
3161def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
3162          (CREQV $s1, $s2)>;
3163
3164// GE is:
3165//  -1 -1 : T
3166//  -1  0 : F
3167//   0 -1 : T
3168//   0  0 : T
3169//
3170// UGE is:
3171//   1 1 : T
3172//   1 0 : T
3173//   0 1 : F
3174//   0 0 : T
3175def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
3176          (CRORC $s2, $s1)>;
3177def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
3178          (CRORC $s1, $s2)>;
3179
3180// GT is:
3181//  -1 -1 : F
3182//  -1  0 : F
3183//   0 -1 : T
3184//   0  0 : F
3185//
3186// UGT is:
3187//  1 1 : F
3188//  1 0 : T
3189//  0 1 : F
3190//  0 0 : F
3191def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
3192          (CRANDC $s2, $s1)>;
3193def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
3194          (CRANDC $s1, $s2)>;
3195
3196def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
3197          (CRXOR $s1, $s2)>;
3198
3199// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
3200// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3201// floating-point types.
3202
3203multiclass CRNotPat<dag pattern, dag result> {
3204  def : Pat<pattern, (crnot result)>;
3205  def : Pat<(not pattern), result>;
3206
3207  // We can also fold the crnot into an extension:
3208  def : Pat<(i32 (zext pattern)),
3209            (SELECT_I4 result, (LI 0), (LI 1))>;
3210  def : Pat<(i32 (sext pattern)),
3211            (SELECT_I4 result, (LI 0), (LI -1))>;
3212
3213  // We can also fold the crnot into an extension:
3214  def : Pat<(i64 (zext pattern)),
3215            (SELECT_I8 result, (LI8 0), (LI8 1))>;
3216  def : Pat<(i64 (sext pattern)),
3217            (SELECT_I8 result, (LI8 0), (LI8 -1))>;
3218
3219  // FIXME: We should choose either a zext or a sext based on other constants
3220  // already around.
3221  def : Pat<(i32 (anyext pattern)),
3222            (SELECT_I4 result, (LI 0), (LI 1))>;
3223
3224  def : Pat<(i64 (anyext pattern)),
3225            (SELECT_I8 result, (LI8 0), (LI8 1))>;
3226}
3227
3228// FIXME: Because of what seems like a bug in TableGen's type-inference code,
3229// we need to write imm:$imm in the output patterns below, not just $imm, or
3230// else the resulting matcher will not correctly add the immediate operand
3231// (making it a register operand instead).
3232
3233// extended SETCC.
3234multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
3235                       OutPatFrag rfrag, OutPatFrag rfrag8> {
3236  def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
3237            (rfrag $s1)>;
3238  def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
3239            (rfrag8 $s1)>;
3240  def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
3241            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
3242  def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
3243            (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
3244
3245  def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
3246            (rfrag $s1)>;
3247  def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
3248            (rfrag8 $s1)>;
3249  def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
3250            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
3251  def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
3252            (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
3253}
3254
3255// Note that we do all inversions below with i(32|64)not, instead of using
3256// (xori x, 1) because on the A2 nor has single-cycle latency while xori
3257// has 2-cycle latency.
3258
3259defm : ExtSetCCPat<SETEQ,
3260                   PatFrag<(ops node:$in, node:$cc),
3261                           (setcc $in, 0, $cc)>,
3262                   OutPatFrag<(ops node:$in),
3263                              (RLWINM (CNTLZW $in), 27, 31, 31)>,
3264                   OutPatFrag<(ops node:$in),
3265                              (RLDICL (CNTLZD $in), 58, 63)> >;
3266
3267defm : ExtSetCCPat<SETNE,
3268                   PatFrag<(ops node:$in, node:$cc),
3269                           (setcc $in, 0, $cc)>,
3270                   OutPatFrag<(ops node:$in),
3271                              (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
3272                   OutPatFrag<(ops node:$in),
3273                              (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
3274
3275defm : ExtSetCCPat<SETLT,
3276                   PatFrag<(ops node:$in, node:$cc),
3277                           (setcc $in, 0, $cc)>,
3278                   OutPatFrag<(ops node:$in),
3279                              (RLWINM $in, 1, 31, 31)>,
3280                   OutPatFrag<(ops node:$in),
3281                              (RLDICL $in, 1, 63)> >;
3282
3283defm : ExtSetCCPat<SETGE,
3284                   PatFrag<(ops node:$in, node:$cc),
3285                           (setcc $in, 0, $cc)>,
3286                   OutPatFrag<(ops node:$in),
3287                              (RLWINM (i32not $in), 1, 31, 31)>,
3288                   OutPatFrag<(ops node:$in),
3289                              (RLDICL (i64not $in), 1, 63)> >;
3290
3291defm : ExtSetCCPat<SETGT,
3292                   PatFrag<(ops node:$in, node:$cc),
3293                           (setcc $in, 0, $cc)>,
3294                   OutPatFrag<(ops node:$in),
3295                              (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
3296                   OutPatFrag<(ops node:$in),
3297                              (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
3298
3299defm : ExtSetCCPat<SETLE,
3300                   PatFrag<(ops node:$in, node:$cc),
3301                           (setcc $in, 0, $cc)>,
3302                   OutPatFrag<(ops node:$in),
3303                              (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
3304                   OutPatFrag<(ops node:$in),
3305                              (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
3306
3307defm : ExtSetCCPat<SETLT,
3308                   PatFrag<(ops node:$in, node:$cc),
3309                           (setcc $in, -1, $cc)>,
3310                   OutPatFrag<(ops node:$in),
3311                              (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
3312                   OutPatFrag<(ops node:$in),
3313                              (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3314
3315defm : ExtSetCCPat<SETGE,
3316                   PatFrag<(ops node:$in, node:$cc),
3317                           (setcc $in, -1, $cc)>,
3318                   OutPatFrag<(ops node:$in),
3319                              (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
3320                   OutPatFrag<(ops node:$in),
3321                              (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3322
3323defm : ExtSetCCPat<SETGT,
3324                   PatFrag<(ops node:$in, node:$cc),
3325                           (setcc $in, -1, $cc)>,
3326                   OutPatFrag<(ops node:$in),
3327                              (RLWINM (i32not $in), 1, 31, 31)>,
3328                   OutPatFrag<(ops node:$in),
3329                              (RLDICL (i64not $in), 1, 63)> >;
3330
3331defm : ExtSetCCPat<SETLE,
3332                   PatFrag<(ops node:$in, node:$cc),
3333                           (setcc $in, -1, $cc)>,
3334                   OutPatFrag<(ops node:$in),
3335                              (RLWINM $in, 1, 31, 31)>,
3336                   OutPatFrag<(ops node:$in),
3337                              (RLDICL $in, 1, 63)> >;
3338
3339// An extended SETCC with shift amount.
3340multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag,
3341                            OutPatFrag rfrag, OutPatFrag rfrag8> {
3342  def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
3343            (rfrag $s1, $sa)>;
3344  def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
3345            (rfrag8 $s1, $sa)>;
3346  def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
3347            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>;
3348  def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
3349            (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>;
3350
3351  def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
3352            (rfrag $s1, $sa)>;
3353  def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
3354            (rfrag8 $s1, $sa)>;
3355  def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
3356            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>;
3357  def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
3358            (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>;
3359}
3360
3361defm : ExtSetCCShiftPat<SETNE,
3362                        PatFrag<(ops node:$in, node:$sa, node:$cc),
3363                                (setcc (and $in, (shl 1, $sa)), 0, $cc)>,
3364                        OutPatFrag<(ops node:$in, node:$sa),
3365                                   (RLWNM $in, (SUBFIC $sa, 32), 31, 31)>,
3366                        OutPatFrag<(ops node:$in, node:$sa),
3367                                   (RLDCL $in, (SUBFIC $sa, 64), 63)> >;
3368
3369defm : ExtSetCCShiftPat<SETEQ,
3370                        PatFrag<(ops node:$in, node:$sa, node:$cc),
3371                                (setcc (and $in, (shl 1, $sa)), 0, $cc)>,
3372                        OutPatFrag<(ops node:$in, node:$sa),
3373                                   (RLWNM (i32not $in),
3374                                          (SUBFIC $sa, 32), 31, 31)>,
3375                        OutPatFrag<(ops node:$in, node:$sa),
3376                                   (RLDCL (i64not $in),
3377                                          (SUBFIC $sa, 64), 63)> >;
3378
3379// SETCC for i32.
3380def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
3381          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3382def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
3383          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3384def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
3385          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3386def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
3387          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3388def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
3389          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3390def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
3391          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3392
3393// For non-equality comparisons, the default code would materialize the
3394// constant, then compare against it, like this:
3395//   lis r2, 4660
3396//   ori r2, r2, 22136
3397//   cmpw cr0, r3, r2
3398//   beq cr0,L6
3399// Since we are just comparing for equality, we can emit this instead:
3400//   xoris r0,r3,0x1234
3401//   cmplwi cr0,r0,0x5678
3402//   beq cr0,L6
3403
3404def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
3405          (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3406                                  (LO16 imm:$imm)), sub_eq)>;
3407
3408defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
3409                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3410defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
3411                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3412defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
3413                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3414defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
3415                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3416defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
3417                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3418defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
3419                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3420
3421defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
3422                (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3423                                        (LO16 imm:$imm)), sub_eq)>;
3424
3425def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
3426          (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3427def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
3428          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3429def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
3430          (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3431def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
3432          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3433def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
3434          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3435
3436defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
3437                (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3438defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
3439                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3440defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
3441                (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3442defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
3443                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3444defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
3445                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3446
3447// SETCC for i64.
3448def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
3449          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3450def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
3451          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3452def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
3453          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3454def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
3455          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3456def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
3457          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3458def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
3459          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3460
3461// For non-equality comparisons, the default code would materialize the
3462// constant, then compare against it, like this:
3463//   lis r2, 4660
3464//   ori r2, r2, 22136
3465//   cmpd cr0, r3, r2
3466//   beq cr0,L6
3467// Since we are just comparing for equality, we can emit this instead:
3468//   xoris r0,r3,0x1234
3469//   cmpldi cr0,r0,0x5678
3470//   beq cr0,L6
3471
3472def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
3473          (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3474                                  (LO16 imm:$imm)), sub_eq)>;
3475
3476defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3477                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3478defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
3479                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3480defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
3481                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3482defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
3483                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3484defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
3485                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3486defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
3487                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3488
3489defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
3490                (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3491                                        (LO16 imm:$imm)), sub_eq)>;
3492
3493def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
3494          (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3495def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3496          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3497def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3498          (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3499def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
3500          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3501def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
3502          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3503
3504defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3505                (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3506defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
3507                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3508defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
3509                (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3510defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
3511                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3512defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
3513                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3514
3515// SETCC for f32.
3516def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
3517          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3518def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
3519          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3520def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
3521          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3522def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
3523          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3524def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
3525          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3526def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
3527          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3528def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
3529          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3530
3531defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3532                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3533defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
3534                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3535defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
3536                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3537defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
3538                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3539defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
3540                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3541defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
3542                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3543defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
3544                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3545
3546// SETCC for f64.
3547def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
3548          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3549def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
3550          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3551def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
3552          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3553def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
3554          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3555def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
3556          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3557def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
3558          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3559def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
3560          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3561
3562defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3563                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3564defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
3565                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3566defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
3567                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3568defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
3569                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3570defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
3571                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3572defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
3573                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3574defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
3575                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3576
3577// match select on i1 variables:
3578def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
3579          (CROR (CRAND        $cond , $tval),
3580                (CRAND (crnot $cond), $fval))>;
3581
3582// match selectcc on i1 variables:
3583//   select (lhs == rhs), tval, fval is:
3584//   ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
3585def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
3586           (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3587                 (CRAND (CRORC  $rhs, $lhs), $fval))>;
3588def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)),
3589           (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3590                 (CRAND (CRORC  $lhs, $rhs), $fval))>;
3591def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
3592           (CROR (CRAND (CRORC  $lhs, $rhs), $tval),
3593                 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3594def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)),
3595           (CROR (CRAND (CRORC  $rhs, $lhs), $tval),
3596                 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3597def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
3598           (CROR (CRAND (CREQV $lhs, $rhs), $tval),
3599                 (CRAND (CRXOR $lhs, $rhs), $fval))>;
3600def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
3601           (CROR (CRAND (CRORC  $rhs, $lhs), $tval),
3602                 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3603def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)),
3604           (CROR (CRAND (CRORC  $lhs, $rhs), $tval),
3605                 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3606def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
3607           (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3608                 (CRAND (CRORC  $lhs, $rhs), $fval))>;
3609def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)),
3610           (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3611                 (CRAND (CRORC  $rhs, $lhs), $fval))>;
3612def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
3613           (CROR (CRAND (CREQV $lhs, $rhs), $fval),
3614                 (CRAND (CRXOR $lhs, $rhs), $tval))>;
3615
3616// match selectcc on i1 variables with non-i1 output.
3617def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3618          (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3619def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)),
3620          (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3621def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3622          (SELECT_I4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3623def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)),
3624          (SELECT_I4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3625def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3626          (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3627def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3628          (SELECT_I4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3629def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)),
3630          (SELECT_I4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3631def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3632          (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3633def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)),
3634          (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3635def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3636          (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3637
3638def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3639          (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3640def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)),
3641          (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3642def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3643          (SELECT_I8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3644def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)),
3645          (SELECT_I8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3646def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3647          (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3648def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3649          (SELECT_I8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3650def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)),
3651          (SELECT_I8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3652def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3653          (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3654def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)),
3655          (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3656def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3657          (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3658
3659def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3660          (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3661def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
3662          (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3663def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3664          (SELECT_F4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3665def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),
3666          (SELECT_F4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3667def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3668          (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3669def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3670          (SELECT_F4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3671def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
3672          (SELECT_F4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3673def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3674          (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3675def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
3676          (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3677def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3678          (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3679
3680def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3681          (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3682def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
3683          (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3684def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3685          (SELECT_F8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3686def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)),
3687          (SELECT_F8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3688def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3689          (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3690def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3691          (SELECT_F8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3692def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
3693          (SELECT_F8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3694def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3695          (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3696def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
3697          (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3698def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3699          (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3700
3701def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3702          (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3703def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)),
3704          (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3705def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3706          (SELECT_VRRC (CRORC  $lhs, $rhs), $tval, $fval)>;
3707def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)),
3708          (SELECT_VRRC (CRORC  $rhs, $lhs), $tval, $fval)>;
3709def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3710          (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3711def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3712          (SELECT_VRRC (CRORC  $rhs, $lhs), $tval, $fval)>;
3713def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)),
3714          (SELECT_VRRC (CRORC  $lhs, $rhs), $tval, $fval)>;
3715def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3716          (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3717def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)),
3718          (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3719def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3720          (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3721
3722let usesCustomInserter = 1 in {
3723def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3724                             "#ANDIo_1_EQ_BIT",
3725                             [(set i1:$dst, (trunc (not i32:$in)))]>;
3726def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3727                             "#ANDIo_1_GT_BIT",
3728                             [(set i1:$dst, (trunc i32:$in))]>;
3729
3730def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3731                              "#ANDIo_1_EQ_BIT8",
3732                              [(set i1:$dst, (trunc (not i64:$in)))]>;
3733def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3734                              "#ANDIo_1_GT_BIT8",
3735                              [(set i1:$dst, (trunc i64:$in))]>;
3736}
3737
3738def : Pat<(i1 (not (trunc i32:$in))),
3739           (ANDIo_1_EQ_BIT $in)>;
3740def : Pat<(i1 (not (trunc i64:$in))),
3741           (ANDIo_1_EQ_BIT8 $in)>;
3742
3743//===----------------------------------------------------------------------===//
3744// PowerPC Instructions used for assembler/disassembler only
3745//
3746
3747// FIXME: For B=0 or B > 8, the registers following RT are used.
3748// WARNING: Do not add patterns for this instruction without fixing this.
3749def LSWI  : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3750                            "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3751
3752// FIXME: For B=0 or B > 8, the registers following RT are used.
3753// WARNING: Do not add patterns for this instruction without fixing this.
3754def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3755                            "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3756
3757def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3758                         "isync", IIC_SprISYNC, []>;
3759
3760def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3761                    "icbi $src", IIC_LdStICBI, []>;
3762
3763// We used to have EIEIO as value but E[0-9A-Z] is a reserved name
3764def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3765                           "eieio", IIC_LdStLoad, []>;
3766
3767def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3768                         "wait $L", IIC_LdStLoad, []>;
3769
3770def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3771                         "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3772
3773def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3774            "mtsr $SR, $RS", IIC_SprMTSR>;
3775
3776def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3777            "mfsr $RS, $SR", IIC_SprMFSR>;
3778
3779def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3780            "mtsrin $RS, $RB", IIC_SprMTSR>;
3781
3782def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3783            "mfsrin $RS, $RB", IIC_SprMFSR>;
3784
3785def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3786                    "mtmsr $RS, $L", IIC_SprMTMSR>;
3787
3788def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3789                    "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3790  let L = 0;
3791}
3792
3793def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3794              Requires<[IsBookE]> {
3795  bits<1> E;
3796
3797  let Inst{16} = E;
3798  let Inst{21-30} = 163;
3799}
3800
3801def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3802               "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3803def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3804               "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3805
3806def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3807def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3808def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3809def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3810
3811def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3812                  "mfmsr $RT", IIC_SprMFMSR, []>;
3813
3814def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3815                    "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3816
3817def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
3818                     "mcrfs $BF, $BFA", IIC_BrMCR>;
3819
3820def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3821                      "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
3822
3823def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3824                       "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
3825
3826def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
3827def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
3828
3829def MTFSF : XFLForm_1<63, 711, (outs),
3830                      (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3831                      "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
3832def MTFSFo : XFLForm_1<63, 711, (outs),
3833                       (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3834                       "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
3835
3836def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3837def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3838
3839def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3840                        "slbie $RB", IIC_SprSLBIE, []>;
3841
3842def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3843                    "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3844
3845def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3846                       "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3847
3848def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB),
3849                       "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>;
3850
3851def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3852
3853def TLBIA : XForm_0<31, 370, (outs), (ins),
3854                        "tlbia", IIC_SprTLBIA, []>;
3855
3856def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3857                        "tlbsync", IIC_SprTLBSYNC, []>;
3858
3859def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3860                          "tlbiel $RB", IIC_SprTLBIEL, []>;
3861
3862def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3863                          "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3864def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3865                          "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3866
3867def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3868                          "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3869
3870def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3871                IIC_LdStLoad>, Requires<[IsBookE]>;
3872
3873def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3874                IIC_LdStLoad>, Requires<[IsBookE]>;
3875
3876def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3877                           "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3878
3879def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3880                           "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3881
3882def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3883               "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3884
3885def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3886               "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3887
3888def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3889                             "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3890                             Requires<[IsPPC4xx]>;
3891def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3892                              (ins gprc:$RST, gprc:$A, gprc:$B),
3893                              "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3894                              Requires<[IsPPC4xx]>, isDOT;
3895
3896def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3897
3898def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3899                  Requires<[IsBookE]>;
3900def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3901                   Requires<[IsBookE]>;
3902
3903def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3904                   Requires<[IsE500]>;
3905def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3906                    Requires<[IsE500]>;
3907
3908def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3909                      "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3910def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3911                      "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3912
3913def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>;
3914def NAP   : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>;
3915
3916def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
3917
3918def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3919                             "lbzcix $RST, $A, $B", IIC_LdStLoad, []>;
3920def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3921                             "lhzcix $RST, $A, $B", IIC_LdStLoad, []>;
3922def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3923                             "lwzcix $RST, $A, $B", IIC_LdStLoad, []>;
3924def LDCIX :  XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3925                             "ldcix $RST, $A, $B", IIC_LdStLoad, []>;
3926
3927def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3928                             "stbcix $RST, $A, $B", IIC_LdStLoad, []>;
3929def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3930                             "sthcix $RST, $A, $B", IIC_LdStLoad, []>;
3931def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3932                             "stwcix $RST, $A, $B", IIC_LdStLoad, []>;
3933def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3934                             "stdcix $RST, $A, $B", IIC_LdStLoad, []>;
3935
3936//===----------------------------------------------------------------------===//
3937// PowerPC Assembler Instruction Aliases
3938//
3939
3940// Pseudo-instructions for alternate assembly syntax (never used by codegen).
3941// These are aliases that require C++ handling to convert to the target
3942// instruction, while InstAliases can be handled directly by tblgen.
3943class PPCAsmPseudo<string asm, dag iops>
3944  : Instruction {
3945  let Namespace = "PPC";
3946  bit PPC64 = 0;  // Default value, override with isPPC64
3947
3948  let OutOperandList = (outs);
3949  let InOperandList = iops;
3950  let Pattern = [];
3951  let AsmString = asm;
3952  let isAsmParserOnly = 1;
3953  let isPseudo = 1;
3954  let hasNoSchedulingInfo = 1;
3955}
3956
3957def : InstAlias<"sc", (SC 0)>;
3958
3959def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
3960def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>;
3961def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
3962def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
3963
3964def : InstAlias<"wait", (WAIT 0)>;
3965def : InstAlias<"waitrsv", (WAIT 1)>;
3966def : InstAlias<"waitimpl", (WAIT 2)>;
3967
3968def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3969
3970def DCBTx   : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>;
3971def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>;
3972
3973def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3974def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3975def DCBTT  : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>;
3976
3977def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3978def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3979def DCBTSTT  : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>;
3980
3981def DCBFx  : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>;
3982def DCBFL  : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>;
3983def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>;
3984
3985def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3986def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3987def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3988def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3989
3990def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3991def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3992
3993def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3994def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3995
3996def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3997def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3998
3999def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
4000def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
4001
4002def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
4003def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
4004
4005def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
4006def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
4007
4008def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
4009def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
4010
4011def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
4012def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
4013
4014def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
4015def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
4016
4017def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4018def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
4019
4020def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4021def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
4022
4023def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
4024def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
4025
4026def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
4027def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
4028
4029def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
4030def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
4031
4032def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
4033def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
4034def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
4035
4036def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
4037def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
4038
4039def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
4040def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4041def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
4042def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4043
4044def : InstAlias<"xnop", (XORI R0, R0, 0)>;
4045
4046def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
4047def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
4048
4049def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
4050def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
4051
4052def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
4053
4054foreach BATR = 0-3 in {
4055    def : InstAlias<"mtdbatu "#BATR#", $Rx",
4056                    (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
4057                    Requires<[IsPPC6xx]>;
4058    def : InstAlias<"mfdbatu $Rx, "#BATR,
4059                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
4060                    Requires<[IsPPC6xx]>;
4061    def : InstAlias<"mtdbatl "#BATR#", $Rx",
4062                    (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
4063                    Requires<[IsPPC6xx]>;
4064    def : InstAlias<"mfdbatl $Rx, "#BATR,
4065                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
4066                    Requires<[IsPPC6xx]>;
4067    def : InstAlias<"mtibatu "#BATR#", $Rx",
4068                    (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
4069                    Requires<[IsPPC6xx]>;
4070    def : InstAlias<"mfibatu $Rx, "#BATR,
4071                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
4072                    Requires<[IsPPC6xx]>;
4073    def : InstAlias<"mtibatl "#BATR#", $Rx",
4074                    (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
4075                    Requires<[IsPPC6xx]>;
4076    def : InstAlias<"mfibatl $Rx, "#BATR,
4077                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
4078                    Requires<[IsPPC6xx]>;
4079}
4080
4081foreach BR = 0-7 in {
4082    def : InstAlias<"mfbr"#BR#" $Rx",
4083                    (MFDCR gprc:$Rx, !add(BR, 0x80))>,
4084                    Requires<[IsPPC4xx]>;
4085    def : InstAlias<"mtbr"#BR#" $Rx",
4086                    (MTDCR gprc:$Rx, !add(BR, 0x80))>,
4087                    Requires<[IsPPC4xx]>;
4088}
4089
4090def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4091def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
4092
4093def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4094def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
4095
4096def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4097def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
4098
4099def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4100def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
4101
4102def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
4103def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
4104
4105def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4106def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
4107
4108def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
4109
4110def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
4111                        (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
4112def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
4113                         (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
4114def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
4115                         (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
4116def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
4117                          (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
4118
4119def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
4120def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
4121def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
4122def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
4123
4124def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
4125def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
4126
4127def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
4128def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
4129
4130foreach SPRG = 0-3 in {
4131  def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
4132  def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
4133  def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
4134  def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
4135}
4136foreach SPRG = 4-7 in {
4137  def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
4138                  Requires<[IsBookE]>;
4139  def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
4140                  Requires<[IsBookE]>;
4141  def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
4142                  Requires<[IsBookE]>;
4143  def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
4144                  Requires<[IsBookE]>;
4145}
4146
4147def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
4148
4149def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
4150def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
4151
4152def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
4153
4154def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
4155def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
4156
4157def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
4158def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
4159def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
4160def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
4161
4162def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
4163
4164def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
4165                Requires<[IsPPC4xx]>;
4166def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
4167                Requires<[IsPPC4xx]>;
4168def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
4169                Requires<[IsPPC4xx]>;
4170def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
4171                Requires<[IsPPC4xx]>;
4172
4173def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
4174                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4175def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
4176                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4177def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
4178                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4179def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
4180                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4181def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
4182                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4183def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
4184                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4185def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
4186                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4187def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
4188                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4189def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
4190                          (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4191def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
4192                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4193def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
4194                        (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4195def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
4196                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4197def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
4198                        (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4199def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
4200                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4201def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
4202                          (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4203def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
4204                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4205def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
4206                            (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
4207def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
4208                             (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
4209
4210def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
4211def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
4212def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
4213def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
4214def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
4215def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
4216
4217def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
4218def : InstAlias<"cntlzw. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>;
4219// The POWER variant
4220def : MnemonicAlias<"cntlz",  "cntlzw">;
4221def : MnemonicAlias<"cntlz.", "cntlzw.">;
4222
4223def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
4224                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4225def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
4226                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4227def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
4228                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4229def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
4230                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4231def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
4232                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4233def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
4234                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4235def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
4236                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4237def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
4238                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4239def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
4240                        (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4241def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
4242                         (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4243def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
4244                        (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4245def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
4246                         (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4247def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
4248                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4249def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
4250                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4251def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
4252                            (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
4253def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
4254                             (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
4255def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>;
4256
4257def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
4258def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
4259def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
4260def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
4261def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
4262def : InstAlias<"clrldi $rA, $rS, $n",
4263                (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)>;
4264def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
4265def : InstAlias<"lnia $RT", (ADDPCIS g8rc:$RT, 0)>;
4266
4267def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b",
4268                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4269def RLWINMobm : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b",
4270                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4271def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b",
4272                           (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4273def RLWIMIobm : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b",
4274                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4275def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b",
4276                          (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4277def RLWNMobm : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b",
4278                           (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4279
4280// These generic branch instruction forms are used for the assembler parser only.
4281// Defs and Uses are conservative, since we don't know the BO value.
4282let PPC970_Unit = 7 in {
4283  let Defs = [CTR], Uses = [CTR, RM] in {
4284    def gBC : BForm_3<16, 0, 0, (outs),
4285                      (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
4286                      "bc $bo, $bi, $dst">;
4287    def gBCA : BForm_3<16, 1, 0, (outs),
4288                       (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
4289                       "bca $bo, $bi, $dst">;
4290    let isAsmParserOnly = 1 in {
4291      def gBCat : BForm_3_at<16, 0, 0, (outs),
4292                             (ins u5imm:$bo, atimm:$at, crbitrc:$bi,
4293                                  condbrtarget:$dst),
4294                                  "bc$at $bo, $bi, $dst">;
4295      def gBCAat : BForm_3_at<16, 1, 0, (outs),
4296                              (ins u5imm:$bo, atimm:$at, crbitrc:$bi,
4297                                   abscondbrtarget:$dst),
4298                                   "bca$at $bo, $bi, $dst">;
4299    } // isAsmParserOnly = 1
4300  }
4301  let Defs = [LR, CTR], Uses = [CTR, RM] in {
4302    def gBCL : BForm_3<16, 0, 1, (outs),
4303                       (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
4304                       "bcl $bo, $bi, $dst">;
4305    def gBCLA : BForm_3<16, 1, 1, (outs),
4306                        (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
4307                        "bcla $bo, $bi, $dst">;
4308    let isAsmParserOnly = 1 in {
4309      def gBCLat : BForm_3_at<16, 0, 1, (outs),
4310                         (ins u5imm:$bo, atimm:$at, crbitrc:$bi,
4311                              condbrtarget:$dst),
4312                              "bcl$at $bo, $bi, $dst">;
4313      def gBCLAat : BForm_3_at<16, 1, 1, (outs),
4314                          (ins u5imm:$bo, atimm:$at, crbitrc:$bi,
4315                               abscondbrtarget:$dst),
4316                               "bcla$at $bo, $bi, $dst">;
4317    } // // isAsmParserOnly = 1
4318  }
4319  let Defs = [CTR], Uses = [CTR, LR, RM] in
4320    def gBCLR : XLForm_2<19, 16, 0, (outs),
4321                         (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4322                         "bclr $bo, $bi, $bh", IIC_BrB, []>;
4323  let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
4324    def gBCLRL : XLForm_2<19, 16, 1, (outs),
4325                          (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4326                          "bclrl $bo, $bi, $bh", IIC_BrB, []>;
4327  let Defs = [CTR], Uses = [CTR, LR, RM] in
4328    def gBCCTR : XLForm_2<19, 528, 0, (outs),
4329                          (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4330                          "bcctr $bo, $bi, $bh", IIC_BrB, []>;
4331  let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
4332    def gBCCTRL : XLForm_2<19, 528, 1, (outs),
4333                           (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4334                           "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
4335}
4336
4337multiclass BranchSimpleMnemonicAT<string pm, int at> {
4338  def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi,
4339                                                    condbrtarget:$dst)>;
4340  def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi,
4341                                                      condbrtarget:$dst)>;
4342  def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi,
4343                                                      condbrtarget:$dst)>;
4344  def : InstAlias<"bcla"#pm#" $bo, $bi, $dst", (gBCLAat u5imm:$bo, at, crbitrc:$bi,
4345                                                        condbrtarget:$dst)>;
4346}
4347defm : BranchSimpleMnemonicAT<"+", 3>;
4348defm : BranchSimpleMnemonicAT<"-", 2>;
4349
4350def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
4351def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
4352def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
4353def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
4354
4355multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
4356  def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
4357  def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
4358  def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
4359  def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
4360  def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
4361  def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
4362}
4363multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
4364  : BranchSimpleMnemonic1<name, pm, bo> {
4365  def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
4366  def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
4367}
4368defm : BranchSimpleMnemonic2<"t", "", 12>;
4369defm : BranchSimpleMnemonic2<"f", "", 4>;
4370defm : BranchSimpleMnemonic2<"t", "-", 14>;
4371defm : BranchSimpleMnemonic2<"f", "-", 6>;
4372defm : BranchSimpleMnemonic2<"t", "+", 15>;
4373defm : BranchSimpleMnemonic2<"f", "+", 7>;
4374defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
4375defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
4376defm : BranchSimpleMnemonic1<"dzt", "", 10>;
4377defm : BranchSimpleMnemonic1<"dzf", "", 2>;
4378
4379multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
4380  def : InstAlias<"b"#name#pm#" $cc, $dst",
4381                  (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
4382  def : InstAlias<"b"#name#pm#" $dst",
4383                  (BCC bibo, CR0, condbrtarget:$dst)>;
4384
4385  def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
4386                  (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
4387  def : InstAlias<"b"#name#"a"#pm#" $dst",
4388                  (BCCA bibo, CR0, abscondbrtarget:$dst)>;
4389
4390  def : InstAlias<"b"#name#"lr"#pm#" $cc",
4391                  (BCCLR bibo, crrc:$cc)>;
4392  def : InstAlias<"b"#name#"lr"#pm,
4393                  (BCCLR bibo, CR0)>;
4394
4395  def : InstAlias<"b"#name#"ctr"#pm#" $cc",
4396                  (BCCCTR bibo, crrc:$cc)>;
4397  def : InstAlias<"b"#name#"ctr"#pm,
4398                  (BCCCTR bibo, CR0)>;
4399
4400  def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
4401                  (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
4402  def : InstAlias<"b"#name#"l"#pm#" $dst",
4403                  (BCCL bibo, CR0, condbrtarget:$dst)>;
4404
4405  def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
4406                  (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
4407  def : InstAlias<"b"#name#"la"#pm#" $dst",
4408                  (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
4409
4410  def : InstAlias<"b"#name#"lrl"#pm#" $cc",
4411                  (BCCLRL bibo, crrc:$cc)>;
4412  def : InstAlias<"b"#name#"lrl"#pm,
4413                  (BCCLRL bibo, CR0)>;
4414
4415  def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
4416                  (BCCCTRL bibo, crrc:$cc)>;
4417  def : InstAlias<"b"#name#"ctrl"#pm,
4418                  (BCCCTRL bibo, CR0)>;
4419}
4420multiclass BranchExtendedMnemonic<string name, int bibo> {
4421  defm : BranchExtendedMnemonicPM<name, "", bibo>;
4422  defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
4423  defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
4424}
4425defm : BranchExtendedMnemonic<"lt", 12>;
4426defm : BranchExtendedMnemonic<"gt", 44>;
4427defm : BranchExtendedMnemonic<"eq", 76>;
4428defm : BranchExtendedMnemonic<"un", 108>;
4429defm : BranchExtendedMnemonic<"so", 108>;
4430defm : BranchExtendedMnemonic<"ge", 4>;
4431defm : BranchExtendedMnemonic<"nl", 4>;
4432defm : BranchExtendedMnemonic<"le", 36>;
4433defm : BranchExtendedMnemonic<"ng", 36>;
4434defm : BranchExtendedMnemonic<"ne", 68>;
4435defm : BranchExtendedMnemonic<"nu", 100>;
4436defm : BranchExtendedMnemonic<"ns", 100>;
4437
4438def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
4439def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
4440def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
4441def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
4442def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
4443def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
4444def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
4445def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
4446
4447def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
4448def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
4449def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
4450def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
4451def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
4452def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
4453def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
4454def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
4455
4456multiclass TrapExtendedMnemonic<string name, int to> {
4457  def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
4458  def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
4459  def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
4460  def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
4461}
4462defm : TrapExtendedMnemonic<"lt", 16>;
4463defm : TrapExtendedMnemonic<"le", 20>;
4464defm : TrapExtendedMnemonic<"eq", 4>;
4465defm : TrapExtendedMnemonic<"ge", 12>;
4466defm : TrapExtendedMnemonic<"gt", 8>;
4467defm : TrapExtendedMnemonic<"nl", 12>;
4468defm : TrapExtendedMnemonic<"ne", 24>;
4469defm : TrapExtendedMnemonic<"ng", 20>;
4470defm : TrapExtendedMnemonic<"llt", 2>;
4471defm : TrapExtendedMnemonic<"lle", 6>;
4472defm : TrapExtendedMnemonic<"lge", 5>;
4473defm : TrapExtendedMnemonic<"lgt", 1>;
4474defm : TrapExtendedMnemonic<"lnl", 5>;
4475defm : TrapExtendedMnemonic<"lng", 6>;
4476defm : TrapExtendedMnemonic<"u", 31>;
4477
4478// Atomic loads
4479def : Pat<(atomic_load_8  iaddr:$src), (LBZ  memri:$src)>;
4480def : Pat<(atomic_load_16 iaddr:$src), (LHZ  memri:$src)>;
4481def : Pat<(atomic_load_32 iaddr:$src), (LWZ  memri:$src)>;
4482def : Pat<(atomic_load_8  xaddr:$src), (LBZX memrr:$src)>;
4483def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
4484def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
4485
4486// Atomic stores
4487def : Pat<(atomic_store_8  iaddr:$ptr, i32:$val), (STB  gprc:$val, memri:$ptr)>;
4488def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH  gprc:$val, memri:$ptr)>;
4489def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW  gprc:$val, memri:$ptr)>;
4490def : Pat<(atomic_store_8  xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
4491def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
4492def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;
4493
4494let Predicates = [IsISA3_0] in {
4495
4496// Copy-Paste Facility
4497// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to
4498// PASTE for naming consistency.
4499let mayLoad = 1 in
4500def CP_COPY   : X_L1_RA5_RB5<31, 774, "copy"  , gprc, IIC_LdStCOPY, []>;
4501
4502let mayStore = 1 in
4503def CP_PASTE  : X_L1_RA5_RB5<31, 902, "paste" , gprc, IIC_LdStPASTE, []>;
4504
4505let mayStore = 1, Defs = [CR0] in
4506def CP_PASTEo : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isDOT;
4507
4508def CP_COPYx  : PPCAsmPseudo<"copy $rA, $rB" , (ins gprc:$rA, gprc:$rB)>;
4509def CP_PASTEx : PPCAsmPseudo<"paste $rA, $rB", (ins gprc:$rA, gprc:$rB)>;
4510def CP_COPY_FIRST : PPCAsmPseudo<"copy_first $rA, $rB",
4511                                  (ins gprc:$rA, gprc:$rB)>;
4512def CP_PASTE_LAST : PPCAsmPseudo<"paste_last $rA, $rB",
4513                                  (ins gprc:$rA, gprc:$rB)>;
4514def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cp_abort", IIC_SprABORT, []>;
4515
4516// Message Synchronize
4517def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>;
4518
4519// Power-Saving Mode Instruction:
4520def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>;
4521
4522} // IsISA3_0
4523
4524// Fast 32-bit reverse bits algorithm:
4525// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit):
4526// n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xAAAAAAAA);
4527// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit):
4528// n = ((n >> 2) & 0x33333333) | ((n << 2) & 0xCCCCCCCC);
4529// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit):
4530// n = ((n >> 4) & 0x0F0F0F0F) | ((n << 4) & 0xF0F0F0F0);
4531// Step 4: byte reverse (Suppose n = [B1,B2,B3,B4]):
4532// Step 4.1: Put B4,B2 in the right position (rotate left 3 bytes):
4533// n' = (n rotl 24);  After which n' = [B4, B1, B2, B3]
4534// Step 4.2: Insert B3 to the right position:
4535// n' = rlwimi n', n, 8, 8, 15;  After which n' = [B4, B3, B2, B3]
4536// Step 4.3: Insert B1 to the right position:
4537// n' = rlwimi n', n, 8, 24, 31;  After which n' = [B4, B3, B2, B1]
4538def MaskValues {
4539  dag Lo1 = (ORI (LIS 0x5555), 0x5555);
4540  dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA);
4541  dag Lo2 = (ORI (LIS 0x3333), 0x3333);
4542  dag Hi2 = (ORI (LIS 0xCCCC), 0xCCCC);
4543  dag Lo4 = (ORI (LIS 0x0F0F), 0x0F0F);
4544  dag Hi4 = (ORI (LIS 0xF0F0), 0xF0F0);
4545}
4546
4547def Shift1 {
4548  dag Right = (RLWINM $A, 31, 1, 31);
4549  dag Left = (RLWINM $A, 1, 0, 30);
4550}
4551
4552def Swap1 {
4553  dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1),
4554   (AND Shift1.Left, MaskValues.Hi1));
4555}
4556
4557def Shift2 {
4558  dag Right = (RLWINM Swap1.Bit, 30, 2, 31);
4559  dag Left = (RLWINM Swap1.Bit, 2, 0, 29);
4560}
4561
4562def Swap2 {
4563  dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2),
4564                 (AND Shift2.Left, MaskValues.Hi2));
4565}
4566
4567def Shift4 {
4568  dag Right = (RLWINM Swap2.Bits, 28, 4, 31);
4569  dag Left = (RLWINM Swap2.Bits, 4, 0, 27);
4570}
4571
4572def Swap4 {
4573  dag Bits = (OR (AND Shift4.Right, MaskValues.Lo4),
4574                 (AND Shift4.Left, MaskValues.Hi4));
4575}
4576
4577def Rotate {
4578  dag Left3Bytes = (RLWINM Swap4.Bits, 24, 0, 31);
4579}
4580
4581def RotateInsertByte3 {
4582  dag Left = (RLWIMI Rotate.Left3Bytes, Swap4.Bits, 8, 8, 15);
4583}
4584
4585def RotateInsertByte1 {
4586  dag Left = (RLWIMI RotateInsertByte3.Left, Swap4.Bits, 8, 24, 31);
4587}
4588
4589def : Pat<(i32 (bitreverse i32:$A)),
4590  (RLDICL_32 RotateInsertByte1.Left, 0, 32)>;
4591
4592// Fast 64-bit reverse bits algorithm:
4593// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit):
4594// n = ((n >> 1) & 0x5555555555555555) | ((n << 1) & 0xAAAAAAAAAAAAAAAA);
4595// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit):
4596// n = ((n >> 2) & 0x3333333333333333) | ((n << 2) & 0xCCCCCCCCCCCCCCCC);
4597// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit):
4598// n = ((n >> 4) & 0x0F0F0F0F0F0F0F0F) | ((n << 4) & 0xF0F0F0F0F0F0F0F0);
4599// Step 4: byte reverse (Suppose n = [B0,B1,B2,B3,B4,B5,B6,B7]):
4600// Apply the same byte reverse algorithm mentioned above for the fast 32-bit
4601// reverse to both the high 32 bit and low 32 bit of the 64 bit value. And
4602// then OR them together to get the final result.
4603def MaskValues64 {
4604  dag Lo1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo1, sub_32));
4605  dag Hi1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi1, sub_32));
4606  dag Lo2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo2, sub_32));
4607  dag Hi2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi2, sub_32));
4608  dag Lo4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo4, sub_32));
4609  dag Hi4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi4, sub_32));
4610}
4611
4612def DWMaskValues {
4613  dag Lo1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo1, 32, 31), 0x5555), 0x5555);
4614  dag Hi1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi1, 32, 31), 0xAAAA), 0xAAAA);
4615  dag Lo2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo2, 32, 31), 0x3333), 0x3333);
4616  dag Hi2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi2, 32, 31), 0xCCCC), 0xCCCC);
4617  dag Lo4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo4, 32, 31), 0x0F0F), 0x0F0F);
4618  dag Hi4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi4, 32, 31), 0xF0F0), 0xF0F0);
4619}
4620
4621def DWSwapInByte {
4622  dag Swap1 = (OR8 (AND8 (RLDICL $A, 63, 1), DWMaskValues.Lo1),
4623                   (AND8 (RLDICR $A, 1, 62), DWMaskValues.Hi1));
4624  dag Swap2 = (OR8 (AND8 (RLDICL DWSwapInByte.Swap1, 62, 2), DWMaskValues.Lo2),
4625                   (AND8 (RLDICR DWSwapInByte.Swap1, 2, 61), DWMaskValues.Hi2));
4626  dag Swap4 = (OR8 (AND8 (RLDICL DWSwapInByte.Swap2, 60, 4), DWMaskValues.Lo4),
4627                   (AND8 (RLDICR DWSwapInByte.Swap2, 4, 59), DWMaskValues.Hi4));
4628}
4629
4630// Intra-byte swap is done, now start inter-byte swap.
4631def DWBytes4567 {
4632  dag Word = (i32 (EXTRACT_SUBREG DWSwapInByte.Swap4, sub_32));
4633}
4634
4635def DWBytes7456 {
4636  dag Word = (RLWINM DWBytes4567.Word, 24, 0, 31);
4637}
4638
4639def DWBytes7656 {
4640  dag Word = (RLWIMI DWBytes7456.Word, DWBytes4567.Word, 8, 8, 15);
4641}
4642
4643// B7 B6 B5 B4 in the right order
4644def DWBytes7654 {
4645  dag Word = (RLWIMI DWBytes7656.Word, DWBytes4567.Word, 8, 24, 31);
4646  dag DWord =
4647    (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), DWBytes7654.Word, sub_32));
4648}
4649
4650def DWBytes0123 {
4651  dag Word = (i32 (EXTRACT_SUBREG (RLDICL DWSwapInByte.Swap4, 32, 32), sub_32));
4652}
4653
4654def DWBytes3012 {
4655  dag Word = (RLWINM DWBytes0123.Word, 24, 0, 31);
4656}
4657
4658def DWBytes3212 {
4659  dag Word = (RLWIMI DWBytes3012.Word, DWBytes0123.Word, 8, 8, 15);
4660}
4661
4662// B3 B2 B1 B0 in the right order
4663def DWBytes3210 {
4664  dag Word = (RLWIMI DWBytes3212.Word, DWBytes0123.Word, 8, 24, 31);
4665  dag DWord =
4666    (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), DWBytes3210.Word, sub_32));
4667}
4668
4669// Now both high word and low word are reversed, next
4670// swap the high word and low word.
4671def : Pat<(i64 (bitreverse i64:$A)),
4672  (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>;
4673