1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the subset of the 32-bit PowerPC instruction set, as used
11// by the PowerPC instruction selector.
12//
13//===----------------------------------------------------------------------===//
14
15include "PPCInstrFormats.td"
16
17//===----------------------------------------------------------------------===//
18// PowerPC specific type constraints.
19//
20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21  SDTCisVT<0, f64>, SDTCisPtrTy<1>
22]>;
23def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24  SDTCisVT<0, f64>, SDTCisPtrTy<1>
25]>;
26def SDT_PPCLxsizx : SDTypeProfile<1, 2, [
27  SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
28]>;
29def SDT_PPCstxsix : SDTypeProfile<0, 3, [
30  SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
31]>;
32def SDT_PPCVexts  : SDTypeProfile<1, 2, [
33  SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2>
34]>;
35
36def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
37                                           SDTCisVT<1, i32> ]>;
38def SDT_PPCCallSeqEnd   : SDCallSeqEnd<[ SDTCisVT<0, i32>,
39                                         SDTCisVT<1, i32> ]>;
40def SDT_PPCvperm   : SDTypeProfile<1, 3, [
41  SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
42]>;
43
44def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>,
45  SDTCisVec<1>, SDTCisInt<2>
46]>;
47
48def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>,
49  SDTCisVec<1>, SDTCisVec<2>, SDTCisPtrTy<3>
50]>;
51
52def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>,
53  SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3>
54]>;
55
56def SDT_PPCVecReverse: SDTypeProfile<1, 1, [ SDTCisVec<0>,
57  SDTCisVec<1>
58]>;
59
60def SDT_PPCxxpermdi: SDTypeProfile<1, 3, [ SDTCisVec<0>,
61  SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3>
62]>;
63
64def SDT_PPCvcmp : SDTypeProfile<1, 3, [
65  SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
66]>;
67
68def SDT_PPCcondbr : SDTypeProfile<0, 3, [
69  SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
70]>;
71
72def SDT_PPClbrx : SDTypeProfile<1, 2, [
73  SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
74]>;
75def SDT_PPCstbrx : SDTypeProfile<0, 3, [
76  SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
77]>;
78
79def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
80  SDTCisPtrTy<0>, SDTCisVT<1, i32>
81]>;
82
83def tocentry32 : Operand<iPTR> {
84  let MIOperandInfo = (ops i32imm:$imm);
85}
86
87def SDT_PPCqvfperm   : SDTypeProfile<1, 3, [
88  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3>
89]>;
90def SDT_PPCqvgpci   : SDTypeProfile<1, 1, [
91  SDTCisVec<0>, SDTCisInt<1>
92]>;
93def SDT_PPCqvaligni   : SDTypeProfile<1, 3, [
94  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>
95]>;
96def SDT_PPCqvesplati   : SDTypeProfile<1, 2, [
97  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>
98]>;
99
100def SDT_PPCqbflt : SDTypeProfile<1, 1, [
101  SDTCisVec<0>, SDTCisVec<1>
102]>;
103
104def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [
105  SDTCisVec<0>, SDTCisPtrTy<1>
106]>;
107
108//===----------------------------------------------------------------------===//
109// PowerPC specific DAG Nodes.
110//
111
112def PPCfre    : SDNode<"PPCISD::FRE",     SDTFPUnaryOp, []>;
113def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
114
115def PPCfcfid  : SDNode<"PPCISD::FCFID",   SDTFPUnaryOp, []>;
116def PPCfcfidu : SDNode<"PPCISD::FCFIDU",  SDTFPUnaryOp, []>;
117def PPCfcfids : SDNode<"PPCISD::FCFIDS",  SDTFPRoundOp, []>;
118def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
119def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
120def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
121def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
122def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
123def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
124                       [SDNPHasChain, SDNPMayStore]>;
125def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
126                       [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
127def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
128                       [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
129def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx,
130                       [SDNPHasChain, SDNPMayLoad]>;
131def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix,
132                       [SDNPHasChain, SDNPMayStore]>;
133def PPCVexts  : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>;
134
135// Extract FPSCR (not modeled at the DAG level).
136def PPCmffs   : SDNode<"PPCISD::MFFS",
137                       SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
138
139// Perform FADD in round-to-zero mode.
140def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
141
142
143def PPCfsel   : SDNode<"PPCISD::FSEL",
144   // Type constraint for fsel.
145   SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
146                        SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
147
148def PPChi       : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
149def PPClo       : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
150def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp,
151                         [SDNPMayLoad, SDNPMemOperand]>;
152def PPCvmaddfp  : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
153def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
154
155def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
156
157def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
158def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
159                            [SDNPMayLoad]>;
160def PPCaddTls     : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
161def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
162def PPCaddiTlsgdL   : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
163def PPCgetTlsAddr   : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
164def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR",
165                               SDTypeProfile<1, 3, [
166                                 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
167                                 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
168def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
169def PPCaddiTlsldL   : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
170def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
171def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR",
172                               SDTypeProfile<1, 3, [
173                                 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
174                                 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
175def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;
176def PPCaddiDtprelL   : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
177
178def PPCvperm     : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
179def PPCxxsplt    : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>;
180def PPCxxinsert  : SDNode<"PPCISD::XXINSERT", SDT_PPCVecInsert, []>;
181def PPCxxreverse : SDNode<"PPCISD::XXREVERSE", SDT_PPCVecReverse, []>;
182def PPCxxpermdi  : SDNode<"PPCISD::XXPERMDI", SDT_PPCxxpermdi, []>;
183def PPCvecshl    : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>;
184
185def PPCqvfperm   : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>;
186def PPCqvgpci    : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>;
187def PPCqvaligni  : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>;
188def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>;
189
190def PPCqbflt     : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>;
191
192def PPCqvlfsb    : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb,
193                          [SDNPHasChain, SDNPMayLoad]>;
194
195def PPCcmpb     : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>;
196
197// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
198// amounts.  These nodes are generated by the multi-precision shift code.
199def PPCsrl        : SDNode<"PPCISD::SRL"       , SDTIntShiftOp>;
200def PPCsra        : SDNode<"PPCISD::SRA"       , SDTIntShiftOp>;
201def PPCshl        : SDNode<"PPCISD::SHL"       , SDTIntShiftOp>;
202
203// These are target-independent nodes, but have target-specific formats.
204def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
205                           [SDNPHasChain, SDNPOutGlue]>;
206def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_PPCCallSeqEnd,
207                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
208
209def SDT_PPCCall   : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
210def PPCcall  : SDNode<"PPCISD::CALL", SDT_PPCCall,
211                      [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
212                       SDNPVariadic]>;
213def PPCcall_nop  : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
214                          [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
215                           SDNPVariadic]>;
216def PPCmtctr      : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
217                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
218def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
219                      [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
220                       SDNPVariadic]>;
221def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC",
222                               SDTypeProfile<0, 1, []>,
223                               [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
224                                SDNPVariadic]>;
225
226def retflag       : SDNode<"PPCISD::RET_FLAG", SDTNone,
227                           [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
228
229def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
230                        [SDNPHasChain,  SDNPOptInGlue, SDNPVariadic]>;
231
232def PPCeh_sjlj_setjmp  : SDNode<"PPCISD::EH_SJLJ_SETJMP",
233                                SDTypeProfile<1, 1, [SDTCisInt<0>,
234                                                     SDTCisPtrTy<1>]>,
235                                [SDNPHasChain, SDNPSideEffect]>;
236def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
237                                SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
238                                [SDNPHasChain, SDNPSideEffect]>;
239
240def SDT_PPCsc     : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
241def PPCsc         : SDNode<"PPCISD::SC", SDT_PPCsc,
242                           [SDNPHasChain, SDNPSideEffect]>;
243
244def PPCclrbhrb    : SDNode<"PPCISD::CLRBHRB", SDTNone,
245                           [SDNPHasChain, SDNPSideEffect]>;
246def PPCmfbhrbe    : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>;
247def PPCrfebb      : SDNode<"PPCISD::RFEBB", SDT_PPCsc,
248                           [SDNPHasChain, SDNPSideEffect]>;
249
250def PPCvcmp       : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
251def PPCvcmp_o     : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
252
253def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
254                           [SDNPHasChain, SDNPOptInGlue]>;
255
256def PPClbrx       : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
257                           [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
258def PPCstbrx      : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
259                           [SDNPHasChain, SDNPMayStore]>;
260
261// Instructions to set/unset CR bit 6 for SVR4 vararg calls
262def PPCcr6set   : SDNode<"PPCISD::CR6SET", SDTNone,
263                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
264def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
265                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
266
267// Instructions to support dynamic alloca.
268def SDTDynOp  : SDTypeProfile<1, 2, []>;
269def SDTDynAreaOp  : SDTypeProfile<1, 1, []>;
270def PPCdynalloc   : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
271def PPCdynareaoffset   : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>;
272
273//===----------------------------------------------------------------------===//
274// PowerPC specific transformation functions and pattern fragments.
275//
276
277def SHL32 : SDNodeXForm<imm, [{
278  // Transformation function: 31 - imm
279  return getI32Imm(31 - N->getZExtValue(), SDLoc(N));
280}]>;
281
282def SRL32 : SDNodeXForm<imm, [{
283  // Transformation function: 32 - imm
284  return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N))
285                           : getI32Imm(0, SDLoc(N));
286}]>;
287
288def LO16 : SDNodeXForm<imm, [{
289  // Transformation function: get the low 16 bits.
290  return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N));
291}]>;
292
293def HI16 : SDNodeXForm<imm, [{
294  // Transformation function: shift the immediate value down into the low bits.
295  return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N));
296}]>;
297
298def HA16 : SDNodeXForm<imm, [{
299  // Transformation function: shift the immediate value down into the low bits.
300  int Val = N->getZExtValue();
301  return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N));
302}]>;
303def MB : SDNodeXForm<imm, [{
304  // Transformation function: get the start bit of a mask
305  unsigned mb = 0, me;
306  (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
307  return getI32Imm(mb, SDLoc(N));
308}]>;
309
310def ME : SDNodeXForm<imm, [{
311  // Transformation function: get the end bit of a mask
312  unsigned mb, me = 0;
313  (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
314  return getI32Imm(me, SDLoc(N));
315}]>;
316def maskimm32 : PatLeaf<(imm), [{
317  // maskImm predicate - True if immediate is a run of ones.
318  unsigned mb, me;
319  if (N->getValueType(0) == MVT::i32)
320    return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
321  else
322    return false;
323}]>;
324
325def imm32SExt16  : Operand<i32>, ImmLeaf<i32, [{
326  // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
327  // sign extended field.  Used by instructions like 'addi'.
328  return (int32_t)Imm == (short)Imm;
329}]>;
330def imm64SExt16  : Operand<i64>, ImmLeaf<i64, [{
331  // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
332  // sign extended field.  Used by instructions like 'addi'.
333  return (int64_t)Imm == (short)Imm;
334}]>;
335def immZExt16  : PatLeaf<(imm), [{
336  // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
337  // field.  Used by instructions like 'ori'.
338  return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
339}], LO16>;
340def immAnyExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm) || isUInt<8>(Imm); }]>;
341def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>;
342
343// imm16Shifted* - These match immediates where the low 16-bits are zero.  There
344// are two forms: imm16ShiftedSExt and imm16ShiftedZExt.  These two forms are
345// identical in 32-bit mode, but in 64-bit mode, they return true if the
346// immediate fits into a sign/zero extended 32-bit immediate (with the low bits
347// clear).
348def imm16ShiftedZExt : PatLeaf<(imm), [{
349  // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
350  // immediate are set.  Used by instructions like 'xoris'.
351  return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
352}], HI16>;
353
354def imm16ShiftedSExt : PatLeaf<(imm), [{
355  // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
356  // immediate are set.  Used by instructions like 'addis'.  Identical to
357  // imm16ShiftedZExt in 32-bit mode.
358  if (N->getZExtValue() & 0xFFFF) return false;
359  if (N->getValueType(0) == MVT::i32)
360    return true;
361  // For 64-bit, make sure it is sext right.
362  return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
363}], HI16>;
364
365def imm64ZExt32  : Operand<i64>, ImmLeaf<i64, [{
366  // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
367  // zero extended field.
368  return isUInt<32>(Imm);
369}]>;
370
371// Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
372// restricted memrix (4-aligned) constants are alignment sensitive. If these
373// offsets are hidden behind TOC entries than the values of the lower-order
374// bits cannot be checked directly. As a result, we need to also incorporate
375// an alignment check into the relevant patterns.
376
377def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
378  return cast<LoadSDNode>(N)->getAlignment() >= 4;
379}]>;
380def aligned4store : PatFrag<(ops node:$val, node:$ptr),
381                            (store node:$val, node:$ptr), [{
382  return cast<StoreSDNode>(N)->getAlignment() >= 4;
383}]>;
384def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
385  return cast<LoadSDNode>(N)->getAlignment() >= 4;
386}]>;
387def aligned4pre_store : PatFrag<
388                          (ops node:$val, node:$base, node:$offset),
389                          (pre_store node:$val, node:$base, node:$offset), [{
390  return cast<StoreSDNode>(N)->getAlignment() >= 4;
391}]>;
392
393def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
394  return cast<LoadSDNode>(N)->getAlignment() < 4;
395}]>;
396def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
397                              (store node:$val, node:$ptr), [{
398  return cast<StoreSDNode>(N)->getAlignment() < 4;
399}]>;
400def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
401  return cast<LoadSDNode>(N)->getAlignment() < 4;
402}]>;
403
404//===----------------------------------------------------------------------===//
405// PowerPC Flag Definitions.
406
407class isPPC64 { bit PPC64 = 1; }
408class isDOT   { bit RC = 1; }
409
410class RegConstraint<string C> {
411  string Constraints = C;
412}
413class NoEncode<string E> {
414  string DisableEncoding = E;
415}
416
417
418//===----------------------------------------------------------------------===//
419// PowerPC Operand Definitions.
420
421// In the default PowerPC assembler syntax, registers are specified simply
422// by number, so they cannot be distinguished from immediate values (without
423// looking at the opcode).  This means that the default operand matching logic
424// for the asm parser does not work, and we need to specify custom matchers.
425// Since those can only be specified with RegisterOperand classes and not
426// directly on the RegisterClass, all instructions patterns used by the asm
427// parser need to use a RegisterOperand (instead of a RegisterClass) for
428// all their register operands.
429// For this purpose, we define one RegisterOperand for each RegisterClass,
430// using the same name as the class, just in lower case.
431
432def PPCRegGPRCAsmOperand : AsmOperandClass {
433  let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
434}
435def gprc : RegisterOperand<GPRC> {
436  let ParserMatchClass = PPCRegGPRCAsmOperand;
437}
438def PPCRegG8RCAsmOperand : AsmOperandClass {
439  let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
440}
441def g8rc : RegisterOperand<G8RC> {
442  let ParserMatchClass = PPCRegG8RCAsmOperand;
443}
444def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
445  let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
446}
447def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
448  let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
449}
450def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
451  let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
452}
453def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
454  let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
455}
456def PPCRegF8RCAsmOperand : AsmOperandClass {
457  let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
458}
459def f8rc : RegisterOperand<F8RC> {
460  let ParserMatchClass = PPCRegF8RCAsmOperand;
461}
462def PPCRegF4RCAsmOperand : AsmOperandClass {
463  let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
464}
465def f4rc : RegisterOperand<F4RC> {
466  let ParserMatchClass = PPCRegF4RCAsmOperand;
467}
468def PPCRegVRRCAsmOperand : AsmOperandClass {
469  let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
470}
471def vrrc : RegisterOperand<VRRC> {
472  let ParserMatchClass = PPCRegVRRCAsmOperand;
473}
474def PPCRegVFRCAsmOperand : AsmOperandClass {
475  let Name = "RegVFRC"; let PredicateMethod = "isRegNumber";
476}
477def vfrc : RegisterOperand<VFRC> {
478  let ParserMatchClass = PPCRegVFRCAsmOperand;
479}
480def PPCRegCRBITRCAsmOperand : AsmOperandClass {
481  let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
482}
483def crbitrc : RegisterOperand<CRBITRC> {
484  let ParserMatchClass = PPCRegCRBITRCAsmOperand;
485}
486def PPCRegCRRCAsmOperand : AsmOperandClass {
487  let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
488}
489def crrc : RegisterOperand<CRRC> {
490  let ParserMatchClass = PPCRegCRRCAsmOperand;
491}
492def crrc0 : RegisterOperand<CRRC0> {
493  let ParserMatchClass = PPCRegCRRCAsmOperand;
494}
495
496def PPCU1ImmAsmOperand : AsmOperandClass {
497  let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
498  let RenderMethod = "addImmOperands";
499}
500def u1imm   : Operand<i32> {
501  let PrintMethod = "printU1ImmOperand";
502  let ParserMatchClass = PPCU1ImmAsmOperand;
503}
504
505def PPCU2ImmAsmOperand : AsmOperandClass {
506  let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
507  let RenderMethod = "addImmOperands";
508}
509def u2imm   : Operand<i32> {
510  let PrintMethod = "printU2ImmOperand";
511  let ParserMatchClass = PPCU2ImmAsmOperand;
512}
513
514def PPCATBitsAsHintAsmOperand : AsmOperandClass {
515  let Name = "ATBitsAsHint"; let PredicateMethod = "isATBitsAsHint";
516  let RenderMethod = "addImmOperands"; // Irrelevant, predicate always fails.
517}
518def atimm   : Operand<i32> {
519  let PrintMethod = "printATBitsAsHint";
520  let ParserMatchClass = PPCATBitsAsHintAsmOperand;
521}
522
523def PPCU3ImmAsmOperand : AsmOperandClass {
524  let Name = "U3Imm"; let PredicateMethod = "isU3Imm";
525  let RenderMethod = "addImmOperands";
526}
527def u3imm   : Operand<i32> {
528  let PrintMethod = "printU3ImmOperand";
529  let ParserMatchClass = PPCU3ImmAsmOperand;
530}
531
532def PPCU4ImmAsmOperand : AsmOperandClass {
533  let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
534  let RenderMethod = "addImmOperands";
535}
536def u4imm   : Operand<i32> {
537  let PrintMethod = "printU4ImmOperand";
538  let ParserMatchClass = PPCU4ImmAsmOperand;
539}
540def PPCS5ImmAsmOperand : AsmOperandClass {
541  let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
542  let RenderMethod = "addImmOperands";
543}
544def s5imm   : Operand<i32> {
545  let PrintMethod = "printS5ImmOperand";
546  let ParserMatchClass = PPCS5ImmAsmOperand;
547  let DecoderMethod = "decodeSImmOperand<5>";
548}
549def PPCU5ImmAsmOperand : AsmOperandClass {
550  let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
551  let RenderMethod = "addImmOperands";
552}
553def u5imm   : Operand<i32> {
554  let PrintMethod = "printU5ImmOperand";
555  let ParserMatchClass = PPCU5ImmAsmOperand;
556  let DecoderMethod = "decodeUImmOperand<5>";
557}
558def PPCU6ImmAsmOperand : AsmOperandClass {
559  let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
560  let RenderMethod = "addImmOperands";
561}
562def u6imm   : Operand<i32> {
563  let PrintMethod = "printU6ImmOperand";
564  let ParserMatchClass = PPCU6ImmAsmOperand;
565  let DecoderMethod = "decodeUImmOperand<6>";
566}
567def PPCU7ImmAsmOperand : AsmOperandClass {
568  let Name = "U7Imm"; let PredicateMethod = "isU7Imm";
569  let RenderMethod = "addImmOperands";
570}
571def u7imm   : Operand<i32> {
572  let PrintMethod = "printU7ImmOperand";
573  let ParserMatchClass = PPCU7ImmAsmOperand;
574  let DecoderMethod = "decodeUImmOperand<7>";
575}
576def PPCU8ImmAsmOperand : AsmOperandClass {
577  let Name = "U8Imm"; let PredicateMethod = "isU8Imm";
578  let RenderMethod = "addImmOperands";
579}
580def u8imm   : Operand<i32> {
581  let PrintMethod = "printU8ImmOperand";
582  let ParserMatchClass = PPCU8ImmAsmOperand;
583  let DecoderMethod = "decodeUImmOperand<8>";
584}
585def PPCU10ImmAsmOperand : AsmOperandClass {
586  let Name = "U10Imm"; let PredicateMethod = "isU10Imm";
587  let RenderMethod = "addImmOperands";
588}
589def u10imm  : Operand<i32> {
590  let PrintMethod = "printU10ImmOperand";
591  let ParserMatchClass = PPCU10ImmAsmOperand;
592  let DecoderMethod = "decodeUImmOperand<10>";
593}
594def PPCU12ImmAsmOperand : AsmOperandClass {
595  let Name = "U12Imm"; let PredicateMethod = "isU12Imm";
596  let RenderMethod = "addImmOperands";
597}
598def u12imm  : Operand<i32> {
599  let PrintMethod = "printU12ImmOperand";
600  let ParserMatchClass = PPCU12ImmAsmOperand;
601  let DecoderMethod = "decodeUImmOperand<12>";
602}
603def PPCS16ImmAsmOperand : AsmOperandClass {
604  let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
605  let RenderMethod = "addS16ImmOperands";
606}
607def s16imm  : Operand<i32> {
608  let PrintMethod = "printS16ImmOperand";
609  let EncoderMethod = "getImm16Encoding";
610  let ParserMatchClass = PPCS16ImmAsmOperand;
611  let DecoderMethod = "decodeSImmOperand<16>";
612}
613def PPCU16ImmAsmOperand : AsmOperandClass {
614  let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
615  let RenderMethod = "addU16ImmOperands";
616}
617def u16imm  : Operand<i32> {
618  let PrintMethod = "printU16ImmOperand";
619  let EncoderMethod = "getImm16Encoding";
620  let ParserMatchClass = PPCU16ImmAsmOperand;
621  let DecoderMethod = "decodeUImmOperand<16>";
622}
623def PPCS17ImmAsmOperand : AsmOperandClass {
624  let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
625  let RenderMethod = "addS16ImmOperands";
626}
627def s17imm  : Operand<i32> {
628  // This operand type is used for addis/lis to allow the assembler parser
629  // to accept immediates in the range -65536..65535 for compatibility with
630  // the GNU assembler.  The operand is treated as 16-bit otherwise.
631  let PrintMethod = "printS16ImmOperand";
632  let EncoderMethod = "getImm16Encoding";
633  let ParserMatchClass = PPCS17ImmAsmOperand;
634  let DecoderMethod = "decodeSImmOperand<16>";
635}
636
637def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
638
639def PPCDirectBrAsmOperand : AsmOperandClass {
640  let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
641  let RenderMethod = "addBranchTargetOperands";
642}
643def directbrtarget : Operand<OtherVT> {
644  let PrintMethod = "printBranchOperand";
645  let EncoderMethod = "getDirectBrEncoding";
646  let ParserMatchClass = PPCDirectBrAsmOperand;
647}
648def absdirectbrtarget : Operand<OtherVT> {
649  let PrintMethod = "printAbsBranchOperand";
650  let EncoderMethod = "getAbsDirectBrEncoding";
651  let ParserMatchClass = PPCDirectBrAsmOperand;
652}
653def PPCCondBrAsmOperand : AsmOperandClass {
654  let Name = "CondBr"; let PredicateMethod = "isCondBr";
655  let RenderMethod = "addBranchTargetOperands";
656}
657def condbrtarget : Operand<OtherVT> {
658  let PrintMethod = "printBranchOperand";
659  let EncoderMethod = "getCondBrEncoding";
660  let ParserMatchClass = PPCCondBrAsmOperand;
661}
662def abscondbrtarget : Operand<OtherVT> {
663  let PrintMethod = "printAbsBranchOperand";
664  let EncoderMethod = "getAbsCondBrEncoding";
665  let ParserMatchClass = PPCCondBrAsmOperand;
666}
667def calltarget : Operand<iPTR> {
668  let PrintMethod = "printBranchOperand";
669  let EncoderMethod = "getDirectBrEncoding";
670  let ParserMatchClass = PPCDirectBrAsmOperand;
671}
672def abscalltarget : Operand<iPTR> {
673  let PrintMethod = "printAbsBranchOperand";
674  let EncoderMethod = "getAbsDirectBrEncoding";
675  let ParserMatchClass = PPCDirectBrAsmOperand;
676}
677def PPCCRBitMaskOperand : AsmOperandClass {
678 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
679}
680def crbitm: Operand<i8> {
681  let PrintMethod = "printcrbitm";
682  let EncoderMethod = "get_crbitm_encoding";
683  let DecoderMethod = "decodeCRBitMOperand";
684  let ParserMatchClass = PPCCRBitMaskOperand;
685}
686// Address operands
687// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
688def PPCRegGxRCNoR0Operand : AsmOperandClass {
689  let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
690}
691def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
692  let ParserMatchClass = PPCRegGxRCNoR0Operand;
693}
694// A version of ptr_rc usable with the asm parser.
695def PPCRegGxRCOperand : AsmOperandClass {
696  let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
697}
698def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
699  let ParserMatchClass = PPCRegGxRCOperand;
700}
701
702def PPCDispRIOperand : AsmOperandClass {
703 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
704 let RenderMethod = "addS16ImmOperands";
705}
706def dispRI : Operand<iPTR> {
707  let ParserMatchClass = PPCDispRIOperand;
708}
709def PPCDispRIXOperand : AsmOperandClass {
710 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
711 let RenderMethod = "addImmOperands";
712}
713def dispRIX : Operand<iPTR> {
714  let ParserMatchClass = PPCDispRIXOperand;
715}
716def PPCDispRIX16Operand : AsmOperandClass {
717 let Name = "DispRIX16"; let PredicateMethod = "isS16ImmX16";
718 let RenderMethod = "addImmOperands";
719}
720def dispRIX16 : Operand<iPTR> {
721  let ParserMatchClass = PPCDispRIX16Operand;
722}
723def PPCDispSPE8Operand : AsmOperandClass {
724 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
725 let RenderMethod = "addImmOperands";
726}
727def dispSPE8 : Operand<iPTR> {
728  let ParserMatchClass = PPCDispSPE8Operand;
729}
730def PPCDispSPE4Operand : AsmOperandClass {
731 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
732 let RenderMethod = "addImmOperands";
733}
734def dispSPE4 : Operand<iPTR> {
735  let ParserMatchClass = PPCDispSPE4Operand;
736}
737def PPCDispSPE2Operand : AsmOperandClass {
738 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
739 let RenderMethod = "addImmOperands";
740}
741def dispSPE2 : Operand<iPTR> {
742  let ParserMatchClass = PPCDispSPE2Operand;
743}
744
745def memri : Operand<iPTR> {
746  let PrintMethod = "printMemRegImm";
747  let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
748  let EncoderMethod = "getMemRIEncoding";
749  let DecoderMethod = "decodeMemRIOperands";
750}
751def memrr : Operand<iPTR> {
752  let PrintMethod = "printMemRegReg";
753  let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
754}
755def memrix : Operand<iPTR> {   // memri where the imm is 4-aligned.
756  let PrintMethod = "printMemRegImm";
757  let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
758  let EncoderMethod = "getMemRIXEncoding";
759  let DecoderMethod = "decodeMemRIXOperands";
760}
761def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16:27}
762  let PrintMethod = "printMemRegImm";
763  let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg);
764  let EncoderMethod = "getMemRIX16Encoding";
765  let DecoderMethod = "decodeMemRIX16Operands";
766}
767def spe8dis : Operand<iPTR> {   // SPE displacement where the imm is 8-aligned.
768  let PrintMethod = "printMemRegImm";
769  let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
770  let EncoderMethod = "getSPE8DisEncoding";
771}
772def spe4dis : Operand<iPTR> {   // SPE displacement where the imm is 4-aligned.
773  let PrintMethod = "printMemRegImm";
774  let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
775  let EncoderMethod = "getSPE4DisEncoding";
776}
777def spe2dis : Operand<iPTR> {   // SPE displacement where the imm is 2-aligned.
778  let PrintMethod = "printMemRegImm";
779  let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
780  let EncoderMethod = "getSPE2DisEncoding";
781}
782
783// A single-register address. This is used with the SjLj
784// pseudo-instructions which tranlates to LD/LWZ.  These instructions requires
785// G8RC_NOX0 registers.
786def memr : Operand<iPTR> {
787  let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg);
788}
789def PPCTLSRegOperand : AsmOperandClass {
790  let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
791  let RenderMethod = "addTLSRegOperands";
792}
793def tlsreg32 : Operand<i32> {
794  let EncoderMethod = "getTLSRegEncoding";
795  let ParserMatchClass = PPCTLSRegOperand;
796}
797def tlsgd32 : Operand<i32> {}
798def tlscall32 : Operand<i32> {
799  let PrintMethod = "printTLSCall";
800  let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
801  let EncoderMethod = "getTLSCallEncoding";
802}
803
804// PowerPC Predicate operand.
805def pred : Operand<OtherVT> {
806  let PrintMethod = "printPredicateOperand";
807  let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
808}
809
810// Define PowerPC specific addressing mode.
811def iaddr  : ComplexPattern<iPTR, 2, "SelectAddrImm",    [], []>;
812def xaddr  : ComplexPattern<iPTR, 2, "SelectAddrIdx",    [], []>;
813def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
814def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4",  [], []>; // "std"
815
816// The address in a single register. This is used with the SjLj
817// pseudo-instructions.
818def addr   : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
819
820/// This is just the offset part of iaddr, used for preinc.
821def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
822
823//===----------------------------------------------------------------------===//
824// PowerPC Instruction Predicate Definitions.
825def In32BitMode  : Predicate<"!PPCSubTarget->isPPC64()">;
826def In64BitMode  : Predicate<"PPCSubTarget->isPPC64()">;
827def IsBookE  : Predicate<"PPCSubTarget->isBookE()">;
828def IsNotBookE  : Predicate<"!PPCSubTarget->isBookE()">;
829def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
830def HasSYNC   : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
831def IsPPC4xx  : Predicate<"PPCSubTarget->isPPC4xx()">;
832def IsPPC6xx  : Predicate<"PPCSubTarget->isPPC6xx()">;
833def IsE500  : Predicate<"PPCSubTarget->isE500()">;
834def HasSPE  : Predicate<"PPCSubTarget->HasSPE()">;
835def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
836def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">;
837def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
838def NaNsFPMath   : Predicate<"!TM.Options.NoNaNsFPMath">;
839def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">;
840def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">;
841def IsISA3_0 : Predicate<"PPCSubTarget->isISA3_0()">;
842
843//===----------------------------------------------------------------------===//
844// PowerPC Multiclass Definitions.
845
846multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
847                    string asmbase, string asmstr, InstrItinClass itin,
848                    list<dag> pattern> {
849  let BaseName = asmbase in {
850    def NAME : XForm_6<opcode, xo, OOL, IOL,
851                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
852                       pattern>, RecFormRel;
853    let Defs = [CR0] in
854    def o    : XForm_6<opcode, xo, OOL, IOL,
855                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
856                       []>, isDOT, RecFormRel;
857  }
858}
859
860multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
861                     string asmbase, string asmstr, InstrItinClass itin,
862                     list<dag> pattern> {
863  let BaseName = asmbase in {
864    let Defs = [CARRY] in
865    def NAME : XForm_6<opcode, xo, OOL, IOL,
866                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
867                       pattern>, RecFormRel;
868    let Defs = [CARRY, CR0] in
869    def o    : XForm_6<opcode, xo, OOL, IOL,
870                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
871                       []>, isDOT, RecFormRel;
872  }
873}
874
875multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
876                      string asmbase, string asmstr, InstrItinClass itin,
877                      list<dag> pattern> {
878  let BaseName = asmbase in {
879    let Defs = [CARRY] in
880    def NAME : XForm_10<opcode, xo, OOL, IOL,
881                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
882                       pattern>, RecFormRel;
883    let Defs = [CARRY, CR0] in
884    def o    : XForm_10<opcode, xo, OOL, IOL,
885                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
886                       []>, isDOT, RecFormRel;
887  }
888}
889
890multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
891                    string asmbase, string asmstr, InstrItinClass itin,
892                    list<dag> pattern> {
893  let BaseName = asmbase in {
894    def NAME : XForm_11<opcode, xo, OOL, IOL,
895                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
896                       pattern>, RecFormRel;
897    let Defs = [CR0] in
898    def o    : XForm_11<opcode, xo, OOL, IOL,
899                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
900                       []>, isDOT, RecFormRel;
901  }
902}
903
904multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
905                    string asmbase, string asmstr, InstrItinClass itin,
906                    list<dag> pattern> {
907  let BaseName = asmbase in {
908    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
909                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
910                       pattern>, RecFormRel;
911    let Defs = [CR0] in
912    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
913                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
914                       []>, isDOT, RecFormRel;
915  }
916}
917
918// Multiclass for instructions for which the non record form is not cracked
919// and the record form is cracked (i.e. divw, mullw, etc.)
920multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
921                      string asmbase, string asmstr, InstrItinClass itin,
922                      list<dag> pattern> {
923  let BaseName = asmbase in {
924    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
925                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
926                       pattern>, RecFormRel;
927    let Defs = [CR0] in
928    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
929                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
930                       []>, isDOT, RecFormRel, PPC970_DGroup_First,
931                       PPC970_DGroup_Cracked;
932  }
933}
934
935multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
936                      string asmbase, string asmstr, InstrItinClass itin,
937                      list<dag> pattern> {
938  let BaseName = asmbase in {
939    let Defs = [CARRY] in
940    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
941                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
942                       pattern>, RecFormRel;
943    let Defs = [CARRY, CR0] in
944    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
945                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
946                       []>, isDOT, RecFormRel;
947  }
948}
949
950multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
951                    string asmbase, string asmstr, InstrItinClass itin,
952                    list<dag> pattern> {
953  let BaseName = asmbase in {
954    def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
955                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
956                       pattern>, RecFormRel;
957    let Defs = [CR0] in
958    def o    : XOForm_3<opcode, xo, oe, OOL, IOL,
959                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
960                       []>, isDOT, RecFormRel;
961  }
962}
963
964multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
965                      string asmbase, string asmstr, InstrItinClass itin,
966                      list<dag> pattern> {
967  let BaseName = asmbase in {
968    let Defs = [CARRY] in
969    def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
970                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
971                       pattern>, RecFormRel;
972    let Defs = [CARRY, CR0] in
973    def o    : XOForm_3<opcode, xo, oe, OOL, IOL,
974                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
975                       []>, isDOT, RecFormRel;
976  }
977}
978
979multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
980                    string asmbase, string asmstr, InstrItinClass itin,
981                    list<dag> pattern> {
982  let BaseName = asmbase in {
983    def NAME : MForm_2<opcode, OOL, IOL,
984                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
985                       pattern>, RecFormRel;
986    let Defs = [CR0] in
987    def o    : MForm_2<opcode, OOL, IOL,
988                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
989                       []>, isDOT, RecFormRel;
990  }
991}
992
993multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
994                    string asmbase, string asmstr, InstrItinClass itin,
995                    list<dag> pattern> {
996  let BaseName = asmbase in {
997    def NAME : MDForm_1<opcode, xo, OOL, IOL,
998                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
999                       pattern>, RecFormRel;
1000    let Defs = [CR0] in
1001    def o    : MDForm_1<opcode, xo, OOL, IOL,
1002                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1003                       []>, isDOT, RecFormRel;
1004  }
1005}
1006
1007multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
1008                     string asmbase, string asmstr, InstrItinClass itin,
1009                     list<dag> pattern> {
1010  let BaseName = asmbase in {
1011    def NAME : MDSForm_1<opcode, xo, OOL, IOL,
1012                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1013                        pattern>, RecFormRel;
1014    let Defs = [CR0] in
1015    def o    : MDSForm_1<opcode, xo, OOL, IOL,
1016                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1017                        []>, isDOT, RecFormRel;
1018  }
1019}
1020
1021multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
1022                      string asmbase, string asmstr, InstrItinClass itin,
1023                      list<dag> pattern> {
1024  let BaseName = asmbase in {
1025    let Defs = [CARRY] in
1026    def NAME : XSForm_1<opcode, xo, OOL, IOL,
1027                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1028                       pattern>, RecFormRel;
1029    let Defs = [CARRY, CR0] in
1030    def o    : XSForm_1<opcode, xo, OOL, IOL,
1031                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1032                       []>, isDOT, RecFormRel;
1033  }
1034}
1035
1036multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
1037                    string asmbase, string asmstr, InstrItinClass itin,
1038                    list<dag> pattern> {
1039  let BaseName = asmbase in {
1040    def NAME : XForm_26<opcode, xo, OOL, IOL,
1041                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1042                       pattern>, RecFormRel;
1043    let Defs = [CR1] in
1044    def o    : XForm_26<opcode, xo, OOL, IOL,
1045                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1046                       []>, isDOT, RecFormRel;
1047  }
1048}
1049
1050multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
1051                    string asmbase, string asmstr, InstrItinClass itin,
1052                    list<dag> pattern> {
1053  let BaseName = asmbase in {
1054    def NAME : XForm_28<opcode, xo, OOL, IOL,
1055                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1056                       pattern>, RecFormRel;
1057    let Defs = [CR1] in
1058    def o    : XForm_28<opcode, xo, OOL, IOL,
1059                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1060                       []>, isDOT, RecFormRel;
1061  }
1062}
1063
1064multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
1065                    string asmbase, string asmstr, InstrItinClass itin,
1066                    list<dag> pattern> {
1067  let BaseName = asmbase in {
1068    def NAME : AForm_1<opcode, xo, OOL, IOL,
1069                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1070                       pattern>, RecFormRel;
1071    let Defs = [CR1] in
1072    def o    : AForm_1<opcode, xo, OOL, IOL,
1073                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1074                       []>, isDOT, RecFormRel;
1075  }
1076}
1077
1078multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
1079                    string asmbase, string asmstr, InstrItinClass itin,
1080                    list<dag> pattern> {
1081  let BaseName = asmbase in {
1082    def NAME : AForm_2<opcode, xo, OOL, IOL,
1083                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1084                       pattern>, RecFormRel;
1085    let Defs = [CR1] in
1086    def o    : AForm_2<opcode, xo, OOL, IOL,
1087                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1088                       []>, isDOT, RecFormRel;
1089  }
1090}
1091
1092multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
1093                    string asmbase, string asmstr, InstrItinClass itin,
1094                    list<dag> pattern> {
1095  let BaseName = asmbase in {
1096    def NAME : AForm_3<opcode, xo, OOL, IOL,
1097                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1098                       pattern>, RecFormRel;
1099    let Defs = [CR1] in
1100    def o    : AForm_3<opcode, xo, OOL, IOL,
1101                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1102                       []>, isDOT, RecFormRel;
1103  }
1104}
1105
1106//===----------------------------------------------------------------------===//
1107// PowerPC Instruction Definitions.
1108
1109// Pseudo-instructions:
1110
1111let hasCtrlDep = 1 in {
1112let Defs = [R1], Uses = [R1] in {
1113def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
1114                              "#ADJCALLSTACKDOWN $amt1 $amt2",
1115                              [(callseq_start timm:$amt1, timm:$amt2)]>;
1116def ADJCALLSTACKUP   : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
1117                              "#ADJCALLSTACKUP $amt1 $amt2",
1118                              [(callseq_end timm:$amt1, timm:$amt2)]>;
1119}
1120
1121def UPDATE_VRSAVE    : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
1122                              "UPDATE_VRSAVE $rD, $rS", []>;
1123}
1124
1125let Defs = [R1], Uses = [R1] in
1126def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
1127                       [(set i32:$result,
1128                             (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
1129def DYNAREAOFFSET : Pseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET",
1130                       [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>;
1131
1132// SELECT_CC_* - Used to implement the SELECT_CC DAG operation.  Expanded after
1133// instruction selection into a branch sequence.
1134let usesCustomInserter = 1,    // Expanded after instruction selection.
1135    PPC970_Single = 1 in {
1136  // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
1137  // because either operand might become the first operand in an isel, and
1138  // that operand cannot be r0.
1139  def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
1140                              gprc_nor0:$T, gprc_nor0:$F,
1141                              i32imm:$BROPC), "#SELECT_CC_I4",
1142                              []>;
1143  def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
1144                              g8rc_nox0:$T, g8rc_nox0:$F,
1145                              i32imm:$BROPC), "#SELECT_CC_I8",
1146                              []>;
1147  def SELECT_CC_F4  : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1148                              i32imm:$BROPC), "#SELECT_CC_F4",
1149                              []>;
1150  def SELECT_CC_F8  : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
1151                              i32imm:$BROPC), "#SELECT_CC_F8",
1152                              []>;
1153  def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
1154                              i32imm:$BROPC), "#SELECT_CC_VRRC",
1155                              []>;
1156
1157  // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
1158  // register bit directly.
1159  def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
1160                          gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
1161                          [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
1162  def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
1163                          g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
1164                          [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
1165  def SELECT_F4  : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
1166                          f4rc:$T, f4rc:$F), "#SELECT_F4",
1167                          [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
1168  def SELECT_F8  : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
1169                          f8rc:$T, f8rc:$F), "#SELECT_F8",
1170                          [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
1171  def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
1172                          vrrc:$T, vrrc:$F), "#SELECT_VRRC",
1173                          [(set v4i32:$dst,
1174                                (select i1:$cond, v4i32:$T, v4i32:$F))]>;
1175}
1176
1177// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
1178// scavenge a register for it.
1179let mayStore = 1 in {
1180def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
1181                     "#SPILL_CR", []>;
1182def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1183                         "#SPILL_CRBIT", []>;
1184}
1185
1186// RESTORE_CR - Indicate that we're restoring the CR register (previously
1187// spilled), so we'll need to scavenge a register for it.
1188let mayLoad = 1 in {
1189def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1190                     "#RESTORE_CR", []>;
1191def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1192                           "#RESTORE_CRBIT", []>;
1193}
1194
1195let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1196  let isReturn = 1, Uses = [LR, RM] in
1197    def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1198                           [(retflag)]>, Requires<[In32BitMode]>;
1199  let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1200    def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1201                            []>;
1202
1203    let isCodeGenOnly = 1 in {
1204      def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1205                               "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1206                               []>;
1207
1208      def BCCTR :  XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1209                                "bcctr 12, $bi, 0", IIC_BrB, []>;
1210      def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1211                                "bcctr 4, $bi, 0", IIC_BrB, []>;
1212    }
1213  }
1214}
1215
1216let Defs = [LR] in
1217  def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1218                   PPC970_Unit_BRU;
1219let Defs = [LR] in
1220  def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1221                    PPC970_Unit_BRU;
1222
1223let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1224  let isBarrier = 1 in {
1225  def B   : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1226                  "b $dst", IIC_BrB,
1227                  [(br bb:$dst)]>;
1228  def BA  : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1229                  "ba $dst", IIC_BrB, []>;
1230  }
1231
1232  // BCC represents an arbitrary conditional branch on a predicate.
1233  // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1234  // a two-value operand where a dag node expects two operands. :(
1235  let isCodeGenOnly = 1 in {
1236    class BCC_class : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1237                            "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1238                            /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1239    def BCC : BCC_class;
1240
1241    // The same as BCC, except that it's not a terminator. Used for introducing
1242    // control flow dependency without creating new blocks.
1243    let isTerminator = 0 in def CTRL_DEP : BCC_class;
1244
1245    def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1246                     "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1247
1248    let isReturn = 1, Uses = [LR, RM] in
1249    def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1250                           "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1251  }
1252
1253  let isCodeGenOnly = 1 in {
1254    let Pattern = [(brcond i1:$bi, bb:$dst)] in
1255    def BC  : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1256             "bc 12, $bi, $dst">;
1257
1258    let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1259    def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1260             "bc 4, $bi, $dst">;
1261
1262    let isReturn = 1, Uses = [LR, RM] in
1263    def BCLR  : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1264                             "bclr 12, $bi, 0", IIC_BrB, []>;
1265    def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1266                             "bclr 4, $bi, 0", IIC_BrB, []>;
1267  }
1268
1269  let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1270   def BDZLR  : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1271                             "bdzlr", IIC_BrB, []>;
1272   def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1273                             "bdnzlr", IIC_BrB, []>;
1274   def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1275                             "bdzlr+", IIC_BrB, []>;
1276   def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1277                             "bdnzlr+", IIC_BrB, []>;
1278   def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1279                             "bdzlr-", IIC_BrB, []>;
1280   def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1281                             "bdnzlr-", IIC_BrB, []>;
1282  }
1283
1284  let Defs = [CTR], Uses = [CTR] in {
1285    def BDZ  : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1286                       "bdz $dst">;
1287    def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1288                       "bdnz $dst">;
1289    def BDZA  : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1290                        "bdza $dst">;
1291    def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1292                        "bdnza $dst">;
1293    def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1294                       "bdz+ $dst">;
1295    def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1296                       "bdnz+ $dst">;
1297    def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1298                        "bdza+ $dst">;
1299    def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1300                        "bdnza+ $dst">;
1301    def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1302                       "bdz- $dst">;
1303    def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1304                       "bdnz- $dst">;
1305    def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1306                        "bdza- $dst">;
1307    def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1308                        "bdnza- $dst">;
1309  }
1310}
1311
1312// The unconditional BCL used by the SjLj setjmp code.
1313let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1314  let Defs = [LR], Uses = [RM] in {
1315    def BCLalways  : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1316                            "bcl 20, 31, $dst">;
1317  }
1318}
1319
1320let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1321  // Convenient aliases for call instructions
1322  let Uses = [RM] in {
1323    def BL  : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1324                    "bl $func", IIC_BrB, []>;  // See Pat patterns below.
1325    def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1326                    "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1327
1328    let isCodeGenOnly = 1 in {
1329      def BL_TLS  : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1330                          "bl $func", IIC_BrB, []>;
1331      def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1332                       "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1333      def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1334                        "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1335
1336      def BCL  : BForm_4<16, 12, 0, 1, (outs),
1337                         (ins crbitrc:$bi, condbrtarget:$dst),
1338                         "bcl 12, $bi, $dst">;
1339      def BCLn : BForm_4<16, 4, 0, 1, (outs),
1340                         (ins crbitrc:$bi, condbrtarget:$dst),
1341                         "bcl 4, $bi, $dst">;
1342    }
1343  }
1344  let Uses = [CTR, RM] in {
1345    def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1346                             "bctrl", IIC_BrB, [(PPCbctrl)]>,
1347                Requires<[In32BitMode]>;
1348
1349    let isCodeGenOnly = 1 in {
1350      def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1351                                "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1352                                []>;
1353
1354      def BCCTRL  : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1355                                 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1356      def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1357                                 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1358    }
1359  }
1360  let Uses = [LR, RM] in {
1361    def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1362                            "blrl", IIC_BrB, []>;
1363
1364    let isCodeGenOnly = 1 in {
1365      def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1366                              "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1367                              []>;
1368
1369      def BCLRL  : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1370                                "bclrl 12, $bi, 0", IIC_BrB, []>;
1371      def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1372                                "bclrl 4, $bi, 0", IIC_BrB, []>;
1373    }
1374  }
1375  let Defs = [CTR], Uses = [CTR, RM] in {
1376    def BDZL  : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1377                        "bdzl $dst">;
1378    def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1379                        "bdnzl $dst">;
1380    def BDZLA  : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1381                         "bdzla $dst">;
1382    def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1383                         "bdnzla $dst">;
1384    def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1385                        "bdzl+ $dst">;
1386    def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1387                        "bdnzl+ $dst">;
1388    def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1389                         "bdzla+ $dst">;
1390    def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1391                         "bdnzla+ $dst">;
1392    def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1393                        "bdzl- $dst">;
1394    def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1395                        "bdnzl- $dst">;
1396    def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1397                         "bdzla- $dst">;
1398    def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1399                         "bdnzla- $dst">;
1400  }
1401  let Defs = [CTR], Uses = [CTR, LR, RM] in {
1402    def BDZLRL  : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1403                               "bdzlrl", IIC_BrB, []>;
1404    def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1405                               "bdnzlrl", IIC_BrB, []>;
1406    def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1407                               "bdzlrl+", IIC_BrB, []>;
1408    def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1409                               "bdnzlrl+", IIC_BrB, []>;
1410    def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1411                               "bdzlrl-", IIC_BrB, []>;
1412    def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1413                               "bdnzlrl-", IIC_BrB, []>;
1414  }
1415}
1416
1417let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1418def TCRETURNdi :Pseudo< (outs),
1419                        (ins calltarget:$dst, i32imm:$offset),
1420                 "#TC_RETURNd $dst $offset",
1421                 []>;
1422
1423
1424let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1425def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1426                 "#TC_RETURNa $func $offset",
1427                 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1428
1429let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1430def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1431                 "#TC_RETURNr $dst $offset",
1432                 []>;
1433
1434
1435let isCodeGenOnly = 1 in {
1436
1437let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1438    isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM]  in
1439def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1440                            []>, Requires<[In32BitMode]>;
1441
1442let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1443    isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1444def TAILB   : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1445                  "b $dst", IIC_BrB,
1446                  []>;
1447
1448let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1449    isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1450def TAILBA   : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1451                  "ba $dst", IIC_BrB,
1452                  []>;
1453
1454}
1455
1456let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1457  let Defs = [CTR] in
1458  def EH_SjLj_SetJmp32  : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1459                            "#EH_SJLJ_SETJMP32",
1460                            [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1461                          Requires<[In32BitMode]>;
1462  let isTerminator = 1 in
1463  def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1464                            "#EH_SJLJ_LONGJMP32",
1465                            [(PPCeh_sjlj_longjmp addr:$buf)]>,
1466                          Requires<[In32BitMode]>;
1467}
1468
1469// This pseudo is never removed from the function, as it serves as
1470// a terminator.  Size is set to 0 to prevent the builtin assembler
1471// from emitting it.
1472let isBranch = 1, isTerminator = 1, Size = 0 in {
1473  def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1474                        "#EH_SjLj_Setup\t$dst", []>;
1475}
1476
1477// System call.
1478let PPC970_Unit = 7 in {
1479  def SC     : SCForm<17, 1, (outs), (ins i32imm:$lev),
1480                      "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1481}
1482
1483// Branch history rolling buffer.
1484def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB,
1485                      [(PPCclrbhrb)]>,
1486                      PPC970_DGroup_Single;
1487// The $dmy argument used for MFBHRBE is not needed; however, including
1488// it avoids automatic generation of PPCFastISel::fastEmit_i(), which
1489// interferes with necessary special handling (see PPCFastISel.cpp).
1490def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD),
1491                         (ins u10imm:$imm, u10imm:$dmy),
1492                         "mfbhrbe $rD, $imm", IIC_BrB,
1493                         [(set i32:$rD,
1494                               (PPCmfbhrbe imm:$imm, imm:$dmy))]>,
1495                         PPC970_DGroup_First;
1496
1497def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm",
1498                     IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>,
1499                     PPC970_DGroup_Single;
1500
1501// DCB* instructions.
1502def DCBA   : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1503                      IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1504                      PPC970_DGroup_Single;
1505def DCBI   : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1506                      IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1507                      PPC970_DGroup_Single;
1508def DCBST  : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1509                      IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1510                      PPC970_DGroup_Single;
1511def DCBZ   : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1512                      IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1513                      PPC970_DGroup_Single;
1514def DCBZL  : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1515                      IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1516                      PPC970_DGroup_Single;
1517
1518def DCBF   : DCB_Form_hint<86, (outs), (ins u5imm:$TH, memrr:$dst),
1519                      "dcbf $dst, $TH", IIC_LdStDCBF, []>,
1520                      PPC970_DGroup_Single;
1521
1522let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in {
1523def DCBT   : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst),
1524                      "dcbt $dst, $TH", IIC_LdStDCBF, []>,
1525                      PPC970_DGroup_Single;
1526def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst),
1527                      "dcbtst $dst, $TH", IIC_LdStDCBF, []>,
1528                      PPC970_DGroup_Single;
1529} // hasSideEffects = 0
1530
1531def ICBLC  : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, memrr:$src),
1532                       "icblc $CT, $src", IIC_LdStStore>, Requires<[HasICBT]>;
1533def ICBLQ  : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, memrr:$src),
1534                       "icblq. $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1535def ICBT  : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1536                       "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1537def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src),
1538                       "icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1539
1540def : Pat<(int_ppc_dcbt xoaddr:$dst),
1541          (DCBT 0, xoaddr:$dst)>;
1542def : Pat<(int_ppc_dcbtst xoaddr:$dst),
1543          (DCBTST 0, xoaddr:$dst)>;
1544def : Pat<(int_ppc_dcbf xoaddr:$dst),
1545          (DCBF 0, xoaddr:$dst)>;
1546
1547def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1548          (DCBT 0, xoaddr:$dst)>;   // data prefetch for loads
1549def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1550          (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores
1551def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1552          (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
1553
1554// Atomic operations
1555let usesCustomInserter = 1 in {
1556  let Defs = [CR0] in {
1557    def ATOMIC_LOAD_ADD_I8 : Pseudo<
1558      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1559      [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1560    def ATOMIC_LOAD_SUB_I8 : Pseudo<
1561      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1562      [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1563    def ATOMIC_LOAD_AND_I8 : Pseudo<
1564      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1565      [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1566    def ATOMIC_LOAD_OR_I8 : Pseudo<
1567      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1568      [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1569    def ATOMIC_LOAD_XOR_I8 : Pseudo<
1570      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1571      [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1572    def ATOMIC_LOAD_NAND_I8 : Pseudo<
1573      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1574      [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1575    def ATOMIC_LOAD_MIN_I8 : Pseudo<
1576      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8",
1577      [(set i32:$dst, (atomic_load_min_8 xoaddr:$ptr, i32:$incr))]>;
1578    def ATOMIC_LOAD_MAX_I8 : Pseudo<
1579      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8",
1580      [(set i32:$dst, (atomic_load_max_8 xoaddr:$ptr, i32:$incr))]>;
1581    def ATOMIC_LOAD_UMIN_I8 : Pseudo<
1582      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8",
1583      [(set i32:$dst, (atomic_load_umin_8 xoaddr:$ptr, i32:$incr))]>;
1584    def ATOMIC_LOAD_UMAX_I8 : Pseudo<
1585      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8",
1586      [(set i32:$dst, (atomic_load_umax_8 xoaddr:$ptr, i32:$incr))]>;
1587    def ATOMIC_LOAD_ADD_I16 : Pseudo<
1588      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1589      [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1590    def ATOMIC_LOAD_SUB_I16 : Pseudo<
1591      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1592      [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1593    def ATOMIC_LOAD_AND_I16 : Pseudo<
1594      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1595      [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1596    def ATOMIC_LOAD_OR_I16 : Pseudo<
1597      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1598      [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1599    def ATOMIC_LOAD_XOR_I16 : Pseudo<
1600      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1601      [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1602    def ATOMIC_LOAD_NAND_I16 : Pseudo<
1603      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1604      [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1605    def ATOMIC_LOAD_MIN_I16 : Pseudo<
1606      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16",
1607      [(set i32:$dst, (atomic_load_min_16 xoaddr:$ptr, i32:$incr))]>;
1608    def ATOMIC_LOAD_MAX_I16 : Pseudo<
1609      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16",
1610      [(set i32:$dst, (atomic_load_max_16 xoaddr:$ptr, i32:$incr))]>;
1611    def ATOMIC_LOAD_UMIN_I16 : Pseudo<
1612      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16",
1613      [(set i32:$dst, (atomic_load_umin_16 xoaddr:$ptr, i32:$incr))]>;
1614    def ATOMIC_LOAD_UMAX_I16 : Pseudo<
1615      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16",
1616      [(set i32:$dst, (atomic_load_umax_16 xoaddr:$ptr, i32:$incr))]>;
1617    def ATOMIC_LOAD_ADD_I32 : Pseudo<
1618      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1619      [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1620    def ATOMIC_LOAD_SUB_I32 : Pseudo<
1621      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1622      [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1623    def ATOMIC_LOAD_AND_I32 : Pseudo<
1624      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1625      [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1626    def ATOMIC_LOAD_OR_I32 : Pseudo<
1627      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1628      [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1629    def ATOMIC_LOAD_XOR_I32 : Pseudo<
1630      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1631      [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1632    def ATOMIC_LOAD_NAND_I32 : Pseudo<
1633      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1634      [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1635    def ATOMIC_LOAD_MIN_I32 : Pseudo<
1636      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32",
1637      [(set i32:$dst, (atomic_load_min_32 xoaddr:$ptr, i32:$incr))]>;
1638    def ATOMIC_LOAD_MAX_I32 : Pseudo<
1639      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32",
1640      [(set i32:$dst, (atomic_load_max_32 xoaddr:$ptr, i32:$incr))]>;
1641    def ATOMIC_LOAD_UMIN_I32 : Pseudo<
1642      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32",
1643      [(set i32:$dst, (atomic_load_umin_32 xoaddr:$ptr, i32:$incr))]>;
1644    def ATOMIC_LOAD_UMAX_I32 : Pseudo<
1645      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32",
1646      [(set i32:$dst, (atomic_load_umax_32 xoaddr:$ptr, i32:$incr))]>;
1647
1648    def ATOMIC_CMP_SWAP_I8 : Pseudo<
1649      (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1650      [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1651    def ATOMIC_CMP_SWAP_I16 : Pseudo<
1652      (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1653      [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1654    def ATOMIC_CMP_SWAP_I32 : Pseudo<
1655      (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1656      [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1657
1658    def ATOMIC_SWAP_I8 : Pseudo<
1659      (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1660      [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1661    def ATOMIC_SWAP_I16 : Pseudo<
1662      (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1663      [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1664    def ATOMIC_SWAP_I32 : Pseudo<
1665      (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1666      [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1667  }
1668}
1669
1670// Instructions to support atomic operations
1671let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {
1672def LBARX : XForm_1<31,  52, (outs gprc:$rD), (ins memrr:$src),
1673                    "lbarx $rD, $src", IIC_LdStLWARX, []>,
1674                    Requires<[HasPartwordAtomics]>;
1675
1676def LHARX : XForm_1<31,  116, (outs gprc:$rD), (ins memrr:$src),
1677                    "lharx $rD, $src", IIC_LdStLWARX, []>,
1678                    Requires<[HasPartwordAtomics]>;
1679
1680def LWARX : XForm_1<31,  20, (outs gprc:$rD), (ins memrr:$src),
1681                    "lwarx $rD, $src", IIC_LdStLWARX, []>;
1682
1683// Instructions to support lock versions of atomics
1684// (EH=1 - see Power ISA 2.07 Book II 4.4.2)
1685def LBARXL : XForm_1<31,  52, (outs gprc:$rD), (ins memrr:$src),
1686                     "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1687                     Requires<[HasPartwordAtomics]>;
1688
1689def LHARXL : XForm_1<31,  116, (outs gprc:$rD), (ins memrr:$src),
1690                     "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1691                     Requires<[HasPartwordAtomics]>;
1692
1693def LWARXL : XForm_1<31,  20, (outs gprc:$rD), (ins memrr:$src),
1694                     "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT;
1695
1696// The atomic instructions use the destination register as well as the next one
1697// or two registers in order (modulo 31).
1698let hasExtraSrcRegAllocReq = 1 in
1699def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC),
1700                         "lwat $rD, $rA, $FC", IIC_LdStLoad>,
1701           Requires<[IsISA3_0]>;
1702}
1703
1704let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in {
1705def STBCX : XForm_1<31, 694, (outs), (ins gprc:$rS, memrr:$dst),
1706                    "stbcx. $rS, $dst", IIC_LdStSTWCX, []>,
1707                    isDOT, Requires<[HasPartwordAtomics]>;
1708
1709def STHCX : XForm_1<31, 726, (outs), (ins gprc:$rS, memrr:$dst),
1710                    "sthcx. $rS, $dst", IIC_LdStSTWCX, []>,
1711                    isDOT, Requires<[HasPartwordAtomics]>;
1712
1713def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1714                    "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT;
1715}
1716
1717let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
1718def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC),
1719                          "stwat $rS, $rA, $FC", IIC_LdStStore>,
1720            Requires<[IsISA3_0]>;
1721
1722let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1723def TRAP  : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1724
1725def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1726                     "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1727def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1728                 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1729def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1730                     "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1731def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1732                 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1733
1734//===----------------------------------------------------------------------===//
1735// PPC32 Load Instructions.
1736//
1737
1738// Unindexed (r+i) Loads.
1739let PPC970_Unit = 2 in {
1740def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1741                  "lbz $rD, $src", IIC_LdStLoad,
1742                  [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1743def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1744                  "lha $rD, $src", IIC_LdStLHA,
1745                  [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1746                  PPC970_DGroup_Cracked;
1747def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1748                  "lhz $rD, $src", IIC_LdStLoad,
1749                  [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1750def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1751                  "lwz $rD, $src", IIC_LdStLoad,
1752                  [(set i32:$rD, (load iaddr:$src))]>;
1753
1754def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1755                  "lfs $rD, $src", IIC_LdStLFD,
1756                  [(set f32:$rD, (load iaddr:$src))]>;
1757def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1758                  "lfd $rD, $src", IIC_LdStLFD,
1759                  [(set f64:$rD, (load iaddr:$src))]>;
1760
1761
1762// Unindexed (r+i) Loads with Update (preinc).
1763let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {
1764def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1765                   "lbzu $rD, $addr", IIC_LdStLoadUpd,
1766                   []>, RegConstraint<"$addr.reg = $ea_result">,
1767                   NoEncode<"$ea_result">;
1768
1769def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1770                   "lhau $rD, $addr", IIC_LdStLHAU,
1771                   []>, RegConstraint<"$addr.reg = $ea_result">,
1772                   NoEncode<"$ea_result">;
1773
1774def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1775                   "lhzu $rD, $addr", IIC_LdStLoadUpd,
1776                   []>, RegConstraint<"$addr.reg = $ea_result">,
1777                   NoEncode<"$ea_result">;
1778
1779def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1780                   "lwzu $rD, $addr", IIC_LdStLoadUpd,
1781                   []>, RegConstraint<"$addr.reg = $ea_result">,
1782                   NoEncode<"$ea_result">;
1783
1784def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1785                  "lfsu $rD, $addr", IIC_LdStLFDU,
1786                  []>, RegConstraint<"$addr.reg = $ea_result">,
1787                   NoEncode<"$ea_result">;
1788
1789def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1790                  "lfdu $rD, $addr", IIC_LdStLFDU,
1791                  []>, RegConstraint<"$addr.reg = $ea_result">,
1792                   NoEncode<"$ea_result">;
1793
1794
1795// Indexed (r+r) Loads with Update (preinc).
1796def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1797                   (ins memrr:$addr),
1798                   "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1799                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1800                   NoEncode<"$ea_result">;
1801
1802def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1803                   (ins memrr:$addr),
1804                   "lhaux $rD, $addr", IIC_LdStLHAUX,
1805                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1806                   NoEncode<"$ea_result">;
1807
1808def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1809                   (ins memrr:$addr),
1810                   "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1811                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1812                   NoEncode<"$ea_result">;
1813
1814def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1815                   (ins memrr:$addr),
1816                   "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1817                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1818                   NoEncode<"$ea_result">;
1819
1820def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1821                   (ins memrr:$addr),
1822                   "lfsux $rD, $addr", IIC_LdStLFDUX,
1823                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1824                   NoEncode<"$ea_result">;
1825
1826def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1827                   (ins memrr:$addr),
1828                   "lfdux $rD, $addr", IIC_LdStLFDUX,
1829                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1830                   NoEncode<"$ea_result">;
1831}
1832}
1833
1834// Indexed (r+r) Loads.
1835//
1836let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in {
1837def LBZX : XForm_1<31,  87, (outs gprc:$rD), (ins memrr:$src),
1838                   "lbzx $rD, $src", IIC_LdStLoad,
1839                   [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1840def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1841                   "lhax $rD, $src", IIC_LdStLHA,
1842                   [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1843                   PPC970_DGroup_Cracked;
1844def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1845                   "lhzx $rD, $src", IIC_LdStLoad,
1846                   [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1847def LWZX : XForm_1<31,  23, (outs gprc:$rD), (ins memrr:$src),
1848                   "lwzx $rD, $src", IIC_LdStLoad,
1849                   [(set i32:$rD, (load xaddr:$src))]>;
1850def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1851                   "lhbrx $rD, $src", IIC_LdStLoad,
1852                   [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1853def LWBRX : XForm_1<31,  534, (outs gprc:$rD), (ins memrr:$src),
1854                   "lwbrx $rD, $src", IIC_LdStLoad,
1855                   [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1856
1857def LFSX   : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1858                      "lfsx $frD, $src", IIC_LdStLFD,
1859                      [(set f32:$frD, (load xaddr:$src))]>;
1860def LFDX   : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1861                      "lfdx $frD, $src", IIC_LdStLFD,
1862                      [(set f64:$frD, (load xaddr:$src))]>;
1863
1864def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1865                      "lfiwax $frD, $src", IIC_LdStLFD,
1866                      [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1867def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1868                      "lfiwzx $frD, $src", IIC_LdStLFD,
1869                      [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1870}
1871
1872// Load Multiple
1873def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1874                  "lmw $rD, $src", IIC_LdStLMW, []>;
1875
1876//===----------------------------------------------------------------------===//
1877// PPC32 Store Instructions.
1878//
1879
1880// Unindexed (r+i) Stores.
1881let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
1882def STB  : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1883                   "stb $rS, $src", IIC_LdStStore,
1884                   [(truncstorei8 i32:$rS, iaddr:$src)]>;
1885def STH  : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1886                   "sth $rS, $src", IIC_LdStStore,
1887                   [(truncstorei16 i32:$rS, iaddr:$src)]>;
1888def STW  : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1889                   "stw $rS, $src", IIC_LdStStore,
1890                   [(store i32:$rS, iaddr:$src)]>;
1891def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1892                   "stfs $rS, $dst", IIC_LdStSTFD,
1893                   [(store f32:$rS, iaddr:$dst)]>;
1894def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1895                   "stfd $rS, $dst", IIC_LdStSTFD,
1896                   [(store f64:$rS, iaddr:$dst)]>;
1897}
1898
1899// Unindexed (r+i) Stores with Update (preinc).
1900let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
1901def STBU  : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1902                    "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1903                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1904def STHU  : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1905                    "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1906                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1907def STWU  : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1908                    "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1909                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1910def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1911                    "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1912                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1913def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1914                    "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1915                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1916}
1917
1918// Patterns to match the pre-inc stores.  We can't put the patterns on
1919// the instruction definitions directly as ISel wants the address base
1920// and offset to be separate operands, not a single complex operand.
1921def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1922          (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1923def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1924          (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1925def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1926          (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1927def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1928          (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1929def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1930          (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1931
1932// Indexed (r+r) Stores.
1933let PPC970_Unit = 2 in {
1934def STBX  : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1935                   "stbx $rS, $dst", IIC_LdStStore,
1936                   [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1937                   PPC970_DGroup_Cracked;
1938def STHX  : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1939                   "sthx $rS, $dst", IIC_LdStStore,
1940                   [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1941                   PPC970_DGroup_Cracked;
1942def STWX  : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1943                   "stwx $rS, $dst", IIC_LdStStore,
1944                   [(store i32:$rS, xaddr:$dst)]>,
1945                   PPC970_DGroup_Cracked;
1946
1947def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1948                   "sthbrx $rS, $dst", IIC_LdStStore,
1949                   [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1950                   PPC970_DGroup_Cracked;
1951def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1952                   "stwbrx $rS, $dst", IIC_LdStStore,
1953                   [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1954                   PPC970_DGroup_Cracked;
1955
1956def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1957                     "stfiwx $frS, $dst", IIC_LdStSTFD,
1958                     [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1959
1960def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1961                     "stfsx $frS, $dst", IIC_LdStSTFD,
1962                     [(store f32:$frS, xaddr:$dst)]>;
1963def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1964                     "stfdx $frS, $dst", IIC_LdStSTFD,
1965                     [(store f64:$frS, xaddr:$dst)]>;
1966}
1967
1968// Indexed (r+r) Stores with Update (preinc).
1969let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
1970def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1971                    "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1972                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1973                    PPC970_DGroup_Cracked;
1974def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1975                    "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1976                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1977                    PPC970_DGroup_Cracked;
1978def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1979                    "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1980                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1981                    PPC970_DGroup_Cracked;
1982def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1983                    "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1984                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1985                    PPC970_DGroup_Cracked;
1986def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1987                    "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1988                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1989                    PPC970_DGroup_Cracked;
1990}
1991
1992// Patterns to match the pre-inc stores.  We can't put the patterns on
1993// the instruction definitions directly as ISel wants the address base
1994// and offset to be separate operands, not a single complex operand.
1995def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1996          (STBUX $rS, $ptrreg, $ptroff)>;
1997def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1998          (STHUX $rS, $ptrreg, $ptroff)>;
1999def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
2000          (STWUX $rS, $ptrreg, $ptroff)>;
2001def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
2002          (STFSUX $rS, $ptrreg, $ptroff)>;
2003def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
2004          (STFDUX $rS, $ptrreg, $ptroff)>;
2005
2006// Store Multiple
2007def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
2008                   "stmw $rS, $dst", IIC_LdStLMW, []>;
2009
2010def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
2011                        "sync $L", IIC_LdStSync, []>;
2012
2013let isCodeGenOnly = 1 in {
2014  def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
2015                           "msync", IIC_LdStSync, []> {
2016    let L = 0;
2017  }
2018}
2019
2020def : Pat<(int_ppc_sync),   (SYNC 0)>, Requires<[HasSYNC]>;
2021def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
2022def : Pat<(int_ppc_sync),   (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2023def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2024
2025//===----------------------------------------------------------------------===//
2026// PPC32 Arithmetic Instructions.
2027//
2028
2029let PPC970_Unit = 1 in {  // FXU Operations.
2030def ADDI   : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
2031                     "addi $rD, $rA, $imm", IIC_IntSimple,
2032                     [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
2033let BaseName = "addic" in {
2034let Defs = [CARRY] in
2035def ADDIC  : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
2036                     "addic $rD, $rA, $imm", IIC_IntGeneral,
2037                     [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
2038                     RecFormRel, PPC970_DGroup_Cracked;
2039let Defs = [CARRY, CR0] in
2040def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
2041                     "addic. $rD, $rA, $imm", IIC_IntGeneral,
2042                     []>, isDOT, RecFormRel;
2043}
2044def ADDIS  : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
2045                     "addis $rD, $rA, $imm", IIC_IntSimple,
2046                     [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
2047let isCodeGenOnly = 1 in
2048def LA     : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
2049                     "la $rD, $sym($rA)", IIC_IntGeneral,
2050                     [(set i32:$rD, (add i32:$rA,
2051                                          (PPClo tglobaladdr:$sym, 0)))]>;
2052def MULLI  : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
2053                     "mulli $rD, $rA, $imm", IIC_IntMulLI,
2054                     [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
2055let Defs = [CARRY] in
2056def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
2057                     "subfic $rD, $rA, $imm", IIC_IntGeneral,
2058                     [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
2059
2060let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
2061  def LI  : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
2062                       "li $rD, $imm", IIC_IntSimple,
2063                       [(set i32:$rD, imm32SExt16:$imm)]>;
2064  def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
2065                       "lis $rD, $imm", IIC_IntSimple,
2066                       [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
2067}
2068}
2069
2070let PPC970_Unit = 1 in {  // FXU Operations.
2071let Defs = [CR0] in {
2072def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2073                    "andi. $dst, $src1, $src2", IIC_IntGeneral,
2074                    [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
2075                    isDOT;
2076def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2077                    "andis. $dst, $src1, $src2", IIC_IntGeneral,
2078                    [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
2079                    isDOT;
2080}
2081def ORI   : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2082                    "ori $dst, $src1, $src2", IIC_IntSimple,
2083                    [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
2084def ORIS  : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2085                    "oris $dst, $src1, $src2", IIC_IntSimple,
2086                    [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
2087def XORI  : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2088                    "xori $dst, $src1, $src2", IIC_IntSimple,
2089                    [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
2090def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
2091                    "xoris $dst, $src1, $src2", IIC_IntSimple,
2092                    [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
2093
2094def NOP   : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
2095                         []>;
2096let isCodeGenOnly = 1 in {
2097// The POWER6 and POWER7 have special group-terminating nops.
2098def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
2099                                        "ori 1, 1, 0", IIC_IntSimple, []>;
2100def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
2101                                        "ori 2, 2, 0", IIC_IntSimple, []>;
2102}
2103
2104let isCompare = 1, hasSideEffects = 0 in {
2105  def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
2106                          "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
2107  def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
2108                           "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
2109  def CMPRB  : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF),
2110                                (ins u1imm:$L, g8rc:$rA, g8rc:$rB),
2111                                "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>,
2112               Requires<[IsISA3_0]>;
2113}
2114}
2115
2116let PPC970_Unit = 1, hasSideEffects = 0 in {  // FXU Operations.
2117let isCommutable = 1 in {
2118defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2119                     "nand", "$rA, $rS, $rB", IIC_IntSimple,
2120                     [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
2121defm AND  : XForm_6r<31,  28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2122                     "and", "$rA, $rS, $rB", IIC_IntSimple,
2123                     [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
2124} // isCommutable
2125defm ANDC : XForm_6r<31,  60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2126                     "andc", "$rA, $rS, $rB", IIC_IntSimple,
2127                     [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
2128let isCommutable = 1 in {
2129defm OR   : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2130                     "or", "$rA, $rS, $rB", IIC_IntSimple,
2131                     [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
2132defm NOR  : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2133                     "nor", "$rA, $rS, $rB", IIC_IntSimple,
2134                     [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
2135} // isCommutable
2136defm ORC  : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2137                     "orc", "$rA, $rS, $rB", IIC_IntSimple,
2138                     [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
2139let isCommutable = 1 in {
2140defm EQV  : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2141                     "eqv", "$rA, $rS, $rB", IIC_IntSimple,
2142                     [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
2143defm XOR  : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2144                     "xor", "$rA, $rS, $rB", IIC_IntSimple,
2145                     [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
2146} // isCommutable
2147defm SLW  : XForm_6r<31,  24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2148                     "slw", "$rA, $rS, $rB", IIC_IntGeneral,
2149                     [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
2150defm SRW  : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2151                     "srw", "$rA, $rS, $rB", IIC_IntGeneral,
2152                     [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
2153defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2154                      "sraw", "$rA, $rS, $rB", IIC_IntShift,
2155                      [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
2156}
2157
2158let PPC970_Unit = 1 in {  // FXU Operations.
2159let hasSideEffects = 0 in {
2160defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
2161                        "srawi", "$rA, $rS, $SH", IIC_IntShift,
2162                        [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
2163defm CNTLZW : XForm_11r<31,  26, (outs gprc:$rA), (ins gprc:$rS),
2164                        "cntlzw", "$rA, $rS", IIC_IntGeneral,
2165                        [(set i32:$rA, (ctlz i32:$rS))]>;
2166defm CNTTZW : XForm_11r<31, 538, (outs gprc:$rA), (ins gprc:$rS),
2167                        "cnttzw", "$rA, $rS", IIC_IntGeneral,
2168                        [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>;
2169defm EXTSB  : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
2170                        "extsb", "$rA, $rS", IIC_IntSimple,
2171                        [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
2172defm EXTSH  : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
2173                        "extsh", "$rA, $rS", IIC_IntSimple,
2174                        [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
2175
2176let isCommutable = 1 in
2177def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2178                   "cmpb $rA, $rS, $rB", IIC_IntGeneral,
2179                   [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>;
2180}
2181let isCompare = 1, hasSideEffects = 0 in {
2182  def CMPW   : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
2183                            "cmpw $crD, $rA, $rB", IIC_IntCompare>;
2184  def CMPLW  : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
2185                            "cmplw $crD, $rA, $rB", IIC_IntCompare>;
2186}
2187}
2188let PPC970_Unit = 3 in {  // FPU Operations.
2189//def FCMPO  : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
2190//                      "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
2191let isCompare = 1, hasSideEffects = 0 in {
2192  def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
2193                        "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
2194  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2195  def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
2196                        "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
2197}
2198
2199def FTDIV: XForm_17<63, 128, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
2200                      "ftdiv $crD, $fA, $fB", IIC_FPCompare>;
2201def FTSQRT: XForm_17a<63, 160, (outs crrc:$crD), (ins f8rc:$fB),
2202                      "ftsqrt $crD, $fB", IIC_FPCompare>;
2203
2204let Uses = [RM] in {
2205  let hasSideEffects = 0 in {
2206  defm FCTIW  : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
2207                          "fctiw", "$frD, $frB", IIC_FPGeneral,
2208                          []>;
2209  defm FCTIWU  : XForm_26r<63, 142, (outs f8rc:$frD), (ins f8rc:$frB),
2210                          "fctiwu", "$frD, $frB", IIC_FPGeneral,
2211                          []>;
2212  defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
2213                          "fctiwz", "$frD, $frB", IIC_FPGeneral,
2214                          [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
2215
2216  defm FRSP   : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
2217                          "frsp", "$frD, $frB", IIC_FPGeneral,
2218                          [(set f32:$frD, (fpround f64:$frB))]>;
2219
2220  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2221  defm FRIND  : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
2222                          "frin", "$frD, $frB", IIC_FPGeneral,
2223                          [(set f64:$frD, (fround f64:$frB))]>;
2224  defm FRINS  : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
2225                          "frin", "$frD, $frB", IIC_FPGeneral,
2226                          [(set f32:$frD, (fround f32:$frB))]>;
2227  }
2228
2229  let hasSideEffects = 0 in {
2230  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2231  defm FRIPD  : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
2232                          "frip", "$frD, $frB", IIC_FPGeneral,
2233                          [(set f64:$frD, (fceil f64:$frB))]>;
2234  defm FRIPS  : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
2235                          "frip", "$frD, $frB", IIC_FPGeneral,
2236                          [(set f32:$frD, (fceil f32:$frB))]>;
2237  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2238  defm FRIZD  : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
2239                          "friz", "$frD, $frB", IIC_FPGeneral,
2240                          [(set f64:$frD, (ftrunc f64:$frB))]>;
2241  defm FRIZS  : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
2242                          "friz", "$frD, $frB", IIC_FPGeneral,
2243                          [(set f32:$frD, (ftrunc f32:$frB))]>;
2244  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2245  defm FRIMD  : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
2246                          "frim", "$frD, $frB", IIC_FPGeneral,
2247                          [(set f64:$frD, (ffloor f64:$frB))]>;
2248  defm FRIMS  : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
2249                          "frim", "$frD, $frB", IIC_FPGeneral,
2250                          [(set f32:$frD, (ffloor f32:$frB))]>;
2251
2252  defm FSQRT  : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
2253                          "fsqrt", "$frD, $frB", IIC_FPSqrtD,
2254                          [(set f64:$frD, (fsqrt f64:$frB))]>;
2255  defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
2256                          "fsqrts", "$frD, $frB", IIC_FPSqrtS,
2257                          [(set f32:$frD, (fsqrt f32:$frB))]>;
2258  }
2259  }
2260}
2261
2262/// Note that FMR is defined as pseudo-ops on the PPC970 because they are
2263/// often coalesced away and we don't want the dispatch group builder to think
2264/// that they will fill slots (which could cause the load of a LSU reject to
2265/// sneak into a d-group with a store).
2266let hasSideEffects = 0 in
2267defm FMR   : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
2268                       "fmr", "$frD, $frB", IIC_FPGeneral,
2269                       []>,  // (set f32:$frD, f32:$frB)
2270                       PPC970_Unit_Pseudo;
2271
2272let PPC970_Unit = 3, hasSideEffects = 0 in {  // FPU Operations.
2273// These are artificially split into two different forms, for 4/8 byte FP.
2274defm FABSS  : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
2275                        "fabs", "$frD, $frB", IIC_FPGeneral,
2276                        [(set f32:$frD, (fabs f32:$frB))]>;
2277let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2278defm FABSD  : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
2279                        "fabs", "$frD, $frB", IIC_FPGeneral,
2280                        [(set f64:$frD, (fabs f64:$frB))]>;
2281defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
2282                        "fnabs", "$frD, $frB", IIC_FPGeneral,
2283                        [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
2284let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2285defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
2286                        "fnabs", "$frD, $frB", IIC_FPGeneral,
2287                        [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
2288defm FNEGS  : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
2289                        "fneg", "$frD, $frB", IIC_FPGeneral,
2290                        [(set f32:$frD, (fneg f32:$frB))]>;
2291let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2292defm FNEGD  : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
2293                        "fneg", "$frD, $frB", IIC_FPGeneral,
2294                        [(set f64:$frD, (fneg f64:$frB))]>;
2295
2296defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
2297                        "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2298                        [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
2299let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2300defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
2301                        "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2302                        [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
2303
2304// Reciprocal estimates.
2305defm FRE      : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
2306                          "fre", "$frD, $frB", IIC_FPGeneral,
2307                          [(set f64:$frD, (PPCfre f64:$frB))]>;
2308defm FRES     : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
2309                          "fres", "$frD, $frB", IIC_FPGeneral,
2310                          [(set f32:$frD, (PPCfre f32:$frB))]>;
2311defm FRSQRTE  : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
2312                          "frsqrte", "$frD, $frB", IIC_FPGeneral,
2313                          [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
2314defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
2315                          "frsqrtes", "$frD, $frB", IIC_FPGeneral,
2316                          [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
2317}
2318
2319// XL-Form instructions.  condition register logical ops.
2320//
2321let hasSideEffects = 0 in
2322def MCRF   : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
2323                      "mcrf $BF, $BFA", IIC_BrMCR>,
2324             PPC970_DGroup_First, PPC970_Unit_CRU;
2325
2326// FIXME: According to the ISA (section 2.5.1 of version 2.06), the
2327// condition-register logical instructions have preferred forms. Specifically,
2328// it is preferred that the bit specified by the BT field be in the same
2329// condition register as that specified by the bit BB. We might want to account
2330// for this via hinting the register allocator and anti-dep breakers, or we
2331// could constrain the register class to force this constraint and then loosen
2332// it during register allocation via convertToThreeAddress or some similar
2333// mechanism.
2334
2335let isCommutable = 1 in {
2336def CRAND  : XLForm_1<19, 257, (outs crbitrc:$CRD),
2337                               (ins crbitrc:$CRA, crbitrc:$CRB),
2338                      "crand $CRD, $CRA, $CRB", IIC_BrCR,
2339                      [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2340
2341def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2342                               (ins crbitrc:$CRA, crbitrc:$CRB),
2343                      "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2344                      [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2345
2346def CROR   : XLForm_1<19, 449, (outs crbitrc:$CRD),
2347                               (ins crbitrc:$CRA, crbitrc:$CRB),
2348                      "cror $CRD, $CRA, $CRB", IIC_BrCR,
2349                      [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2350
2351def CRXOR  : XLForm_1<19, 193, (outs crbitrc:$CRD),
2352                               (ins crbitrc:$CRA, crbitrc:$CRB),
2353                      "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2354                      [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2355
2356def CRNOR  : XLForm_1<19, 33, (outs crbitrc:$CRD),
2357                              (ins crbitrc:$CRA, crbitrc:$CRB),
2358                      "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2359                      [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2360
2361def CREQV  : XLForm_1<19, 289, (outs crbitrc:$CRD),
2362                               (ins crbitrc:$CRA, crbitrc:$CRB),
2363                      "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2364                      [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2365} // isCommutable
2366
2367def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2368                               (ins crbitrc:$CRA, crbitrc:$CRB),
2369                      "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2370                      [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2371
2372def CRORC  : XLForm_1<19, 417, (outs crbitrc:$CRD),
2373                               (ins crbitrc:$CRA, crbitrc:$CRB),
2374                      "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2375                      [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2376
2377let isCodeGenOnly = 1 in {
2378def CRSET  : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2379              "creqv $dst, $dst, $dst", IIC_BrCR,
2380              [(set i1:$dst, 1)]>;
2381
2382def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2383              "crxor $dst, $dst, $dst", IIC_BrCR,
2384              [(set i1:$dst, 0)]>;
2385
2386let Defs = [CR1EQ], CRD = 6 in {
2387def CR6SET  : XLForm_1_ext<19, 289, (outs), (ins),
2388              "creqv 6, 6, 6", IIC_BrCR,
2389              [(PPCcr6set)]>;
2390
2391def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2392              "crxor 6, 6, 6", IIC_BrCR,
2393              [(PPCcr6unset)]>;
2394}
2395}
2396
2397// XFX-Form instructions.  Instructions that deal with SPRs.
2398//
2399
2400def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2401                      "mfspr $RT, $SPR", IIC_SprMFSPR>;
2402def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2403                      "mtspr $SPR, $RT", IIC_SprMTSPR>;
2404
2405def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2406                     "mftb $RT, $SPR", IIC_SprMFTB>;
2407
2408def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR),
2409                     "mfpmr $RT, $SPR", IIC_SprMFPMR>;
2410
2411def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT),
2412                     "mtpmr $SPR, $RT", IIC_SprMTPMR>;
2413
2414
2415// A pseudo-instruction used to implement the read of the 64-bit cycle counter
2416// on a 32-bit target.
2417let hasSideEffects = 1, usesCustomInserter = 1 in
2418def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins),
2419                    "#ReadTB", []>;
2420
2421let Uses = [CTR] in {
2422def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2423                          "mfctr $rT", IIC_SprMFSPR>,
2424            PPC970_DGroup_First, PPC970_Unit_FXU;
2425}
2426let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2427def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2428                          "mtctr $rS", IIC_SprMTSPR>,
2429            PPC970_DGroup_First, PPC970_Unit_FXU;
2430}
2431let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2432let Pattern = [(int_ppc_mtctr i32:$rS)] in
2433def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2434                              "mtctr $rS", IIC_SprMTSPR>,
2435                PPC970_DGroup_First, PPC970_Unit_FXU;
2436}
2437
2438let Defs = [LR] in {
2439def MTLR  : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2440                          "mtlr $rS", IIC_SprMTSPR>,
2441            PPC970_DGroup_First, PPC970_Unit_FXU;
2442}
2443let Uses = [LR] in {
2444def MFLR  : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2445                          "mflr $rT", IIC_SprMFSPR>,
2446            PPC970_DGroup_First, PPC970_Unit_FXU;
2447}
2448
2449let isCodeGenOnly = 1 in {
2450  // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2451  // like a GPR on the PPC970.  As such, copies in and out have the same
2452  // performance characteristics as an OR instruction.
2453  def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2454                               "mtspr 256, $rS", IIC_IntGeneral>,
2455                 PPC970_DGroup_Single, PPC970_Unit_FXU;
2456  def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2457                               "mfspr $rT, 256", IIC_IntGeneral>,
2458                 PPC970_DGroup_First, PPC970_Unit_FXU;
2459
2460  def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2461                                (outs VRSAVERC:$reg), (ins gprc:$rS),
2462                                "mtspr 256, $rS", IIC_IntGeneral>,
2463                  PPC970_DGroup_Single, PPC970_Unit_FXU;
2464  def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2465                                (ins VRSAVERC:$reg),
2466                                "mfspr $rT, 256", IIC_IntGeneral>,
2467                  PPC970_DGroup_First, PPC970_Unit_FXU;
2468}
2469
2470// Aliases for mtvrsave/mfvrsave to mfspr/mtspr.
2471def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>;
2472def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>;
2473
2474// SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2475// so we'll need to scavenge a register for it.
2476let mayStore = 1 in
2477def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2478                     "#SPILL_VRSAVE", []>;
2479
2480// RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2481// spilled), so we'll need to scavenge a register for it.
2482let mayLoad = 1 in
2483def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2484                     "#RESTORE_VRSAVE", []>;
2485
2486let hasSideEffects = 0 in {
2487// mtocrf's input needs to be prepared by shifting by an amount dependent
2488// on the cr register selected. Thus, post-ra anti-dep breaking must not
2489// later change that register assignment.
2490let hasExtraDefRegAllocReq = 1 in {
2491def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2492                       "mtocrf $FXM, $ST", IIC_BrMCRX>,
2493            PPC970_DGroup_First, PPC970_Unit_CRU;
2494
2495// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that
2496// is dependent on the cr fields being set.
2497def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2498                      "mtcrf $FXM, $rS", IIC_BrMCRX>,
2499            PPC970_MicroCode, PPC970_Unit_CRU;
2500} // hasExtraDefRegAllocReq = 1
2501
2502// mfocrf's input needs to be prepared by shifting by an amount dependent
2503// on the cr register selected. Thus, post-ra anti-dep breaking must not
2504// later change that register assignment.
2505let hasExtraSrcRegAllocReq = 1 in {
2506def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2507                       "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2508            PPC970_DGroup_First, PPC970_Unit_CRU;
2509
2510// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that
2511// is dependent on the cr fields being copied.
2512def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2513                     "mfcr $rT", IIC_SprMFCR>,
2514                     PPC970_MicroCode, PPC970_Unit_CRU;
2515} // hasExtraSrcRegAllocReq = 1
2516
2517def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins),
2518                   "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>;
2519} // hasSideEffects = 0
2520
2521// Pseudo instruction to perform FADD in round-to-zero mode.
2522let usesCustomInserter = 1, Uses = [RM] in {
2523  def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2524                      [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2525}
2526
2527// The above pseudo gets expanded to make use of the following instructions
2528// to manipulate FPSCR.  Note that FPSCR is not modeled at the DAG level.
2529let Uses = [RM], Defs = [RM] in {
2530  def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2531                        "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2532               PPC970_DGroup_Single, PPC970_Unit_FPU;
2533  def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2534                        "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2535               PPC970_DGroup_Single, PPC970_Unit_FPU;
2536  let isCodeGenOnly = 1 in
2537  def MTFSFb  : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2538                        "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2539                PPC970_DGroup_Single, PPC970_Unit_FPU;
2540}
2541let Uses = [RM] in {
2542  def MFFS   : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2543                         "mffs $rT", IIC_IntMFFS,
2544                         [(set f64:$rT, (PPCmffs))]>,
2545               PPC970_DGroup_Single, PPC970_Unit_FPU;
2546
2547  let Defs = [CR1] in
2548  def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2549                      "mffs. $rT", IIC_IntMFFS, []>, isDOT;
2550}
2551
2552let Predicates = [IsISA3_0] in {
2553def MODSW : XForm_8<31, 779, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2554                        "modsw $rT, $rA, $rB", IIC_IntDivW,
2555                        [(set i32:$rT, (srem i32:$rA, i32:$rB))]>;
2556def MODUW : XForm_8<31, 267, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2557                        "moduw $rT, $rA, $rB", IIC_IntDivW,
2558                        [(set i32:$rT, (urem i32:$rA, i32:$rB))]>;
2559}
2560
2561let PPC970_Unit = 1, hasSideEffects = 0 in {  // FXU Operations.
2562// XO-Form instructions.  Arithmetic instructions that can set overflow bit
2563let isCommutable = 1 in
2564defm ADD4  : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2565                       "add", "$rT, $rA, $rB", IIC_IntSimple,
2566                       [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2567let isCodeGenOnly = 1 in
2568def ADD4TLS  : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2569                       "add $rT, $rA, $rB", IIC_IntSimple,
2570                       [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2571let isCommutable = 1 in
2572defm ADDC  : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2573                        "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2574                        [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2575                        PPC970_DGroup_Cracked;
2576
2577defm DIVW  : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2578                          "divw", "$rT, $rA, $rB", IIC_IntDivW,
2579                          [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>;
2580defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2581                          "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2582                          [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>;
2583def DIVWE : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2584                     "divwe $rT, $rA, $rB", IIC_IntDivW,
2585                     [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>,
2586                     Requires<[HasExtDiv]>;
2587let Defs = [CR0] in
2588def DIVWEo : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2589                      "divwe. $rT, $rA, $rB", IIC_IntDivW,
2590                      []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2591                      Requires<[HasExtDiv]>;
2592def DIVWEU : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2593                      "divweu $rT, $rA, $rB", IIC_IntDivW,
2594                      [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>,
2595                      Requires<[HasExtDiv]>;
2596let Defs = [CR0] in
2597def DIVWEUo : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2598                       "divweu. $rT, $rA, $rB", IIC_IntDivW,
2599                       []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2600                       Requires<[HasExtDiv]>;
2601let isCommutable = 1 in {
2602defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2603                       "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2604                       [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2605defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2606                       "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2607                       [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2608defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2609                       "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2610                       [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2611} // isCommutable
2612defm SUBF  : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2613                       "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2614                       [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2615defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2616                        "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2617                        [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2618                        PPC970_DGroup_Cracked;
2619defm NEG    : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2620                        "neg", "$rT, $rA", IIC_IntSimple,
2621                        [(set i32:$rT, (ineg i32:$rA))]>;
2622let Uses = [CARRY] in {
2623let isCommutable = 1 in
2624defm ADDE  : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2625                        "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2626                        [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2627defm ADDME  : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2628                         "addme", "$rT, $rA", IIC_IntGeneral,
2629                         [(set i32:$rT, (adde i32:$rA, -1))]>;
2630defm ADDZE  : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2631                         "addze", "$rT, $rA", IIC_IntGeneral,
2632                         [(set i32:$rT, (adde i32:$rA, 0))]>;
2633defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2634                        "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2635                        [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2636defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2637                         "subfme", "$rT, $rA", IIC_IntGeneral,
2638                         [(set i32:$rT, (sube -1, i32:$rA))]>;
2639defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2640                         "subfze", "$rT, $rA", IIC_IntGeneral,
2641                         [(set i32:$rT, (sube 0, i32:$rA))]>;
2642}
2643}
2644
2645// A-Form instructions.  Most of the instructions executed in the FPU are of
2646// this type.
2647//
2648let PPC970_Unit = 3, hasSideEffects = 0 in {  // FPU Operations.
2649let Uses = [RM] in {
2650let isCommutable = 1 in {
2651  defm FMADD : AForm_1r<63, 29,
2652                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2653                      "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2654                      [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2655  defm FMADDS : AForm_1r<59, 29,
2656                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2657                      "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2658                      [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2659  defm FMSUB : AForm_1r<63, 28,
2660                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2661                      "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2662                      [(set f64:$FRT,
2663                            (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2664  defm FMSUBS : AForm_1r<59, 28,
2665                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2666                      "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2667                      [(set f32:$FRT,
2668                            (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2669  defm FNMADD : AForm_1r<63, 31,
2670                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2671                      "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2672                      [(set f64:$FRT,
2673                            (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2674  defm FNMADDS : AForm_1r<59, 31,
2675                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2676                      "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2677                      [(set f32:$FRT,
2678                            (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2679  defm FNMSUB : AForm_1r<63, 30,
2680                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2681                      "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2682                      [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2683                                                 (fneg f64:$FRB))))]>;
2684  defm FNMSUBS : AForm_1r<59, 30,
2685                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2686                      "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2687                      [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2688                                                 (fneg f32:$FRB))))]>;
2689} // isCommutable
2690}
2691// FSEL is artificially split into 4 and 8-byte forms for the result.  To avoid
2692// having 4 of these, force the comparison to always be an 8-byte double (code
2693// should use an FMRSD if the input comparison value really wants to be a float)
2694// and 4/8 byte forms for the result and operand type..
2695let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2696defm FSELD : AForm_1r<63, 23,
2697                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2698                      "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2699                      [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2700defm FSELS : AForm_1r<63, 23,
2701                      (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2702                      "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2703                      [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2704let Uses = [RM] in {
2705  let isCommutable = 1 in {
2706  defm FADD  : AForm_2r<63, 21,
2707                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2708                        "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2709                        [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2710  defm FADDS : AForm_2r<59, 21,
2711                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2712                        "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2713                        [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2714  } // isCommutable
2715  defm FDIV  : AForm_2r<63, 18,
2716                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2717                        "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2718                        [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2719  defm FDIVS : AForm_2r<59, 18,
2720                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2721                        "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2722                        [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2723  let isCommutable = 1 in {
2724  defm FMUL  : AForm_3r<63, 25,
2725                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2726                        "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2727                        [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2728  defm FMULS : AForm_3r<59, 25,
2729                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2730                        "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2731                        [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2732  } // isCommutable
2733  defm FSUB  : AForm_2r<63, 20,
2734                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2735                        "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2736                        [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2737  defm FSUBS : AForm_2r<59, 20,
2738                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2739                        "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2740                        [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2741  }
2742}
2743
2744let hasSideEffects = 0 in {
2745let PPC970_Unit = 1 in {  // FXU Operations.
2746  let isSelect = 1 in
2747  def ISEL  : AForm_4<31, 15,
2748                     (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2749                     "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
2750                     []>;
2751}
2752
2753let PPC970_Unit = 1 in {  // FXU Operations.
2754// M-Form instructions.  rotate and mask instructions.
2755//
2756let isCommutable = 1 in {
2757// RLWIMI can be commuted if the rotate amount is zero.
2758defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2759                       (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2760                       u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2761                       IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2762                       RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2763}
2764let BaseName = "rlwinm" in {
2765def RLWINM : MForm_2<21,
2766                     (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2767                     "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2768                     []>, RecFormRel;
2769let Defs = [CR0] in
2770def RLWINMo : MForm_2<21,
2771                      (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2772                      "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2773                      []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2774}
2775defm RLWNM  : MForm_2r<23, (outs gprc:$rA),
2776                       (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2777                       "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2778                       []>;
2779}
2780} // hasSideEffects = 0
2781
2782//===----------------------------------------------------------------------===//
2783// PowerPC Instruction Patterns
2784//
2785
2786// Arbitrary immediate support.  Implement in terms of LIS/ORI.
2787def : Pat<(i32 imm:$imm),
2788          (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2789
2790// Implement the 'not' operation with the NOR instruction.
2791def i32not : OutPatFrag<(ops node:$in),
2792                        (NOR $in, $in)>;
2793def        : Pat<(not i32:$in),
2794                 (i32not $in)>;
2795
2796// ADD an arbitrary immediate.
2797def : Pat<(add i32:$in, imm:$imm),
2798          (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2799// OR an arbitrary immediate.
2800def : Pat<(or i32:$in, imm:$imm),
2801          (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2802// XOR an arbitrary immediate.
2803def : Pat<(xor i32:$in, imm:$imm),
2804          (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2805// SUBFIC
2806def : Pat<(sub imm32SExt16:$imm, i32:$in),
2807          (SUBFIC $in, imm:$imm)>;
2808
2809// SHL/SRL
2810def : Pat<(shl i32:$in, (i32 imm:$imm)),
2811          (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2812def : Pat<(srl i32:$in, (i32 imm:$imm)),
2813          (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2814
2815// ROTL
2816def : Pat<(rotl i32:$in, i32:$sh),
2817          (RLWNM $in, $sh, 0, 31)>;
2818def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2819          (RLWINM $in, imm:$imm, 0, 31)>;
2820
2821// RLWNM
2822def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2823          (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2824
2825// Calls
2826def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2827          (BL tglobaladdr:$dst)>;
2828def : Pat<(PPCcall (i32 texternalsym:$dst)),
2829          (BL texternalsym:$dst)>;
2830
2831def : Pat<(PPCtc_return (i32 tglobaladdr:$dst),  imm:$imm),
2832          (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2833
2834def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2835          (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2836
2837def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2838          (TCRETURNri CTRRC:$dst, imm:$imm)>;
2839
2840
2841
2842// Hi and Lo for Darwin Global Addresses.
2843def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2844def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2845def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2846def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2847def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2848def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2849def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2850def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2851def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2852          (ADDIS $in, tglobaltlsaddr:$g)>;
2853def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2854          (ADDI $in, tglobaltlsaddr:$g)>;
2855def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2856          (ADDIS $in, tglobaladdr:$g)>;
2857def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2858          (ADDIS $in, tconstpool:$g)>;
2859def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2860          (ADDIS $in, tjumptable:$g)>;
2861def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2862          (ADDIS $in, tblockaddress:$g)>;
2863
2864// Support for thread-local storage.
2865def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2866                [(set i32:$rD, (PPCppc32GOT))]>;
2867
2868// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2869// This uses two output registers, the first as the real output, the second as a
2870// temporary register, used internally in code generation.
2871def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2872                []>, NoEncode<"$rT">;
2873
2874def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2875                           "#LDgotTprelL32",
2876                           [(set i32:$rD,
2877                             (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2878def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2879          (ADD4TLS $in, tglobaltlsaddr:$g)>;
2880
2881def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2882                         "#ADDItlsgdL32",
2883                         [(set i32:$rD,
2884                           (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2885// LR is a true define, while the rest of the Defs are clobbers.  R3 is
2886// explicitly defined when this op is created, so not mentioned here.
2887let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2888    Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2889def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2890                          "GETtlsADDR32",
2891                          [(set i32:$rD,
2892                            (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2893// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded.  R3 and LR
2894// are true defines while the rest of the Defs are clobbers.
2895let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2896    Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2897def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD),
2898                              (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2899                              "#ADDItlsgdLADDR32",
2900                              [(set i32:$rD,
2901                                (PPCaddiTlsgdLAddr i32:$reg,
2902                                                   tglobaltlsaddr:$disp,
2903                                                   tglobaltlsaddr:$sym))]>;
2904def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2905                          "#ADDItlsldL32",
2906                          [(set i32:$rD,
2907                            (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2908// LR is a true define, while the rest of the Defs are clobbers.  R3 is
2909// explicitly defined when this op is created, so not mentioned here.
2910let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2911    Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2912def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2913                            "GETtlsldADDR32",
2914                            [(set i32:$rD,
2915                              (PPCgetTlsldAddr i32:$reg,
2916                                               tglobaltlsaddr:$sym))]>;
2917// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded.  R3 and LR
2918// are true defines while the rest of the Defs are clobbers.
2919let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2920    Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2921def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD),
2922                              (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2923                              "#ADDItlsldLADDR32",
2924                              [(set i32:$rD,
2925                                (PPCaddiTlsldLAddr i32:$reg,
2926                                                   tglobaltlsaddr:$disp,
2927                                                   tglobaltlsaddr:$sym))]>;
2928def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2929                           "#ADDIdtprelL32",
2930                           [(set i32:$rD,
2931                             (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2932def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2933                            "#ADDISdtprelHA32",
2934                            [(set i32:$rD,
2935                              (PPCaddisDtprelHA i32:$reg,
2936                                                tglobaltlsaddr:$disp))]>;
2937
2938// Support for Position-independent code
2939def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2940                   "#LWZtoc",
2941                   [(set i32:$rD,
2942                      (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2943// Get Global (GOT) Base Register offset, from the word immediately preceding
2944// the function label.
2945def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2946
2947
2948// Standard shifts.  These are represented separately from the real shifts above
2949// so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2950// amounts.
2951def : Pat<(sra i32:$rS, i32:$rB),
2952          (SRAW $rS, $rB)>;
2953def : Pat<(srl i32:$rS, i32:$rB),
2954          (SRW $rS, $rB)>;
2955def : Pat<(shl i32:$rS, i32:$rB),
2956          (SLW $rS, $rB)>;
2957
2958def : Pat<(zextloadi1 iaddr:$src),
2959          (LBZ iaddr:$src)>;
2960def : Pat<(zextloadi1 xaddr:$src),
2961          (LBZX xaddr:$src)>;
2962def : Pat<(extloadi1 iaddr:$src),
2963          (LBZ iaddr:$src)>;
2964def : Pat<(extloadi1 xaddr:$src),
2965          (LBZX xaddr:$src)>;
2966def : Pat<(extloadi8 iaddr:$src),
2967          (LBZ iaddr:$src)>;
2968def : Pat<(extloadi8 xaddr:$src),
2969          (LBZX xaddr:$src)>;
2970def : Pat<(extloadi16 iaddr:$src),
2971          (LHZ iaddr:$src)>;
2972def : Pat<(extloadi16 xaddr:$src),
2973          (LHZX xaddr:$src)>;
2974def : Pat<(f64 (extloadf32 iaddr:$src)),
2975          (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2976def : Pat<(f64 (extloadf32 xaddr:$src)),
2977          (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2978
2979def : Pat<(f64 (fpextend f32:$src)),
2980          (COPY_TO_REGCLASS $src, F8RC)>;
2981
2982// Only seq_cst fences require the heavyweight sync (SYNC 0).
2983// All others can use the lightweight sync (SYNC 1).
2984// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
2985// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
2986// versions of Power.
2987def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2988def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2989def : Pat<(atomic_fence (imm),   (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
2990def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2991
2992// Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2993def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2994          (FNMSUB $A, $C, $B)>;
2995def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2996          (FNMSUB $A, $C, $B)>;
2997def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2998          (FNMSUBS $A, $C, $B)>;
2999def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
3000          (FNMSUBS $A, $C, $B)>;
3001
3002// FCOPYSIGN's operand types need not agree.
3003def : Pat<(fcopysign f64:$frB, f32:$frA),
3004          (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
3005def : Pat<(fcopysign f32:$frB, f64:$frA),
3006          (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
3007
3008include "PPCInstrAltivec.td"
3009include "PPCInstrSPE.td"
3010include "PPCInstr64Bit.td"
3011include "PPCInstrVSX.td"
3012include "PPCInstrQPX.td"
3013include "PPCInstrHTM.td"
3014
3015def crnot : OutPatFrag<(ops node:$in),
3016                       (CRNOR $in, $in)>;
3017def       : Pat<(not i1:$in),
3018                (crnot $in)>;
3019
3020// Patterns for arithmetic i1 operations.
3021def : Pat<(add i1:$a, i1:$b),
3022          (CRXOR $a, $b)>;
3023def : Pat<(sub i1:$a, i1:$b),
3024          (CRXOR $a, $b)>;
3025def : Pat<(mul i1:$a, i1:$b),
3026          (CRAND $a, $b)>;
3027
3028// We're sometimes asked to materialize i1 -1, which is just 1 in this case
3029// (-1 is used to mean all bits set).
3030def : Pat<(i1 -1), (CRSET)>;
3031
3032// i1 extensions, implemented in terms of isel.
3033def : Pat<(i32 (zext i1:$in)),
3034          (SELECT_I4 $in, (LI 1), (LI 0))>;
3035def : Pat<(i32 (sext i1:$in)),
3036          (SELECT_I4 $in, (LI -1), (LI 0))>;
3037
3038def : Pat<(i64 (zext i1:$in)),
3039          (SELECT_I8 $in, (LI8 1), (LI8 0))>;
3040def : Pat<(i64 (sext i1:$in)),
3041          (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
3042
3043// FIXME: We should choose either a zext or a sext based on other constants
3044// already around.
3045def : Pat<(i32 (anyext i1:$in)),
3046          (SELECT_I4 $in, (LI 1), (LI 0))>;
3047def : Pat<(i64 (anyext i1:$in)),
3048          (SELECT_I8 $in, (LI8 1), (LI8 0))>;
3049
3050// match setcc on i1 variables.
3051// CRANDC is:
3052//   1 1 : F
3053//   1 0 : T
3054//   0 1 : F
3055//   0 0 : F
3056//
3057// LT is:
3058//  -1 -1  : F
3059//  -1  0  : T
3060//   0 -1  : F
3061//   0  0  : F
3062//
3063// ULT is:
3064//   1 1 : F
3065//   1 0 : F
3066//   0 1 : T
3067//   0 0 : F
3068def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
3069          (CRANDC $s1, $s2)>;
3070def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
3071          (CRANDC $s2, $s1)>;
3072// CRORC is:
3073//   1 1 : T
3074//   1 0 : T
3075//   0 1 : F
3076//   0 0 : T
3077//
3078// LE is:
3079//  -1 -1 : T
3080//  -1  0 : T
3081//   0 -1 : F
3082//   0  0 : T
3083//
3084// ULE is:
3085//   1 1 : T
3086//   1 0 : F
3087//   0 1 : T
3088//   0 0 : T
3089def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
3090          (CRORC $s1, $s2)>;
3091def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
3092          (CRORC $s2, $s1)>;
3093
3094def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
3095          (CREQV $s1, $s2)>;
3096
3097// GE is:
3098//  -1 -1 : T
3099//  -1  0 : F
3100//   0 -1 : T
3101//   0  0 : T
3102//
3103// UGE is:
3104//   1 1 : T
3105//   1 0 : T
3106//   0 1 : F
3107//   0 0 : T
3108def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
3109          (CRORC $s2, $s1)>;
3110def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
3111          (CRORC $s1, $s2)>;
3112
3113// GT is:
3114//  -1 -1 : F
3115//  -1  0 : F
3116//   0 -1 : T
3117//   0  0 : F
3118//
3119// UGT is:
3120//  1 1 : F
3121//  1 0 : T
3122//  0 1 : F
3123//  0 0 : F
3124def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
3125          (CRANDC $s2, $s1)>;
3126def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
3127          (CRANDC $s1, $s2)>;
3128
3129def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
3130          (CRXOR $s1, $s2)>;
3131
3132// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
3133// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3134// floating-point types.
3135
3136multiclass CRNotPat<dag pattern, dag result> {
3137  def : Pat<pattern, (crnot result)>;
3138  def : Pat<(not pattern), result>;
3139
3140  // We can also fold the crnot into an extension:
3141  def : Pat<(i32 (zext pattern)),
3142            (SELECT_I4 result, (LI 0), (LI 1))>;
3143  def : Pat<(i32 (sext pattern)),
3144            (SELECT_I4 result, (LI 0), (LI -1))>;
3145
3146  // We can also fold the crnot into an extension:
3147  def : Pat<(i64 (zext pattern)),
3148            (SELECT_I8 result, (LI8 0), (LI8 1))>;
3149  def : Pat<(i64 (sext pattern)),
3150            (SELECT_I8 result, (LI8 0), (LI8 -1))>;
3151
3152  // FIXME: We should choose either a zext or a sext based on other constants
3153  // already around.
3154  def : Pat<(i32 (anyext pattern)),
3155            (SELECT_I4 result, (LI 0), (LI 1))>;
3156
3157  def : Pat<(i64 (anyext pattern)),
3158            (SELECT_I8 result, (LI8 0), (LI8 1))>;
3159}
3160
3161// FIXME: Because of what seems like a bug in TableGen's type-inference code,
3162// we need to write imm:$imm in the output patterns below, not just $imm, or
3163// else the resulting matcher will not correctly add the immediate operand
3164// (making it a register operand instead).
3165
3166// extended SETCC.
3167multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
3168                       OutPatFrag rfrag, OutPatFrag rfrag8> {
3169  def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
3170            (rfrag $s1)>;
3171  def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
3172            (rfrag8 $s1)>;
3173  def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
3174            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
3175  def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
3176            (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
3177
3178  def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
3179            (rfrag $s1)>;
3180  def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
3181            (rfrag8 $s1)>;
3182  def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
3183            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
3184  def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
3185            (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
3186}
3187
3188// Note that we do all inversions below with i(32|64)not, instead of using
3189// (xori x, 1) because on the A2 nor has single-cycle latency while xori
3190// has 2-cycle latency.
3191
3192defm : ExtSetCCPat<SETEQ,
3193                   PatFrag<(ops node:$in, node:$cc),
3194                           (setcc $in, 0, $cc)>,
3195                   OutPatFrag<(ops node:$in),
3196                              (RLWINM (CNTLZW $in), 27, 31, 31)>,
3197                   OutPatFrag<(ops node:$in),
3198                              (RLDICL (CNTLZD $in), 58, 63)> >;
3199
3200defm : ExtSetCCPat<SETNE,
3201                   PatFrag<(ops node:$in, node:$cc),
3202                           (setcc $in, 0, $cc)>,
3203                   OutPatFrag<(ops node:$in),
3204                              (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
3205                   OutPatFrag<(ops node:$in),
3206                              (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
3207
3208defm : ExtSetCCPat<SETLT,
3209                   PatFrag<(ops node:$in, node:$cc),
3210                           (setcc $in, 0, $cc)>,
3211                   OutPatFrag<(ops node:$in),
3212                              (RLWINM $in, 1, 31, 31)>,
3213                   OutPatFrag<(ops node:$in),
3214                              (RLDICL $in, 1, 63)> >;
3215
3216defm : ExtSetCCPat<SETGE,
3217                   PatFrag<(ops node:$in, node:$cc),
3218                           (setcc $in, 0, $cc)>,
3219                   OutPatFrag<(ops node:$in),
3220                              (RLWINM (i32not $in), 1, 31, 31)>,
3221                   OutPatFrag<(ops node:$in),
3222                              (RLDICL (i64not $in), 1, 63)> >;
3223
3224defm : ExtSetCCPat<SETGT,
3225                   PatFrag<(ops node:$in, node:$cc),
3226                           (setcc $in, 0, $cc)>,
3227                   OutPatFrag<(ops node:$in),
3228                              (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
3229                   OutPatFrag<(ops node:$in),
3230                              (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
3231
3232defm : ExtSetCCPat<SETLE,
3233                   PatFrag<(ops node:$in, node:$cc),
3234                           (setcc $in, 0, $cc)>,
3235                   OutPatFrag<(ops node:$in),
3236                              (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
3237                   OutPatFrag<(ops node:$in),
3238                              (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
3239
3240defm : ExtSetCCPat<SETLT,
3241                   PatFrag<(ops node:$in, node:$cc),
3242                           (setcc $in, -1, $cc)>,
3243                   OutPatFrag<(ops node:$in),
3244                              (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
3245                   OutPatFrag<(ops node:$in),
3246                              (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3247
3248defm : ExtSetCCPat<SETGE,
3249                   PatFrag<(ops node:$in, node:$cc),
3250                           (setcc $in, -1, $cc)>,
3251                   OutPatFrag<(ops node:$in),
3252                              (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
3253                   OutPatFrag<(ops node:$in),
3254                              (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3255
3256defm : ExtSetCCPat<SETGT,
3257                   PatFrag<(ops node:$in, node:$cc),
3258                           (setcc $in, -1, $cc)>,
3259                   OutPatFrag<(ops node:$in),
3260                              (RLWINM (i32not $in), 1, 31, 31)>,
3261                   OutPatFrag<(ops node:$in),
3262                              (RLDICL (i64not $in), 1, 63)> >;
3263
3264defm : ExtSetCCPat<SETLE,
3265                   PatFrag<(ops node:$in, node:$cc),
3266                           (setcc $in, -1, $cc)>,
3267                   OutPatFrag<(ops node:$in),
3268                              (RLWINM $in, 1, 31, 31)>,
3269                   OutPatFrag<(ops node:$in),
3270                              (RLDICL $in, 1, 63)> >;
3271
3272// An extended SETCC with shift amount.
3273multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag,
3274                            OutPatFrag rfrag, OutPatFrag rfrag8> {
3275  def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
3276            (rfrag $s1, $sa)>;
3277  def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
3278            (rfrag8 $s1, $sa)>;
3279  def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
3280            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>;
3281  def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
3282            (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>;
3283
3284  def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
3285            (rfrag $s1, $sa)>;
3286  def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
3287            (rfrag8 $s1, $sa)>;
3288  def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))),
3289            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>;
3290  def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))),
3291            (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>;
3292}
3293
3294defm : ExtSetCCShiftPat<SETNE,
3295                        PatFrag<(ops node:$in, node:$sa, node:$cc),
3296                                (setcc (and $in, (shl 1, $sa)), 0, $cc)>,
3297                        OutPatFrag<(ops node:$in, node:$sa),
3298                                   (RLWNM $in, (SUBFIC $sa, 32), 31, 31)>,
3299                        OutPatFrag<(ops node:$in, node:$sa),
3300                                   (RLDCL $in, (SUBFIC $sa, 64), 63)> >;
3301
3302defm : ExtSetCCShiftPat<SETEQ,
3303                        PatFrag<(ops node:$in, node:$sa, node:$cc),
3304                                (setcc (and $in, (shl 1, $sa)), 0, $cc)>,
3305                        OutPatFrag<(ops node:$in, node:$sa),
3306                                   (RLWNM (i32not $in),
3307                                          (SUBFIC $sa, 32), 31, 31)>,
3308                        OutPatFrag<(ops node:$in, node:$sa),
3309                                   (RLDCL (i64not $in),
3310                                          (SUBFIC $sa, 64), 63)> >;
3311
3312// SETCC for i32.
3313def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
3314          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3315def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
3316          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3317def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
3318          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3319def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
3320          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3321def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
3322          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3323def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
3324          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3325
3326// For non-equality comparisons, the default code would materialize the
3327// constant, then compare against it, like this:
3328//   lis r2, 4660
3329//   ori r2, r2, 22136
3330//   cmpw cr0, r3, r2
3331//   beq cr0,L6
3332// Since we are just comparing for equality, we can emit this instead:
3333//   xoris r0,r3,0x1234
3334//   cmplwi cr0,r0,0x5678
3335//   beq cr0,L6
3336
3337def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
3338          (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3339                                  (LO16 imm:$imm)), sub_eq)>;
3340
3341defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
3342                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3343defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
3344                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3345defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
3346                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3347defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
3348                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3349defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
3350                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3351defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
3352                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3353
3354defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
3355                (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3356                                        (LO16 imm:$imm)), sub_eq)>;
3357
3358def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
3359          (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3360def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
3361          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3362def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
3363          (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3364def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
3365          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3366def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
3367          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3368
3369defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
3370                (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3371defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
3372                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3373defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
3374                (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3375defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
3376                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3377defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
3378                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3379
3380// SETCC for i64.
3381def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
3382          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3383def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
3384          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3385def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
3386          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3387def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
3388          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3389def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
3390          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3391def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
3392          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3393
3394// For non-equality comparisons, the default code would materialize the
3395// constant, then compare against it, like this:
3396//   lis r2, 4660
3397//   ori r2, r2, 22136
3398//   cmpd cr0, r3, r2
3399//   beq cr0,L6
3400// Since we are just comparing for equality, we can emit this instead:
3401//   xoris r0,r3,0x1234
3402//   cmpldi cr0,r0,0x5678
3403//   beq cr0,L6
3404
3405def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
3406          (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3407                                  (LO16 imm:$imm)), sub_eq)>;
3408
3409defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3410                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3411defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
3412                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3413defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
3414                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3415defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
3416                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3417defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
3418                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3419defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
3420                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3421
3422defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
3423                (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3424                                        (LO16 imm:$imm)), sub_eq)>;
3425
3426def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
3427          (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3428def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3429          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3430def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3431          (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3432def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
3433          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3434def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
3435          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3436
3437defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3438                (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3439defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
3440                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3441defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
3442                (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3443defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
3444                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3445defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
3446                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3447
3448// SETCC for f32.
3449def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
3450          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3451def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
3452          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3453def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
3454          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3455def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
3456          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3457def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
3458          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3459def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
3460          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3461def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
3462          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3463
3464defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3465                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3466defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
3467                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3468defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
3469                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3470defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
3471                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3472defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
3473                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3474defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
3475                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3476defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
3477                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3478
3479// SETCC for f64.
3480def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
3481          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3482def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
3483          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3484def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
3485          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3486def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
3487          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3488def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
3489          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3490def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
3491          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3492def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
3493          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3494
3495defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3496                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3497defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
3498                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3499defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
3500                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3501defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
3502                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3503defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
3504                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3505defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
3506                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3507defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
3508                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3509
3510// match select on i1 variables:
3511def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
3512          (CROR (CRAND        $cond , $tval),
3513                (CRAND (crnot $cond), $fval))>;
3514
3515// match selectcc on i1 variables:
3516//   select (lhs == rhs), tval, fval is:
3517//   ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
3518def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
3519           (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3520                 (CRAND (CRORC  $rhs, $lhs), $fval))>;
3521def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)),
3522           (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3523                 (CRAND (CRORC  $lhs, $rhs), $fval))>;
3524def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
3525           (CROR (CRAND (CRORC  $lhs, $rhs), $tval),
3526                 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3527def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)),
3528           (CROR (CRAND (CRORC  $rhs, $lhs), $tval),
3529                 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3530def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
3531           (CROR (CRAND (CREQV $lhs, $rhs), $tval),
3532                 (CRAND (CRXOR $lhs, $rhs), $fval))>;
3533def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
3534           (CROR (CRAND (CRORC  $rhs, $lhs), $tval),
3535                 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3536def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)),
3537           (CROR (CRAND (CRORC  $lhs, $rhs), $tval),
3538                 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3539def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
3540           (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3541                 (CRAND (CRORC  $lhs, $rhs), $fval))>;
3542def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)),
3543           (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3544                 (CRAND (CRORC  $rhs, $lhs), $fval))>;
3545def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
3546           (CROR (CRAND (CREQV $lhs, $rhs), $fval),
3547                 (CRAND (CRXOR $lhs, $rhs), $tval))>;
3548
3549// match selectcc on i1 variables with non-i1 output.
3550def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3551          (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3552def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)),
3553          (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3554def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3555          (SELECT_I4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3556def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)),
3557          (SELECT_I4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3558def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3559          (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3560def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3561          (SELECT_I4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3562def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)),
3563          (SELECT_I4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3564def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3565          (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3566def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)),
3567          (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3568def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3569          (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3570
3571def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3572          (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3573def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)),
3574          (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3575def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3576          (SELECT_I8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3577def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)),
3578          (SELECT_I8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3579def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3580          (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3581def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3582          (SELECT_I8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3583def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)),
3584          (SELECT_I8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3585def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3586          (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3587def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)),
3588          (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3589def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3590          (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3591
3592def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3593          (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3594def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
3595          (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3596def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3597          (SELECT_F4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3598def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),
3599          (SELECT_F4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3600def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3601          (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3602def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3603          (SELECT_F4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3604def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
3605          (SELECT_F4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3606def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3607          (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3608def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
3609          (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3610def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3611          (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3612
3613def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3614          (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3615def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
3616          (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3617def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3618          (SELECT_F8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3619def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)),
3620          (SELECT_F8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3621def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3622          (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3623def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3624          (SELECT_F8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3625def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
3626          (SELECT_F8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3627def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3628          (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3629def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
3630          (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3631def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3632          (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3633
3634def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3635          (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3636def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)),
3637          (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3638def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3639          (SELECT_VRRC (CRORC  $lhs, $rhs), $tval, $fval)>;
3640def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)),
3641          (SELECT_VRRC (CRORC  $rhs, $lhs), $tval, $fval)>;
3642def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3643          (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3644def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3645          (SELECT_VRRC (CRORC  $rhs, $lhs), $tval, $fval)>;
3646def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)),
3647          (SELECT_VRRC (CRORC  $lhs, $rhs), $tval, $fval)>;
3648def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3649          (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3650def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)),
3651          (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3652def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3653          (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3654
3655let usesCustomInserter = 1 in {
3656def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3657                             "#ANDIo_1_EQ_BIT",
3658                             [(set i1:$dst, (trunc (not i32:$in)))]>;
3659def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3660                             "#ANDIo_1_GT_BIT",
3661                             [(set i1:$dst, (trunc i32:$in))]>;
3662
3663def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3664                              "#ANDIo_1_EQ_BIT8",
3665                              [(set i1:$dst, (trunc (not i64:$in)))]>;
3666def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3667                              "#ANDIo_1_GT_BIT8",
3668                              [(set i1:$dst, (trunc i64:$in))]>;
3669}
3670
3671def : Pat<(i1 (not (trunc i32:$in))),
3672           (ANDIo_1_EQ_BIT $in)>;
3673def : Pat<(i1 (not (trunc i64:$in))),
3674           (ANDIo_1_EQ_BIT8 $in)>;
3675
3676//===----------------------------------------------------------------------===//
3677// PowerPC Instructions used for assembler/disassembler only
3678//
3679
3680// FIXME: For B=0 or B > 8, the registers following RT are used.
3681// WARNING: Do not add patterns for this instruction without fixing this.
3682def LSWI  : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3683                            "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3684
3685// FIXME: For B=0 or B > 8, the registers following RT are used.
3686// WARNING: Do not add patterns for this instruction without fixing this.
3687def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3688                            "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3689
3690def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3691                         "isync", IIC_SprISYNC, []>;
3692
3693def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3694                    "icbi $src", IIC_LdStICBI, []>;
3695
3696// We used to have EIEIO as value but E[0-9A-Z] is a reserved name
3697def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3698                           "eieio", IIC_LdStLoad, []>;
3699
3700def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3701                         "wait $L", IIC_LdStLoad, []>;
3702
3703def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3704                         "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3705
3706def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3707            "mtsr $SR, $RS", IIC_SprMTSR>;
3708
3709def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3710            "mfsr $RS, $SR", IIC_SprMFSR>;
3711
3712def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3713            "mtsrin $RS, $RB", IIC_SprMTSR>;
3714
3715def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3716            "mfsrin $RS, $RB", IIC_SprMFSR>;
3717
3718def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3719                    "mtmsr $RS, $L", IIC_SprMTMSR>;
3720
3721def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3722                    "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3723  let L = 0;
3724}
3725
3726def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3727              Requires<[IsBookE]> {
3728  bits<1> E;
3729
3730  let Inst{16} = E;
3731  let Inst{21-30} = 163;
3732}
3733
3734def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3735               "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3736def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3737               "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3738
3739def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3740def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3741def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3742def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3743
3744def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3745                  "mfmsr $RT", IIC_SprMFMSR, []>;
3746
3747def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3748                    "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3749
3750def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
3751                     "mcrfs $BF, $BFA", IIC_BrMCR>;
3752
3753def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3754                      "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
3755
3756def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3757                       "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
3758
3759def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
3760def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
3761
3762def MTFSF : XFLForm_1<63, 711, (outs),
3763                      (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3764                      "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
3765def MTFSFo : XFLForm_1<63, 711, (outs),
3766                       (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3767                       "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
3768
3769def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3770def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3771
3772def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3773                        "slbie $RB", IIC_SprSLBIE, []>;
3774
3775def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3776                    "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3777
3778def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3779                       "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3780
3781def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB),
3782                       "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>;
3783
3784def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3785
3786def TLBIA : XForm_0<31, 370, (outs), (ins),
3787                        "tlbia", IIC_SprTLBIA, []>;
3788
3789def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3790                        "tlbsync", IIC_SprTLBSYNC, []>;
3791
3792def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3793                          "tlbiel $RB", IIC_SprTLBIEL, []>;
3794
3795def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3796                          "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3797def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3798                          "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3799
3800def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3801                          "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3802
3803def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3804                IIC_LdStLoad>, Requires<[IsBookE]>;
3805
3806def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3807                IIC_LdStLoad>, Requires<[IsBookE]>;
3808
3809def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3810                           "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3811
3812def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3813                           "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3814
3815def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3816               "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3817
3818def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3819               "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3820
3821def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3822                             "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3823                             Requires<[IsPPC4xx]>;
3824def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3825                              (ins gprc:$RST, gprc:$A, gprc:$B),
3826                              "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3827                              Requires<[IsPPC4xx]>, isDOT;
3828
3829def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3830
3831def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3832                  Requires<[IsBookE]>;
3833def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3834                   Requires<[IsBookE]>;
3835
3836def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3837                   Requires<[IsE500]>;
3838def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3839                    Requires<[IsE500]>;
3840
3841def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3842                      "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3843def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3844                      "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3845
3846def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>;
3847def NAP   : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>;
3848
3849def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
3850
3851def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3852                             "lbzcix $RST, $A, $B", IIC_LdStLoad, []>;
3853def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3854                             "lhzcix $RST, $A, $B", IIC_LdStLoad, []>;
3855def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3856                             "lwzcix $RST, $A, $B", IIC_LdStLoad, []>;
3857def LDCIX :  XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3858                             "ldcix $RST, $A, $B", IIC_LdStLoad, []>;
3859
3860def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3861                             "stbcix $RST, $A, $B", IIC_LdStLoad, []>;
3862def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3863                             "sthcix $RST, $A, $B", IIC_LdStLoad, []>;
3864def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3865                             "stwcix $RST, $A, $B", IIC_LdStLoad, []>;
3866def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3867                             "stdcix $RST, $A, $B", IIC_LdStLoad, []>;
3868
3869//===----------------------------------------------------------------------===//
3870// PowerPC Assembler Instruction Aliases
3871//
3872
3873// Pseudo-instructions for alternate assembly syntax (never used by codegen).
3874// These are aliases that require C++ handling to convert to the target
3875// instruction, while InstAliases can be handled directly by tblgen.
3876class PPCAsmPseudo<string asm, dag iops>
3877  : Instruction {
3878  let Namespace = "PPC";
3879  bit PPC64 = 0;  // Default value, override with isPPC64
3880
3881  let OutOperandList = (outs);
3882  let InOperandList = iops;
3883  let Pattern = [];
3884  let AsmString = asm;
3885  let isAsmParserOnly = 1;
3886  let isPseudo = 1;
3887}
3888
3889def : InstAlias<"sc", (SC 0)>;
3890
3891def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
3892def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>;
3893def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
3894def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
3895
3896def : InstAlias<"wait", (WAIT 0)>;
3897def : InstAlias<"waitrsv", (WAIT 1)>;
3898def : InstAlias<"waitimpl", (WAIT 2)>;
3899
3900def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3901
3902def DCBTx   : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>;
3903def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>;
3904
3905def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3906def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3907def DCBTT  : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>;
3908
3909def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3910def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3911def DCBTSTT  : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>;
3912
3913def DCBFx  : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>;
3914def DCBFL  : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>;
3915def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>;
3916
3917def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3918def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3919def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3920def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3921
3922def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3923def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3924
3925def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3926def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3927
3928def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3929def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3930
3931def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3932def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3933
3934def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3935def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3936
3937def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3938def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3939
3940def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3941def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3942
3943def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3944def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3945
3946def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3947def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3948
3949def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3950def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3951
3952def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3953def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3954
3955def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3956def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3957
3958def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3959def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3960
3961def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3962def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3963
3964def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3965def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3966def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3967
3968def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3969def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3970
3971def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3972def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3973def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3974def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3975
3976def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3977
3978def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3979def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3980
3981def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3982def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3983
3984def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3985
3986foreach BATR = 0-3 in {
3987    def : InstAlias<"mtdbatu "#BATR#", $Rx",
3988                    (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3989                    Requires<[IsPPC6xx]>;
3990    def : InstAlias<"mfdbatu $Rx, "#BATR,
3991                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3992                    Requires<[IsPPC6xx]>;
3993    def : InstAlias<"mtdbatl "#BATR#", $Rx",
3994                    (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3995                    Requires<[IsPPC6xx]>;
3996    def : InstAlias<"mfdbatl $Rx, "#BATR,
3997                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3998                    Requires<[IsPPC6xx]>;
3999    def : InstAlias<"mtibatu "#BATR#", $Rx",
4000                    (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
4001                    Requires<[IsPPC6xx]>;
4002    def : InstAlias<"mfibatu $Rx, "#BATR,
4003                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
4004                    Requires<[IsPPC6xx]>;
4005    def : InstAlias<"mtibatl "#BATR#", $Rx",
4006                    (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
4007                    Requires<[IsPPC6xx]>;
4008    def : InstAlias<"mfibatl $Rx, "#BATR,
4009                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
4010                    Requires<[IsPPC6xx]>;
4011}
4012
4013foreach BR = 0-7 in {
4014    def : InstAlias<"mfbr"#BR#" $Rx",
4015                    (MFDCR gprc:$Rx, !add(BR, 0x80))>,
4016                    Requires<[IsPPC4xx]>;
4017    def : InstAlias<"mtbr"#BR#" $Rx",
4018                    (MTDCR gprc:$Rx, !add(BR, 0x80))>,
4019                    Requires<[IsPPC4xx]>;
4020}
4021
4022def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4023def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
4024
4025def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4026def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
4027
4028def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4029def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
4030
4031def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4032def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
4033
4034def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
4035def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
4036
4037def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
4038def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
4039
4040def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
4041
4042def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
4043                        (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
4044def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
4045                         (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
4046def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
4047                         (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
4048def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
4049                          (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
4050
4051def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
4052def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
4053def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
4054def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
4055
4056def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
4057def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
4058
4059def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
4060def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
4061
4062foreach SPRG = 0-3 in {
4063  def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
4064  def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
4065  def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
4066  def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
4067}
4068foreach SPRG = 4-7 in {
4069  def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
4070                  Requires<[IsBookE]>;
4071  def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
4072                  Requires<[IsBookE]>;
4073  def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
4074                  Requires<[IsBookE]>;
4075  def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
4076                  Requires<[IsBookE]>;
4077}
4078
4079def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
4080
4081def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
4082def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
4083
4084def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
4085
4086def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
4087def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
4088
4089def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
4090def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
4091def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
4092def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
4093
4094def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
4095
4096def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
4097                Requires<[IsPPC4xx]>;
4098def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
4099                Requires<[IsPPC4xx]>;
4100def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
4101                Requires<[IsPPC4xx]>;
4102def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
4103                Requires<[IsPPC4xx]>;
4104
4105def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
4106                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4107def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
4108                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4109def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
4110                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4111def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
4112                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4113def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
4114                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4115def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
4116                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4117def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
4118                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4119def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
4120                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
4121def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
4122                          (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4123def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
4124                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4125def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
4126                        (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4127def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
4128                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4129def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
4130                        (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4131def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
4132                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4133def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
4134                          (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4135def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
4136                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
4137def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
4138                            (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
4139def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
4140                             (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
4141
4142def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
4143def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
4144def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
4145def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
4146def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
4147def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
4148
4149def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
4150def : InstAlias<"cntlzw. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>;
4151// The POWER variant
4152def : MnemonicAlias<"cntlz",  "cntlzw">;
4153def : MnemonicAlias<"cntlz.", "cntlzw.">;
4154
4155def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
4156                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4157def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
4158                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4159def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
4160                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4161def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
4162                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4163def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
4164                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4165def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
4166                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
4167def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
4168                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4169def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
4170                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4171def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
4172                        (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4173def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
4174                         (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4175def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
4176                        (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4177def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
4178                         (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4179def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
4180                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4181def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
4182                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
4183def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
4184                            (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
4185def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
4186                             (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
4187
4188def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
4189def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
4190def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
4191def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
4192def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
4193def : InstAlias<"clrldi $rA, $rS, $n",
4194                (RLDICL_32 gprc:$rA, gprc:$rS, 0, u6imm:$n)>;
4195def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
4196
4197def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b",
4198                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4199def RLWINMobm : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b",
4200                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4201def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b",
4202                           (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4203def RLWIMIobm : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b",
4204                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4205def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b",
4206                          (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4207def RLWNMobm : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b",
4208                           (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
4209
4210// These generic branch instruction forms are used for the assembler parser only.
4211// Defs and Uses are conservative, since we don't know the BO value.
4212let PPC970_Unit = 7 in {
4213  let Defs = [CTR], Uses = [CTR, RM] in {
4214    def gBC : BForm_3<16, 0, 0, (outs),
4215                      (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
4216                      "bc $bo, $bi, $dst">;
4217    def gBCA : BForm_3<16, 1, 0, (outs),
4218                       (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
4219                       "bca $bo, $bi, $dst">;
4220    let isAsmParserOnly = 1 in {
4221      def gBCat : BForm_3_at<16, 0, 0, (outs),
4222                             (ins u5imm:$bo, atimm:$at, crbitrc:$bi,
4223                                  condbrtarget:$dst),
4224                                  "bc$at $bo, $bi, $dst">;
4225      def gBCAat : BForm_3_at<16, 1, 0, (outs),
4226                              (ins u5imm:$bo, atimm:$at, crbitrc:$bi,
4227                                   abscondbrtarget:$dst),
4228                                   "bca$at $bo, $bi, $dst">;
4229    } // isAsmParserOnly = 1
4230  }
4231  let Defs = [LR, CTR], Uses = [CTR, RM] in {
4232    def gBCL : BForm_3<16, 0, 1, (outs),
4233                       (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
4234                       "bcl $bo, $bi, $dst">;
4235    def gBCLA : BForm_3<16, 1, 1, (outs),
4236                        (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
4237                        "bcla $bo, $bi, $dst">;
4238    let isAsmParserOnly = 1 in {
4239      def gBCLat : BForm_3_at<16, 0, 1, (outs),
4240                         (ins u5imm:$bo, atimm:$at, crbitrc:$bi,
4241                              condbrtarget:$dst),
4242                              "bcl$at $bo, $bi, $dst">;
4243      def gBCLAat : BForm_3_at<16, 1, 1, (outs),
4244                          (ins u5imm:$bo, atimm:$at, crbitrc:$bi,
4245                               abscondbrtarget:$dst),
4246                               "bcla$at $bo, $bi, $dst">;
4247    } // // isAsmParserOnly = 1
4248  }
4249  let Defs = [CTR], Uses = [CTR, LR, RM] in
4250    def gBCLR : XLForm_2<19, 16, 0, (outs),
4251                         (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4252                         "bclr $bo, $bi, $bh", IIC_BrB, []>;
4253  let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
4254    def gBCLRL : XLForm_2<19, 16, 1, (outs),
4255                          (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4256                          "bclrl $bo, $bi, $bh", IIC_BrB, []>;
4257  let Defs = [CTR], Uses = [CTR, LR, RM] in
4258    def gBCCTR : XLForm_2<19, 528, 0, (outs),
4259                          (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4260                          "bcctr $bo, $bi, $bh", IIC_BrB, []>;
4261  let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
4262    def gBCCTRL : XLForm_2<19, 528, 1, (outs),
4263                           (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
4264                           "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
4265}
4266
4267multiclass BranchSimpleMnemonicAT<string pm, int at> {
4268  def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi,
4269                                                    condbrtarget:$dst)>;
4270  def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi,
4271                                                      condbrtarget:$dst)>;
4272  def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi,
4273                                                      condbrtarget:$dst)>;
4274  def : InstAlias<"bcla"#pm#" $bo, $bi, $dst", (gBCLAat u5imm:$bo, at, crbitrc:$bi,
4275                                                        condbrtarget:$dst)>;
4276}
4277defm : BranchSimpleMnemonicAT<"+", 3>;
4278defm : BranchSimpleMnemonicAT<"-", 2>;
4279
4280def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
4281def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
4282def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
4283def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
4284
4285multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
4286  def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
4287  def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
4288  def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
4289  def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
4290  def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
4291  def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
4292}
4293multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
4294  : BranchSimpleMnemonic1<name, pm, bo> {
4295  def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
4296  def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
4297}
4298defm : BranchSimpleMnemonic2<"t", "", 12>;
4299defm : BranchSimpleMnemonic2<"f", "", 4>;
4300defm : BranchSimpleMnemonic2<"t", "-", 14>;
4301defm : BranchSimpleMnemonic2<"f", "-", 6>;
4302defm : BranchSimpleMnemonic2<"t", "+", 15>;
4303defm : BranchSimpleMnemonic2<"f", "+", 7>;
4304defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
4305defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
4306defm : BranchSimpleMnemonic1<"dzt", "", 10>;
4307defm : BranchSimpleMnemonic1<"dzf", "", 2>;
4308
4309multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
4310  def : InstAlias<"b"#name#pm#" $cc, $dst",
4311                  (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
4312  def : InstAlias<"b"#name#pm#" $dst",
4313                  (BCC bibo, CR0, condbrtarget:$dst)>;
4314
4315  def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
4316                  (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
4317  def : InstAlias<"b"#name#"a"#pm#" $dst",
4318                  (BCCA bibo, CR0, abscondbrtarget:$dst)>;
4319
4320  def : InstAlias<"b"#name#"lr"#pm#" $cc",
4321                  (BCCLR bibo, crrc:$cc)>;
4322  def : InstAlias<"b"#name#"lr"#pm,
4323                  (BCCLR bibo, CR0)>;
4324
4325  def : InstAlias<"b"#name#"ctr"#pm#" $cc",
4326                  (BCCCTR bibo, crrc:$cc)>;
4327  def : InstAlias<"b"#name#"ctr"#pm,
4328                  (BCCCTR bibo, CR0)>;
4329
4330  def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
4331                  (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
4332  def : InstAlias<"b"#name#"l"#pm#" $dst",
4333                  (BCCL bibo, CR0, condbrtarget:$dst)>;
4334
4335  def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
4336                  (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
4337  def : InstAlias<"b"#name#"la"#pm#" $dst",
4338                  (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
4339
4340  def : InstAlias<"b"#name#"lrl"#pm#" $cc",
4341                  (BCCLRL bibo, crrc:$cc)>;
4342  def : InstAlias<"b"#name#"lrl"#pm,
4343                  (BCCLRL bibo, CR0)>;
4344
4345  def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
4346                  (BCCCTRL bibo, crrc:$cc)>;
4347  def : InstAlias<"b"#name#"ctrl"#pm,
4348                  (BCCCTRL bibo, CR0)>;
4349}
4350multiclass BranchExtendedMnemonic<string name, int bibo> {
4351  defm : BranchExtendedMnemonicPM<name, "", bibo>;
4352  defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
4353  defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
4354}
4355defm : BranchExtendedMnemonic<"lt", 12>;
4356defm : BranchExtendedMnemonic<"gt", 44>;
4357defm : BranchExtendedMnemonic<"eq", 76>;
4358defm : BranchExtendedMnemonic<"un", 108>;
4359defm : BranchExtendedMnemonic<"so", 108>;
4360defm : BranchExtendedMnemonic<"ge", 4>;
4361defm : BranchExtendedMnemonic<"nl", 4>;
4362defm : BranchExtendedMnemonic<"le", 36>;
4363defm : BranchExtendedMnemonic<"ng", 36>;
4364defm : BranchExtendedMnemonic<"ne", 68>;
4365defm : BranchExtendedMnemonic<"nu", 100>;
4366defm : BranchExtendedMnemonic<"ns", 100>;
4367
4368def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
4369def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
4370def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
4371def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
4372def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
4373def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
4374def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
4375def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
4376
4377def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
4378def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
4379def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
4380def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
4381def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
4382def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
4383def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
4384def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
4385
4386multiclass TrapExtendedMnemonic<string name, int to> {
4387  def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
4388  def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
4389  def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
4390  def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
4391}
4392defm : TrapExtendedMnemonic<"lt", 16>;
4393defm : TrapExtendedMnemonic<"le", 20>;
4394defm : TrapExtendedMnemonic<"eq", 4>;
4395defm : TrapExtendedMnemonic<"ge", 12>;
4396defm : TrapExtendedMnemonic<"gt", 8>;
4397defm : TrapExtendedMnemonic<"nl", 12>;
4398defm : TrapExtendedMnemonic<"ne", 24>;
4399defm : TrapExtendedMnemonic<"ng", 20>;
4400defm : TrapExtendedMnemonic<"llt", 2>;
4401defm : TrapExtendedMnemonic<"lle", 6>;
4402defm : TrapExtendedMnemonic<"lge", 5>;
4403defm : TrapExtendedMnemonic<"lgt", 1>;
4404defm : TrapExtendedMnemonic<"lnl", 5>;
4405defm : TrapExtendedMnemonic<"lng", 6>;
4406defm : TrapExtendedMnemonic<"u", 31>;
4407
4408// Atomic loads
4409def : Pat<(atomic_load_8  iaddr:$src), (LBZ  memri:$src)>;
4410def : Pat<(atomic_load_16 iaddr:$src), (LHZ  memri:$src)>;
4411def : Pat<(atomic_load_32 iaddr:$src), (LWZ  memri:$src)>;
4412def : Pat<(atomic_load_8  xaddr:$src), (LBZX memrr:$src)>;
4413def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
4414def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
4415
4416// Atomic stores
4417def : Pat<(atomic_store_8  iaddr:$ptr, i32:$val), (STB  gprc:$val, memri:$ptr)>;
4418def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH  gprc:$val, memri:$ptr)>;
4419def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW  gprc:$val, memri:$ptr)>;
4420def : Pat<(atomic_store_8  xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
4421def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
4422def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;
4423
4424let Predicates = [IsISA3_0] in {
4425
4426// Copy-Paste Facility
4427// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to
4428// PASTE for naming consistency.
4429let mayLoad = 1 in
4430def CP_COPY   : X_L1_RA5_RB5<31, 774, "copy"  , gprc, IIC_LdStCOPY, []>;
4431
4432let mayStore = 1 in
4433def CP_PASTE  : X_L1_RA5_RB5<31, 902, "paste" , gprc, IIC_LdStPASTE, []>;
4434
4435let mayStore = 1, Defs = [CR0] in
4436def CP_PASTEo : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isDOT;
4437
4438def CP_COPYx  : PPCAsmPseudo<"copy $rA, $rB" , (ins gprc:$rA, gprc:$rB)>;
4439def CP_PASTEx : PPCAsmPseudo<"paste $rA, $rB", (ins gprc:$rA, gprc:$rB)>;
4440def CP_COPY_FIRST : PPCAsmPseudo<"copy_first $rA, $rB",
4441                                  (ins gprc:$rA, gprc:$rB)>;
4442def CP_PASTE_LAST : PPCAsmPseudo<"paste_last $rA, $rB",
4443                                  (ins gprc:$rA, gprc:$rB)>;
4444def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cp_abort", IIC_SprABORT, []>;
4445
4446// Message Synchronize
4447def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>;
4448
4449// Power-Saving Mode Instruction:
4450def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>;
4451
4452} // IsISA3_0
4453