1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the subset of the 32-bit PowerPC instruction set, as used 10// by the PowerPC instruction selector. 11// 12//===----------------------------------------------------------------------===// 13 14include "PPCInstrFormats.td" 15 16//===----------------------------------------------------------------------===// 17// PowerPC specific type constraints. 18// 19def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 20 SDTCisVT<0, f64>, SDTCisPtrTy<1> 21]>; 22def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x 23 SDTCisVT<0, f64>, SDTCisPtrTy<1> 24]>; 25def SDT_PPCLxsizx : SDTypeProfile<1, 2, [ 26 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 27]>; 28def SDT_PPCstxsix : SDTypeProfile<0, 3, [ 29 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 30]>; 31def SDT_PPCcv_fp_to_int : SDTypeProfile<1, 1, [ 32 SDTCisFP<0>, SDTCisFP<1> 33 ]>; 34def SDT_PPCstore_scal_int_from_vsr : SDTypeProfile<0, 3, [ 35 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 36]>; 37def SDT_PPCVexts : SDTypeProfile<1, 2, [ 38 SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2> 39]>; 40 41def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 42 SDTCisVT<1, i32> ]>; 43def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 44 SDTCisVT<1, i32> ]>; 45def SDT_PPCvperm : SDTypeProfile<1, 3, [ 46 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 47]>; 48 49def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>, 50 SDTCisVec<1>, SDTCisInt<2> 51]>; 52 53def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>, 54 SDTCisVec<1>, SDTCisVec<2>, SDTCisPtrTy<3> 55]>; 56 57def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>, 58 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 59]>; 60 61def SDT_PPCxxpermdi: SDTypeProfile<1, 3, [ SDTCisVec<0>, 62 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 63]>; 64 65def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 66 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 67]>; 68 69def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 70 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 71]>; 72 73def SDT_PPClbrx : SDTypeProfile<1, 2, [ 74 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 75]>; 76def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 77 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 78]>; 79 80def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 81 SDTCisPtrTy<0>, SDTCisVT<1, i32> 82]>; 83 84def tocentry32 : Operand<iPTR> { 85 let MIOperandInfo = (ops i32imm:$imm); 86} 87 88def SDT_PPCqvfperm : SDTypeProfile<1, 3, [ 89 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3> 90]>; 91def SDT_PPCqvgpci : SDTypeProfile<1, 1, [ 92 SDTCisVec<0>, SDTCisInt<1> 93]>; 94def SDT_PPCqvaligni : SDTypeProfile<1, 3, [ 95 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3> 96]>; 97def SDT_PPCqvesplati : SDTypeProfile<1, 2, [ 98 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2> 99]>; 100 101def SDT_PPCqbflt : SDTypeProfile<1, 1, [ 102 SDTCisVec<0>, SDTCisVec<1> 103]>; 104 105def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [ 106 SDTCisVec<0>, SDTCisPtrTy<1> 107]>; 108 109def SDT_PPCextswsli : SDTypeProfile<1, 2, [ // extswsli 110 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisInt<2> 111]>; 112 113def SDT_PPCFPMinMax : SDTypeProfile<1, 2, [ 114 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 115]>; 116 117//===----------------------------------------------------------------------===// 118// PowerPC specific DAG Nodes. 119// 120 121def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>; 122def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>; 123 124def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; 125def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; 126def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>; 127def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>; 128def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 129def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 130def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>; 131def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>; 132 133def PPCcv_fp_to_uint_in_vsr: 134 SDNode<"PPCISD::FP_TO_UINT_IN_VSR", SDT_PPCcv_fp_to_int, []>; 135def PPCcv_fp_to_sint_in_vsr: 136 SDNode<"PPCISD::FP_TO_SINT_IN_VSR", SDT_PPCcv_fp_to_int, []>; 137def PPCstore_scal_int_from_vsr: 138 SDNode<"PPCISD::ST_VSR_SCAL_INT", SDT_PPCstore_scal_int_from_vsr, 139 [SDNPHasChain, SDNPMayStore]>; 140def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 141 [SDNPHasChain, SDNPMayStore]>; 142def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx, 143 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 144def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx, 145 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 146def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx, 147 [SDNPHasChain, SDNPMayLoad]>; 148def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix, 149 [SDNPHasChain, SDNPMayStore]>; 150def PPCVexts : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>; 151 152// Extract FPSCR (not modeled at the DAG level). 153def PPCmffs : SDNode<"PPCISD::MFFS", 154 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 155 [SDNPHasChain]>; 156 157// Perform FADD in round-to-zero mode. 158def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>; 159 160 161def PPCfsel : SDNode<"PPCISD::FSEL", 162 // Type constraint for fsel. 163 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 164 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 165def PPCxsmaxc : SDNode<"PPCISD::XSMAXCDP", SDT_PPCFPMinMax, []>; 166def PPCxsminc : SDNode<"PPCISD::XSMINCDP", SDT_PPCFPMinMax, []>; 167def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 168def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 169def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, 170 [SDNPMayLoad, SDNPMemOperand]>; 171def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 172def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 173 174def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>; 175 176def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 177def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 178 [SDNPMayLoad]>; 179def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 180def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 181def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 182def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 183def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR", 184 SDTypeProfile<1, 3, [ 185 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 186 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 187def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 188def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 189def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 190def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR", 191 SDTypeProfile<1, 3, [ 192 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 193 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 194def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>; 195def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 196 197def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 198def PPCxxsplt : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>; 199def PPCvecinsert : SDNode<"PPCISD::VECINSERT", SDT_PPCVecInsert, []>; 200def PPCxxpermdi : SDNode<"PPCISD::XXPERMDI", SDT_PPCxxpermdi, []>; 201def PPCvecshl : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>; 202 203def PPCqvfperm : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>; 204def PPCqvgpci : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>; 205def PPCqvaligni : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>; 206def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>; 207 208def PPCqbflt : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>; 209 210def PPCqvlfsb : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb, 211 [SDNPHasChain, SDNPMayLoad]>; 212 213def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>; 214 215// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 216// amounts. These nodes are generated by the multi-precision shift code. 217def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 218def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 219def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 220 221def PPCextswsli : SDNode<"PPCISD::EXTSWSLI" , SDT_PPCextswsli>; 222 223// Move 2 i64 values into a VSX register 224def PPCbuild_fp128: SDNode<"PPCISD::BUILD_FP128", 225 SDTypeProfile<1, 2, 226 [SDTCisFP<0>, SDTCisSameSizeAs<1,2>, 227 SDTCisSameAs<1,2>]>, 228 []>; 229 230def PPCbuild_spe64: SDNode<"PPCISD::BUILD_SPE64", 231 SDTypeProfile<1, 2, 232 [SDTCisVT<0, f64>, SDTCisVT<1,i32>, 233 SDTCisVT<1,i32>]>, 234 []>; 235 236def PPCextract_spe : SDNode<"PPCISD::EXTRACT_SPE", 237 SDTypeProfile<1, 2, 238 [SDTCisVT<0, i32>, SDTCisVT<1, f64>, 239 SDTCisPtrTy<2>]>, 240 []>; 241 242// These are target-independent nodes, but have target-specific formats. 243def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 244 [SDNPHasChain, SDNPOutGlue]>; 245def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 246 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 247 248def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 249def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 250 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 251 SDNPVariadic]>; 252def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall, 253 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 254 SDNPVariadic]>; 255def PPCcall_notoc : SDNode<"PPCISD::CALL_NOTOC", SDT_PPCCall, 256 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 257 SDNPVariadic]>; 258def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 259 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 260def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone, 261 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 262 SDNPVariadic]>; 263def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC", 264 SDTypeProfile<0, 1, []>, 265 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 266 SDNPVariadic]>; 267 268def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 269 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 270 271def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 272 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 273 274def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP", 275 SDTypeProfile<1, 1, [SDTCisInt<0>, 276 SDTCisPtrTy<1>]>, 277 [SDNPHasChain, SDNPSideEffect]>; 278def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP", 279 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 280 [SDNPHasChain, SDNPSideEffect]>; 281 282def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 283def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc, 284 [SDNPHasChain, SDNPSideEffect]>; 285 286def PPCclrbhrb : SDNode<"PPCISD::CLRBHRB", SDTNone, 287 [SDNPHasChain, SDNPSideEffect]>; 288def PPCmfbhrbe : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>; 289def PPCrfebb : SDNode<"PPCISD::RFEBB", SDT_PPCsc, 290 [SDNPHasChain, SDNPSideEffect]>; 291 292def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 293def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>; 294 295def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 296 [SDNPHasChain, SDNPOptInGlue]>; 297 298// PPC-specific atomic operations. 299def PPCatomicCmpSwap_8 : 300 SDNode<"PPCISD::ATOMIC_CMP_SWAP_8", SDTAtomic3, 301 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 302def PPCatomicCmpSwap_16 : 303 SDNode<"PPCISD::ATOMIC_CMP_SWAP_16", SDTAtomic3, 304 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 305def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 306 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 307def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 308 [SDNPHasChain, SDNPMayStore]>; 309 310// Instructions to set/unset CR bit 6 for SVR4 vararg calls 311def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 312 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 313def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 314 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 315 316// Instructions to support dynamic alloca. 317def SDTDynOp : SDTypeProfile<1, 2, []>; 318def SDTDynAreaOp : SDTypeProfile<1, 1, []>; 319def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 320def PPCdynareaoffset : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>; 321 322// PC Relative Specific Nodes 323def PPCmatpcreladdr : SDNode<"PPCISD::MAT_PCREL_ADDR", SDTIntUnaryOp, []>; 324 325//===----------------------------------------------------------------------===// 326// PowerPC specific transformation functions and pattern fragments. 327// 328 329def SHL32 : SDNodeXForm<imm, [{ 330 // Transformation function: 31 - imm 331 return getI32Imm(31 - N->getZExtValue(), SDLoc(N)); 332}]>; 333 334def SRL32 : SDNodeXForm<imm, [{ 335 // Transformation function: 32 - imm 336 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N)) 337 : getI32Imm(0, SDLoc(N)); 338}]>; 339 340def LO16 : SDNodeXForm<imm, [{ 341 // Transformation function: get the low 16 bits. 342 return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N)); 343}]>; 344 345def HI16 : SDNodeXForm<imm, [{ 346 // Transformation function: shift the immediate value down into the low bits. 347 return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N)); 348}]>; 349 350def HA16 : SDNodeXForm<imm, [{ 351 // Transformation function: shift the immediate value down into the low bits. 352 long Val = N->getZExtValue(); 353 return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N)); 354}]>; 355def MB : SDNodeXForm<imm, [{ 356 // Transformation function: get the start bit of a mask 357 unsigned mb = 0, me; 358 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 359 return getI32Imm(mb, SDLoc(N)); 360}]>; 361 362def ME : SDNodeXForm<imm, [{ 363 // Transformation function: get the end bit of a mask 364 unsigned mb, me = 0; 365 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 366 return getI32Imm(me, SDLoc(N)); 367}]>; 368def maskimm32 : PatLeaf<(imm), [{ 369 // maskImm predicate - True if immediate is a run of ones. 370 unsigned mb, me; 371 if (N->getValueType(0) == MVT::i32) 372 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 373 else 374 return false; 375}]>; 376 377def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{ 378 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit 379 // sign extended field. Used by instructions like 'addi'. 380 return (int32_t)Imm == (short)Imm; 381}]>; 382def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{ 383 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit 384 // sign extended field. Used by instructions like 'addi'. 385 return (int64_t)Imm == (short)Imm; 386}]>; 387def immZExt16 : PatLeaf<(imm), [{ 388 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 389 // field. Used by instructions like 'ori'. 390 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 391}], LO16>; 392def immNonAllOneAnyExt8 : ImmLeaf<i32, [{ 393 return (isInt<8>(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF)); 394}]>; 395def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>; 396 397// imm16Shifted* - These match immediates where the low 16-bits are zero. There 398// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 399// identical in 32-bit mode, but in 64-bit mode, they return true if the 400// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 401// clear). 402def imm16ShiftedZExt : PatLeaf<(imm), [{ 403 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 404 // immediate are set. Used by instructions like 'xoris'. 405 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 406}], HI16>; 407 408def imm16ShiftedSExt : PatLeaf<(imm), [{ 409 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 410 // immediate are set. Used by instructions like 'addis'. Identical to 411 // imm16ShiftedZExt in 32-bit mode. 412 if (N->getZExtValue() & 0xFFFF) return false; 413 if (N->getValueType(0) == MVT::i32) 414 return true; 415 // For 64-bit, make sure it is sext right. 416 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 417}], HI16>; 418 419def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{ 420 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit 421 // zero extended field. 422 return isUInt<32>(Imm); 423}]>; 424 425// Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require 426// restricted memrix (4-aligned) constants are alignment sensitive. If these 427// offsets are hidden behind TOC entries than the values of the lower-order 428// bits cannot be checked directly. As a result, we need to also incorporate 429// an alignment check into the relevant patterns. 430 431def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 432 return cast<LoadSDNode>(N)->getAlignment() >= 4; 433}]>; 434def aligned4store : PatFrag<(ops node:$val, node:$ptr), 435 (store node:$val, node:$ptr), [{ 436 return cast<StoreSDNode>(N)->getAlignment() >= 4; 437}]>; 438def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 439 return cast<LoadSDNode>(N)->getAlignment() >= 4; 440}]>; 441def aligned4pre_store : PatFrag< 442 (ops node:$val, node:$base, node:$offset), 443 (pre_store node:$val, node:$base, node:$offset), [{ 444 return cast<StoreSDNode>(N)->getAlignment() >= 4; 445}]>; 446 447def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 448 return cast<LoadSDNode>(N)->getAlignment() < 4; 449}]>; 450def unaligned4store : PatFrag<(ops node:$val, node:$ptr), 451 (store node:$val, node:$ptr), [{ 452 return cast<StoreSDNode>(N)->getAlignment() < 4; 453}]>; 454def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 455 return cast<LoadSDNode>(N)->getAlignment() < 4; 456}]>; 457 458// This is a somewhat weaker condition than actually checking for 16-byte 459// alignment. It is simply checking that the displacement can be represented 460// as an immediate that is a multiple of 16 (i.e. the requirements for DQ-Form 461// instructions). 462def quadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 463 return isOffsetMultipleOf(N, 16); 464}]>; 465def quadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 466 (store node:$val, node:$ptr), [{ 467 return isOffsetMultipleOf(N, 16); 468}]>; 469def nonQuadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 470 return !isOffsetMultipleOf(N, 16); 471}]>; 472def nonQuadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 473 (store node:$val, node:$ptr), [{ 474 return !isOffsetMultipleOf(N, 16); 475}]>; 476 477// PatFrag for binary operation whose operands are both non-constant 478class BinOpWithoutSImm16Operand<SDNode opcode> : 479 PatFrag<(ops node:$left, node:$right), (opcode node:$left, node:$right), [{ 480 int16_t Imm; 481 return !isIntS16Immediate(N->getOperand(0), Imm) 482 && !isIntS16Immediate(N->getOperand(1), Imm); 483}]>; 484 485def add_without_simm16 : BinOpWithoutSImm16Operand<add>; 486def mul_without_simm16 : BinOpWithoutSImm16Operand<mul>; 487 488//===----------------------------------------------------------------------===// 489// PowerPC Flag Definitions. 490 491class isPPC64 { bit PPC64 = 1; } 492class isRecordForm { bit RC = 1; } 493 494class RegConstraint<string C> { 495 string Constraints = C; 496} 497class NoEncode<string E> { 498 string DisableEncoding = E; 499} 500 501 502//===----------------------------------------------------------------------===// 503// PowerPC Operand Definitions. 504 505// In the default PowerPC assembler syntax, registers are specified simply 506// by number, so they cannot be distinguished from immediate values (without 507// looking at the opcode). This means that the default operand matching logic 508// for the asm parser does not work, and we need to specify custom matchers. 509// Since those can only be specified with RegisterOperand classes and not 510// directly on the RegisterClass, all instructions patterns used by the asm 511// parser need to use a RegisterOperand (instead of a RegisterClass) for 512// all their register operands. 513// For this purpose, we define one RegisterOperand for each RegisterClass, 514// using the same name as the class, just in lower case. 515 516def PPCRegGPRCAsmOperand : AsmOperandClass { 517 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber"; 518} 519def gprc : RegisterOperand<GPRC> { 520 let ParserMatchClass = PPCRegGPRCAsmOperand; 521} 522def PPCRegG8RCAsmOperand : AsmOperandClass { 523 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber"; 524} 525def g8rc : RegisterOperand<G8RC> { 526 let ParserMatchClass = PPCRegG8RCAsmOperand; 527} 528def PPCRegGPRCNoR0AsmOperand : AsmOperandClass { 529 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber"; 530} 531def gprc_nor0 : RegisterOperand<GPRC_NOR0> { 532 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand; 533} 534def PPCRegG8RCNoX0AsmOperand : AsmOperandClass { 535 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber"; 536} 537def g8rc_nox0 : RegisterOperand<G8RC_NOX0> { 538 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand; 539} 540def PPCRegF8RCAsmOperand : AsmOperandClass { 541 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber"; 542} 543def f8rc : RegisterOperand<F8RC> { 544 let ParserMatchClass = PPCRegF8RCAsmOperand; 545} 546def PPCRegF4RCAsmOperand : AsmOperandClass { 547 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber"; 548} 549def f4rc : RegisterOperand<F4RC> { 550 let ParserMatchClass = PPCRegF4RCAsmOperand; 551} 552def PPCRegVRRCAsmOperand : AsmOperandClass { 553 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber"; 554} 555def vrrc : RegisterOperand<VRRC> { 556 let ParserMatchClass = PPCRegVRRCAsmOperand; 557} 558def PPCRegVFRCAsmOperand : AsmOperandClass { 559 let Name = "RegVFRC"; let PredicateMethod = "isRegNumber"; 560} 561def vfrc : RegisterOperand<VFRC> { 562 let ParserMatchClass = PPCRegVFRCAsmOperand; 563} 564def PPCRegCRBITRCAsmOperand : AsmOperandClass { 565 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber"; 566} 567def crbitrc : RegisterOperand<CRBITRC> { 568 let ParserMatchClass = PPCRegCRBITRCAsmOperand; 569} 570def PPCRegCRRCAsmOperand : AsmOperandClass { 571 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber"; 572} 573def crrc : RegisterOperand<CRRC> { 574 let ParserMatchClass = PPCRegCRRCAsmOperand; 575} 576def PPCRegSPERCAsmOperand : AsmOperandClass { 577 let Name = "RegSPERC"; let PredicateMethod = "isRegNumber"; 578} 579def sperc : RegisterOperand<SPERC> { 580 let ParserMatchClass = PPCRegSPERCAsmOperand; 581} 582def PPCRegSPE4RCAsmOperand : AsmOperandClass { 583 let Name = "RegSPE4RC"; let PredicateMethod = "isRegNumber"; 584} 585def spe4rc : RegisterOperand<GPRC> { 586 let ParserMatchClass = PPCRegSPE4RCAsmOperand; 587} 588 589def PPCU1ImmAsmOperand : AsmOperandClass { 590 let Name = "U1Imm"; let PredicateMethod = "isU1Imm"; 591 let RenderMethod = "addImmOperands"; 592} 593def u1imm : Operand<i32> { 594 let PrintMethod = "printU1ImmOperand"; 595 let ParserMatchClass = PPCU1ImmAsmOperand; 596} 597 598def PPCU2ImmAsmOperand : AsmOperandClass { 599 let Name = "U2Imm"; let PredicateMethod = "isU2Imm"; 600 let RenderMethod = "addImmOperands"; 601} 602def u2imm : Operand<i32> { 603 let PrintMethod = "printU2ImmOperand"; 604 let ParserMatchClass = PPCU2ImmAsmOperand; 605} 606 607def PPCATBitsAsHintAsmOperand : AsmOperandClass { 608 let Name = "ATBitsAsHint"; let PredicateMethod = "isATBitsAsHint"; 609 let RenderMethod = "addImmOperands"; // Irrelevant, predicate always fails. 610} 611def atimm : Operand<i32> { 612 let PrintMethod = "printATBitsAsHint"; 613 let ParserMatchClass = PPCATBitsAsHintAsmOperand; 614} 615 616def PPCU3ImmAsmOperand : AsmOperandClass { 617 let Name = "U3Imm"; let PredicateMethod = "isU3Imm"; 618 let RenderMethod = "addImmOperands"; 619} 620def u3imm : Operand<i32> { 621 let PrintMethod = "printU3ImmOperand"; 622 let ParserMatchClass = PPCU3ImmAsmOperand; 623} 624 625def PPCU4ImmAsmOperand : AsmOperandClass { 626 let Name = "U4Imm"; let PredicateMethod = "isU4Imm"; 627 let RenderMethod = "addImmOperands"; 628} 629def u4imm : Operand<i32> { 630 let PrintMethod = "printU4ImmOperand"; 631 let ParserMatchClass = PPCU4ImmAsmOperand; 632} 633def PPCS5ImmAsmOperand : AsmOperandClass { 634 let Name = "S5Imm"; let PredicateMethod = "isS5Imm"; 635 let RenderMethod = "addImmOperands"; 636} 637def s5imm : Operand<i32> { 638 let PrintMethod = "printS5ImmOperand"; 639 let ParserMatchClass = PPCS5ImmAsmOperand; 640 let DecoderMethod = "decodeSImmOperand<5>"; 641} 642def PPCU5ImmAsmOperand : AsmOperandClass { 643 let Name = "U5Imm"; let PredicateMethod = "isU5Imm"; 644 let RenderMethod = "addImmOperands"; 645} 646def u5imm : Operand<i32> { 647 let PrintMethod = "printU5ImmOperand"; 648 let ParserMatchClass = PPCU5ImmAsmOperand; 649 let DecoderMethod = "decodeUImmOperand<5>"; 650} 651def PPCU6ImmAsmOperand : AsmOperandClass { 652 let Name = "U6Imm"; let PredicateMethod = "isU6Imm"; 653 let RenderMethod = "addImmOperands"; 654} 655def u6imm : Operand<i32> { 656 let PrintMethod = "printU6ImmOperand"; 657 let ParserMatchClass = PPCU6ImmAsmOperand; 658 let DecoderMethod = "decodeUImmOperand<6>"; 659} 660def PPCU7ImmAsmOperand : AsmOperandClass { 661 let Name = "U7Imm"; let PredicateMethod = "isU7Imm"; 662 let RenderMethod = "addImmOperands"; 663} 664def u7imm : Operand<i32> { 665 let PrintMethod = "printU7ImmOperand"; 666 let ParserMatchClass = PPCU7ImmAsmOperand; 667 let DecoderMethod = "decodeUImmOperand<7>"; 668} 669def PPCU8ImmAsmOperand : AsmOperandClass { 670 let Name = "U8Imm"; let PredicateMethod = "isU8Imm"; 671 let RenderMethod = "addImmOperands"; 672} 673def u8imm : Operand<i32> { 674 let PrintMethod = "printU8ImmOperand"; 675 let ParserMatchClass = PPCU8ImmAsmOperand; 676 let DecoderMethod = "decodeUImmOperand<8>"; 677} 678def PPCU10ImmAsmOperand : AsmOperandClass { 679 let Name = "U10Imm"; let PredicateMethod = "isU10Imm"; 680 let RenderMethod = "addImmOperands"; 681} 682def u10imm : Operand<i32> { 683 let PrintMethod = "printU10ImmOperand"; 684 let ParserMatchClass = PPCU10ImmAsmOperand; 685 let DecoderMethod = "decodeUImmOperand<10>"; 686} 687def PPCU12ImmAsmOperand : AsmOperandClass { 688 let Name = "U12Imm"; let PredicateMethod = "isU12Imm"; 689 let RenderMethod = "addImmOperands"; 690} 691def u12imm : Operand<i32> { 692 let PrintMethod = "printU12ImmOperand"; 693 let ParserMatchClass = PPCU12ImmAsmOperand; 694 let DecoderMethod = "decodeUImmOperand<12>"; 695} 696def PPCS16ImmAsmOperand : AsmOperandClass { 697 let Name = "S16Imm"; let PredicateMethod = "isS16Imm"; 698 let RenderMethod = "addS16ImmOperands"; 699} 700def s16imm : Operand<i32> { 701 let PrintMethod = "printS16ImmOperand"; 702 let EncoderMethod = "getImm16Encoding"; 703 let ParserMatchClass = PPCS16ImmAsmOperand; 704 let DecoderMethod = "decodeSImmOperand<16>"; 705} 706def PPCU16ImmAsmOperand : AsmOperandClass { 707 let Name = "U16Imm"; let PredicateMethod = "isU16Imm"; 708 let RenderMethod = "addU16ImmOperands"; 709} 710def u16imm : Operand<i32> { 711 let PrintMethod = "printU16ImmOperand"; 712 let EncoderMethod = "getImm16Encoding"; 713 let ParserMatchClass = PPCU16ImmAsmOperand; 714 let DecoderMethod = "decodeUImmOperand<16>"; 715} 716def PPCS17ImmAsmOperand : AsmOperandClass { 717 let Name = "S17Imm"; let PredicateMethod = "isS17Imm"; 718 let RenderMethod = "addS16ImmOperands"; 719} 720def s17imm : Operand<i32> { 721 // This operand type is used for addis/lis to allow the assembler parser 722 // to accept immediates in the range -65536..65535 for compatibility with 723 // the GNU assembler. The operand is treated as 16-bit otherwise. 724 let PrintMethod = "printS16ImmOperand"; 725 let EncoderMethod = "getImm16Encoding"; 726 let ParserMatchClass = PPCS17ImmAsmOperand; 727 let DecoderMethod = "decodeSImmOperand<16>"; 728} 729def PPCS34ImmAsmOperand : AsmOperandClass { 730 let Name = "S34Imm"; 731 let PredicateMethod = "isS34Imm"; 732 let RenderMethod = "addImmOperands"; 733} 734def s34imm : Operand<i64> { 735 let PrintMethod = "printS34ImmOperand"; 736 let EncoderMethod = "getImm34Encoding"; 737 let ParserMatchClass = PPCS34ImmAsmOperand; 738 let DecoderMethod = "decodeSImmOperand<34>"; 739} 740def PPCImmZeroAsmOperand : AsmOperandClass { 741 let Name = "ImmZero"; 742 let PredicateMethod = "isImmZero"; 743 let RenderMethod = "addImmOperands"; 744} 745def immZero : Operand<i32> { 746 let PrintMethod = "printImmZeroOperand"; 747 let ParserMatchClass = PPCImmZeroAsmOperand; 748 let DecoderMethod = "decodeImmZeroOperand"; 749} 750 751def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>; 752 753def PPCDirectBrAsmOperand : AsmOperandClass { 754 let Name = "DirectBr"; let PredicateMethod = "isDirectBr"; 755 let RenderMethod = "addBranchTargetOperands"; 756} 757def directbrtarget : Operand<OtherVT> { 758 let PrintMethod = "printBranchOperand"; 759 let EncoderMethod = "getDirectBrEncoding"; 760 let DecoderMethod = "decodeDirectBrTarget"; 761 let ParserMatchClass = PPCDirectBrAsmOperand; 762 let OperandType = "OPERAND_PCREL"; 763} 764def absdirectbrtarget : Operand<OtherVT> { 765 let PrintMethod = "printAbsBranchOperand"; 766 let EncoderMethod = "getAbsDirectBrEncoding"; 767 let ParserMatchClass = PPCDirectBrAsmOperand; 768} 769def PPCCondBrAsmOperand : AsmOperandClass { 770 let Name = "CondBr"; let PredicateMethod = "isCondBr"; 771 let RenderMethod = "addBranchTargetOperands"; 772} 773def condbrtarget : Operand<OtherVT> { 774 let PrintMethod = "printBranchOperand"; 775 let EncoderMethod = "getCondBrEncoding"; 776 let DecoderMethod = "decodeCondBrTarget"; 777 let ParserMatchClass = PPCCondBrAsmOperand; 778 let OperandType = "OPERAND_PCREL"; 779} 780def abscondbrtarget : Operand<OtherVT> { 781 let PrintMethod = "printAbsBranchOperand"; 782 let EncoderMethod = "getAbsCondBrEncoding"; 783 let ParserMatchClass = PPCCondBrAsmOperand; 784} 785def calltarget : Operand<iPTR> { 786 let PrintMethod = "printBranchOperand"; 787 let EncoderMethod = "getDirectBrEncoding"; 788 let DecoderMethod = "decodeDirectBrTarget"; 789 let ParserMatchClass = PPCDirectBrAsmOperand; 790 let OperandType = "OPERAND_PCREL"; 791} 792def abscalltarget : Operand<iPTR> { 793 let PrintMethod = "printAbsBranchOperand"; 794 let EncoderMethod = "getAbsDirectBrEncoding"; 795 let ParserMatchClass = PPCDirectBrAsmOperand; 796} 797def PPCCRBitMaskOperand : AsmOperandClass { 798 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask"; 799} 800def crbitm: Operand<i8> { 801 let PrintMethod = "printcrbitm"; 802 let EncoderMethod = "get_crbitm_encoding"; 803 let DecoderMethod = "decodeCRBitMOperand"; 804 let ParserMatchClass = PPCCRBitMaskOperand; 805} 806// Address operands 807// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode). 808def PPCRegGxRCNoR0Operand : AsmOperandClass { 809 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber"; 810} 811def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> { 812 let ParserMatchClass = PPCRegGxRCNoR0Operand; 813} 814 815// New addressing modes with 34 bit immediates. 816def PPCDispRI34Operand : AsmOperandClass { 817 let Name = "DispRI34"; let PredicateMethod = "isS34Imm"; 818 let RenderMethod = "addImmOperands"; 819} 820def dispRI34 : Operand<iPTR> { 821 let ParserMatchClass = PPCDispRI34Operand; 822} 823def memri34 : Operand<iPTR> { // memri, imm is a 34-bit value. 824 let PrintMethod = "printMemRegImm34"; 825 let MIOperandInfo = (ops dispRI34:$imm, ptr_rc_nor0:$reg); 826 let EncoderMethod = "getMemRI34Encoding"; 827 let DecoderMethod = "decodeMemRI34Operands"; 828} 829// memri, imm is a 34-bit value for pc-relative instructions where 830// base register is set to zero. 831def memri34_pcrel : Operand<iPTR> { // memri, imm is a 34-bit value. 832 let PrintMethod = "printMemRegImm34PCRel"; 833 let MIOperandInfo = (ops dispRI34:$imm, immZero:$reg); 834 let EncoderMethod = "getMemRI34PCRelEncoding"; 835 let DecoderMethod = "decodeMemRI34PCRelOperands"; 836} 837 838// A version of ptr_rc usable with the asm parser. 839def PPCRegGxRCOperand : AsmOperandClass { 840 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber"; 841} 842def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> { 843 let ParserMatchClass = PPCRegGxRCOperand; 844} 845 846def PPCDispRIOperand : AsmOperandClass { 847 let Name = "DispRI"; let PredicateMethod = "isS16Imm"; 848 let RenderMethod = "addS16ImmOperands"; 849} 850def dispRI : Operand<iPTR> { 851 let ParserMatchClass = PPCDispRIOperand; 852} 853def PPCDispRIXOperand : AsmOperandClass { 854 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4"; 855 let RenderMethod = "addImmOperands"; 856} 857def dispRIX : Operand<iPTR> { 858 let ParserMatchClass = PPCDispRIXOperand; 859} 860def PPCDispRIX16Operand : AsmOperandClass { 861 let Name = "DispRIX16"; let PredicateMethod = "isS16ImmX16"; 862 let RenderMethod = "addImmOperands"; 863} 864def dispRIX16 : Operand<iPTR> { 865 let ParserMatchClass = PPCDispRIX16Operand; 866} 867def PPCDispSPE8Operand : AsmOperandClass { 868 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8"; 869 let RenderMethod = "addImmOperands"; 870} 871def dispSPE8 : Operand<iPTR> { 872 let ParserMatchClass = PPCDispSPE8Operand; 873} 874def PPCDispSPE4Operand : AsmOperandClass { 875 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4"; 876 let RenderMethod = "addImmOperands"; 877} 878def dispSPE4 : Operand<iPTR> { 879 let ParserMatchClass = PPCDispSPE4Operand; 880} 881def PPCDispSPE2Operand : AsmOperandClass { 882 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2"; 883 let RenderMethod = "addImmOperands"; 884} 885def dispSPE2 : Operand<iPTR> { 886 let ParserMatchClass = PPCDispSPE2Operand; 887} 888 889def memri : Operand<iPTR> { 890 let PrintMethod = "printMemRegImm"; 891 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); 892 let EncoderMethod = "getMemRIEncoding"; 893 let DecoderMethod = "decodeMemRIOperands"; 894} 895def memrr : Operand<iPTR> { 896 let PrintMethod = "printMemRegReg"; 897 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg); 898} 899def memrix : Operand<iPTR> { // memri where the imm is 4-aligned. 900 let PrintMethod = "printMemRegImm"; 901 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); 902 let EncoderMethod = "getMemRIXEncoding"; 903 let DecoderMethod = "decodeMemRIXOperands"; 904} 905def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16:27} 906 let PrintMethod = "printMemRegImm"; 907 let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg); 908 let EncoderMethod = "getMemRIX16Encoding"; 909 let DecoderMethod = "decodeMemRIX16Operands"; 910} 911def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned. 912 let PrintMethod = "printMemRegImm"; 913 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg); 914 let EncoderMethod = "getSPE8DisEncoding"; 915 let DecoderMethod = "decodeSPE8Operands"; 916} 917def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned. 918 let PrintMethod = "printMemRegImm"; 919 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg); 920 let EncoderMethod = "getSPE4DisEncoding"; 921 let DecoderMethod = "decodeSPE4Operands"; 922} 923def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned. 924 let PrintMethod = "printMemRegImm"; 925 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg); 926 let EncoderMethod = "getSPE2DisEncoding"; 927 let DecoderMethod = "decodeSPE2Operands"; 928} 929 930// A single-register address. This is used with the SjLj 931// pseudo-instructions which tranlates to LD/LWZ. These instructions requires 932// G8RC_NOX0 registers. 933def memr : Operand<iPTR> { 934 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg); 935} 936def PPCTLSRegOperand : AsmOperandClass { 937 let Name = "TLSReg"; let PredicateMethod = "isTLSReg"; 938 let RenderMethod = "addTLSRegOperands"; 939} 940def tlsreg32 : Operand<i32> { 941 let EncoderMethod = "getTLSRegEncoding"; 942 let ParserMatchClass = PPCTLSRegOperand; 943} 944def tlsgd32 : Operand<i32> {} 945def tlscall32 : Operand<i32> { 946 let PrintMethod = "printTLSCall"; 947 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym); 948 let EncoderMethod = "getTLSCallEncoding"; 949} 950 951// PowerPC Predicate operand. 952def pred : Operand<OtherVT> { 953 let PrintMethod = "printPredicateOperand"; 954 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg); 955} 956 957// Define PowerPC specific addressing mode. 958 959// d-form 960def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; // "stb" 961// ds-form 962def iaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std" 963// dq-form 964def iaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrImmX16", [], []>; // "stxv" 965 966// Below forms are all x-form addressing mode, use three different ones so we 967// can make a accurate check for x-form instructions in ISEL. 968// x-form addressing mode whose associated diplacement form is D. 969def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; // "stbx" 970// x-form addressing mode whose associated diplacement form is DS. 971def xaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrIdxX4", [], []>; // "stdx" 972// x-form addressing mode whose associated diplacement form is DQ. 973def xaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrIdxX16", [], []>; // "stxvx" 974 975def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 976 977// The address in a single register. This is used with the SjLj 978// pseudo-instructions. 979def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>; 980 981/// This is just the offset part of iaddr, used for preinc. 982def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 983 984// PC Relative Address 985def pcreladdr : ComplexPattern<iPTR, 1, "SelectAddrPCRel", [], []>; 986 987//===----------------------------------------------------------------------===// 988// PowerPC Instruction Predicate Definitions. 989def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">; 990def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">; 991def IsBookE : Predicate<"PPCSubTarget->isBookE()">; 992def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">; 993def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">; 994def HasSYNC : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">; 995def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">; 996def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">; 997def IsE500 : Predicate<"PPCSubTarget->isE500()">; 998def HasSPE : Predicate<"PPCSubTarget->hasSPE()">; 999def HasICBT : Predicate<"PPCSubTarget->hasICBT()">; 1000def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">; 1001def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">; 1002def NaNsFPMath : Predicate<"!TM.Options.NoNaNsFPMath">; 1003def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">; 1004def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">; 1005def IsISA3_0 : Predicate<"PPCSubTarget->isISA3_0()">; 1006def HasFPU : Predicate<"PPCSubTarget->hasFPU()">; 1007def PCRelativeMemops : Predicate<"PPCSubTarget->hasPCRelativeMemops()">; 1008 1009//===----------------------------------------------------------------------===// 1010// PowerPC Multiclass Definitions. 1011 1012multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1013 string asmbase, string asmstr, InstrItinClass itin, 1014 list<dag> pattern> { 1015 let BaseName = asmbase in { 1016 def NAME : XForm_6<opcode, xo, OOL, IOL, 1017 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1018 pattern>, RecFormRel; 1019 let Defs = [CR0] in 1020 def _rec : XForm_6<opcode, xo, OOL, IOL, 1021 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1022 []>, isRecordForm, RecFormRel; 1023 } 1024} 1025 1026multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1027 string asmbase, string asmstr, InstrItinClass itin, 1028 list<dag> pattern> { 1029 let BaseName = asmbase in { 1030 let Defs = [CARRY] in 1031 def NAME : XForm_6<opcode, xo, OOL, IOL, 1032 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1033 pattern>, RecFormRel; 1034 let Defs = [CARRY, CR0] in 1035 def _rec : XForm_6<opcode, xo, OOL, IOL, 1036 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1037 []>, isRecordForm, RecFormRel; 1038 } 1039} 1040 1041multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1042 string asmbase, string asmstr, InstrItinClass itin, 1043 list<dag> pattern> { 1044 let BaseName = asmbase in { 1045 let Defs = [CARRY] in 1046 def NAME : XForm_10<opcode, xo, OOL, IOL, 1047 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1048 pattern>, RecFormRel; 1049 let Defs = [CARRY, CR0] in 1050 def _rec : XForm_10<opcode, xo, OOL, IOL, 1051 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1052 []>, isRecordForm, RecFormRel; 1053 } 1054} 1055 1056multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1057 string asmbase, string asmstr, InstrItinClass itin, 1058 list<dag> pattern> { 1059 let BaseName = asmbase in { 1060 def NAME : XForm_11<opcode, xo, OOL, IOL, 1061 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1062 pattern>, RecFormRel; 1063 let Defs = [CR0] in 1064 def _rec : XForm_11<opcode, xo, OOL, IOL, 1065 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1066 []>, isRecordForm, RecFormRel; 1067 } 1068} 1069 1070multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1071 string asmbase, string asmstr, InstrItinClass itin, 1072 list<dag> pattern> { 1073 let BaseName = asmbase in { 1074 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 1075 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1076 pattern>, RecFormRel; 1077 let Defs = [CR0] in 1078 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 1079 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1080 []>, isRecordForm, RecFormRel; 1081 } 1082} 1083 1084// Multiclass for instructions which have a record overflow form as well 1085// as a record form but no carry (i.e. mulld, mulldo, subf, subfo, etc.) 1086multiclass XOForm_1rx<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1087 string asmbase, string asmstr, InstrItinClass itin, 1088 list<dag> pattern> { 1089 let BaseName = asmbase in { 1090 def NAME : XOForm_1<opcode, xo, 0, OOL, IOL, 1091 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1092 pattern>, RecFormRel; 1093 let Defs = [CR0] in 1094 def _rec : XOForm_1<opcode, xo, 0, OOL, IOL, 1095 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1096 []>, isRecordForm, RecFormRel; 1097 } 1098 let BaseName = !strconcat(asmbase, "O") in { 1099 let Defs = [XER] in 1100 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 1101 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1102 []>, RecFormRel; 1103 let Defs = [XER, CR0] in 1104 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 1105 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1106 []>, isRecordForm, RecFormRel; 1107 } 1108} 1109 1110// Multiclass for instructions for which the non record form is not cracked 1111// and the record form is cracked (i.e. divw, mullw, etc.) 1112multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1113 string asmbase, string asmstr, InstrItinClass itin, 1114 list<dag> pattern> { 1115 let BaseName = asmbase in { 1116 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 1117 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1118 pattern>, RecFormRel; 1119 let Defs = [CR0] in 1120 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 1121 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1122 []>, isRecordForm, RecFormRel, PPC970_DGroup_First, 1123 PPC970_DGroup_Cracked; 1124 } 1125 let BaseName = !strconcat(asmbase, "O") in { 1126 let Defs = [XER] in 1127 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 1128 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1129 []>, RecFormRel; 1130 let Defs = [XER, CR0] in 1131 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 1132 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1133 []>, isRecordForm, RecFormRel; 1134 } 1135} 1136 1137multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1138 string asmbase, string asmstr, InstrItinClass itin, 1139 list<dag> pattern> { 1140 let BaseName = asmbase in { 1141 let Defs = [CARRY] in 1142 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 1143 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1144 pattern>, RecFormRel; 1145 let Defs = [CARRY, CR0] in 1146 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 1147 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1148 []>, isRecordForm, RecFormRel; 1149 } 1150 let BaseName = !strconcat(asmbase, "O") in { 1151 let Defs = [CARRY, XER] in 1152 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 1153 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1154 []>, RecFormRel; 1155 let Defs = [CARRY, XER, CR0] in 1156 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 1157 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1158 []>, isRecordForm, RecFormRel; 1159 } 1160} 1161 1162multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1163 string asmbase, string asmstr, InstrItinClass itin, 1164 list<dag> pattern> { 1165 let BaseName = asmbase in { 1166 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 1167 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1168 pattern>, RecFormRel; 1169 let Defs = [CR0] in 1170 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 1171 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1172 []>, isRecordForm, RecFormRel; 1173 } 1174 let BaseName = !strconcat(asmbase, "O") in { 1175 let Defs = [XER] in 1176 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 1177 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1178 []>, RecFormRel; 1179 let Defs = [XER, CR0] in 1180 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 1181 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1182 []>, isRecordForm, RecFormRel; 1183 } 1184} 1185 1186multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1187 string asmbase, string asmstr, InstrItinClass itin, 1188 list<dag> pattern> { 1189 let BaseName = asmbase in { 1190 let Defs = [CARRY] in 1191 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 1192 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1193 pattern>, RecFormRel; 1194 let Defs = [CARRY, CR0] in 1195 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 1196 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1197 []>, isRecordForm, RecFormRel; 1198 } 1199 let BaseName = !strconcat(asmbase, "O") in { 1200 let Defs = [CARRY, XER] in 1201 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 1202 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1203 []>, RecFormRel; 1204 let Defs = [CARRY, XER, CR0] in 1205 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 1206 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1207 []>, isRecordForm, RecFormRel; 1208 } 1209} 1210 1211multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL, 1212 string asmbase, string asmstr, InstrItinClass itin, 1213 list<dag> pattern> { 1214 let BaseName = asmbase in { 1215 def NAME : MForm_2<opcode, OOL, IOL, 1216 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1217 pattern>, RecFormRel; 1218 let Defs = [CR0] in 1219 def _rec : MForm_2<opcode, OOL, IOL, 1220 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1221 []>, isRecordForm, RecFormRel; 1222 } 1223} 1224 1225multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 1226 string asmbase, string asmstr, InstrItinClass itin, 1227 list<dag> pattern> { 1228 let BaseName = asmbase in { 1229 def NAME : MDForm_1<opcode, xo, OOL, IOL, 1230 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1231 pattern>, RecFormRel; 1232 let Defs = [CR0] in 1233 def _rec : MDForm_1<opcode, xo, OOL, IOL, 1234 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1235 []>, isRecordForm, RecFormRel; 1236 } 1237} 1238 1239multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 1240 string asmbase, string asmstr, InstrItinClass itin, 1241 list<dag> pattern> { 1242 let BaseName = asmbase in { 1243 def NAME : MDSForm_1<opcode, xo, OOL, IOL, 1244 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1245 pattern>, RecFormRel; 1246 let Defs = [CR0] in 1247 def _rec : MDSForm_1<opcode, xo, OOL, IOL, 1248 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1249 []>, isRecordForm, RecFormRel; 1250 } 1251} 1252 1253multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1254 string asmbase, string asmstr, InstrItinClass itin, 1255 list<dag> pattern> { 1256 let BaseName = asmbase in { 1257 let Defs = [CARRY] in 1258 def NAME : XSForm_1<opcode, xo, OOL, IOL, 1259 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1260 pattern>, RecFormRel; 1261 let Defs = [CARRY, CR0] in 1262 def _rec : XSForm_1<opcode, xo, OOL, IOL, 1263 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1264 []>, isRecordForm, RecFormRel; 1265 } 1266} 1267 1268multiclass XSForm_1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1269 string asmbase, string asmstr, InstrItinClass itin, 1270 list<dag> pattern> { 1271 let BaseName = asmbase in { 1272 def NAME : XSForm_1<opcode, xo, OOL, IOL, 1273 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1274 pattern>, RecFormRel; 1275 let Defs = [CR0] in 1276 def _rec : XSForm_1<opcode, xo, OOL, IOL, 1277 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1278 []>, isRecordForm, RecFormRel; 1279 } 1280} 1281 1282multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1283 string asmbase, string asmstr, InstrItinClass itin, 1284 list<dag> pattern> { 1285 let BaseName = asmbase in { 1286 def NAME : XForm_26<opcode, xo, OOL, IOL, 1287 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1288 pattern>, RecFormRel; 1289 let Defs = [CR1] in 1290 def _rec : XForm_26<opcode, xo, OOL, IOL, 1291 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1292 []>, isRecordForm, RecFormRel; 1293 } 1294} 1295 1296multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1297 string asmbase, string asmstr, InstrItinClass itin, 1298 list<dag> pattern> { 1299 let BaseName = asmbase in { 1300 def NAME : XForm_28<opcode, xo, OOL, IOL, 1301 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1302 pattern>, RecFormRel; 1303 let Defs = [CR1] in 1304 def _rec : XForm_28<opcode, xo, OOL, IOL, 1305 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1306 []>, isRecordForm, RecFormRel; 1307 } 1308} 1309 1310multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1311 string asmbase, string asmstr, InstrItinClass itin, 1312 list<dag> pattern> { 1313 let BaseName = asmbase in { 1314 def NAME : AForm_1<opcode, xo, OOL, IOL, 1315 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1316 pattern>, RecFormRel; 1317 let Defs = [CR1] in 1318 def _rec : AForm_1<opcode, xo, OOL, IOL, 1319 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1320 []>, isRecordForm, RecFormRel; 1321 } 1322} 1323 1324multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1325 string asmbase, string asmstr, InstrItinClass itin, 1326 list<dag> pattern> { 1327 let BaseName = asmbase in { 1328 def NAME : AForm_2<opcode, xo, OOL, IOL, 1329 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1330 pattern>, RecFormRel; 1331 let Defs = [CR1] in 1332 def _rec : AForm_2<opcode, xo, OOL, IOL, 1333 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1334 []>, isRecordForm, RecFormRel; 1335 } 1336} 1337 1338multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1339 string asmbase, string asmstr, InstrItinClass itin, 1340 list<dag> pattern> { 1341 let BaseName = asmbase in { 1342 def NAME : AForm_3<opcode, xo, OOL, IOL, 1343 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1344 pattern>, RecFormRel; 1345 let Defs = [CR1] in 1346 def _rec : AForm_3<opcode, xo, OOL, IOL, 1347 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1348 []>, isRecordForm, RecFormRel; 1349 } 1350} 1351 1352//===----------------------------------------------------------------------===// 1353// PowerPC Instruction Definitions. 1354 1355// Pseudo instructions: 1356 1357let hasCtrlDep = 1 in { 1358let Defs = [R1], Uses = [R1] in { 1359def ADJCALLSTACKDOWN : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1360 "#ADJCALLSTACKDOWN $amt1 $amt2", 1361 [(callseq_start timm:$amt1, timm:$amt2)]>; 1362def ADJCALLSTACKUP : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1363 "#ADJCALLSTACKUP $amt1 $amt2", 1364 [(callseq_end timm:$amt1, timm:$amt2)]>; 1365} 1366 1367def UPDATE_VRSAVE : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$rS), 1368 "UPDATE_VRSAVE $rD, $rS", []>; 1369} 1370 1371let Defs = [R1], Uses = [R1] in 1372def DYNALLOC : PPCEmitTimePseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC", 1373 [(set i32:$result, 1374 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; 1375def DYNAREAOFFSET : PPCEmitTimePseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET", 1376 [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 1377 1378// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 1379// instruction selection into a branch sequence. 1380let PPC970_Single = 1 in { 1381 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes 1382 // because either operand might become the first operand in an isel, and 1383 // that operand cannot be r0. 1384 def SELECT_CC_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crrc:$cond, 1385 gprc_nor0:$T, gprc_nor0:$F, 1386 i32imm:$BROPC), "#SELECT_CC_I4", 1387 []>; 1388 def SELECT_CC_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crrc:$cond, 1389 g8rc_nox0:$T, g8rc_nox0:$F, 1390 i32imm:$BROPC), "#SELECT_CC_I8", 1391 []>; 1392 def SELECT_CC_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F, 1393 i32imm:$BROPC), "#SELECT_CC_F4", 1394 []>; 1395 def SELECT_CC_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F, 1396 i32imm:$BROPC), "#SELECT_CC_F8", 1397 []>; 1398 def SELECT_CC_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1399 i32imm:$BROPC), "#SELECT_CC_F16", 1400 []>; 1401 def SELECT_CC_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1402 i32imm:$BROPC), "#SELECT_CC_VRRC", 1403 []>; 1404 1405 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition 1406 // register bit directly. 1407 def SELECT_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crbitrc:$cond, 1408 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4", 1409 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>; 1410 def SELECT_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crbitrc:$cond, 1411 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8", 1412 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>; 1413let Predicates = [HasFPU] in { 1414 def SELECT_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crbitrc:$cond, 1415 f4rc:$T, f4rc:$F), "#SELECT_F4", 1416 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>; 1417 def SELECT_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crbitrc:$cond, 1418 f8rc:$T, f8rc:$F), "#SELECT_F8", 1419 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>; 1420 def SELECT_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1421 vrrc:$T, vrrc:$F), "#SELECT_F16", 1422 [(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>; 1423} 1424 def SELECT_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1425 vrrc:$T, vrrc:$F), "#SELECT_VRRC", 1426 [(set v4i32:$dst, 1427 (select i1:$cond, v4i32:$T, v4i32:$F))]>; 1428} 1429 1430// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 1431// scavenge a register for it. 1432let mayStore = 1 in { 1433def SPILL_CR : PPCEmitTimePseudo<(outs), (ins crrc:$cond, memri:$F), 1434 "#SPILL_CR", []>; 1435def SPILL_CRBIT : PPCEmitTimePseudo<(outs), (ins crbitrc:$cond, memri:$F), 1436 "#SPILL_CRBIT", []>; 1437} 1438 1439// RESTORE_CR - Indicate that we're restoring the CR register (previously 1440// spilled), so we'll need to scavenge a register for it. 1441let mayLoad = 1 in { 1442def RESTORE_CR : PPCEmitTimePseudo<(outs crrc:$cond), (ins memri:$F), 1443 "#RESTORE_CR", []>; 1444def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F), 1445 "#RESTORE_CRBIT", []>; 1446} 1447 1448let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 1449 let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in 1450 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 1451 [(retflag)]>, Requires<[In32BitMode]>; 1452 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { 1453 let isPredicable = 1 in 1454 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1455 []>; 1456 1457 let isCodeGenOnly = 1 in { 1458 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 1459 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 1460 []>; 1461 1462 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 1463 "bcctr 12, $bi, 0", IIC_BrB, []>; 1464 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 1465 "bcctr 4, $bi, 0", IIC_BrB, []>; 1466 } 1467 } 1468} 1469 1470// Set the float rounding mode. 1471let Uses = [RM], Defs = [RM] in { 1472def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND), 1473 "#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>; 1474 1475def SETRND : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins gprc:$in), 1476 "#SETRND", [(set f64:$FRT, (int_ppc_setrnd gprc :$in))]>; 1477} 1478 1479let Defs = [LR] in 1480 def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>, 1481 PPC970_Unit_BRU; 1482let Defs = [LR] in 1483 def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>, 1484 PPC970_Unit_BRU; 1485 1486let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 1487 let isBarrier = 1 in { 1488 let isPredicable = 1 in 1489 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), 1490 "b $dst", IIC_BrB, 1491 [(br bb:$dst)]>; 1492 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst), 1493 "ba $dst", IIC_BrB, []>; 1494 } 1495 1496 // BCC represents an arbitrary conditional branch on a predicate. 1497 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 1498 // a two-value operand where a dag node expects two operands. :( 1499 let isCodeGenOnly = 1 in { 1500 class BCC_class : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), 1501 "b${cond:cc}${cond:pm} ${cond:reg}, $dst" 1502 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>; 1503 def BCC : BCC_class; 1504 1505 // The same as BCC, except that it's not a terminator. Used for introducing 1506 // control flow dependency without creating new blocks. 1507 let isTerminator = 0 in def CTRL_DEP : BCC_class; 1508 1509 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst), 1510 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">; 1511 1512 let isReturn = 1, Uses = [LR, RM] in 1513 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond), 1514 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>; 1515 } 1516 1517 let isCodeGenOnly = 1 in { 1518 let Pattern = [(brcond i1:$bi, bb:$dst)] in 1519 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1520 "bc 12, $bi, $dst">; 1521 1522 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in 1523 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1524 "bc 4, $bi, $dst">; 1525 1526 let isReturn = 1, Uses = [LR, RM] in 1527 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi), 1528 "bclr 12, $bi, 0", IIC_BrB, []>; 1529 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi), 1530 "bclr 4, $bi, 0", IIC_BrB, []>; 1531 } 1532 1533 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in { 1534 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 1535 "bdzlr", IIC_BrB, []>; 1536 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 1537 "bdnzlr", IIC_BrB, []>; 1538 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins), 1539 "bdzlr+", IIC_BrB, []>; 1540 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins), 1541 "bdnzlr+", IIC_BrB, []>; 1542 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins), 1543 "bdzlr-", IIC_BrB, []>; 1544 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins), 1545 "bdnzlr-", IIC_BrB, []>; 1546 } 1547 1548 let Defs = [CTR], Uses = [CTR] in { 1549 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 1550 "bdz $dst">; 1551 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 1552 "bdnz $dst">; 1553 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst), 1554 "bdza $dst">; 1555 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst), 1556 "bdnza $dst">; 1557 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst), 1558 "bdz+ $dst">; 1559 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst), 1560 "bdnz+ $dst">; 1561 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst), 1562 "bdza+ $dst">; 1563 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst), 1564 "bdnza+ $dst">; 1565 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst), 1566 "bdz- $dst">; 1567 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst), 1568 "bdnz- $dst">; 1569 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst), 1570 "bdza- $dst">; 1571 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst), 1572 "bdnza- $dst">; 1573 } 1574} 1575 1576// The unconditional BCL used by the SjLj setjmp code. 1577let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in { 1578 let Defs = [LR], Uses = [RM] in { 1579 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst), 1580 "bcl 20, 31, $dst">; 1581 } 1582} 1583 1584let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 1585 // Convenient aliases for call instructions 1586 let Uses = [RM] in { 1587 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func), 1588 "bl $func", IIC_BrB, []>; // See Pat patterns below. 1589 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 1590 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>; 1591 1592 let isCodeGenOnly = 1 in { 1593 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func), 1594 "bl $func", IIC_BrB, []>; 1595 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst), 1596 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">; 1597 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst), 1598 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">; 1599 1600 def BCL : BForm_4<16, 12, 0, 1, (outs), 1601 (ins crbitrc:$bi, condbrtarget:$dst), 1602 "bcl 12, $bi, $dst">; 1603 def BCLn : BForm_4<16, 4, 0, 1, (outs), 1604 (ins crbitrc:$bi, condbrtarget:$dst), 1605 "bcl 4, $bi, $dst">; 1606 def BL_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 1607 (outs), (ins calltarget:$func), 1608 "bl $func\n\tnop", IIC_BrB, []>; 1609 } 1610 } 1611 let Uses = [CTR, RM] in { 1612 let isPredicable = 1 in 1613 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1614 "bctrl", IIC_BrB, [(PPCbctrl)]>, 1615 Requires<[In32BitMode]>; 1616 1617 let isCodeGenOnly = 1 in { 1618 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 1619 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 1620 []>; 1621 1622 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 1623 "bcctrl 12, $bi, 0", IIC_BrB, []>; 1624 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 1625 "bcctrl 4, $bi, 0", IIC_BrB, []>; 1626 } 1627 } 1628 let Uses = [LR, RM] in { 1629 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins), 1630 "blrl", IIC_BrB, []>; 1631 1632 let isCodeGenOnly = 1 in { 1633 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond), 1634 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB, 1635 []>; 1636 1637 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi), 1638 "bclrl 12, $bi, 0", IIC_BrB, []>; 1639 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi), 1640 "bclrl 4, $bi, 0", IIC_BrB, []>; 1641 } 1642 } 1643 let Defs = [CTR], Uses = [CTR, RM] in { 1644 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst), 1645 "bdzl $dst">; 1646 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst), 1647 "bdnzl $dst">; 1648 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst), 1649 "bdzla $dst">; 1650 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst), 1651 "bdnzla $dst">; 1652 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst), 1653 "bdzl+ $dst">; 1654 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst), 1655 "bdnzl+ $dst">; 1656 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst), 1657 "bdzla+ $dst">; 1658 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst), 1659 "bdnzla+ $dst">; 1660 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst), 1661 "bdzl- $dst">; 1662 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst), 1663 "bdnzl- $dst">; 1664 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst), 1665 "bdzla- $dst">; 1666 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst), 1667 "bdnzla- $dst">; 1668 } 1669 let Defs = [CTR], Uses = [CTR, LR, RM] in { 1670 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins), 1671 "bdzlrl", IIC_BrB, []>; 1672 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins), 1673 "bdnzlrl", IIC_BrB, []>; 1674 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins), 1675 "bdzlrl+", IIC_BrB, []>; 1676 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins), 1677 "bdnzlrl+", IIC_BrB, []>; 1678 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins), 1679 "bdzlrl-", IIC_BrB, []>; 1680 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins), 1681 "bdnzlrl-", IIC_BrB, []>; 1682 } 1683} 1684 1685let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1686def TCRETURNdi :PPCEmitTimePseudo< (outs), 1687 (ins calltarget:$dst, i32imm:$offset), 1688 "#TC_RETURNd $dst $offset", 1689 []>; 1690 1691 1692let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1693def TCRETURNai :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 1694 "#TC_RETURNa $func $offset", 1695 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 1696 1697let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1698def TCRETURNri : PPCEmitTimePseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 1699 "#TC_RETURNr $dst $offset", 1700 []>; 1701 1702let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 1703 Defs = [LR, R2], Uses = [CTR, RM], RST = 2 in { 1704 def BCTRL_LWZinto_toc: 1705 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), 1706 (ins memri:$src), "bctrl\n\tlwz 2, $src", IIC_BrB, 1707 [(PPCbctrl_load_toc iaddr:$src)]>, Requires<[In32BitMode]>; 1708 1709} 1710 1711 1712let isCodeGenOnly = 1 in { 1713 1714let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 1715 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 1716def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1717 []>, Requires<[In32BitMode]>; 1718 1719let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1720 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1721def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 1722 "b $dst", IIC_BrB, 1723 []>; 1724 1725let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1726 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1727def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 1728 "ba $dst", IIC_BrB, 1729 []>; 1730 1731} 1732 1733// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 1734// is not. 1735let hasSideEffects = 1 in { 1736 let Defs = [CTR] in 1737 def EH_SjLj_SetJmp32 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 1738 "#EH_SJLJ_SETJMP32", 1739 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 1740 Requires<[In32BitMode]>; 1741} 1742 1743let hasSideEffects = 1, isBarrier = 1 in { 1744 let isTerminator = 1 in 1745 def EH_SjLj_LongJmp32 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 1746 "#EH_SJLJ_LONGJMP32", 1747 [(PPCeh_sjlj_longjmp addr:$buf)]>, 1748 Requires<[In32BitMode]>; 1749} 1750 1751// This pseudo is never removed from the function, as it serves as 1752// a terminator. Size is set to 0 to prevent the builtin assembler 1753// from emitting it. 1754let isBranch = 1, isTerminator = 1, Size = 0 in { 1755 def EH_SjLj_Setup : PPCEmitTimePseudo<(outs), (ins directbrtarget:$dst), 1756 "#EH_SjLj_Setup\t$dst", []>; 1757} 1758 1759// System call. 1760let PPC970_Unit = 7 in { 1761 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev), 1762 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>; 1763} 1764 1765// Branch history rolling buffer. 1766def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB, 1767 [(PPCclrbhrb)]>, 1768 PPC970_DGroup_Single; 1769// The $dmy argument used for MFBHRBE is not needed; however, including 1770// it avoids automatic generation of PPCFastISel::fastEmit_i(), which 1771// interferes with necessary special handling (see PPCFastISel.cpp). 1772def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD), 1773 (ins u10imm:$imm, u10imm:$dmy), 1774 "mfbhrbe $rD, $imm", IIC_BrB, 1775 [(set i32:$rD, 1776 (PPCmfbhrbe imm:$imm, imm:$dmy))]>, 1777 PPC970_DGroup_First; 1778 1779def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm", 1780 IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>, 1781 PPC970_DGroup_Single; 1782 1783// DCB* instructions. 1784def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst", 1785 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 1786 PPC970_DGroup_Single; 1787def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst", 1788 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 1789 PPC970_DGroup_Single; 1790def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst", 1791 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 1792 PPC970_DGroup_Single; 1793def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst", 1794 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 1795 PPC970_DGroup_Single; 1796def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst", 1797 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 1798 PPC970_DGroup_Single; 1799 1800def DCBF : DCB_Form_hint<86, (outs), (ins u5imm:$TH, memrr:$dst), 1801 "dcbf $dst, $TH", IIC_LdStDCBF, []>, 1802 PPC970_DGroup_Single; 1803 1804let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { 1805def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst), 1806 "dcbt $dst, $TH", IIC_LdStDCBF, []>, 1807 PPC970_DGroup_Single; 1808def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst), 1809 "dcbtst $dst, $TH", IIC_LdStDCBF, []>, 1810 PPC970_DGroup_Single; 1811} // hasSideEffects = 0 1812 1813def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, memrr:$src), 1814 "icblc $CT, $src", IIC_LdStStore>, Requires<[HasICBT]>; 1815def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, memrr:$src), 1816 "icblq. $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 1817def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src), 1818 "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 1819def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src), 1820 "icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 1821 1822def : Pat<(int_ppc_dcbt xoaddr:$dst), 1823 (DCBT 0, xoaddr:$dst)>; 1824def : Pat<(int_ppc_dcbtst xoaddr:$dst), 1825 (DCBTST 0, xoaddr:$dst)>; 1826def : Pat<(int_ppc_dcbf xoaddr:$dst), 1827 (DCBF 0, xoaddr:$dst)>; 1828 1829def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), 1830 (DCBT 0, xoaddr:$dst)>; // data prefetch for loads 1831def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)), 1832 (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores 1833def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)), 1834 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read) 1835 1836// Atomic operations 1837// FIXME: some of these might be used with constant operands. This will result 1838// in constant materialization instructions that may be redundant. We currently 1839// clean this up in PPCMIPeephole with calls to 1840// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 1841// in the first place. 1842let Defs = [CR0] in { 1843 def ATOMIC_LOAD_ADD_I8 : PPCCustomInserterPseudo< 1844 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8", 1845 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>; 1846 def ATOMIC_LOAD_SUB_I8 : PPCCustomInserterPseudo< 1847 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8", 1848 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>; 1849 def ATOMIC_LOAD_AND_I8 : PPCCustomInserterPseudo< 1850 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8", 1851 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>; 1852 def ATOMIC_LOAD_OR_I8 : PPCCustomInserterPseudo< 1853 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8", 1854 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>; 1855 def ATOMIC_LOAD_XOR_I8 : PPCCustomInserterPseudo< 1856 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8", 1857 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>; 1858 def ATOMIC_LOAD_NAND_I8 : PPCCustomInserterPseudo< 1859 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8", 1860 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>; 1861 def ATOMIC_LOAD_MIN_I8 : PPCCustomInserterPseudo< 1862 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8", 1863 [(set i32:$dst, (atomic_load_min_8 xoaddr:$ptr, i32:$incr))]>; 1864 def ATOMIC_LOAD_MAX_I8 : PPCCustomInserterPseudo< 1865 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8", 1866 [(set i32:$dst, (atomic_load_max_8 xoaddr:$ptr, i32:$incr))]>; 1867 def ATOMIC_LOAD_UMIN_I8 : PPCCustomInserterPseudo< 1868 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8", 1869 [(set i32:$dst, (atomic_load_umin_8 xoaddr:$ptr, i32:$incr))]>; 1870 def ATOMIC_LOAD_UMAX_I8 : PPCCustomInserterPseudo< 1871 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8", 1872 [(set i32:$dst, (atomic_load_umax_8 xoaddr:$ptr, i32:$incr))]>; 1873 def ATOMIC_LOAD_ADD_I16 : PPCCustomInserterPseudo< 1874 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16", 1875 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>; 1876 def ATOMIC_LOAD_SUB_I16 : PPCCustomInserterPseudo< 1877 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16", 1878 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>; 1879 def ATOMIC_LOAD_AND_I16 : PPCCustomInserterPseudo< 1880 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16", 1881 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>; 1882 def ATOMIC_LOAD_OR_I16 : PPCCustomInserterPseudo< 1883 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16", 1884 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>; 1885 def ATOMIC_LOAD_XOR_I16 : PPCCustomInserterPseudo< 1886 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16", 1887 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>; 1888 def ATOMIC_LOAD_NAND_I16 : PPCCustomInserterPseudo< 1889 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16", 1890 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>; 1891 def ATOMIC_LOAD_MIN_I16 : PPCCustomInserterPseudo< 1892 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16", 1893 [(set i32:$dst, (atomic_load_min_16 xoaddr:$ptr, i32:$incr))]>; 1894 def ATOMIC_LOAD_MAX_I16 : PPCCustomInserterPseudo< 1895 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16", 1896 [(set i32:$dst, (atomic_load_max_16 xoaddr:$ptr, i32:$incr))]>; 1897 def ATOMIC_LOAD_UMIN_I16 : PPCCustomInserterPseudo< 1898 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16", 1899 [(set i32:$dst, (atomic_load_umin_16 xoaddr:$ptr, i32:$incr))]>; 1900 def ATOMIC_LOAD_UMAX_I16 : PPCCustomInserterPseudo< 1901 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16", 1902 [(set i32:$dst, (atomic_load_umax_16 xoaddr:$ptr, i32:$incr))]>; 1903 def ATOMIC_LOAD_ADD_I32 : PPCCustomInserterPseudo< 1904 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32", 1905 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>; 1906 def ATOMIC_LOAD_SUB_I32 : PPCCustomInserterPseudo< 1907 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32", 1908 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>; 1909 def ATOMIC_LOAD_AND_I32 : PPCCustomInserterPseudo< 1910 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32", 1911 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>; 1912 def ATOMIC_LOAD_OR_I32 : PPCCustomInserterPseudo< 1913 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32", 1914 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>; 1915 def ATOMIC_LOAD_XOR_I32 : PPCCustomInserterPseudo< 1916 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32", 1917 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>; 1918 def ATOMIC_LOAD_NAND_I32 : PPCCustomInserterPseudo< 1919 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32", 1920 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>; 1921 def ATOMIC_LOAD_MIN_I32 : PPCCustomInserterPseudo< 1922 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32", 1923 [(set i32:$dst, (atomic_load_min_32 xoaddr:$ptr, i32:$incr))]>; 1924 def ATOMIC_LOAD_MAX_I32 : PPCCustomInserterPseudo< 1925 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32", 1926 [(set i32:$dst, (atomic_load_max_32 xoaddr:$ptr, i32:$incr))]>; 1927 def ATOMIC_LOAD_UMIN_I32 : PPCCustomInserterPseudo< 1928 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32", 1929 [(set i32:$dst, (atomic_load_umin_32 xoaddr:$ptr, i32:$incr))]>; 1930 def ATOMIC_LOAD_UMAX_I32 : PPCCustomInserterPseudo< 1931 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32", 1932 [(set i32:$dst, (atomic_load_umax_32 xoaddr:$ptr, i32:$incr))]>; 1933 1934 def ATOMIC_CMP_SWAP_I8 : PPCCustomInserterPseudo< 1935 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8", 1936 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>; 1937 def ATOMIC_CMP_SWAP_I16 : PPCCustomInserterPseudo< 1938 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 1939 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>; 1940 def ATOMIC_CMP_SWAP_I32 : PPCCustomInserterPseudo< 1941 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 1942 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>; 1943 1944 def ATOMIC_SWAP_I8 : PPCCustomInserterPseudo< 1945 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8", 1946 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>; 1947 def ATOMIC_SWAP_I16 : PPCCustomInserterPseudo< 1948 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16", 1949 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>; 1950 def ATOMIC_SWAP_I32 : PPCCustomInserterPseudo< 1951 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32", 1952 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>; 1953} 1954 1955def : Pat<(PPCatomicCmpSwap_8 xoaddr:$ptr, i32:$old, i32:$new), 1956 (ATOMIC_CMP_SWAP_I8 xoaddr:$ptr, i32:$old, i32:$new)>; 1957def : Pat<(PPCatomicCmpSwap_16 xoaddr:$ptr, i32:$old, i32:$new), 1958 (ATOMIC_CMP_SWAP_I16 xoaddr:$ptr, i32:$old, i32:$new)>; 1959 1960// Instructions to support atomic operations 1961let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 1962def LBARX : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src), 1963 "lbarx $rD, $src", IIC_LdStLWARX, []>, 1964 Requires<[HasPartwordAtomics]>; 1965 1966def LHARX : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src), 1967 "lharx $rD, $src", IIC_LdStLWARX, []>, 1968 Requires<[HasPartwordAtomics]>; 1969 1970def LWARX : XForm_1_memOp<31, 20, (outs gprc:$rD), (ins memrr:$src), 1971 "lwarx $rD, $src", IIC_LdStLWARX, []>; 1972 1973// Instructions to support lock versions of atomics 1974// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 1975def LBARXL : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src), 1976 "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm, 1977 Requires<[HasPartwordAtomics]>; 1978 1979def LHARXL : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src), 1980 "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm, 1981 Requires<[HasPartwordAtomics]>; 1982 1983def LWARXL : XForm_1_memOp<31, 20, (outs gprc:$rD), (ins memrr:$src), 1984 "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm; 1985 1986// The atomic instructions use the destination register as well as the next one 1987// or two registers in order (modulo 31). 1988let hasExtraSrcRegAllocReq = 1 in 1989def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC), 1990 "lwat $rD, $rA, $FC", IIC_LdStLoad>, 1991 Requires<[IsISA3_0]>; 1992} 1993 1994let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { 1995def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$rS, memrr:$dst), 1996 "stbcx. $rS, $dst", IIC_LdStSTWCX, []>, 1997 isRecordForm, Requires<[HasPartwordAtomics]>; 1998 1999def STHCX : XForm_1_memOp<31, 726, (outs), (ins gprc:$rS, memrr:$dst), 2000 "sthcx. $rS, $dst", IIC_LdStSTWCX, []>, 2001 isRecordForm, Requires<[HasPartwordAtomics]>; 2002 2003def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$rS, memrr:$dst), 2004 "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isRecordForm; 2005} 2006 2007let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 2008def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC), 2009 "stwat $rS, $rA, $FC", IIC_LdStStore>, 2010 Requires<[IsISA3_0]>; 2011 2012let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 2013def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>; 2014 2015def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm), 2016 "twi $to, $rA, $imm", IIC_IntTrapW, []>; 2017def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB), 2018 "tw $to, $rA, $rB", IIC_IntTrapW, []>; 2019def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm), 2020 "tdi $to, $rA, $imm", IIC_IntTrapD, []>; 2021def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB), 2022 "td $to, $rA, $rB", IIC_IntTrapD, []>; 2023 2024//===----------------------------------------------------------------------===// 2025// PPC32 Load Instructions. 2026// 2027 2028// Unindexed (r+i) Loads. 2029let PPC970_Unit = 2 in { 2030def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src), 2031 "lbz $rD, $src", IIC_LdStLoad, 2032 [(set i32:$rD, (zextloadi8 iaddr:$src))]>; 2033def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src), 2034 "lha $rD, $src", IIC_LdStLHA, 2035 [(set i32:$rD, (sextloadi16 iaddr:$src))]>, 2036 PPC970_DGroup_Cracked; 2037def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src), 2038 "lhz $rD, $src", IIC_LdStLoad, 2039 [(set i32:$rD, (zextloadi16 iaddr:$src))]>; 2040def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src), 2041 "lwz $rD, $src", IIC_LdStLoad, 2042 [(set i32:$rD, (load iaddr:$src))]>; 2043 2044let Predicates = [HasFPU] in { 2045def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src), 2046 "lfs $rD, $src", IIC_LdStLFD, 2047 [(set f32:$rD, (load iaddr:$src))]>; 2048def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src), 2049 "lfd $rD, $src", IIC_LdStLFD, 2050 [(set f64:$rD, (load iaddr:$src))]>; 2051} 2052 2053 2054// Unindexed (r+i) Loads with Update (preinc). 2055let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 2056def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2057 "lbzu $rD, $addr", IIC_LdStLoadUpd, 2058 []>, RegConstraint<"$addr.reg = $ea_result">, 2059 NoEncode<"$ea_result">; 2060 2061def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2062 "lhau $rD, $addr", IIC_LdStLHAU, 2063 []>, RegConstraint<"$addr.reg = $ea_result">, 2064 NoEncode<"$ea_result">; 2065 2066def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2067 "lhzu $rD, $addr", IIC_LdStLoadUpd, 2068 []>, RegConstraint<"$addr.reg = $ea_result">, 2069 NoEncode<"$ea_result">; 2070 2071def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2072 "lwzu $rD, $addr", IIC_LdStLoadUpd, 2073 []>, RegConstraint<"$addr.reg = $ea_result">, 2074 NoEncode<"$ea_result">; 2075 2076let Predicates = [HasFPU] in { 2077def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2078 "lfsu $rD, $addr", IIC_LdStLFDU, 2079 []>, RegConstraint<"$addr.reg = $ea_result">, 2080 NoEncode<"$ea_result">; 2081 2082def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2083 "lfdu $rD, $addr", IIC_LdStLFDU, 2084 []>, RegConstraint<"$addr.reg = $ea_result">, 2085 NoEncode<"$ea_result">; 2086} 2087 2088 2089// Indexed (r+r) Loads with Update (preinc). 2090def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 2091 (ins memrr:$addr), 2092 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 2093 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2094 NoEncode<"$ea_result">; 2095 2096def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 2097 (ins memrr:$addr), 2098 "lhaux $rD, $addr", IIC_LdStLHAUX, 2099 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2100 NoEncode<"$ea_result">; 2101 2102def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 2103 (ins memrr:$addr), 2104 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 2105 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2106 NoEncode<"$ea_result">; 2107 2108def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 2109 (ins memrr:$addr), 2110 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 2111 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2112 NoEncode<"$ea_result">; 2113 2114let Predicates = [HasFPU] in { 2115def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), 2116 (ins memrr:$addr), 2117 "lfsux $rD, $addr", IIC_LdStLFDUX, 2118 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2119 NoEncode<"$ea_result">; 2120 2121def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), 2122 (ins memrr:$addr), 2123 "lfdux $rD, $addr", IIC_LdStLFDUX, 2124 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2125 NoEncode<"$ea_result">; 2126} 2127} 2128} 2129 2130// Indexed (r+r) Loads. 2131// 2132let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { 2133def LBZX : XForm_1_memOp<31, 87, (outs gprc:$rD), (ins memrr:$src), 2134 "lbzx $rD, $src", IIC_LdStLoad, 2135 [(set i32:$rD, (zextloadi8 xaddr:$src))]>; 2136def LHAX : XForm_1_memOp<31, 343, (outs gprc:$rD), (ins memrr:$src), 2137 "lhax $rD, $src", IIC_LdStLHA, 2138 [(set i32:$rD, (sextloadi16 xaddr:$src))]>, 2139 PPC970_DGroup_Cracked; 2140def LHZX : XForm_1_memOp<31, 279, (outs gprc:$rD), (ins memrr:$src), 2141 "lhzx $rD, $src", IIC_LdStLoad, 2142 [(set i32:$rD, (zextloadi16 xaddr:$src))]>; 2143def LWZX : XForm_1_memOp<31, 23, (outs gprc:$rD), (ins memrr:$src), 2144 "lwzx $rD, $src", IIC_LdStLoad, 2145 [(set i32:$rD, (load xaddr:$src))]>; 2146def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$rD), (ins memrr:$src), 2147 "lhbrx $rD, $src", IIC_LdStLoad, 2148 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>; 2149def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$rD), (ins memrr:$src), 2150 "lwbrx $rD, $src", IIC_LdStLoad, 2151 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>; 2152 2153let Predicates = [HasFPU] in { 2154def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$frD), (ins memrr:$src), 2155 "lfsx $frD, $src", IIC_LdStLFD, 2156 [(set f32:$frD, (load xaddr:$src))]>; 2157def LFDX : XForm_25_memOp<31, 599, (outs f8rc:$frD), (ins memrr:$src), 2158 "lfdx $frD, $src", IIC_LdStLFD, 2159 [(set f64:$frD, (load xaddr:$src))]>; 2160 2161def LFIWAX : XForm_25_memOp<31, 855, (outs f8rc:$frD), (ins memrr:$src), 2162 "lfiwax $frD, $src", IIC_LdStLFD, 2163 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>; 2164def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$frD), (ins memrr:$src), 2165 "lfiwzx $frD, $src", IIC_LdStLFD, 2166 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>; 2167} 2168} 2169 2170// Load Multiple 2171let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in 2172def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src), 2173 "lmw $rD, $src", IIC_LdStLMW, []>; 2174 2175//===----------------------------------------------------------------------===// 2176// PPC32 Store Instructions. 2177// 2178 2179// Unindexed (r+i) Stores. 2180let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2181def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$dst), 2182 "stb $rS, $dst", IIC_LdStStore, 2183 [(truncstorei8 i32:$rS, iaddr:$dst)]>; 2184def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$dst), 2185 "sth $rS, $dst", IIC_LdStStore, 2186 [(truncstorei16 i32:$rS, iaddr:$dst)]>; 2187def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$dst), 2188 "stw $rS, $dst", IIC_LdStStore, 2189 [(store i32:$rS, iaddr:$dst)]>; 2190let Predicates = [HasFPU] in { 2191def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst), 2192 "stfs $rS, $dst", IIC_LdStSTFD, 2193 [(store f32:$rS, iaddr:$dst)]>; 2194def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst), 2195 "stfd $rS, $dst", IIC_LdStSTFD, 2196 [(store f64:$rS, iaddr:$dst)]>; 2197} 2198} 2199 2200// Unindexed (r+i) Stores with Update (preinc). 2201let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2202def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 2203 "stbu $rS, $dst", IIC_LdStSTU, []>, 2204 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2205def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 2206 "sthu $rS, $dst", IIC_LdStSTU, []>, 2207 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2208def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 2209 "stwu $rS, $dst", IIC_LdStSTU, []>, 2210 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2211let Predicates = [HasFPU] in { 2212def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst), 2213 "stfsu $rS, $dst", IIC_LdStSTFDU, []>, 2214 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2215def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst), 2216 "stfdu $rS, $dst", IIC_LdStSTFDU, []>, 2217 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2218} 2219} 2220 2221// Patterns to match the pre-inc stores. We can't put the patterns on 2222// the instruction definitions directly as ISel wants the address base 2223// and offset to be separate operands, not a single complex operand. 2224def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2225 (STBU $rS, iaddroff:$ptroff, $ptrreg)>; 2226def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2227 (STHU $rS, iaddroff:$ptroff, $ptrreg)>; 2228def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2229 (STWU $rS, iaddroff:$ptroff, $ptrreg)>; 2230def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2231 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>; 2232def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2233 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>; 2234 2235// Indexed (r+r) Stores. 2236let PPC970_Unit = 2 in { 2237def STBX : XForm_8_memOp<31, 215, (outs), (ins gprc:$rS, memrr:$dst), 2238 "stbx $rS, $dst", IIC_LdStStore, 2239 [(truncstorei8 i32:$rS, xaddr:$dst)]>, 2240 PPC970_DGroup_Cracked; 2241def STHX : XForm_8_memOp<31, 407, (outs), (ins gprc:$rS, memrr:$dst), 2242 "sthx $rS, $dst", IIC_LdStStore, 2243 [(truncstorei16 i32:$rS, xaddr:$dst)]>, 2244 PPC970_DGroup_Cracked; 2245def STWX : XForm_8_memOp<31, 151, (outs), (ins gprc:$rS, memrr:$dst), 2246 "stwx $rS, $dst", IIC_LdStStore, 2247 [(store i32:$rS, xaddr:$dst)]>, 2248 PPC970_DGroup_Cracked; 2249 2250def STHBRX: XForm_8_memOp<31, 918, (outs), (ins gprc:$rS, memrr:$dst), 2251 "sthbrx $rS, $dst", IIC_LdStStore, 2252 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>, 2253 PPC970_DGroup_Cracked; 2254def STWBRX: XForm_8_memOp<31, 662, (outs), (ins gprc:$rS, memrr:$dst), 2255 "stwbrx $rS, $dst", IIC_LdStStore, 2256 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>, 2257 PPC970_DGroup_Cracked; 2258 2259let Predicates = [HasFPU] in { 2260def STFIWX: XForm_28_memOp<31, 983, (outs), (ins f8rc:$frS, memrr:$dst), 2261 "stfiwx $frS, $dst", IIC_LdStSTFD, 2262 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>; 2263 2264def STFSX : XForm_28_memOp<31, 663, (outs), (ins f4rc:$frS, memrr:$dst), 2265 "stfsx $frS, $dst", IIC_LdStSTFD, 2266 [(store f32:$frS, xaddr:$dst)]>; 2267def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$frS, memrr:$dst), 2268 "stfdx $frS, $dst", IIC_LdStSTFD, 2269 [(store f64:$frS, xaddr:$dst)]>; 2270} 2271} 2272 2273// Indexed (r+r) Stores with Update (preinc). 2274let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2275def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 2276 (ins gprc:$rS, memrr:$dst), 2277 "stbux $rS, $dst", IIC_LdStSTUX, []>, 2278 RegConstraint<"$dst.ptrreg = $ea_res">, 2279 NoEncode<"$ea_res">, 2280 PPC970_DGroup_Cracked; 2281def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 2282 (ins gprc:$rS, memrr:$dst), 2283 "sthux $rS, $dst", IIC_LdStSTUX, []>, 2284 RegConstraint<"$dst.ptrreg = $ea_res">, 2285 NoEncode<"$ea_res">, 2286 PPC970_DGroup_Cracked; 2287def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 2288 (ins gprc:$rS, memrr:$dst), 2289 "stwux $rS, $dst", IIC_LdStSTUX, []>, 2290 RegConstraint<"$dst.ptrreg = $ea_res">, 2291 NoEncode<"$ea_res">, 2292 PPC970_DGroup_Cracked; 2293let Predicates = [HasFPU] in { 2294def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res), 2295 (ins f4rc:$rS, memrr:$dst), 2296 "stfsux $rS, $dst", IIC_LdStSTFDU, []>, 2297 RegConstraint<"$dst.ptrreg = $ea_res">, 2298 NoEncode<"$ea_res">, 2299 PPC970_DGroup_Cracked; 2300def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res), 2301 (ins f8rc:$rS, memrr:$dst), 2302 "stfdux $rS, $dst", IIC_LdStSTFDU, []>, 2303 RegConstraint<"$dst.ptrreg = $ea_res">, 2304 NoEncode<"$ea_res">, 2305 PPC970_DGroup_Cracked; 2306} 2307} 2308 2309// Patterns to match the pre-inc stores. We can't put the patterns on 2310// the instruction definitions directly as ISel wants the address base 2311// and offset to be separate operands, not a single complex operand. 2312def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2313 (STBUX $rS, $ptrreg, $ptroff)>; 2314def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2315 (STHUX $rS, $ptrreg, $ptroff)>; 2316def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2317 (STWUX $rS, $ptrreg, $ptroff)>; 2318let Predicates = [HasFPU] in { 2319def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2320 (STFSUX $rS, $ptrreg, $ptroff)>; 2321def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2322 (STFDUX $rS, $ptrreg, $ptroff)>; 2323} 2324 2325// Store Multiple 2326let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 2327def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst), 2328 "stmw $rS, $dst", IIC_LdStLMW, []>; 2329 2330def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L), 2331 "sync $L", IIC_LdStSync, []>; 2332 2333let isCodeGenOnly = 1 in { 2334 def MSYNC : XForm_24_sync<31, 598, (outs), (ins), 2335 "msync", IIC_LdStSync, []> { 2336 let L = 0; 2337 } 2338} 2339 2340// We used to have EIEIO as value but E[0-9A-Z] is a reserved name 2341def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins), 2342 "eieio", IIC_LdStLoad, []>; 2343 2344def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2345def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2346def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2347def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2348def : Pat<(int_ppc_eieio), (EnforceIEIO)>; 2349 2350//===----------------------------------------------------------------------===// 2351// PPC32 Arithmetic Instructions. 2352// 2353 2354let PPC970_Unit = 1 in { // FXU Operations. 2355def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm), 2356 "addi $rD, $rA, $imm", IIC_IntSimple, 2357 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>; 2358let BaseName = "addic" in { 2359let Defs = [CARRY] in 2360def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2361 "addic $rD, $rA, $imm", IIC_IntGeneral, 2362 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>, 2363 RecFormRel, PPC970_DGroup_Cracked; 2364let Defs = [CARRY, CR0] in 2365def ADDIC_rec : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2366 "addic. $rD, $rA, $imm", IIC_IntGeneral, 2367 []>, isRecordForm, RecFormRel; 2368} 2369def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm), 2370 "addis $rD, $rA, $imm", IIC_IntSimple, 2371 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>; 2372let isCodeGenOnly = 1 in 2373def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym), 2374 "la $rD, $sym($rA)", IIC_IntGeneral, 2375 [(set i32:$rD, (add i32:$rA, 2376 (PPClo tglobaladdr:$sym, 0)))]>; 2377def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2378 "mulli $rD, $rA, $imm", IIC_IntMulLI, 2379 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>; 2380let Defs = [CARRY] in 2381def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2382 "subfic $rD, $rA, $imm", IIC_IntGeneral, 2383 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>; 2384 2385let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 2386 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm), 2387 "li $rD, $imm", IIC_IntSimple, 2388 [(set i32:$rD, imm32SExt16:$imm)]>; 2389 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm), 2390 "lis $rD, $imm", IIC_IntSimple, 2391 [(set i32:$rD, imm16ShiftedSExt:$imm)]>; 2392} 2393} 2394 2395let PPC970_Unit = 1 in { // FXU Operations. 2396let Defs = [CR0] in { 2397def ANDI_rec : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2398 "andi. $dst, $src1, $src2", IIC_IntGeneral, 2399 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>, 2400 isRecordForm; 2401def ANDIS_rec : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2402 "andis. $dst, $src1, $src2", IIC_IntGeneral, 2403 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>, 2404 isRecordForm; 2405} 2406def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2407 "ori $dst, $src1, $src2", IIC_IntSimple, 2408 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>; 2409def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2410 "oris $dst, $src1, $src2", IIC_IntSimple, 2411 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>; 2412def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2413 "xori $dst, $src1, $src2", IIC_IntSimple, 2414 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>; 2415def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2416 "xoris $dst, $src1, $src2", IIC_IntSimple, 2417 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>; 2418 2419def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple, 2420 []>; 2421let isCodeGenOnly = 1 in { 2422// The POWER6 and POWER7 have special group-terminating nops. 2423def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins), 2424 "ori 1, 1, 0", IIC_IntSimple, []>; 2425def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins), 2426 "ori 2, 2, 0", IIC_IntSimple, []>; 2427} 2428 2429let isCompare = 1, hasSideEffects = 0 in { 2430 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm), 2431 "cmpwi $crD, $rA, $imm", IIC_IntCompare>; 2432 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2), 2433 "cmplwi $dst, $src1, $src2", IIC_IntCompare>; 2434 def CMPRB : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF), 2435 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 2436 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 2437 Requires<[IsISA3_0]>; 2438} 2439} 2440 2441let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2442let isCommutable = 1 in { 2443defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2444 "nand", "$rA, $rS, $rB", IIC_IntSimple, 2445 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>; 2446defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2447 "and", "$rA, $rS, $rB", IIC_IntSimple, 2448 [(set i32:$rA, (and i32:$rS, i32:$rB))]>; 2449} // isCommutable 2450defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2451 "andc", "$rA, $rS, $rB", IIC_IntSimple, 2452 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>; 2453let isCommutable = 1 in { 2454defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2455 "or", "$rA, $rS, $rB", IIC_IntSimple, 2456 [(set i32:$rA, (or i32:$rS, i32:$rB))]>; 2457defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2458 "nor", "$rA, $rS, $rB", IIC_IntSimple, 2459 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>; 2460} // isCommutable 2461defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2462 "orc", "$rA, $rS, $rB", IIC_IntSimple, 2463 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>; 2464let isCommutable = 1 in { 2465defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2466 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 2467 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>; 2468defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2469 "xor", "$rA, $rS, $rB", IIC_IntSimple, 2470 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>; 2471} // isCommutable 2472defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2473 "slw", "$rA, $rS, $rB", IIC_IntGeneral, 2474 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>; 2475defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2476 "srw", "$rA, $rS, $rB", IIC_IntGeneral, 2477 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>; 2478defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2479 "sraw", "$rA, $rS, $rB", IIC_IntShift, 2480 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>; 2481} 2482 2483let PPC970_Unit = 1 in { // FXU Operations. 2484let hasSideEffects = 0 in { 2485defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH), 2486 "srawi", "$rA, $rS, $SH", IIC_IntShift, 2487 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>; 2488defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS), 2489 "cntlzw", "$rA, $rS", IIC_IntGeneral, 2490 [(set i32:$rA, (ctlz i32:$rS))]>; 2491defm CNTTZW : XForm_11r<31, 538, (outs gprc:$rA), (ins gprc:$rS), 2492 "cnttzw", "$rA, $rS", IIC_IntGeneral, 2493 [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>; 2494defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS), 2495 "extsb", "$rA, $rS", IIC_IntSimple, 2496 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>; 2497defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS), 2498 "extsh", "$rA, $rS", IIC_IntSimple, 2499 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>; 2500 2501let isCommutable = 1 in 2502def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2503 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 2504 [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>; 2505} 2506let isCompare = 1, hasSideEffects = 0 in { 2507 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 2508 "cmpw $crD, $rA, $rB", IIC_IntCompare>; 2509 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 2510 "cmplw $crD, $rA, $rB", IIC_IntCompare>; 2511} 2512} 2513let PPC970_Unit = 3, Predicates = [HasFPU] in { // FPU Operations. 2514//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), 2515// "fcmpo $crD, $fA, $fB", IIC_FPCompare>; 2516let isCompare = 1, hasSideEffects = 0 in { 2517 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), 2518 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 2519 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2520 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 2521 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 2522} 2523 2524def FTDIV: XForm_17<63, 128, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 2525 "ftdiv $crD, $fA, $fB", IIC_FPCompare>; 2526def FTSQRT: XForm_17a<63, 160, (outs crrc:$crD), (ins f8rc:$fB), 2527 "ftsqrt $crD, $fB", IIC_FPCompare>; 2528 2529let Uses = [RM] in { 2530 let hasSideEffects = 0 in { 2531 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB), 2532 "fctiw", "$frD, $frB", IIC_FPGeneral, 2533 []>; 2534 defm FCTIWU : XForm_26r<63, 142, (outs f8rc:$frD), (ins f8rc:$frB), 2535 "fctiwu", "$frD, $frB", IIC_FPGeneral, 2536 []>; 2537 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB), 2538 "fctiwz", "$frD, $frB", IIC_FPGeneral, 2539 [(set f64:$frD, (PPCfctiwz f64:$frB))]>; 2540 2541 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB), 2542 "frsp", "$frD, $frB", IIC_FPGeneral, 2543 [(set f32:$frD, (fpround f64:$frB))]>; 2544 2545 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2546 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB), 2547 "frin", "$frD, $frB", IIC_FPGeneral, 2548 [(set f64:$frD, (fround f64:$frB))]>; 2549 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB), 2550 "frin", "$frD, $frB", IIC_FPGeneral, 2551 [(set f32:$frD, (fround f32:$frB))]>; 2552 } 2553 2554 let hasSideEffects = 0 in { 2555 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2556 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB), 2557 "frip", "$frD, $frB", IIC_FPGeneral, 2558 [(set f64:$frD, (fceil f64:$frB))]>; 2559 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB), 2560 "frip", "$frD, $frB", IIC_FPGeneral, 2561 [(set f32:$frD, (fceil f32:$frB))]>; 2562 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2563 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB), 2564 "friz", "$frD, $frB", IIC_FPGeneral, 2565 [(set f64:$frD, (ftrunc f64:$frB))]>; 2566 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB), 2567 "friz", "$frD, $frB", IIC_FPGeneral, 2568 [(set f32:$frD, (ftrunc f32:$frB))]>; 2569 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2570 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB), 2571 "frim", "$frD, $frB", IIC_FPGeneral, 2572 [(set f64:$frD, (ffloor f64:$frB))]>; 2573 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB), 2574 "frim", "$frD, $frB", IIC_FPGeneral, 2575 [(set f32:$frD, (ffloor f32:$frB))]>; 2576 2577 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB), 2578 "fsqrt", "$frD, $frB", IIC_FPSqrtD, 2579 [(set f64:$frD, (fsqrt f64:$frB))]>; 2580 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB), 2581 "fsqrts", "$frD, $frB", IIC_FPSqrtS, 2582 [(set f32:$frD, (fsqrt f32:$frB))]>; 2583 } 2584 } 2585} 2586 2587/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 2588/// often coalesced away and we don't want the dispatch group builder to think 2589/// that they will fill slots (which could cause the load of a LSU reject to 2590/// sneak into a d-group with a store). 2591let hasSideEffects = 0, Predicates = [HasFPU] in 2592defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB), 2593 "fmr", "$frD, $frB", IIC_FPGeneral, 2594 []>, // (set f32:$frD, f32:$frB) 2595 PPC970_Unit_Pseudo; 2596 2597let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 2598// These are artificially split into two different forms, for 4/8 byte FP. 2599defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB), 2600 "fabs", "$frD, $frB", IIC_FPGeneral, 2601 [(set f32:$frD, (fabs f32:$frB))]>; 2602let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2603defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB), 2604 "fabs", "$frD, $frB", IIC_FPGeneral, 2605 [(set f64:$frD, (fabs f64:$frB))]>; 2606defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB), 2607 "fnabs", "$frD, $frB", IIC_FPGeneral, 2608 [(set f32:$frD, (fneg (fabs f32:$frB)))]>; 2609let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2610defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB), 2611 "fnabs", "$frD, $frB", IIC_FPGeneral, 2612 [(set f64:$frD, (fneg (fabs f64:$frB)))]>; 2613defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB), 2614 "fneg", "$frD, $frB", IIC_FPGeneral, 2615 [(set f32:$frD, (fneg f32:$frB))]>; 2616let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2617defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB), 2618 "fneg", "$frD, $frB", IIC_FPGeneral, 2619 [(set f64:$frD, (fneg f64:$frB))]>; 2620 2621defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB), 2622 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 2623 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>; 2624let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2625defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB), 2626 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 2627 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>; 2628 2629// Reciprocal estimates. 2630defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB), 2631 "fre", "$frD, $frB", IIC_FPGeneral, 2632 [(set f64:$frD, (PPCfre f64:$frB))]>; 2633defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB), 2634 "fres", "$frD, $frB", IIC_FPGeneral, 2635 [(set f32:$frD, (PPCfre f32:$frB))]>; 2636defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB), 2637 "frsqrte", "$frD, $frB", IIC_FPGeneral, 2638 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>; 2639defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB), 2640 "frsqrtes", "$frD, $frB", IIC_FPGeneral, 2641 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>; 2642} 2643 2644// XL-Form instructions. condition register logical ops. 2645// 2646let hasSideEffects = 0 in 2647def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA), 2648 "mcrf $BF, $BFA", IIC_BrMCR>, 2649 PPC970_DGroup_First, PPC970_Unit_CRU; 2650 2651// FIXME: According to the ISA (section 2.5.1 of version 2.06), the 2652// condition-register logical instructions have preferred forms. Specifically, 2653// it is preferred that the bit specified by the BT field be in the same 2654// condition register as that specified by the bit BB. We might want to account 2655// for this via hinting the register allocator and anti-dep breakers, or we 2656// could constrain the register class to force this constraint and then loosen 2657// it during register allocation via convertToThreeAddress or some similar 2658// mechanism. 2659 2660let isCommutable = 1 in { 2661def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD), 2662 (ins crbitrc:$CRA, crbitrc:$CRB), 2663 "crand $CRD, $CRA, $CRB", IIC_BrCR, 2664 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>; 2665 2666def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD), 2667 (ins crbitrc:$CRA, crbitrc:$CRB), 2668 "crnand $CRD, $CRA, $CRB", IIC_BrCR, 2669 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>; 2670 2671def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD), 2672 (ins crbitrc:$CRA, crbitrc:$CRB), 2673 "cror $CRD, $CRA, $CRB", IIC_BrCR, 2674 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>; 2675 2676def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD), 2677 (ins crbitrc:$CRA, crbitrc:$CRB), 2678 "crxor $CRD, $CRA, $CRB", IIC_BrCR, 2679 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>; 2680 2681def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD), 2682 (ins crbitrc:$CRA, crbitrc:$CRB), 2683 "crnor $CRD, $CRA, $CRB", IIC_BrCR, 2684 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>; 2685 2686def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD), 2687 (ins crbitrc:$CRA, crbitrc:$CRB), 2688 "creqv $CRD, $CRA, $CRB", IIC_BrCR, 2689 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>; 2690} // isCommutable 2691 2692def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD), 2693 (ins crbitrc:$CRA, crbitrc:$CRB), 2694 "crandc $CRD, $CRA, $CRB", IIC_BrCR, 2695 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>; 2696 2697def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD), 2698 (ins crbitrc:$CRA, crbitrc:$CRB), 2699 "crorc $CRD, $CRA, $CRB", IIC_BrCR, 2700 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>; 2701 2702let isCodeGenOnly = 1 in { 2703let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 2704def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins), 2705 "creqv $dst, $dst, $dst", IIC_BrCR, 2706 [(set i1:$dst, 1)]>; 2707 2708def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins), 2709 "crxor $dst, $dst, $dst", IIC_BrCR, 2710 [(set i1:$dst, 0)]>; 2711} 2712 2713let Defs = [CR1EQ], CRD = 6 in { 2714def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 2715 "creqv 6, 6, 6", IIC_BrCR, 2716 [(PPCcr6set)]>; 2717 2718def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 2719 "crxor 6, 6, 6", IIC_BrCR, 2720 [(PPCcr6unset)]>; 2721} 2722} 2723 2724// XFX-Form instructions. Instructions that deal with SPRs. 2725// 2726 2727def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR), 2728 "mfspr $RT, $SPR", IIC_SprMFSPR>; 2729def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT), 2730 "mtspr $SPR, $RT", IIC_SprMTSPR>; 2731 2732def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR), 2733 "mftb $RT, $SPR", IIC_SprMFTB>; 2734 2735def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR), 2736 "mfpmr $RT, $SPR", IIC_SprMFPMR>; 2737 2738def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT), 2739 "mtpmr $SPR, $RT", IIC_SprMTPMR>; 2740 2741 2742// A pseudo-instruction used to implement the read of the 64-bit cycle counter 2743// on a 32-bit target. 2744let hasSideEffects = 1 in 2745def ReadTB : PPCCustomInserterPseudo<(outs gprc:$lo, gprc:$hi), (ins), 2746 "#ReadTB", []>; 2747 2748let Uses = [CTR] in { 2749def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins), 2750 "mfctr $rT", IIC_SprMFSPR>, 2751 PPC970_DGroup_First, PPC970_Unit_FXU; 2752} 2753let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in { 2754def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 2755 "mtctr $rS", IIC_SprMTSPR>, 2756 PPC970_DGroup_First, PPC970_Unit_FXU; 2757} 2758let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in { 2759let Pattern = [(int_set_loop_iterations i32:$rS)] in 2760def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 2761 "mtctr $rS", IIC_SprMTSPR>, 2762 PPC970_DGroup_First, PPC970_Unit_FXU; 2763} 2764 2765let hasSideEffects = 0 in { 2766let Defs = [LR] in { 2767def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS), 2768 "mtlr $rS", IIC_SprMTSPR>, 2769 PPC970_DGroup_First, PPC970_Unit_FXU; 2770} 2771let Uses = [LR] in { 2772def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins), 2773 "mflr $rT", IIC_SprMFSPR>, 2774 PPC970_DGroup_First, PPC970_Unit_FXU; 2775} 2776} 2777 2778let isCodeGenOnly = 1 in { 2779 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed 2780 // like a GPR on the PPC970. As such, copies in and out have the same 2781 // performance characteristics as an OR instruction. 2782 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS), 2783 "mtspr 256, $rS", IIC_IntGeneral>, 2784 PPC970_DGroup_Single, PPC970_Unit_FXU; 2785 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins), 2786 "mfspr $rT, 256", IIC_IntGeneral>, 2787 PPC970_DGroup_First, PPC970_Unit_FXU; 2788 2789 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256, 2790 (outs VRSAVERC:$reg), (ins gprc:$rS), 2791 "mtspr 256, $rS", IIC_IntGeneral>, 2792 PPC970_DGroup_Single, PPC970_Unit_FXU; 2793 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), 2794 (ins VRSAVERC:$reg), 2795 "mfspr $rT, 256", IIC_IntGeneral>, 2796 PPC970_DGroup_First, PPC970_Unit_FXU; 2797} 2798 2799// Aliases for mtvrsave/mfvrsave to mfspr/mtspr. 2800def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>; 2801def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>; 2802 2803// SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register, 2804// so we'll need to scavenge a register for it. 2805let mayStore = 1 in 2806def SPILL_VRSAVE : PPCEmitTimePseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F), 2807 "#SPILL_VRSAVE", []>; 2808 2809// RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously 2810// spilled), so we'll need to scavenge a register for it. 2811let mayLoad = 1 in 2812def RESTORE_VRSAVE : PPCEmitTimePseudo<(outs VRSAVERC:$vrsave), (ins memri:$F), 2813 "#RESTORE_VRSAVE", []>; 2814 2815let hasSideEffects = 0 in { 2816// mtocrf's input needs to be prepared by shifting by an amount dependent 2817// on the cr register selected. Thus, post-ra anti-dep breaking must not 2818// later change that register assignment. 2819let hasExtraDefRegAllocReq = 1 in { 2820def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST), 2821 "mtocrf $FXM, $ST", IIC_BrMCRX>, 2822 PPC970_DGroup_First, PPC970_Unit_CRU; 2823 2824// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 2825// is dependent on the cr fields being set. 2826def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS), 2827 "mtcrf $FXM, $rS", IIC_BrMCRX>, 2828 PPC970_MicroCode, PPC970_Unit_CRU; 2829} // hasExtraDefRegAllocReq = 1 2830 2831// mfocrf's input needs to be prepared by shifting by an amount dependent 2832// on the cr register selected. Thus, post-ra anti-dep breaking must not 2833// later change that register assignment. 2834let hasExtraSrcRegAllocReq = 1 in { 2835def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM), 2836 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 2837 PPC970_DGroup_First, PPC970_Unit_CRU; 2838 2839// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 2840// is dependent on the cr fields being copied. 2841def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins), 2842 "mfcr $rT", IIC_SprMFCR>, 2843 PPC970_MicroCode, PPC970_Unit_CRU; 2844} // hasExtraSrcRegAllocReq = 1 2845 2846def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins), 2847 "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>; 2848} // hasSideEffects = 0 2849 2850let Predicates = [HasFPU] in { 2851// Custom inserter instruction to perform FADD in round-to-zero mode. 2852let Uses = [RM] in { 2853 def FADDrtz: PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "", 2854 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>; 2855} 2856 2857// The above pseudo gets expanded to make use of the following instructions 2858// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. 2859let Uses = [RM], Defs = [RM] in { 2860 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 2861 "mtfsb0 $FM", IIC_IntMTFSB0, []>, 2862 PPC970_DGroup_Single, PPC970_Unit_FPU; 2863 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 2864 "mtfsb1 $FM", IIC_IntMTFSB0, []>, 2865 PPC970_DGroup_Single, PPC970_Unit_FPU; 2866 let isCodeGenOnly = 1 in 2867 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT), 2868 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>, 2869 PPC970_DGroup_Single, PPC970_Unit_FPU; 2870} 2871let Uses = [RM] in { 2872 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins), 2873 "mffs $rT", IIC_IntMFFS, 2874 [(set f64:$rT, (PPCmffs))]>, 2875 PPC970_DGroup_Single, PPC970_Unit_FPU; 2876 2877 let Defs = [CR1] in 2878 def MFFS_rec : XForm_42<63, 583, (outs f8rc:$rT), (ins), 2879 "mffs. $rT", IIC_IntMFFS, []>, isRecordForm; 2880 2881 def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$rT), (ins), 2882 "mffsce $rT", IIC_IntMFFS, []>, 2883 PPC970_DGroup_Single, PPC970_Unit_FPU; 2884 2885 def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$rT), 2886 (ins f8rc:$FRB), "mffscdrn $rT, $FRB", 2887 IIC_IntMFFS, []>, 2888 PPC970_DGroup_Single, PPC970_Unit_FPU; 2889 2890 def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$rT), 2891 (ins u3imm:$DRM), 2892 "mffscdrni $rT, $DRM", 2893 IIC_IntMFFS, []>, 2894 PPC970_DGroup_Single, PPC970_Unit_FPU; 2895 2896 def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$rT), 2897 (ins f8rc:$FRB), "mffscrn $rT, $FRB", 2898 IIC_IntMFFS, []>, 2899 PPC970_DGroup_Single, PPC970_Unit_FPU; 2900 2901 def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$rT), 2902 (ins u2imm:$RM), "mffscrni $rT, $RM", 2903 IIC_IntMFFS, []>, 2904 PPC970_DGroup_Single, PPC970_Unit_FPU; 2905 2906 def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$rT), (ins), 2907 "mffsl $rT", IIC_IntMFFS, []>, 2908 PPC970_DGroup_Single, PPC970_Unit_FPU; 2909} 2910} 2911 2912let Predicates = [IsISA3_0] in { 2913def MODSW : XForm_8<31, 779, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2914 "modsw $rT, $rA, $rB", IIC_IntDivW, 2915 [(set i32:$rT, (srem i32:$rA, i32:$rB))]>; 2916def MODUW : XForm_8<31, 267, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2917 "moduw $rT, $rA, $rB", IIC_IntDivW, 2918 [(set i32:$rT, (urem i32:$rA, i32:$rB))]>; 2919} 2920 2921let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2922// XO-Form instructions. Arithmetic instructions that can set overflow bit 2923let isCommutable = 1 in 2924defm ADD4 : XOForm_1rx<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2925 "add", "$rT, $rA, $rB", IIC_IntSimple, 2926 [(set i32:$rT, (add i32:$rA, i32:$rB))]>; 2927let isCodeGenOnly = 1 in 2928def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB), 2929 "add $rT, $rA, $rB", IIC_IntSimple, 2930 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>; 2931let isCommutable = 1 in 2932defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2933 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 2934 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>, 2935 PPC970_DGroup_Cracked; 2936 2937defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2938 "divw", "$rT, $rA, $rB", IIC_IntDivW, 2939 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>; 2940defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2941 "divwu", "$rT, $rA, $rB", IIC_IntDivW, 2942 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>; 2943defm DIVWE : XOForm_1rcr<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2944 "divwe", "$rT, $rA, $rB", IIC_IntDivW, 2945 [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>, 2946 Requires<[HasExtDiv]>; 2947defm DIVWEU : XOForm_1rcr<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2948 "divweu", "$rT, $rA, $rB", IIC_IntDivW, 2949 [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>, 2950 Requires<[HasExtDiv]>; 2951let isCommutable = 1 in { 2952defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2953 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW, 2954 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>; 2955defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2956 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU, 2957 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>; 2958defm MULLW : XOForm_1rx<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2959 "mullw", "$rT, $rA, $rB", IIC_IntMulHW, 2960 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>; 2961} // isCommutable 2962defm SUBF : XOForm_1rx<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2963 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 2964 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>; 2965defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2966 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 2967 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>, 2968 PPC970_DGroup_Cracked; 2969defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA), 2970 "neg", "$rT, $rA", IIC_IntSimple, 2971 [(set i32:$rT, (ineg i32:$rA))]>; 2972let Uses = [CARRY] in { 2973let isCommutable = 1 in 2974defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2975 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 2976 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>; 2977defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA), 2978 "addme", "$rT, $rA", IIC_IntGeneral, 2979 [(set i32:$rT, (adde i32:$rA, -1))]>; 2980defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA), 2981 "addze", "$rT, $rA", IIC_IntGeneral, 2982 [(set i32:$rT, (adde i32:$rA, 0))]>; 2983defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2984 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 2985 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>; 2986defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA), 2987 "subfme", "$rT, $rA", IIC_IntGeneral, 2988 [(set i32:$rT, (sube -1, i32:$rA))]>; 2989defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA), 2990 "subfze", "$rT, $rA", IIC_IntGeneral, 2991 [(set i32:$rT, (sube 0, i32:$rA))]>; 2992} 2993} 2994 2995// A-Form instructions. Most of the instructions executed in the FPU are of 2996// this type. 2997// 2998let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 2999let Uses = [RM] in { 3000let isCommutable = 1 in { 3001 defm FMADD : AForm_1r<63, 29, 3002 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3003 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3004 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>; 3005 defm FMADDS : AForm_1r<59, 29, 3006 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3007 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3008 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>; 3009 defm FMSUB : AForm_1r<63, 28, 3010 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3011 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3012 [(set f64:$FRT, 3013 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>; 3014 defm FMSUBS : AForm_1r<59, 28, 3015 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3016 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3017 [(set f32:$FRT, 3018 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>; 3019 defm FNMADD : AForm_1r<63, 31, 3020 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3021 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3022 [(set f64:$FRT, 3023 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>; 3024 defm FNMADDS : AForm_1r<59, 31, 3025 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3026 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3027 [(set f32:$FRT, 3028 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>; 3029 defm FNMSUB : AForm_1r<63, 30, 3030 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3031 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3032 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC, 3033 (fneg f64:$FRB))))]>; 3034 defm FNMSUBS : AForm_1r<59, 30, 3035 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3036 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3037 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC, 3038 (fneg f32:$FRB))))]>; 3039} // isCommutable 3040} 3041// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 3042// having 4 of these, force the comparison to always be an 8-byte double (code 3043// should use an FMRSD if the input comparison value really wants to be a float) 3044// and 4/8 byte forms for the result and operand type.. 3045let Interpretation64Bit = 1, isCodeGenOnly = 1 in 3046defm FSELD : AForm_1r<63, 23, 3047 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3048 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3049 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>; 3050defm FSELS : AForm_1r<63, 23, 3051 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3052 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3053 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>; 3054let Uses = [RM], mayRaiseFPException = 1 in { 3055 let isCommutable = 1 in { 3056 defm FADD : AForm_2r<63, 21, 3057 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3058 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub, 3059 [(set f64:$FRT, (any_fadd f64:$FRA, f64:$FRB))]>; 3060 defm FADDS : AForm_2r<59, 21, 3061 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3062 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral, 3063 [(set f32:$FRT, (any_fadd f32:$FRA, f32:$FRB))]>; 3064 } // isCommutable 3065 defm FDIV : AForm_2r<63, 18, 3066 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3067 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD, 3068 [(set f64:$FRT, (any_fdiv f64:$FRA, f64:$FRB))]>; 3069 defm FDIVS : AForm_2r<59, 18, 3070 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3071 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS, 3072 [(set f32:$FRT, (any_fdiv f32:$FRA, f32:$FRB))]>; 3073 let isCommutable = 1 in { 3074 defm FMUL : AForm_3r<63, 25, 3075 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC), 3076 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused, 3077 [(set f64:$FRT, (any_fmul f64:$FRA, f64:$FRC))]>; 3078 defm FMULS : AForm_3r<59, 25, 3079 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC), 3080 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral, 3081 [(set f32:$FRT, (any_fmul f32:$FRA, f32:$FRC))]>; 3082 } // isCommutable 3083 defm FSUB : AForm_2r<63, 20, 3084 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3085 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub, 3086 [(set f64:$FRT, (any_fsub f64:$FRA, f64:$FRB))]>; 3087 defm FSUBS : AForm_2r<59, 20, 3088 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3089 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral, 3090 [(set f32:$FRT, (any_fsub f32:$FRA, f32:$FRB))]>; 3091 } 3092} 3093 3094let hasSideEffects = 0 in { 3095let PPC970_Unit = 1 in { // FXU Operations. 3096 let isSelect = 1 in 3097 def ISEL : AForm_4<31, 15, 3098 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond), 3099 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 3100 []>; 3101} 3102 3103let PPC970_Unit = 1 in { // FXU Operations. 3104// M-Form instructions. rotate and mask instructions. 3105// 3106let isCommutable = 1 in { 3107// RLWIMI can be commuted if the rotate amount is zero. 3108defm RLWIMI : MForm_2r<20, (outs gprc:$rA), 3109 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB, 3110 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 3111 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 3112 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 3113} 3114let BaseName = "rlwinm" in { 3115def RLWINM : MForm_2<21, 3116 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 3117 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 3118 []>, RecFormRel; 3119let Defs = [CR0] in 3120def RLWINM_rec : MForm_2<21, 3121 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 3122 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 3123 []>, isRecordForm, RecFormRel, PPC970_DGroup_Cracked; 3124} 3125defm RLWNM : MForm_2r<23, (outs gprc:$rA), 3126 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME), 3127 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 3128 []>; 3129} 3130} // hasSideEffects = 0 3131 3132//===----------------------------------------------------------------------===// 3133// PowerPC Instruction Patterns 3134// 3135 3136// Arbitrary immediate support. Implement in terms of LIS/ORI. 3137def : Pat<(i32 imm:$imm), 3138 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 3139 3140// Implement the 'not' operation with the NOR instruction. 3141def i32not : OutPatFrag<(ops node:$in), 3142 (NOR $in, $in)>; 3143def : Pat<(not i32:$in), 3144 (i32not $in)>; 3145 3146// ADD an arbitrary immediate. 3147def : Pat<(add i32:$in, imm:$imm), 3148 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 3149// OR an arbitrary immediate. 3150def : Pat<(or i32:$in, imm:$imm), 3151 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 3152// XOR an arbitrary immediate. 3153def : Pat<(xor i32:$in, imm:$imm), 3154 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 3155// SUBFIC 3156def : Pat<(sub imm32SExt16:$imm, i32:$in), 3157 (SUBFIC $in, imm:$imm)>; 3158 3159// SHL/SRL 3160def : Pat<(shl i32:$in, (i32 imm:$imm)), 3161 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>; 3162def : Pat<(srl i32:$in, (i32 imm:$imm)), 3163 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>; 3164 3165// ROTL 3166def : Pat<(rotl i32:$in, i32:$sh), 3167 (RLWNM $in, $sh, 0, 31)>; 3168def : Pat<(rotl i32:$in, (i32 imm:$imm)), 3169 (RLWINM $in, imm:$imm, 0, 31)>; 3170 3171// RLWNM 3172def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm), 3173 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 3174 3175// Calls 3176def : Pat<(PPCcall (i32 tglobaladdr:$dst)), 3177 (BL tglobaladdr:$dst)>; 3178 3179def : Pat<(PPCcall (i32 texternalsym:$dst)), 3180 (BL texternalsym:$dst)>; 3181 3182// Calls for AIX only 3183def : Pat<(PPCcall (i32 mcsym:$dst)), 3184 (BL mcsym:$dst)>; 3185def : Pat<(PPCcall_nop (i32 mcsym:$dst)), 3186 (BL_NOP mcsym:$dst)>; 3187 3188def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 3189 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 3190 3191def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 3192 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 3193 3194def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 3195 (TCRETURNri CTRRC:$dst, imm:$imm)>; 3196 3197 3198 3199// Hi and Lo for Darwin Global Addresses. 3200def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 3201def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 3202def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 3203def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 3204def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 3205def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 3206def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 3207def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 3208def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in), 3209 (ADDIS $in, tglobaltlsaddr:$g)>; 3210def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in), 3211 (ADDI $in, tglobaltlsaddr:$g)>; 3212def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)), 3213 (ADDIS $in, tglobaladdr:$g)>; 3214def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)), 3215 (ADDIS $in, tconstpool:$g)>; 3216def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)), 3217 (ADDIS $in, tjumptable:$g)>; 3218def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)), 3219 (ADDIS $in, tblockaddress:$g)>; 3220 3221// Support for thread-local storage. 3222def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT", 3223 [(set i32:$rD, (PPCppc32GOT))]>; 3224 3225// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode. 3226// This uses two output registers, the first as the real output, the second as a 3227// temporary register, used internally in code generation. 3228def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT", 3229 []>, NoEncode<"$rT">; 3230 3231def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc_nor0:$rD), (ins s16imm:$disp, gprc_nor0:$reg), 3232 "#LDgotTprelL32", 3233 [(set i32:$rD, 3234 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>; 3235def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g), 3236 (ADD4TLS $in, tglobaltlsaddr:$g)>; 3237 3238def ADDItlsgdL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3239 "#ADDItlsgdL32", 3240 [(set i32:$rD, 3241 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>; 3242// LR is a true define, while the rest of the Defs are clobbers. R3 is 3243// explicitly defined when this op is created, so not mentioned here. 3244let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3245 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3246def GETtlsADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3247 "GETtlsADDR32", 3248 [(set i32:$rD, 3249 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>; 3250// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR 3251// are true defines while the rest of the Defs are clobbers. 3252let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3253 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3254def ADDItlsgdLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3255 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3256 "#ADDItlsgdLADDR32", 3257 [(set i32:$rD, 3258 (PPCaddiTlsgdLAddr i32:$reg, 3259 tglobaltlsaddr:$disp, 3260 tglobaltlsaddr:$sym))]>; 3261def ADDItlsldL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3262 "#ADDItlsldL32", 3263 [(set i32:$rD, 3264 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>; 3265// LR is a true define, while the rest of the Defs are clobbers. R3 is 3266// explicitly defined when this op is created, so not mentioned here. 3267let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3268 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3269def GETtlsldADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3270 "GETtlsldADDR32", 3271 [(set i32:$rD, 3272 (PPCgetTlsldAddr i32:$reg, 3273 tglobaltlsaddr:$sym))]>; 3274// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR 3275// are true defines while the rest of the Defs are clobbers. 3276let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3277 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3278def ADDItlsldLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3279 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3280 "#ADDItlsldLADDR32", 3281 [(set i32:$rD, 3282 (PPCaddiTlsldLAddr i32:$reg, 3283 tglobaltlsaddr:$disp, 3284 tglobaltlsaddr:$sym))]>; 3285def ADDIdtprelL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3286 "#ADDIdtprelL32", 3287 [(set i32:$rD, 3288 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>; 3289def ADDISdtprelHA32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3290 "#ADDISdtprelHA32", 3291 [(set i32:$rD, 3292 (PPCaddisDtprelHA i32:$reg, 3293 tglobaltlsaddr:$disp))]>; 3294 3295// Support for Position-independent code 3296def LWZtoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), 3297 "#LWZtoc", 3298 [(set i32:$rD, 3299 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3300def LWZtocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc_nor0:$reg), 3301 "#LWZtocL", 3302 [(set i32:$rD, 3303 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3304def ADDIStocHA : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp), 3305 "#ADDIStocHA", 3306 [(set i32:$rD, 3307 (PPCtoc_entry i32:$reg, tglobaladdr:$disp))]>; 3308 3309// Get Global (GOT) Base Register offset, from the word immediately preceding 3310// the function label. 3311def UpdateGBR : PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>; 3312 3313// Pseudo-instruction marked for deletion. When deleting the instruction would 3314// cause iterator invalidation in MIR transformation passes, this pseudo can be 3315// used instead. It will be removed unconditionally at pre-emit time (prior to 3316// branch selection). 3317def UNENCODED_NOP: PPCEmitTimePseudo<(outs), (ins), "#UNENCODED_NOP", []>; 3318 3319// Standard shifts. These are represented separately from the real shifts above 3320// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 3321// amounts. 3322def : Pat<(sra i32:$rS, i32:$rB), 3323 (SRAW $rS, $rB)>; 3324def : Pat<(srl i32:$rS, i32:$rB), 3325 (SRW $rS, $rB)>; 3326def : Pat<(shl i32:$rS, i32:$rB), 3327 (SLW $rS, $rB)>; 3328 3329def : Pat<(i32 (zextloadi1 iaddr:$src)), 3330 (LBZ iaddr:$src)>; 3331def : Pat<(i32 (zextloadi1 xaddr:$src)), 3332 (LBZX xaddr:$src)>; 3333def : Pat<(i32 (extloadi1 iaddr:$src)), 3334 (LBZ iaddr:$src)>; 3335def : Pat<(i32 (extloadi1 xaddr:$src)), 3336 (LBZX xaddr:$src)>; 3337def : Pat<(i32 (extloadi8 iaddr:$src)), 3338 (LBZ iaddr:$src)>; 3339def : Pat<(i32 (extloadi8 xaddr:$src)), 3340 (LBZX xaddr:$src)>; 3341def : Pat<(i32 (extloadi16 iaddr:$src)), 3342 (LHZ iaddr:$src)>; 3343def : Pat<(i32 (extloadi16 xaddr:$src)), 3344 (LHZX xaddr:$src)>; 3345let Predicates = [HasFPU] in { 3346def : Pat<(f64 (extloadf32 iaddr:$src)), 3347 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>; 3348def : Pat<(f64 (extloadf32 xaddr:$src)), 3349 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>; 3350 3351def : Pat<(f64 (fpextend f32:$src)), 3352 (COPY_TO_REGCLASS $src, F8RC)>; 3353} 3354 3355// Only seq_cst fences require the heavyweight sync (SYNC 0). 3356// All others can use the lightweight sync (SYNC 1). 3357// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html 3358// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits 3359// versions of Power. 3360def : Pat<(atomic_fence (i64 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3361def : Pat<(atomic_fence (i32 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3362def : Pat<(atomic_fence (timm), (timm)), (SYNC 1)>, Requires<[HasSYNC]>; 3363def : Pat<(atomic_fence (timm), (timm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 3364 3365let Predicates = [HasFPU] in { 3366// Additional FNMSUB patterns: -a*c + b == -(a*c - b) 3367def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B), 3368 (FNMSUB $A, $C, $B)>; 3369def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B), 3370 (FNMSUB $A, $C, $B)>; 3371def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B), 3372 (FNMSUBS $A, $C, $B)>; 3373def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B), 3374 (FNMSUBS $A, $C, $B)>; 3375 3376// FCOPYSIGN's operand types need not agree. 3377def : Pat<(fcopysign f64:$frB, f32:$frA), 3378 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>; 3379def : Pat<(fcopysign f32:$frB, f64:$frA), 3380 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>; 3381} 3382 3383include "PPCInstrAltivec.td" 3384include "PPCInstrSPE.td" 3385include "PPCInstr64Bit.td" 3386include "PPCInstrVSX.td" 3387include "PPCInstrQPX.td" 3388include "PPCInstrHTM.td" 3389 3390def crnot : OutPatFrag<(ops node:$in), 3391 (CRNOR $in, $in)>; 3392def : Pat<(not i1:$in), 3393 (crnot $in)>; 3394 3395// Prefixed instructions may require access to the above defs at a later 3396// time so we include this after the def. 3397include "PPCInstrPrefix.td" 3398 3399// Patterns for arithmetic i1 operations. 3400def : Pat<(add i1:$a, i1:$b), 3401 (CRXOR $a, $b)>; 3402def : Pat<(sub i1:$a, i1:$b), 3403 (CRXOR $a, $b)>; 3404def : Pat<(mul i1:$a, i1:$b), 3405 (CRAND $a, $b)>; 3406 3407// We're sometimes asked to materialize i1 -1, which is just 1 in this case 3408// (-1 is used to mean all bits set). 3409def : Pat<(i1 -1), (CRSET)>; 3410 3411// i1 extensions, implemented in terms of isel. 3412def : Pat<(i32 (zext i1:$in)), 3413 (SELECT_I4 $in, (LI 1), (LI 0))>; 3414def : Pat<(i32 (sext i1:$in)), 3415 (SELECT_I4 $in, (LI -1), (LI 0))>; 3416 3417def : Pat<(i64 (zext i1:$in)), 3418 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3419def : Pat<(i64 (sext i1:$in)), 3420 (SELECT_I8 $in, (LI8 -1), (LI8 0))>; 3421 3422// FIXME: We should choose either a zext or a sext based on other constants 3423// already around. 3424def : Pat<(i32 (anyext i1:$in)), 3425 (SELECT_I4 $in, (LI 1), (LI 0))>; 3426def : Pat<(i64 (anyext i1:$in)), 3427 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3428 3429// match setcc on i1 variables. 3430// CRANDC is: 3431// 1 1 : F 3432// 1 0 : T 3433// 0 1 : F 3434// 0 0 : F 3435// 3436// LT is: 3437// -1 -1 : F 3438// -1 0 : T 3439// 0 -1 : F 3440// 0 0 : F 3441// 3442// ULT is: 3443// 1 1 : F 3444// 1 0 : F 3445// 0 1 : T 3446// 0 0 : F 3447def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)), 3448 (CRANDC $s1, $s2)>; 3449def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)), 3450 (CRANDC $s2, $s1)>; 3451// CRORC is: 3452// 1 1 : T 3453// 1 0 : T 3454// 0 1 : F 3455// 0 0 : T 3456// 3457// LE is: 3458// -1 -1 : T 3459// -1 0 : T 3460// 0 -1 : F 3461// 0 0 : T 3462// 3463// ULE is: 3464// 1 1 : T 3465// 1 0 : F 3466// 0 1 : T 3467// 0 0 : T 3468def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)), 3469 (CRORC $s1, $s2)>; 3470def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), 3471 (CRORC $s2, $s1)>; 3472 3473def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)), 3474 (CREQV $s1, $s2)>; 3475 3476// GE is: 3477// -1 -1 : T 3478// -1 0 : F 3479// 0 -1 : T 3480// 0 0 : T 3481// 3482// UGE is: 3483// 1 1 : T 3484// 1 0 : T 3485// 0 1 : F 3486// 0 0 : T 3487def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), 3488 (CRORC $s2, $s1)>; 3489def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)), 3490 (CRORC $s1, $s2)>; 3491 3492// GT is: 3493// -1 -1 : F 3494// -1 0 : F 3495// 0 -1 : T 3496// 0 0 : F 3497// 3498// UGT is: 3499// 1 1 : F 3500// 1 0 : T 3501// 0 1 : F 3502// 0 0 : F 3503def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)), 3504 (CRANDC $s2, $s1)>; 3505def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)), 3506 (CRANDC $s1, $s2)>; 3507 3508def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)), 3509 (CRXOR $s1, $s2)>; 3510 3511// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE, 3512// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for 3513// floating-point types. 3514 3515multiclass CRNotPat<dag pattern, dag result> { 3516 def : Pat<pattern, (crnot result)>; 3517 def : Pat<(not pattern), result>; 3518 3519 // We can also fold the crnot into an extension: 3520 def : Pat<(i32 (zext pattern)), 3521 (SELECT_I4 result, (LI 0), (LI 1))>; 3522 def : Pat<(i32 (sext pattern)), 3523 (SELECT_I4 result, (LI 0), (LI -1))>; 3524 3525 // We can also fold the crnot into an extension: 3526 def : Pat<(i64 (zext pattern)), 3527 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3528 def : Pat<(i64 (sext pattern)), 3529 (SELECT_I8 result, (LI8 0), (LI8 -1))>; 3530 3531 // FIXME: We should choose either a zext or a sext based on other constants 3532 // already around. 3533 def : Pat<(i32 (anyext pattern)), 3534 (SELECT_I4 result, (LI 0), (LI 1))>; 3535 3536 def : Pat<(i64 (anyext pattern)), 3537 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3538} 3539 3540// FIXME: Because of what seems like a bug in TableGen's type-inference code, 3541// we need to write imm:$imm in the output patterns below, not just $imm, or 3542// else the resulting matcher will not correctly add the immediate operand 3543// (making it a register operand instead). 3544 3545// extended SETCC. 3546multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag, 3547 OutPatFrag rfrag, OutPatFrag rfrag8> { 3548 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))), 3549 (rfrag $s1)>; 3550 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))), 3551 (rfrag8 $s1)>; 3552 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))), 3553 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3554 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))), 3555 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3556 3557 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))), 3558 (rfrag $s1)>; 3559 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))), 3560 (rfrag8 $s1)>; 3561 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))), 3562 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3563 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))), 3564 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3565} 3566 3567// Note that we do all inversions below with i(32|64)not, instead of using 3568// (xori x, 1) because on the A2 nor has single-cycle latency while xori 3569// has 2-cycle latency. 3570 3571defm : ExtSetCCPat<SETEQ, 3572 PatFrag<(ops node:$in, node:$cc), 3573 (setcc $in, 0, $cc)>, 3574 OutPatFrag<(ops node:$in), 3575 (RLWINM (CNTLZW $in), 27, 31, 31)>, 3576 OutPatFrag<(ops node:$in), 3577 (RLDICL (CNTLZD $in), 58, 63)> >; 3578 3579defm : ExtSetCCPat<SETNE, 3580 PatFrag<(ops node:$in, node:$cc), 3581 (setcc $in, 0, $cc)>, 3582 OutPatFrag<(ops node:$in), 3583 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>, 3584 OutPatFrag<(ops node:$in), 3585 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >; 3586 3587defm : ExtSetCCPat<SETLT, 3588 PatFrag<(ops node:$in, node:$cc), 3589 (setcc $in, 0, $cc)>, 3590 OutPatFrag<(ops node:$in), 3591 (RLWINM $in, 1, 31, 31)>, 3592 OutPatFrag<(ops node:$in), 3593 (RLDICL $in, 1, 63)> >; 3594 3595defm : ExtSetCCPat<SETGE, 3596 PatFrag<(ops node:$in, node:$cc), 3597 (setcc $in, 0, $cc)>, 3598 OutPatFrag<(ops node:$in), 3599 (RLWINM (i32not $in), 1, 31, 31)>, 3600 OutPatFrag<(ops node:$in), 3601 (RLDICL (i64not $in), 1, 63)> >; 3602 3603defm : ExtSetCCPat<SETGT, 3604 PatFrag<(ops node:$in, node:$cc), 3605 (setcc $in, 0, $cc)>, 3606 OutPatFrag<(ops node:$in), 3607 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>, 3608 OutPatFrag<(ops node:$in), 3609 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >; 3610 3611defm : ExtSetCCPat<SETLE, 3612 PatFrag<(ops node:$in, node:$cc), 3613 (setcc $in, 0, $cc)>, 3614 OutPatFrag<(ops node:$in), 3615 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>, 3616 OutPatFrag<(ops node:$in), 3617 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >; 3618 3619defm : ExtSetCCPat<SETLT, 3620 PatFrag<(ops node:$in, node:$cc), 3621 (setcc $in, -1, $cc)>, 3622 OutPatFrag<(ops node:$in), 3623 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>, 3624 OutPatFrag<(ops node:$in), 3625 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3626 3627defm : ExtSetCCPat<SETGE, 3628 PatFrag<(ops node:$in, node:$cc), 3629 (setcc $in, -1, $cc)>, 3630 OutPatFrag<(ops node:$in), 3631 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>, 3632 OutPatFrag<(ops node:$in), 3633 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3634 3635defm : ExtSetCCPat<SETGT, 3636 PatFrag<(ops node:$in, node:$cc), 3637 (setcc $in, -1, $cc)>, 3638 OutPatFrag<(ops node:$in), 3639 (RLWINM (i32not $in), 1, 31, 31)>, 3640 OutPatFrag<(ops node:$in), 3641 (RLDICL (i64not $in), 1, 63)> >; 3642 3643defm : ExtSetCCPat<SETLE, 3644 PatFrag<(ops node:$in, node:$cc), 3645 (setcc $in, -1, $cc)>, 3646 OutPatFrag<(ops node:$in), 3647 (RLWINM $in, 1, 31, 31)>, 3648 OutPatFrag<(ops node:$in), 3649 (RLDICL $in, 1, 63)> >; 3650 3651// An extended SETCC with shift amount. 3652multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag, 3653 OutPatFrag rfrag, OutPatFrag rfrag8> { 3654 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3655 (rfrag $s1, $sa)>; 3656 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3657 (rfrag8 $s1, $sa)>; 3658 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3659 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3660 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3661 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3662 3663 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3664 (rfrag $s1, $sa)>; 3665 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3666 (rfrag8 $s1, $sa)>; 3667 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3668 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3669 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3670 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3671} 3672 3673defm : ExtSetCCShiftPat<SETNE, 3674 PatFrag<(ops node:$in, node:$sa, node:$cc), 3675 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3676 OutPatFrag<(ops node:$in, node:$sa), 3677 (RLWNM $in, (SUBFIC $sa, 32), 31, 31)>, 3678 OutPatFrag<(ops node:$in, node:$sa), 3679 (RLDCL $in, (SUBFIC $sa, 64), 63)> >; 3680 3681defm : ExtSetCCShiftPat<SETEQ, 3682 PatFrag<(ops node:$in, node:$sa, node:$cc), 3683 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3684 OutPatFrag<(ops node:$in, node:$sa), 3685 (RLWNM (i32not $in), 3686 (SUBFIC $sa, 32), 31, 31)>, 3687 OutPatFrag<(ops node:$in, node:$sa), 3688 (RLDCL (i64not $in), 3689 (SUBFIC $sa, 64), 63)> >; 3690 3691// SETCC for i32. 3692def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)), 3693 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3694def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)), 3695 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3696def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)), 3697 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3698def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)), 3699 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3700def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)), 3701 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3702def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)), 3703 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3704 3705// For non-equality comparisons, the default code would materialize the 3706// constant, then compare against it, like this: 3707// lis r2, 4660 3708// ori r2, r2, 22136 3709// cmpw cr0, r3, r2 3710// beq cr0,L6 3711// Since we are just comparing for equality, we can emit this instead: 3712// xoris r0,r3,0x1234 3713// cmplwi cr0,r0,0x5678 3714// beq cr0,L6 3715 3716def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)), 3717 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3718 (LO16 imm:$imm)), sub_eq)>; 3719 3720def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)), 3721 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3722def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)), 3723 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3724def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)), 3725 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3726def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)), 3727 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3728def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)), 3729 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3730 3731// SETCC for i64. 3732def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)), 3733 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3734def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)), 3735 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3736def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)), 3737 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3738def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)), 3739 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3740def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)), 3741 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3742def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)), 3743 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3744 3745// For non-equality comparisons, the default code would materialize the 3746// constant, then compare against it, like this: 3747// lis r2, 4660 3748// ori r2, r2, 22136 3749// cmpd cr0, r3, r2 3750// beq cr0,L6 3751// Since we are just comparing for equality, we can emit this instead: 3752// xoris r0,r3,0x1234 3753// cmpldi cr0,r0,0x5678 3754// beq cr0,L6 3755 3756def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)), 3757 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3758 (LO16 imm:$imm)), sub_eq)>; 3759 3760def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)), 3761 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3762def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)), 3763 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3764def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)), 3765 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3766def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)), 3767 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3768def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)), 3769 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3770 3771// Instantiations of CRNotPat for i32. 3772defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)), 3773 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3774defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)), 3775 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3776defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)), 3777 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3778defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)), 3779 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3780defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)), 3781 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3782defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)), 3783 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3784 3785defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 3786 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3787 (LO16 imm:$imm)), sub_eq)>; 3788 3789defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)), 3790 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3791defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)), 3792 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3793defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)), 3794 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3795defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)), 3796 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3797defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)), 3798 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3799 3800// Instantiations of CRNotPat for i64. 3801defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)), 3802 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3803defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)), 3804 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3805defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)), 3806 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3807defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)), 3808 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3809defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)), 3810 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3811defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)), 3812 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3813 3814defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 3815 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3816 (LO16 imm:$imm)), sub_eq)>; 3817 3818defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)), 3819 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3820defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)), 3821 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3822defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)), 3823 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3824defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)), 3825 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3826defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)), 3827 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3828 3829let Predicates = [HasFPU] in { 3830// Instantiations of CRNotPat for f32. 3831defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)), 3832 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 3833defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)), 3834 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 3835defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)), 3836 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 3837defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)), 3838 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 3839defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)), 3840 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 3841defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)), 3842 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 3843defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)), 3844 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>; 3845 3846// Instantiations of CRNotPat for f64. 3847defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)), 3848 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 3849defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)), 3850 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 3851defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)), 3852 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 3853defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)), 3854 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 3855defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)), 3856 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 3857defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)), 3858 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 3859defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)), 3860 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>; 3861 3862// Instantiations of CRNotPat for f128. 3863defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETUGE)), 3864 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>; 3865defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETGE)), 3866 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>; 3867defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETULE)), 3868 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>; 3869defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETLE)), 3870 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>; 3871defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETUNE)), 3872 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>; 3873defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETNE)), 3874 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>; 3875defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETO)), 3876 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_un)>; 3877} 3878 3879// SETCC for f32. 3880let Predicates = [HasFPU] in { 3881def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)), 3882 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 3883def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)), 3884 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 3885def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)), 3886 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 3887def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)), 3888 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 3889def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)), 3890 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 3891def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)), 3892 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 3893def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)), 3894 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>; 3895 3896// SETCC for f64. 3897def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)), 3898 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 3899def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)), 3900 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 3901def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)), 3902 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 3903def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)), 3904 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 3905def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)), 3906 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 3907def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)), 3908 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 3909def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)), 3910 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>; 3911 3912// SETCC for f128. 3913def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETOLT)), 3914 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>; 3915def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETLT)), 3916 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_lt)>; 3917def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETOGT)), 3918 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>; 3919def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETGT)), 3920 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_gt)>; 3921def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETOEQ)), 3922 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>; 3923def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETEQ)), 3924 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_eq)>; 3925def : Pat<(i1 (setcc f128:$s1, f128:$s2, SETUO)), 3926 (EXTRACT_SUBREG (XSCMPUQP $s1, $s2), sub_un)>; 3927 3928} 3929 3930// This must be in this file because it relies on patterns defined in this file 3931// after the inclusion of the instruction sets. 3932let Predicates = [HasSPE] in { 3933// SETCC for f32. 3934def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)), 3935 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3936def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)), 3937 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3938def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)), 3939 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3940def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)), 3941 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3942def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)), 3943 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3944def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)), 3945 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3946 3947defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)), 3948 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3949defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)), 3950 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3951defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)), 3952 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3953defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)), 3954 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3955defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)), 3956 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3957defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)), 3958 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3959 3960// SETCC for f64. 3961def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)), 3962 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3963def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)), 3964 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3965def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)), 3966 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 3967def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)), 3968 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 3969def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)), 3970 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 3971def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)), 3972 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 3973 3974defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)), 3975 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3976defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)), 3977 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3978defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)), 3979 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 3980defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)), 3981 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 3982defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)), 3983 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 3984defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)), 3985 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 3986} 3987// match select on i1 variables: 3988def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)), 3989 (CROR (CRAND $cond , $tval), 3990 (CRAND (crnot $cond), $fval))>; 3991 3992// match selectcc on i1 variables: 3993// select (lhs == rhs), tval, fval is: 3994// ((lhs == rhs) & tval) | (!(lhs == rhs) & fval) 3995def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)), 3996 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 3997 (CRAND (CRORC $rhs, $lhs), $fval))>; 3998def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)), 3999 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 4000 (CRAND (CRORC $lhs, $rhs), $fval))>; 4001def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)), 4002 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 4003 (CRAND (CRANDC $rhs, $lhs), $fval))>; 4004def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)), 4005 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 4006 (CRAND (CRANDC $lhs, $rhs), $fval))>; 4007def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)), 4008 (CROR (CRAND (CREQV $lhs, $rhs), $tval), 4009 (CRAND (CRXOR $lhs, $rhs), $fval))>; 4010def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)), 4011 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 4012 (CRAND (CRANDC $lhs, $rhs), $fval))>; 4013def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)), 4014 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 4015 (CRAND (CRANDC $rhs, $lhs), $fval))>; 4016def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)), 4017 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 4018 (CRAND (CRORC $lhs, $rhs), $fval))>; 4019def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)), 4020 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 4021 (CRAND (CRORC $rhs, $lhs), $fval))>; 4022def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)), 4023 (CROR (CRAND (CREQV $lhs, $rhs), $fval), 4024 (CRAND (CRXOR $lhs, $rhs), $tval))>; 4025 4026// match selectcc on i1 variables with non-i1 output. 4027def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)), 4028 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4029def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)), 4030 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4031def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)), 4032 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 4033def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)), 4034 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 4035def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)), 4036 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>; 4037def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)), 4038 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 4039def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)), 4040 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 4041def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)), 4042 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4043def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)), 4044 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4045def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)), 4046 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>; 4047 4048def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)), 4049 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4050def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)), 4051 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4052def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)), 4053 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 4054def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)), 4055 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 4056def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)), 4057 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>; 4058def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)), 4059 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 4060def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)), 4061 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 4062def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)), 4063 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4064def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)), 4065 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4066def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)), 4067 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>; 4068 4069let Predicates = [HasFPU] in { 4070def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), 4071 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4072def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), 4073 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4074def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), 4075 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 4076def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), 4077 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 4078def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), 4079 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>; 4080def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), 4081 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 4082def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)), 4083 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 4084def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), 4085 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4086def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)), 4087 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4088def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), 4089 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>; 4090 4091def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), 4092 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4093def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)), 4094 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4095def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), 4096 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 4097def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)), 4098 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 4099def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), 4100 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>; 4101def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), 4102 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 4103def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), 4104 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 4105def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), 4106 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4107def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), 4108 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4109def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), 4110 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>; 4111} 4112 4113def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLT)), 4114 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 4115def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULT)), 4116 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 4117def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLE)), 4118 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 4119def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULE)), 4120 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 4121def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETEQ)), 4122 (SELECT_F16 (CREQV $lhs, $rhs), $tval, $fval)>; 4123def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGE)), 4124 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 4125def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGE)), 4126 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 4127def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGT)), 4128 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 4129def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGT)), 4130 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 4131def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETNE)), 4132 (SELECT_F16 (CRXOR $lhs, $rhs), $tval, $fval)>; 4133 4134def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)), 4135 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 4136def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)), 4137 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 4138def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)), 4139 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 4140def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)), 4141 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 4142def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)), 4143 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>; 4144def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)), 4145 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 4146def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)), 4147 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 4148def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)), 4149 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 4150def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)), 4151 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 4152def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)), 4153 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>; 4154 4155def ANDI_rec_1_EQ_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 4156 "#ANDI_rec_1_EQ_BIT", 4157 [(set i1:$dst, (trunc (not i32:$in)))]>; 4158def ANDI_rec_1_GT_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 4159 "#ANDI_rec_1_GT_BIT", 4160 [(set i1:$dst, (trunc i32:$in))]>; 4161 4162def ANDI_rec_1_EQ_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 4163 "#ANDI_rec_1_EQ_BIT8", 4164 [(set i1:$dst, (trunc (not i64:$in)))]>; 4165def ANDI_rec_1_GT_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 4166 "#ANDI_rec_1_GT_BIT8", 4167 [(set i1:$dst, (trunc i64:$in))]>; 4168 4169def : Pat<(i1 (not (trunc i32:$in))), 4170 (ANDI_rec_1_EQ_BIT $in)>; 4171def : Pat<(i1 (not (trunc i64:$in))), 4172 (ANDI_rec_1_EQ_BIT8 $in)>; 4173 4174//===----------------------------------------------------------------------===// 4175// PowerPC Instructions used for assembler/disassembler only 4176// 4177 4178// FIXME: For B=0 or B > 8, the registers following RT are used. 4179// WARNING: Do not add patterns for this instruction without fixing this. 4180def LSWI : XForm_base_r3xo_memOp<31, 597, (outs gprc:$RT), 4181 (ins gprc:$A, u5imm:$B), 4182 "lswi $RT, $A, $B", IIC_LdStLoad, []>; 4183 4184// FIXME: For B=0 or B > 8, the registers following RT are used. 4185// WARNING: Do not add patterns for this instruction without fixing this. 4186def STSWI : XForm_base_r3xo_memOp<31, 725, (outs), 4187 (ins gprc:$RT, gprc:$A, u5imm:$B), 4188 "stswi $RT, $A, $B", IIC_LdStLoad, []>; 4189 4190def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins), 4191 "isync", IIC_SprISYNC, []>; 4192 4193def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src), 4194 "icbi $src", IIC_LdStICBI, []>; 4195 4196def WAIT : XForm_24_sync<31, 30, (outs), (ins i32imm:$L), 4197 "wait $L", IIC_LdStLoad, []>; 4198 4199def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO), 4200 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>; 4201 4202def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR), 4203 "mtsr $SR, $RS", IIC_SprMTSR>; 4204 4205def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR), 4206 "mfsr $RS, $SR", IIC_SprMFSR>; 4207 4208def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB), 4209 "mtsrin $RS, $RB", IIC_SprMTSR>; 4210 4211def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB), 4212 "mfsrin $RS, $RB", IIC_SprMFSR>; 4213 4214def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L), 4215 "mtmsr $RS, $L", IIC_SprMTMSR>; 4216 4217def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS), 4218 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> { 4219 let L = 0; 4220} 4221 4222def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>, 4223 Requires<[IsBookE]> { 4224 bits<1> E; 4225 4226 let Inst{16} = E; 4227 let Inst{21-30} = 163; 4228} 4229 4230def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B), 4231 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4232def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B), 4233 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4234 4235def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4236def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4237def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4238def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4239 4240def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins), 4241 "mfmsr $RT", IIC_SprMFMSR, []>; 4242 4243def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L), 4244 "mtmsrd $RS, $L", IIC_SprMTMSRD>; 4245 4246def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA), 4247 "mcrfs $BF, $BFA", IIC_BrMCR>; 4248 4249def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W), 4250 "mtfsfi $BF, $U, $W", IIC_IntMFFS>; 4251 4252def MTFSFI_rec : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W), 4253 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isRecordForm; 4254 4255def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>; 4256def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec crrc:$BF, i32imm:$U, 0)>; 4257 4258let Predicates = [HasFPU] in { 4259def MTFSF : XFLForm_1<63, 711, (outs), 4260 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W), 4261 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>; 4262def MTFSF_rec : XFLForm_1<63, 711, (outs), 4263 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W), 4264 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isRecordForm; 4265 4266def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4267def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4268} 4269 4270def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB), 4271 "slbie $RB", IIC_SprSLBIE, []>; 4272 4273def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB), 4274 "slbmte $RS, $RB", IIC_SprSLBMTE, []>; 4275 4276def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB), 4277 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>; 4278 4279def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB), 4280 "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>; 4281 4282def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>; 4283 4284let Defs = [CR0] in 4285def SLBFEE_rec : XForm_26<31, 979, (outs gprc:$RT), (ins gprc:$RB), 4286 "slbfee. $RT, $RB", IIC_SprSLBFEE, []>, isRecordForm; 4287 4288def TLBIA : XForm_0<31, 370, (outs), (ins), 4289 "tlbia", IIC_SprTLBIA, []>; 4290 4291def TLBSYNC : XForm_0<31, 566, (outs), (ins), 4292 "tlbsync", IIC_SprTLBSYNC, []>; 4293 4294def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB), 4295 "tlbiel $RB", IIC_SprTLBIEL, []>; 4296 4297def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB), 4298 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4299def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB), 4300 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4301 4302def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB), 4303 "tlbie $RB,$RS", IIC_SprTLBIE, []>; 4304 4305def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B", 4306 IIC_LdStLoad>, Requires<[IsBookE]>; 4307 4308def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B", 4309 IIC_LdStLoad>, Requires<[IsBookE]>; 4310 4311def TLBRE : XForm_24_eieio<31, 946, (outs), (ins), 4312 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4313 4314def TLBWE : XForm_24_eieio<31, 978, (outs), (ins), 4315 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4316 4317def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS), 4318 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4319 4320def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS), 4321 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4322 4323def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B), 4324 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>, 4325 Requires<[IsPPC4xx]>; 4326def TLBSX2D : XForm_base_r3xo<31, 914, (outs), 4327 (ins gprc:$RST, gprc:$A, gprc:$B), 4328 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>, 4329 Requires<[IsPPC4xx]>, isRecordForm; 4330 4331def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>; 4332 4333def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>, 4334 Requires<[IsBookE]>; 4335def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>, 4336 Requires<[IsBookE]>; 4337 4338def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>, 4339 Requires<[IsE500]>; 4340def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>, 4341 Requires<[IsE500]>; 4342 4343def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR), 4344 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>; 4345def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR), 4346 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>; 4347 4348def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>; 4349def NAP : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>; 4350 4351def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>; 4352 4353def LBZCIX : XForm_base_r3xo_memOp<31, 853, (outs gprc:$RST), 4354 (ins gprc:$A, gprc:$B), 4355 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>; 4356def LHZCIX : XForm_base_r3xo_memOp<31, 821, (outs gprc:$RST), 4357 (ins gprc:$A, gprc:$B), 4358 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>; 4359def LWZCIX : XForm_base_r3xo_memOp<31, 789, (outs gprc:$RST), 4360 (ins gprc:$A, gprc:$B), 4361 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>; 4362def LDCIX : XForm_base_r3xo_memOp<31, 885, (outs gprc:$RST), 4363 (ins gprc:$A, gprc:$B), 4364 "ldcix $RST, $A, $B", IIC_LdStLoad, []>; 4365 4366def STBCIX : XForm_base_r3xo_memOp<31, 981, (outs), 4367 (ins gprc:$RST, gprc:$A, gprc:$B), 4368 "stbcix $RST, $A, $B", IIC_LdStLoad, []>; 4369def STHCIX : XForm_base_r3xo_memOp<31, 949, (outs), 4370 (ins gprc:$RST, gprc:$A, gprc:$B), 4371 "sthcix $RST, $A, $B", IIC_LdStLoad, []>; 4372def STWCIX : XForm_base_r3xo_memOp<31, 917, (outs), 4373 (ins gprc:$RST, gprc:$A, gprc:$B), 4374 "stwcix $RST, $A, $B", IIC_LdStLoad, []>; 4375def STDCIX : XForm_base_r3xo_memOp<31, 1013, (outs), 4376 (ins gprc:$RST, gprc:$A, gprc:$B), 4377 "stdcix $RST, $A, $B", IIC_LdStLoad, []>; 4378 4379// External PID Load Store Instructions 4380 4381def LBEPX : XForm_1<31, 95, (outs gprc:$rD), (ins memrr:$src), 4382 "lbepx $rD, $src", IIC_LdStLoad, []>, 4383 Requires<[IsE500]>; 4384 4385def LFDEPX : XForm_25<31, 607, (outs f8rc:$frD), (ins memrr:$src), 4386 "lfdepx $frD, $src", IIC_LdStLFD, []>, 4387 Requires<[IsE500]>; 4388 4389def LHEPX : XForm_1<31, 287, (outs gprc:$rD), (ins memrr:$src), 4390 "lhepx $rD, $src", IIC_LdStLoad, []>, 4391 Requires<[IsE500]>; 4392 4393def LWEPX : XForm_1<31, 31, (outs gprc:$rD), (ins memrr:$src), 4394 "lwepx $rD, $src", IIC_LdStLoad, []>, 4395 Requires<[IsE500]>; 4396 4397def STBEPX : XForm_8<31, 223, (outs), (ins gprc:$rS, memrr:$dst), 4398 "stbepx $rS, $dst", IIC_LdStStore, []>, 4399 Requires<[IsE500]>; 4400 4401def STFDEPX : XForm_28_memOp<31, 735, (outs), (ins f8rc:$frS, memrr:$dst), 4402 "stfdepx $frS, $dst", IIC_LdStSTFD, []>, 4403 Requires<[IsE500]>; 4404 4405def STHEPX : XForm_8<31, 415, (outs), (ins gprc:$rS, memrr:$dst), 4406 "sthepx $rS, $dst", IIC_LdStStore, []>, 4407 Requires<[IsE500]>; 4408 4409def STWEPX : XForm_8<31, 159, (outs), (ins gprc:$rS, memrr:$dst), 4410 "stwepx $rS, $dst", IIC_LdStStore, []>, 4411 Requires<[IsE500]>; 4412 4413def DCBFEP : DCB_Form<127, 0, (outs), (ins memrr:$dst), "dcbfep $dst", 4414 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4415 4416def DCBSTEP : DCB_Form<63, 0, (outs), (ins memrr:$dst), "dcbstep $dst", 4417 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4418 4419def DCBTEP : DCB_Form_hint<319, (outs), (ins memrr:$dst, u5imm:$TH), 4420 "dcbtep $TH, $dst", IIC_LdStDCBF, []>, 4421 Requires<[IsE500]>; 4422 4423def DCBTSTEP : DCB_Form_hint<255, (outs), (ins memrr:$dst, u5imm:$TH), 4424 "dcbtstep $TH, $dst", IIC_LdStDCBF, []>, 4425 Requires<[IsE500]>; 4426 4427def DCBZEP : DCB_Form<1023, 0, (outs), (ins memrr:$dst), "dcbzep $dst", 4428 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4429 4430def DCBZLEP : DCB_Form<1023, 1, (outs), (ins memrr:$dst), "dcbzlep $dst", 4431 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4432 4433def ICBIEP : XForm_1a<31, 991, (outs), (ins memrr:$src), "icbiep $src", 4434 IIC_LdStICBI, []>, Requires<[IsE500]>; 4435 4436//===----------------------------------------------------------------------===// 4437// PowerPC Assembler Instruction Aliases 4438// 4439 4440// Pseudo-instructions for alternate assembly syntax (never used by codegen). 4441// These are aliases that require C++ handling to convert to the target 4442// instruction, while InstAliases can be handled directly by tblgen. 4443class PPCAsmPseudo<string asm, dag iops> 4444 : Instruction { 4445 let Namespace = "PPC"; 4446 bit PPC64 = 0; // Default value, override with isPPC64 4447 4448 let OutOperandList = (outs); 4449 let InOperandList = iops; 4450 let Pattern = []; 4451 let AsmString = asm; 4452 let isAsmParserOnly = 1; 4453 let isPseudo = 1; 4454 let hasNoSchedulingInfo = 1; 4455} 4456 4457def : InstAlias<"sc", (SC 0)>; 4458 4459def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>; 4460def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>; 4461def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>; 4462def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>; 4463 4464def : InstAlias<"wait", (WAIT 0)>; 4465def : InstAlias<"waitrsv", (WAIT 1)>; 4466def : InstAlias<"waitimpl", (WAIT 2)>; 4467 4468def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>; 4469 4470def DCBTx : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>; 4471def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>; 4472 4473def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4474def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4475def DCBTT : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>; 4476 4477def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4478def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4479def DCBTSTT : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>; 4480 4481def DCBFx : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>; 4482def DCBFL : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>; 4483def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>; 4484 4485def : Pat<(int_ppc_dcbfl xoaddr:$dst), 4486 (DCBFL xoaddr:$dst)>; 4487def : Pat<(int_ppc_dcbflp xoaddr:$dst), 4488 (DCBFLP xoaddr:$dst)>; 4489 4490def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4491def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4492def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4493def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4494 4495def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>; 4496def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>; 4497def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>; 4498 4499def : InstAlias<"xnop", (XORI R0, R0, 0)>; 4500 4501foreach BR = 0-7 in { 4502 def : InstAlias<"mfbr"#BR#" $Rx", 4503 (MFDCR gprc:$Rx, !add(BR, 0x80))>, 4504 Requires<[IsPPC4xx]>; 4505 def : InstAlias<"mtbr"#BR#" $Rx", 4506 (MTDCR gprc:$Rx, !add(BR, 0x80))>, 4507 Requires<[IsPPC4xx]>; 4508} 4509 4510def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>; 4511def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>; 4512 4513def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>; 4514def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>; 4515 4516def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>; 4517def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>; 4518 4519def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>; 4520def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>; 4521 4522def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>; 4523def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>; 4524 4525def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>; 4526def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>; 4527 4528def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>; 4529def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>; 4530 4531def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>; 4532def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>; 4533 4534def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>; 4535def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>; 4536 4537def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>; 4538def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>; 4539 4540def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>; 4541def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>; 4542 4543def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>; 4544def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>; 4545 4546def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>; 4547def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>; 4548 4549foreach SPRG = 4-7 in { 4550 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>, 4551 Requires<[IsBookE]>; 4552 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>, 4553 Requires<[IsBookE]>; 4554 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4555 Requires<[IsBookE]>; 4556 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4557 Requires<[IsBookE]>; 4558} 4559 4560foreach SPRG = 0-3 in { 4561 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>; 4562 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>; 4563 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4564 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4565} 4566 4567def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>; 4568def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>; 4569 4570def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>; 4571def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>; 4572 4573def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>; 4574 4575def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>; 4576def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>; 4577 4578foreach BATR = 0-3 in { 4579 def : InstAlias<"mtdbatu "#BATR#", $Rx", 4580 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>, 4581 Requires<[IsPPC6xx]>; 4582 def : InstAlias<"mfdbatu $Rx, "#BATR, 4583 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>, 4584 Requires<[IsPPC6xx]>; 4585 def : InstAlias<"mtdbatl "#BATR#", $Rx", 4586 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>, 4587 Requires<[IsPPC6xx]>; 4588 def : InstAlias<"mfdbatl $Rx, "#BATR, 4589 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>, 4590 Requires<[IsPPC6xx]>; 4591 def : InstAlias<"mtibatu "#BATR#", $Rx", 4592 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>, 4593 Requires<[IsPPC6xx]>; 4594 def : InstAlias<"mfibatu $Rx, "#BATR, 4595 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>, 4596 Requires<[IsPPC6xx]>; 4597 def : InstAlias<"mtibatl "#BATR#", $Rx", 4598 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>, 4599 Requires<[IsPPC6xx]>; 4600 def : InstAlias<"mfibatl $Rx, "#BATR, 4601 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>, 4602 Requires<[IsPPC6xx]>; 4603} 4604 4605def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4606def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>; 4607 4608def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4609def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>; 4610 4611def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4612def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>; 4613 4614def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>; 4615def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4616 4617def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>; 4618def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4619 4620def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4621def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>; 4622 4623def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4624def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>; 4625 4626def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4627def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>; 4628 4629def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4630def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>; 4631 4632 4633def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>; 4634 4635def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>, 4636 Requires<[IsPPC4xx]>; 4637def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>, 4638 Requires<[IsPPC4xx]>; 4639def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>, 4640 Requires<[IsPPC4xx]>; 4641def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>, 4642 Requires<[IsPPC4xx]>; 4643 4644def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>; 4645 4646def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm", 4647 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4648def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm", 4649 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4650def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm", 4651 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4652def SUBIC_rec : PPCAsmPseudo<"subic. $rA, $rB, $imm", 4653 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4654 4655def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b", 4656 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4657def EXTLWI_rec : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b", 4658 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4659def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b", 4660 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4661def EXTRWI_rec : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b", 4662 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4663def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b", 4664 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4665def INSLWI_rec : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b", 4666 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4667def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b", 4668 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4669def INSRWI_rec : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b", 4670 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4671def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n", 4672 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4673def ROTRWI_rec : PPCAsmPseudo<"rotrwi. $rA, $rS, $n", 4674 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4675def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n", 4676 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4677def SLWI_rec : PPCAsmPseudo<"slwi. $rA, $rS, $n", 4678 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4679def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n", 4680 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4681def SRWI_rec : PPCAsmPseudo<"srwi. $rA, $rS, $n", 4682 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4683def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n", 4684 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4685def CLRRWI_rec : PPCAsmPseudo<"clrrwi. $rA, $rS, $n", 4686 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4687def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n", 4688 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4689def CLRLSLWI_rec : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n", 4690 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4691 4692def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4693def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4694def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4695def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM_rec gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4696def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4697def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4698 4699def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>; 4700def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW_rec gprc:$rA, gprc:$rS)>; 4701// The POWER variant 4702def : MnemonicAlias<"cntlz", "cntlzw">; 4703def : MnemonicAlias<"cntlz.", "cntlzw.">; 4704 4705def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b", 4706 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4707def EXTLDI_rec : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b", 4708 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4709def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b", 4710 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4711def EXTRDI_rec : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b", 4712 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4713def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b", 4714 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4715def INSRDI_rec : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b", 4716 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4717def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n", 4718 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4719def ROTRDI_rec : PPCAsmPseudo<"rotrdi. $rA, $rS, $n", 4720 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4721def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n", 4722 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4723def SLDI_rec : PPCAsmPseudo<"sldi. $rA, $rS, $n", 4724 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4725def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n", 4726 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4727def SRDI_rec : PPCAsmPseudo<"srdi. $rA, $rS, $n", 4728 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4729def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n", 4730 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4731def CLRRDI_rec : PPCAsmPseudo<"clrrdi. $rA, $rS, $n", 4732 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4733def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n", 4734 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4735def CLRLSLDI_rec : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n", 4736 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4737def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>; 4738 4739def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4740def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4741def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4742def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4743def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4744def : InstAlias<"clrldi $rA, $rS, $n", 4745 (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)>; 4746def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4747def : InstAlias<"lnia $RT", (ADDPCIS g8rc:$RT, 0)>; 4748 4749def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b", 4750 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4751def RLWINMbm_rec : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b", 4752 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4753def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b", 4754 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4755def RLWIMIbm_rec : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b", 4756 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4757def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b", 4758 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4759def RLWNMbm_rec : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b", 4760 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4761 4762// These generic branch instruction forms are used for the assembler parser only. 4763// Defs and Uses are conservative, since we don't know the BO value. 4764let PPC970_Unit = 7, isBranch = 1 in { 4765 let Defs = [CTR], Uses = [CTR, RM] in { 4766 def gBC : BForm_3<16, 0, 0, (outs), 4767 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 4768 "bc $bo, $bi, $dst">; 4769 def gBCA : BForm_3<16, 1, 0, (outs), 4770 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 4771 "bca $bo, $bi, $dst">; 4772 let isAsmParserOnly = 1 in { 4773 def gBCat : BForm_3_at<16, 0, 0, (outs), 4774 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 4775 condbrtarget:$dst), 4776 "bc$at $bo, $bi, $dst">; 4777 def gBCAat : BForm_3_at<16, 1, 0, (outs), 4778 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 4779 abscondbrtarget:$dst), 4780 "bca$at $bo, $bi, $dst">; 4781 } // isAsmParserOnly = 1 4782 } 4783 let Defs = [LR, CTR], Uses = [CTR, RM] in { 4784 def gBCL : BForm_3<16, 0, 1, (outs), 4785 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 4786 "bcl $bo, $bi, $dst">; 4787 def gBCLA : BForm_3<16, 1, 1, (outs), 4788 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 4789 "bcla $bo, $bi, $dst">; 4790 let isAsmParserOnly = 1 in { 4791 def gBCLat : BForm_3_at<16, 0, 1, (outs), 4792 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 4793 condbrtarget:$dst), 4794 "bcl$at $bo, $bi, $dst">; 4795 def gBCLAat : BForm_3_at<16, 1, 1, (outs), 4796 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 4797 abscondbrtarget:$dst), 4798 "bcla$at $bo, $bi, $dst">; 4799 } // // isAsmParserOnly = 1 4800 } 4801 let Defs = [CTR], Uses = [CTR, LR, RM] in 4802 def gBCLR : XLForm_2<19, 16, 0, (outs), 4803 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4804 "bclr $bo, $bi, $bh", IIC_BrB, []>; 4805 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4806 def gBCLRL : XLForm_2<19, 16, 1, (outs), 4807 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4808 "bclrl $bo, $bi, $bh", IIC_BrB, []>; 4809 let Defs = [CTR], Uses = [CTR, LR, RM] in 4810 def gBCCTR : XLForm_2<19, 528, 0, (outs), 4811 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4812 "bcctr $bo, $bi, $bh", IIC_BrB, []>; 4813 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4814 def gBCCTRL : XLForm_2<19, 528, 1, (outs), 4815 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4816 "bcctrl $bo, $bi, $bh", IIC_BrB, []>; 4817} 4818 4819multiclass BranchSimpleMnemonicAT<string pm, int at> { 4820 def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi, 4821 condbrtarget:$dst)>; 4822 def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi, 4823 condbrtarget:$dst)>; 4824 def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi, 4825 condbrtarget:$dst)>; 4826 def : InstAlias<"bcla"#pm#" $bo, $bi, $dst", (gBCLAat u5imm:$bo, at, crbitrc:$bi, 4827 condbrtarget:$dst)>; 4828} 4829defm : BranchSimpleMnemonicAT<"+", 3>; 4830defm : BranchSimpleMnemonicAT<"-", 2>; 4831 4832def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>; 4833def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>; 4834def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>; 4835def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>; 4836 4837multiclass BranchSimpleMnemonic1<string name, string pm, int bo> { 4838 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>; 4839 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4840 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>; 4841 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>; 4842 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4843 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>; 4844} 4845multiclass BranchSimpleMnemonic2<string name, string pm, int bo> 4846 : BranchSimpleMnemonic1<name, pm, bo> { 4847 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>; 4848 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>; 4849} 4850defm : BranchSimpleMnemonic2<"t", "", 12>; 4851defm : BranchSimpleMnemonic2<"f", "", 4>; 4852defm : BranchSimpleMnemonic2<"t", "-", 14>; 4853defm : BranchSimpleMnemonic2<"f", "-", 6>; 4854defm : BranchSimpleMnemonic2<"t", "+", 15>; 4855defm : BranchSimpleMnemonic2<"f", "+", 7>; 4856defm : BranchSimpleMnemonic1<"dnzt", "", 8>; 4857defm : BranchSimpleMnemonic1<"dnzf", "", 0>; 4858defm : BranchSimpleMnemonic1<"dzt", "", 10>; 4859defm : BranchSimpleMnemonic1<"dzf", "", 2>; 4860 4861multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> { 4862 def : InstAlias<"b"#name#pm#" $cc, $dst", 4863 (BCC bibo, crrc:$cc, condbrtarget:$dst)>; 4864 def : InstAlias<"b"#name#pm#" $dst", 4865 (BCC bibo, CR0, condbrtarget:$dst)>; 4866 4867 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst", 4868 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4869 def : InstAlias<"b"#name#"a"#pm#" $dst", 4870 (BCCA bibo, CR0, abscondbrtarget:$dst)>; 4871 4872 def : InstAlias<"b"#name#"lr"#pm#" $cc", 4873 (BCCLR bibo, crrc:$cc)>; 4874 def : InstAlias<"b"#name#"lr"#pm, 4875 (BCCLR bibo, CR0)>; 4876 4877 def : InstAlias<"b"#name#"ctr"#pm#" $cc", 4878 (BCCCTR bibo, crrc:$cc)>; 4879 def : InstAlias<"b"#name#"ctr"#pm, 4880 (BCCCTR bibo, CR0)>; 4881 4882 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst", 4883 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>; 4884 def : InstAlias<"b"#name#"l"#pm#" $dst", 4885 (BCCL bibo, CR0, condbrtarget:$dst)>; 4886 4887 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst", 4888 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4889 def : InstAlias<"b"#name#"la"#pm#" $dst", 4890 (BCCLA bibo, CR0, abscondbrtarget:$dst)>; 4891 4892 def : InstAlias<"b"#name#"lrl"#pm#" $cc", 4893 (BCCLRL bibo, crrc:$cc)>; 4894 def : InstAlias<"b"#name#"lrl"#pm, 4895 (BCCLRL bibo, CR0)>; 4896 4897 def : InstAlias<"b"#name#"ctrl"#pm#" $cc", 4898 (BCCCTRL bibo, crrc:$cc)>; 4899 def : InstAlias<"b"#name#"ctrl"#pm, 4900 (BCCCTRL bibo, CR0)>; 4901} 4902multiclass BranchExtendedMnemonic<string name, int bibo> { 4903 defm : BranchExtendedMnemonicPM<name, "", bibo>; 4904 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>; 4905 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>; 4906} 4907defm : BranchExtendedMnemonic<"lt", 12>; 4908defm : BranchExtendedMnemonic<"gt", 44>; 4909defm : BranchExtendedMnemonic<"eq", 76>; 4910defm : BranchExtendedMnemonic<"un", 108>; 4911defm : BranchExtendedMnemonic<"so", 108>; 4912defm : BranchExtendedMnemonic<"ge", 4>; 4913defm : BranchExtendedMnemonic<"nl", 4>; 4914defm : BranchExtendedMnemonic<"le", 36>; 4915defm : BranchExtendedMnemonic<"ng", 36>; 4916defm : BranchExtendedMnemonic<"ne", 68>; 4917defm : BranchExtendedMnemonic<"nu", 100>; 4918defm : BranchExtendedMnemonic<"ns", 100>; 4919 4920def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; 4921def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; 4922def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; 4923def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; 4924def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>; 4925def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; 4926def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>; 4927def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; 4928 4929def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>; 4930def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>; 4931def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>; 4932def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>; 4933def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>; 4934def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 4935def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>; 4936def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 4937 4938multiclass TrapExtendedMnemonic<string name, int to> { 4939 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>; 4940 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>; 4941 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>; 4942 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>; 4943} 4944defm : TrapExtendedMnemonic<"lt", 16>; 4945defm : TrapExtendedMnemonic<"le", 20>; 4946defm : TrapExtendedMnemonic<"eq", 4>; 4947defm : TrapExtendedMnemonic<"ge", 12>; 4948defm : TrapExtendedMnemonic<"gt", 8>; 4949defm : TrapExtendedMnemonic<"nl", 12>; 4950defm : TrapExtendedMnemonic<"ne", 24>; 4951defm : TrapExtendedMnemonic<"ng", 20>; 4952defm : TrapExtendedMnemonic<"llt", 2>; 4953defm : TrapExtendedMnemonic<"lle", 6>; 4954defm : TrapExtendedMnemonic<"lge", 5>; 4955defm : TrapExtendedMnemonic<"lgt", 1>; 4956defm : TrapExtendedMnemonic<"lnl", 5>; 4957defm : TrapExtendedMnemonic<"lng", 6>; 4958defm : TrapExtendedMnemonic<"u", 31>; 4959 4960// Atomic loads 4961def : Pat<(atomic_load_8 iaddr:$src), (LBZ memri:$src)>; 4962def : Pat<(atomic_load_16 iaddr:$src), (LHZ memri:$src)>; 4963def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>; 4964def : Pat<(atomic_load_8 xaddr:$src), (LBZX memrr:$src)>; 4965def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>; 4966def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>; 4967 4968// Atomic stores 4969def : Pat<(atomic_store_8 iaddr:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>; 4970def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>; 4971def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>; 4972def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>; 4973def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>; 4974def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>; 4975 4976let Predicates = [IsISA3_0] in { 4977 4978// Copy-Paste Facility 4979// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to 4980// PASTE for naming consistency. 4981let mayLoad = 1 in 4982def CP_COPY : X_L1_RA5_RB5<31, 774, "copy" , gprc, IIC_LdStCOPY, []>; 4983 4984let mayStore = 1 in 4985def CP_PASTE : X_L1_RA5_RB5<31, 902, "paste" , gprc, IIC_LdStPASTE, []>; 4986 4987let mayStore = 1, Defs = [CR0] in 4988def CP_PASTE_rec : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isRecordForm; 4989 4990def CP_COPYx : PPCAsmPseudo<"copy $rA, $rB" , (ins gprc:$rA, gprc:$rB)>; 4991def CP_PASTEx : PPCAsmPseudo<"paste $rA, $rB", (ins gprc:$rA, gprc:$rB)>; 4992def CP_COPY_FIRST : PPCAsmPseudo<"copy_first $rA, $rB", 4993 (ins gprc:$rA, gprc:$rB)>; 4994def CP_PASTE_LAST : PPCAsmPseudo<"paste_last $rA, $rB", 4995 (ins gprc:$rA, gprc:$rB)>; 4996def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cp_abort", IIC_SprABORT, []>; 4997 4998// Message Synchronize 4999def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>; 5000 5001// Power-Saving Mode Instruction: 5002def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>; 5003 5004} // IsISA3_0 5005 5006// Fast 32-bit reverse bits algorithm: 5007// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 5008// n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xAAAAAAAA); 5009// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 5010// n = ((n >> 2) & 0x33333333) | ((n << 2) & 0xCCCCCCCC); 5011// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 5012// n = ((n >> 4) & 0x0F0F0F0F) | ((n << 4) & 0xF0F0F0F0); 5013// Step 4: byte reverse (Suppose n = [B1,B2,B3,B4]): 5014// Step 4.1: Put B4,B2 in the right position (rotate left 3 bytes): 5015// n' = (n rotl 24); After which n' = [B4, B1, B2, B3] 5016// Step 4.2: Insert B3 to the right position: 5017// n' = rlwimi n', n, 8, 8, 15; After which n' = [B4, B3, B2, B3] 5018// Step 4.3: Insert B1 to the right position: 5019// n' = rlwimi n', n, 8, 24, 31; After which n' = [B4, B3, B2, B1] 5020def MaskValues { 5021 dag Lo1 = (ORI (LIS 0x5555), 0x5555); 5022 dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA); 5023 dag Lo2 = (ORI (LIS 0x3333), 0x3333); 5024 dag Hi2 = (ORI (LIS 0xCCCC), 0xCCCC); 5025 dag Lo4 = (ORI (LIS 0x0F0F), 0x0F0F); 5026 dag Hi4 = (ORI (LIS 0xF0F0), 0xF0F0); 5027} 5028 5029def Shift1 { 5030 dag Right = (RLWINM $A, 31, 1, 31); 5031 dag Left = (RLWINM $A, 1, 0, 30); 5032} 5033 5034def Swap1 { 5035 dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1), 5036 (AND Shift1.Left, MaskValues.Hi1)); 5037} 5038 5039def Shift2 { 5040 dag Right = (RLWINM Swap1.Bit, 30, 2, 31); 5041 dag Left = (RLWINM Swap1.Bit, 2, 0, 29); 5042} 5043 5044def Swap2 { 5045 dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2), 5046 (AND Shift2.Left, MaskValues.Hi2)); 5047} 5048 5049def Shift4 { 5050 dag Right = (RLWINM Swap2.Bits, 28, 4, 31); 5051 dag Left = (RLWINM Swap2.Bits, 4, 0, 27); 5052} 5053 5054def Swap4 { 5055 dag Bits = (OR (AND Shift4.Right, MaskValues.Lo4), 5056 (AND Shift4.Left, MaskValues.Hi4)); 5057} 5058 5059def Rotate { 5060 dag Left3Bytes = (RLWINM Swap4.Bits, 24, 0, 31); 5061} 5062 5063def RotateInsertByte3 { 5064 dag Left = (RLWIMI Rotate.Left3Bytes, Swap4.Bits, 8, 8, 15); 5065} 5066 5067def RotateInsertByte1 { 5068 dag Left = (RLWIMI RotateInsertByte3.Left, Swap4.Bits, 8, 24, 31); 5069} 5070 5071def : Pat<(i32 (bitreverse i32:$A)), 5072 (RLDICL_32 RotateInsertByte1.Left, 0, 32)>; 5073 5074// Fast 64-bit reverse bits algorithm: 5075// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 5076// n = ((n >> 1) & 0x5555555555555555) | ((n << 1) & 0xAAAAAAAAAAAAAAAA); 5077// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 5078// n = ((n >> 2) & 0x3333333333333333) | ((n << 2) & 0xCCCCCCCCCCCCCCCC); 5079// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 5080// n = ((n >> 4) & 0x0F0F0F0F0F0F0F0F) | ((n << 4) & 0xF0F0F0F0F0F0F0F0); 5081// Step 4: byte reverse (Suppose n = [B0,B1,B2,B3,B4,B5,B6,B7]): 5082// Apply the same byte reverse algorithm mentioned above for the fast 32-bit 5083// reverse to both the high 32 bit and low 32 bit of the 64 bit value. And 5084// then OR them together to get the final result. 5085def MaskValues64 { 5086 dag Lo1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo1, sub_32)); 5087 dag Hi1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi1, sub_32)); 5088 dag Lo2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo2, sub_32)); 5089 dag Hi2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi2, sub_32)); 5090 dag Lo4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo4, sub_32)); 5091 dag Hi4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi4, sub_32)); 5092} 5093 5094def DWMaskValues { 5095 dag Lo1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo1, 32, 31), 0x5555), 0x5555); 5096 dag Hi1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi1, 32, 31), 0xAAAA), 0xAAAA); 5097 dag Lo2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo2, 32, 31), 0x3333), 0x3333); 5098 dag Hi2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi2, 32, 31), 0xCCCC), 0xCCCC); 5099 dag Lo4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo4, 32, 31), 0x0F0F), 0x0F0F); 5100 dag Hi4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi4, 32, 31), 0xF0F0), 0xF0F0); 5101} 5102 5103def DWSwapInByte { 5104 dag Swap1 = (OR8 (AND8 (RLDICL $A, 63, 1), DWMaskValues.Lo1), 5105 (AND8 (RLDICR $A, 1, 62), DWMaskValues.Hi1)); 5106 dag Swap2 = (OR8 (AND8 (RLDICL Swap1, 62, 2), DWMaskValues.Lo2), 5107 (AND8 (RLDICR Swap1, 2, 61), DWMaskValues.Hi2)); 5108 dag Swap4 = (OR8 (AND8 (RLDICL Swap2, 60, 4), DWMaskValues.Lo4), 5109 (AND8 (RLDICR Swap2, 4, 59), DWMaskValues.Hi4)); 5110} 5111 5112// Intra-byte swap is done, now start inter-byte swap. 5113def DWBytes4567 { 5114 dag Word = (i32 (EXTRACT_SUBREG DWSwapInByte.Swap4, sub_32)); 5115} 5116 5117def DWBytes7456 { 5118 dag Word = (RLWINM DWBytes4567.Word, 24, 0, 31); 5119} 5120 5121def DWBytes7656 { 5122 dag Word = (RLWIMI DWBytes7456.Word, DWBytes4567.Word, 8, 8, 15); 5123} 5124 5125// B7 B6 B5 B4 in the right order 5126def DWBytes7654 { 5127 dag Word = (RLWIMI DWBytes7656.Word, DWBytes4567.Word, 8, 24, 31); 5128 dag DWord = 5129 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5130} 5131 5132def DWBytes0123 { 5133 dag Word = (i32 (EXTRACT_SUBREG (RLDICL DWSwapInByte.Swap4, 32, 32), sub_32)); 5134} 5135 5136def DWBytes3012 { 5137 dag Word = (RLWINM DWBytes0123.Word, 24, 0, 31); 5138} 5139 5140def DWBytes3212 { 5141 dag Word = (RLWIMI DWBytes3012.Word, DWBytes0123.Word, 8, 8, 15); 5142} 5143 5144// B3 B2 B1 B0 in the right order 5145def DWBytes3210 { 5146 dag Word = (RLWIMI DWBytes3212.Word, DWBytes0123.Word, 8, 24, 31); 5147 dag DWord = 5148 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5149} 5150 5151// Now both high word and low word are reversed, next 5152// swap the high word and low word. 5153def : Pat<(i64 (bitreverse i64:$A)), 5154 (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>; 5155