1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the subset of the 32-bit PowerPC instruction set, as used 10// by the PowerPC instruction selector. 11// 12//===----------------------------------------------------------------------===// 13 14include "PPCInstrFormats.td" 15 16//===----------------------------------------------------------------------===// 17// PowerPC specific type constraints. 18// 19def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 20 SDTCisVT<0, f64>, SDTCisPtrTy<1> 21]>; 22def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x 23 SDTCisVT<0, f64>, SDTCisPtrTy<1> 24]>; 25def SDT_PPCLxsizx : SDTypeProfile<1, 2, [ 26 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 27]>; 28def SDT_PPCstxsix : SDTypeProfile<0, 3, [ 29 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 30]>; 31def SDT_PPCcv_fp_to_int : SDTypeProfile<1, 1, [ 32 SDTCisFP<0>, SDTCisFP<1> 33 ]>; 34def SDT_PPCstore_scal_int_from_vsr : SDTypeProfile<0, 3, [ 35 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 36]>; 37def SDT_PPCVexts : SDTypeProfile<1, 2, [ 38 SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2> 39]>; 40 41def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 42 SDTCisVT<1, i32> ]>; 43def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 44 SDTCisVT<1, i32> ]>; 45def SDT_PPCvperm : SDTypeProfile<1, 3, [ 46 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 47]>; 48 49def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>, 50 SDTCisVec<1>, SDTCisInt<2> 51]>; 52 53def SDT_PPCSpToDp : SDTypeProfile<1, 1, [ SDTCisVT<0, v2f64>, 54 SDTCisInt<1> 55]>; 56 57def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>, 58 SDTCisVec<1>, SDTCisVec<2>, SDTCisPtrTy<3> 59]>; 60 61def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>, 62 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 63]>; 64 65def SDT_PPCxxpermdi: SDTypeProfile<1, 3, [ SDTCisVec<0>, 66 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 67]>; 68 69def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 70 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 71]>; 72 73def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 74 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 75]>; 76 77def SDT_PPCFtsqrt : SDTypeProfile<1, 1, [ 78 SDTCisVT<0, i32>]>; 79 80def SDT_PPClbrx : SDTypeProfile<1, 2, [ 81 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 82]>; 83def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 84 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 85]>; 86 87def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 88 SDTCisPtrTy<0>, SDTCisVT<1, i32> 89]>; 90 91def tocentry32 : Operand<iPTR> { 92 let MIOperandInfo = (ops i32imm:$imm); 93} 94 95def SDT_PPCqvfperm : SDTypeProfile<1, 3, [ 96 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3> 97]>; 98def SDT_PPCqvgpci : SDTypeProfile<1, 1, [ 99 SDTCisVec<0>, SDTCisInt<1> 100]>; 101def SDT_PPCqvaligni : SDTypeProfile<1, 3, [ 102 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3> 103]>; 104def SDT_PPCqvesplati : SDTypeProfile<1, 2, [ 105 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2> 106]>; 107 108def SDT_PPCqbflt : SDTypeProfile<1, 1, [ 109 SDTCisVec<0>, SDTCisVec<1> 110]>; 111 112def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [ 113 SDTCisVec<0>, SDTCisPtrTy<1> 114]>; 115 116def SDT_PPCextswsli : SDTypeProfile<1, 2, [ // extswsli 117 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisInt<2> 118]>; 119 120def SDT_PPCFPMinMax : SDTypeProfile<1, 2, [ 121 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 122]>; 123 124//===----------------------------------------------------------------------===// 125// PowerPC specific DAG Nodes. 126// 127 128def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>; 129def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>; 130def PPCfsqrt : SDNode<"PPCISD::FSQRT", SDTFPUnaryOp, []>; 131def PPCftsqrt : SDNode<"PPCISD::FTSQRT", SDT_PPCFtsqrt,[]>; 132 133def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; 134def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; 135def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>; 136def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>; 137def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 138def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 139def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>; 140def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>; 141 142def PPCstrict_fcfid : SDNode<"PPCISD::STRICT_FCFID", 143 SDTFPUnaryOp, [SDNPHasChain]>; 144def PPCstrict_fcfidu : SDNode<"PPCISD::STRICT_FCFIDU", 145 SDTFPUnaryOp, [SDNPHasChain]>; 146def PPCstrict_fcfids : SDNode<"PPCISD::STRICT_FCFIDS", 147 SDTFPRoundOp, [SDNPHasChain]>; 148def PPCstrict_fcfidus : SDNode<"PPCISD::STRICT_FCFIDUS", 149 SDTFPRoundOp, [SDNPHasChain]>; 150 151def PPCany_fcfid : PatFrags<(ops node:$op), 152 [(PPCfcfid node:$op), 153 (PPCstrict_fcfid node:$op)]>; 154def PPCany_fcfidu : PatFrags<(ops node:$op), 155 [(PPCfcfidu node:$op), 156 (PPCstrict_fcfidu node:$op)]>; 157def PPCany_fcfids : PatFrags<(ops node:$op), 158 [(PPCfcfids node:$op), 159 (PPCstrict_fcfids node:$op)]>; 160def PPCany_fcfidus : PatFrags<(ops node:$op), 161 [(PPCfcfidus node:$op), 162 (PPCstrict_fcfidus node:$op)]>; 163 164def PPCcv_fp_to_uint_in_vsr: 165 SDNode<"PPCISD::FP_TO_UINT_IN_VSR", SDT_PPCcv_fp_to_int, []>; 166def PPCcv_fp_to_sint_in_vsr: 167 SDNode<"PPCISD::FP_TO_SINT_IN_VSR", SDT_PPCcv_fp_to_int, []>; 168def PPCstore_scal_int_from_vsr: 169 SDNode<"PPCISD::ST_VSR_SCAL_INT", SDT_PPCstore_scal_int_from_vsr, 170 [SDNPHasChain, SDNPMayStore]>; 171def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 172 [SDNPHasChain, SDNPMayStore]>; 173def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx, 174 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 175def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx, 176 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 177def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx, 178 [SDNPHasChain, SDNPMayLoad]>; 179def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix, 180 [SDNPHasChain, SDNPMayStore]>; 181def PPCVexts : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>; 182 183// Extract FPSCR (not modeled at the DAG level). 184def PPCmffs : SDNode<"PPCISD::MFFS", 185 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 186 [SDNPHasChain]>; 187 188// Perform FADD in round-to-zero mode. 189def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>; 190def PPCstrict_faddrtz: SDNode<"PPCISD::STRICT_FADDRTZ", SDTFPBinOp, 191 [SDNPHasChain]>; 192 193def PPCany_faddrtz: PatFrags<(ops node:$lhs, node:$rhs), 194 [(PPCfaddrtz node:$lhs, node:$rhs), 195 (PPCstrict_faddrtz node:$lhs, node:$rhs)]>; 196 197def PPCfsel : SDNode<"PPCISD::FSEL", 198 // Type constraint for fsel. 199 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 200 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 201def PPCxsmaxc : SDNode<"PPCISD::XSMAXC", SDT_PPCFPMinMax, []>; 202def PPCxsminc : SDNode<"PPCISD::XSMINC", SDT_PPCFPMinMax, []>; 203def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 204def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 205def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, 206 [SDNPMayLoad, SDNPMemOperand]>; 207 208def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>; 209 210def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 211def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 212 [SDNPMayLoad]>; 213def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 214def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 215def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 216def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 217def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR", 218 SDTypeProfile<1, 3, [ 219 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 220 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 221def PPCTlsgdAIX : SDNode<"PPCISD::TLSGD_AIX", SDTIntBinOp>; 222def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 223def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 224def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 225def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR", 226 SDTypeProfile<1, 3, [ 227 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 228 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 229def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>; 230def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 231def PPCpaddiDtprel : SDNode<"PPCISD::PADDI_DTPREL", SDTIntBinOp>; 232 233def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 234def PPCxxsplt : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>; 235def PPCxxspltidp : SDNode<"PPCISD::XXSPLTI_SP_TO_DP", SDT_PPCSpToDp, []>; 236def PPCvecinsert : SDNode<"PPCISD::VECINSERT", SDT_PPCVecInsert, []>; 237def PPCxxpermdi : SDNode<"PPCISD::XXPERMDI", SDT_PPCxxpermdi, []>; 238def PPCvecshl : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>; 239 240def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>; 241 242// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 243// amounts. These nodes are generated by the multi-precision shift code. 244def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 245def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 246def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 247 248def PPCfnmsub : SDNode<"PPCISD::FNMSUB" , SDTFPTernaryOp>; 249 250def PPCextswsli : SDNode<"PPCISD::EXTSWSLI" , SDT_PPCextswsli>; 251 252def PPCstrict_fctidz : SDNode<"PPCISD::STRICT_FCTIDZ", 253 SDTFPUnaryOp, [SDNPHasChain]>; 254def PPCstrict_fctiwz : SDNode<"PPCISD::STRICT_FCTIWZ", 255 SDTFPUnaryOp, [SDNPHasChain]>; 256def PPCstrict_fctiduz : SDNode<"PPCISD::STRICT_FCTIDUZ", 257 SDTFPUnaryOp, [SDNPHasChain]>; 258def PPCstrict_fctiwuz : SDNode<"PPCISD::STRICT_FCTIWUZ", 259 SDTFPUnaryOp, [SDNPHasChain]>; 260 261def PPCany_fctidz : PatFrags<(ops node:$op), 262 [(PPCstrict_fctidz node:$op), 263 (PPCfctidz node:$op)]>; 264def PPCany_fctiwz : PatFrags<(ops node:$op), 265 [(PPCstrict_fctiwz node:$op), 266 (PPCfctiwz node:$op)]>; 267def PPCany_fctiduz : PatFrags<(ops node:$op), 268 [(PPCstrict_fctiduz node:$op), 269 (PPCfctiduz node:$op)]>; 270def PPCany_fctiwuz : PatFrags<(ops node:$op), 271 [(PPCstrict_fctiwuz node:$op), 272 (PPCfctiwuz node:$op)]>; 273 274// Move 2 i64 values into a VSX register 275def PPCbuild_fp128: SDNode<"PPCISD::BUILD_FP128", 276 SDTypeProfile<1, 2, 277 [SDTCisFP<0>, SDTCisSameSizeAs<1,2>, 278 SDTCisSameAs<1,2>]>, 279 []>; 280 281def PPCbuild_spe64: SDNode<"PPCISD::BUILD_SPE64", 282 SDTypeProfile<1, 2, 283 [SDTCisVT<0, f64>, SDTCisVT<1,i32>, 284 SDTCisVT<1,i32>]>, 285 []>; 286 287def PPCextract_spe : SDNode<"PPCISD::EXTRACT_SPE", 288 SDTypeProfile<1, 2, 289 [SDTCisVT<0, i32>, SDTCisVT<1, f64>, 290 SDTCisPtrTy<2>]>, 291 []>; 292 293// These are target-independent nodes, but have target-specific formats. 294def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 295 [SDNPHasChain, SDNPOutGlue]>; 296def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 297 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 298 299def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 300def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 301 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 302 SDNPVariadic]>; 303def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall, 304 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 305 SDNPVariadic]>; 306def PPCcall_notoc : SDNode<"PPCISD::CALL_NOTOC", SDT_PPCCall, 307 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 308 SDNPVariadic]>; 309def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 310 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 311def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone, 312 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 313 SDNPVariadic]>; 314def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC", 315 SDTypeProfile<0, 1, []>, 316 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 317 SDNPVariadic]>; 318 319// Call nodes for strictfp calls (that define RM). 320def PPCcall_rm : SDNode<"PPCISD::CALL_RM", SDT_PPCCall, 321 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 322 SDNPVariadic]>; 323def PPCcall_nop_rm : SDNode<"PPCISD::CALL_NOP_RM", SDT_PPCCall, 324 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 325 SDNPVariadic]>; 326def PPCcall_notoc_rm : SDNode<"PPCISD::CALL_NOTOC_RM", SDT_PPCCall, 327 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 328 SDNPVariadic]>; 329def PPCbctrl_rm : SDNode<"PPCISD::BCTRL_RM", SDTNone, 330 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 331 SDNPVariadic]>; 332def PPCbctrl_load_toc_rm : SDNode<"PPCISD::BCTRL_LOAD_TOC_RM", 333 SDTypeProfile<0, 1, []>, 334 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 335 SDNPVariadic]>; 336 337def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 338 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 339 340def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 341 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 342 343def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP", 344 SDTypeProfile<1, 1, [SDTCisInt<0>, 345 SDTCisPtrTy<1>]>, 346 [SDNPHasChain, SDNPSideEffect]>; 347def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP", 348 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 349 [SDNPHasChain, SDNPSideEffect]>; 350 351def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 352def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc, 353 [SDNPHasChain, SDNPSideEffect]>; 354 355def PPCclrbhrb : SDNode<"PPCISD::CLRBHRB", SDTNone, 356 [SDNPHasChain, SDNPSideEffect]>; 357def PPCmfbhrbe : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>; 358def PPCrfebb : SDNode<"PPCISD::RFEBB", SDT_PPCsc, 359 [SDNPHasChain, SDNPSideEffect]>; 360 361def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 362def PPCvcmp_rec : SDNode<"PPCISD::VCMP_rec", SDT_PPCvcmp, [SDNPOutGlue]>; 363 364def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 365 [SDNPHasChain, SDNPOptInGlue]>; 366 367// PPC-specific atomic operations. 368def PPCatomicCmpSwap_8 : 369 SDNode<"PPCISD::ATOMIC_CMP_SWAP_8", SDTAtomic3, 370 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 371def PPCatomicCmpSwap_16 : 372 SDNode<"PPCISD::ATOMIC_CMP_SWAP_16", SDTAtomic3, 373 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 374def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 375 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 376def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 377 [SDNPHasChain, SDNPMayStore]>; 378 379// Instructions to set/unset CR bit 6 for SVR4 vararg calls 380def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 381 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 382def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 383 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 384 385// Instructions to support dynamic alloca. 386def SDTDynOp : SDTypeProfile<1, 2, []>; 387def SDTDynAreaOp : SDTypeProfile<1, 1, []>; 388def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 389def PPCdynareaoffset : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>; 390def PPCprobedalloca : SDNode<"PPCISD::PROBED_ALLOCA", SDTDynOp, [SDNPHasChain]>; 391 392// PC Relative Specific Nodes 393def PPCmatpcreladdr : SDNode<"PPCISD::MAT_PCREL_ADDR", SDTIntUnaryOp, []>; 394def PPCtlsdynamatpcreladdr : SDNode<"PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR", 395 SDTIntUnaryOp, []>; 396def PPCtlslocalexecmataddr : SDNode<"PPCISD::TLS_LOCAL_EXEC_MAT_ADDR", 397 SDTIntUnaryOp, []>; 398 399//===----------------------------------------------------------------------===// 400// PowerPC specific transformation functions and pattern fragments. 401// 402 403// A floating point immediate that is not a positive zero and can be converted 404// to a single precision floating point non-denormal immediate without loss of 405// information. 406def nzFPImmAsi32 : PatLeaf<(fpimm), [{ 407 APFloat APFloatOfN = N->getValueAPF(); 408 return convertToNonDenormSingle(APFloatOfN) && !N->isExactlyValue(+0.0); 409}]>; 410 411// Convert the floating point immediate into a 32 bit floating point immediate 412// and get a i32 with the resulting bits. 413def getFPAs32BitInt : SDNodeXForm<fpimm, [{ 414 APFloat APFloatOfN = N->getValueAPF(); 415 convertToNonDenormSingle(APFloatOfN); 416 return CurDAG->getTargetConstant(APFloatOfN.bitcastToAPInt().getZExtValue(), 417 SDLoc(N), MVT::i32); 418}]>; 419 420// Check if the value can be converted to be single precision immediate, which 421// can be exploited by XXSPLTIDP. Ensure that it cannot be converted to single 422// precision before exploiting with XXSPLTI32DX. 423def nzFPImmAsi64 : PatLeaf<(fpimm), [{ 424 APFloat APFloatOfN = N->getValueAPF(); 425 return !N->isExactlyValue(+0.0) && !checkConvertToNonDenormSingle(APFloatOfN); 426}]>; 427 428// Get the Hi bits of a 64 bit immediate. 429def getFPAs64BitIntHi : SDNodeXForm<fpimm, [{ 430 APFloat APFloatOfN = N->getValueAPF(); 431 bool Unused; 432 APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 433 &Unused); 434 uint32_t Hi = (uint32_t)((APFloatOfN.bitcastToAPInt().getZExtValue() & 435 0xFFFFFFFF00000000LL) >> 32); 436 return CurDAG->getTargetConstant(Hi, SDLoc(N), MVT::i32); 437}]>; 438 439// Get the Lo bits of a 64 bit immediate. 440def getFPAs64BitIntLo : SDNodeXForm<fpimm, [{ 441 APFloat APFloatOfN = N->getValueAPF(); 442 bool Unused; 443 APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 444 &Unused); 445 uint32_t Lo = (uint32_t)(APFloatOfN.bitcastToAPInt().getZExtValue() & 446 0xFFFFFFFF); 447 return CurDAG->getTargetConstant(Lo, SDLoc(N), MVT::i32); 448}]>; 449 450def imm34 : PatLeaf<(imm), [{ 451 return isInt<34>(N->getSExtValue()); 452}]>; 453 454def getImmAs64BitInt : SDNodeXForm<imm, [{ 455 return getI64Imm(N->getSExtValue(), SDLoc(N)); 456}]>; 457 458def SHL32 : SDNodeXForm<imm, [{ 459 // Transformation function: 31 - imm 460 return getI32Imm(31 - N->getZExtValue(), SDLoc(N)); 461}]>; 462 463def SRL32 : SDNodeXForm<imm, [{ 464 // Transformation function: 32 - imm 465 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N)) 466 : getI32Imm(0, SDLoc(N)); 467}]>; 468 469def LO16 : SDNodeXForm<imm, [{ 470 // Transformation function: get the low 16 bits. 471 return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N)); 472}]>; 473 474def HI16 : SDNodeXForm<imm, [{ 475 // Transformation function: shift the immediate value down into the low bits. 476 return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N)); 477}]>; 478 479def HA16 : SDNodeXForm<imm, [{ 480 // Transformation function: shift the immediate value down into the low bits. 481 long Val = N->getZExtValue(); 482 return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N)); 483}]>; 484def MB : SDNodeXForm<imm, [{ 485 // Transformation function: get the start bit of a mask 486 unsigned mb = 0, me; 487 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 488 return getI32Imm(mb, SDLoc(N)); 489}]>; 490 491def ME : SDNodeXForm<imm, [{ 492 // Transformation function: get the end bit of a mask 493 unsigned mb, me = 0; 494 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 495 return getI32Imm(me, SDLoc(N)); 496}]>; 497def maskimm32 : PatLeaf<(imm), [{ 498 // maskImm predicate - True if immediate is a run of ones. 499 unsigned mb, me; 500 if (N->getValueType(0) == MVT::i32) 501 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 502 else 503 return false; 504}]>; 505 506def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{ 507 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit 508 // sign extended field. Used by instructions like 'addi'. 509 return (int32_t)Imm == (short)Imm; 510}]>; 511def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{ 512 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit 513 // sign extended field. Used by instructions like 'addi'. 514 return (int64_t)Imm == (short)Imm; 515}]>; 516def immZExt16 : PatLeaf<(imm), [{ 517 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 518 // field. Used by instructions like 'ori'. 519 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 520}], LO16>; 521def immNonAllOneAnyExt8 : ImmLeaf<i32, [{ 522 return (isInt<8>(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF)); 523}]>; 524def i32immNonAllOneNonZero : ImmLeaf<i32, [{ return Imm && (Imm != -1); }]>; 525def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>; 526 527// imm16Shifted* - These match immediates where the low 16-bits are zero. There 528// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 529// identical in 32-bit mode, but in 64-bit mode, they return true if the 530// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 531// clear). 532def imm16ShiftedZExt : PatLeaf<(imm), [{ 533 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 534 // immediate are set. Used by instructions like 'xoris'. 535 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 536}], HI16>; 537 538def imm16ShiftedSExt : PatLeaf<(imm), [{ 539 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 540 // immediate are set. Used by instructions like 'addis'. Identical to 541 // imm16ShiftedZExt in 32-bit mode. 542 if (N->getZExtValue() & 0xFFFF) return false; 543 if (N->getValueType(0) == MVT::i32) 544 return true; 545 // For 64-bit, make sure it is sext right. 546 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 547}], HI16>; 548 549def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{ 550 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit 551 // zero extended field. 552 return isUInt<32>(Imm); 553}]>; 554 555// This is a somewhat weaker condition than actually checking for 4-byte 556// alignment. It is simply checking that the displacement can be represented 557// as an immediate that is a multiple of 4 (i.e. the requirements for DS-Form 558// instructions). 559// But some r+i load/store instructions (such as LD, STD, LDU, etc.) that require 560// restricted memrix (4-aligned) constants are alignment sensitive. If these 561// offsets are hidden behind TOC entries than the values of the lower-order 562// bits cannot be checked directly. As a result, we need to also incorporate 563// an alignment check into the relevant patterns. 564 565def DSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 566 return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlignment() >= 4; 567}]>; 568def DSFormStore : PatFrag<(ops node:$val, node:$ptr), 569 (store node:$val, node:$ptr), [{ 570 return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlignment() >= 4; 571}]>; 572def DSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 573 return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlignment() >= 4; 574}]>; 575def DSFormPreStore : PatFrag< 576 (ops node:$val, node:$base, node:$offset), 577 (pre_store node:$val, node:$base, node:$offset), [{ 578 return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlignment() >= 4; 579}]>; 580 581def NonDSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 582 return cast<LoadSDNode>(N)->getAlignment() < 4 && !isOffsetMultipleOf(N, 4); 583}]>; 584def NonDSFormStore : PatFrag<(ops node:$val, node:$ptr), 585 (store node:$val, node:$ptr), [{ 586 return cast<StoreSDNode>(N)->getAlignment() < 4 && !isOffsetMultipleOf(N, 4); 587}]>; 588def NonDSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 589 return cast<LoadSDNode>(N)->getAlignment() < 4 && !isOffsetMultipleOf(N, 4); 590}]>; 591 592// This is a somewhat weaker condition than actually checking for 16-byte 593// alignment. It is simply checking that the displacement can be represented 594// as an immediate that is a multiple of 16 (i.e. the requirements for DQ-Form 595// instructions). 596def quadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 597 return isOffsetMultipleOf(N, 16); 598}]>; 599def quadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 600 (store node:$val, node:$ptr), [{ 601 return isOffsetMultipleOf(N, 16); 602}]>; 603def nonQuadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 604 return !isOffsetMultipleOf(N, 16); 605}]>; 606def nonQuadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 607 (store node:$val, node:$ptr), [{ 608 return !isOffsetMultipleOf(N, 16); 609}]>; 610 611// PatFrag for binary operation whose operands are both non-constant 612class BinOpWithoutSImm16Operand<SDNode opcode> : 613 PatFrag<(ops node:$left, node:$right), (opcode node:$left, node:$right), [{ 614 int16_t Imm; 615 return !isIntS16Immediate(N->getOperand(0), Imm) 616 && !isIntS16Immediate(N->getOperand(1), Imm); 617}]>; 618 619def add_without_simm16 : BinOpWithoutSImm16Operand<add>; 620def mul_without_simm16 : BinOpWithoutSImm16Operand<mul>; 621 622//===----------------------------------------------------------------------===// 623// PowerPC Flag Definitions. 624 625class isPPC64 { bit PPC64 = 1; } 626class isRecordForm { bit RC = 1; } 627 628class RegConstraint<string C> { 629 string Constraints = C; 630} 631class NoEncode<string E> { 632 string DisableEncoding = E; 633} 634 635 636// Define PowerPC specific addressing mode. 637 638// d-form 639def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; // "stb" 640// ds-form 641def iaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std" 642// dq-form 643def iaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrImmX16", [], []>; // "stxv" 644// 8LS:d-form 645def iaddrX34 : ComplexPattern<iPTR, 2, "SelectAddrImmX34", [], []>; // "pstxvp" 646 647// Below forms are all x-form addressing mode, use three different ones so we 648// can make a accurate check for x-form instructions in ISEL. 649// x-form addressing mode whose associated displacement form is D. 650def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; // "stbx" 651// x-form addressing mode whose associated displacement form is DS. 652def xaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrIdxX4", [], []>; // "stdx" 653// x-form addressing mode whose associated displacement form is DQ. 654def xaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrIdxX16", [], []>; // "stxvx" 655 656def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 657 658// The address in a single register. This is used with the SjLj 659// pseudo-instructions. 660def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>; 661 662/// This is just the offset part of iaddr, used for preinc. 663def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 664 665// Load and Store Instruction Selection addressing modes. 666def DForm : ComplexPattern<iPTR, 2, "SelectDForm", [], [SDNPWantParent]>; 667def DSForm : ComplexPattern<iPTR, 2, "SelectDSForm", [], [SDNPWantParent]>; 668def DQForm : ComplexPattern<iPTR, 2, "SelectDQForm", [], [SDNPWantParent]>; 669def XForm : ComplexPattern<iPTR, 2, "SelectXForm", [], [SDNPWantParent]>; 670def ForceXForm : ComplexPattern<iPTR, 2, "SelectForceXForm", [], [SDNPWantParent]>; 671def PCRelForm : ComplexPattern<iPTR, 2, "SelectPCRelForm", [], [SDNPWantParent]>; 672def PDForm : ComplexPattern<iPTR, 2, "SelectPDForm", [], [SDNPWantParent]>; 673 674//===----------------------------------------------------------------------===// 675// PowerPC Instruction Predicate Definitions. 676def In32BitMode : Predicate<"!Subtarget->isPPC64()">; 677def In64BitMode : Predicate<"Subtarget->isPPC64()">; 678def IsBookE : Predicate<"Subtarget->isBookE()">; 679def IsNotBookE : Predicate<"!Subtarget->isBookE()">; 680def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">; 681def HasSYNC : Predicate<"!Subtarget->hasOnlyMSYNC()">; 682def IsPPC4xx : Predicate<"Subtarget->isPPC4xx()">; 683def IsPPC6xx : Predicate<"Subtarget->isPPC6xx()">; 684def IsE500 : Predicate<"Subtarget->isE500()">; 685def HasSPE : Predicate<"Subtarget->hasSPE()">; 686def HasICBT : Predicate<"Subtarget->hasICBT()">; 687def HasPartwordAtomics : Predicate<"Subtarget->hasPartwordAtomics()">; 688def HasQuadwordAtomics : Predicate<"Subtarget->hasQuadwordAtomics()">; 689def NoNaNsFPMath 690 : Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">; 691def NaNsFPMath 692 : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">; 693def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">; 694def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">; 695def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">; 696def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">; 697def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">; 698def HasFPU : Predicate<"Subtarget->hasFPU()">; 699def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">; 700def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">; 701 702// AIX assembler may not be modern enough to support some extended mne. 703def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">, 704 AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>; 705def IsAIX : Predicate<"Subtarget->isAIXABI()">; 706def NotAIX : Predicate<"!Subtarget->isAIXABI()">; 707 708//===----------------------------------------------------------------------===// 709// PowerPC Multiclass Definitions. 710 711multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 712 string asmbase, string asmstr, InstrItinClass itin, 713 list<dag> pattern> { 714 let BaseName = asmbase in { 715 def NAME : XForm_6<opcode, xo, OOL, IOL, 716 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 717 pattern>, RecFormRel; 718 let Defs = [CR0] in 719 def _rec : XForm_6<opcode, xo, OOL, IOL, 720 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 721 []>, isRecordForm, RecFormRel; 722 } 723} 724 725multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 726 string asmbase, string asmstr, InstrItinClass itin, 727 list<dag> pattern> { 728 let BaseName = asmbase in { 729 let Defs = [CARRY] in 730 def NAME : XForm_6<opcode, xo, OOL, IOL, 731 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 732 pattern>, RecFormRel; 733 let Defs = [CARRY, CR0] in 734 def _rec : XForm_6<opcode, xo, OOL, IOL, 735 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 736 []>, isRecordForm, RecFormRel; 737 } 738} 739 740multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 741 string asmbase, string asmstr, InstrItinClass itin, 742 list<dag> pattern> { 743 let BaseName = asmbase in { 744 let Defs = [CARRY] in 745 def NAME : XForm_10<opcode, xo, OOL, IOL, 746 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 747 pattern>, RecFormRel; 748 let Defs = [CARRY, CR0] in 749 def _rec : XForm_10<opcode, xo, OOL, IOL, 750 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 751 []>, isRecordForm, RecFormRel; 752 } 753} 754 755multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 756 string asmbase, string asmstr, InstrItinClass itin, 757 list<dag> pattern> { 758 let BaseName = asmbase in { 759 def NAME : XForm_11<opcode, xo, OOL, IOL, 760 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 761 pattern>, RecFormRel; 762 let Defs = [CR0] in 763 def _rec : XForm_11<opcode, xo, OOL, IOL, 764 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 765 []>, isRecordForm, RecFormRel; 766 } 767} 768 769multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 770 string asmbase, string asmstr, InstrItinClass itin, 771 list<dag> pattern> { 772 let BaseName = asmbase in { 773 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 774 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 775 pattern>, RecFormRel; 776 let Defs = [CR0] in 777 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 778 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 779 []>, isRecordForm, RecFormRel; 780 } 781} 782 783// Multiclass for instructions which have a record overflow form as well 784// as a record form but no carry (i.e. mulld, mulldo, subf, subfo, etc.) 785multiclass XOForm_1rx<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 786 string asmbase, string asmstr, InstrItinClass itin, 787 list<dag> pattern> { 788 let BaseName = asmbase in { 789 def NAME : XOForm_1<opcode, xo, 0, OOL, IOL, 790 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 791 pattern>, RecFormRel; 792 let Defs = [CR0] in 793 def _rec : XOForm_1<opcode, xo, 0, OOL, IOL, 794 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 795 []>, isRecordForm, RecFormRel; 796 } 797 let BaseName = !strconcat(asmbase, "O") in { 798 let Defs = [XER] in 799 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 800 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 801 []>, RecFormRel; 802 let Defs = [XER, CR0] in 803 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 804 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 805 []>, isRecordForm, RecFormRel; 806 } 807} 808 809// Multiclass for instructions for which the non record form is not cracked 810// and the record form is cracked (i.e. divw, mullw, etc.) 811multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 812 string asmbase, string asmstr, InstrItinClass itin, 813 list<dag> pattern> { 814 let BaseName = asmbase in { 815 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 816 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 817 pattern>, RecFormRel; 818 let Defs = [CR0] in 819 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 820 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 821 []>, isRecordForm, RecFormRel, PPC970_DGroup_First, 822 PPC970_DGroup_Cracked; 823 } 824 let BaseName = !strconcat(asmbase, "O") in { 825 let Defs = [XER] in 826 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 827 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 828 []>, RecFormRel; 829 let Defs = [XER, CR0] in 830 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 831 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 832 []>, isRecordForm, RecFormRel; 833 } 834} 835 836multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 837 string asmbase, string asmstr, InstrItinClass itin, 838 list<dag> pattern> { 839 let BaseName = asmbase in { 840 let Defs = [CARRY] in 841 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 842 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 843 pattern>, RecFormRel; 844 let Defs = [CARRY, CR0] in 845 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 846 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 847 []>, isRecordForm, RecFormRel; 848 } 849 let BaseName = !strconcat(asmbase, "O") in { 850 let Defs = [CARRY, XER] in 851 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 852 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 853 []>, RecFormRel; 854 let Defs = [CARRY, XER, CR0] in 855 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 856 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 857 []>, isRecordForm, RecFormRel; 858 } 859} 860 861multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 862 string asmbase, string asmstr, InstrItinClass itin, 863 list<dag> pattern> { 864 let BaseName = asmbase in { 865 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 866 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 867 pattern>, RecFormRel; 868 let Defs = [CR0] in 869 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 870 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 871 []>, isRecordForm, RecFormRel; 872 } 873 let BaseName = !strconcat(asmbase, "O") in { 874 let Defs = [XER] in 875 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 876 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 877 []>, RecFormRel; 878 let Defs = [XER, CR0] in 879 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 880 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 881 []>, isRecordForm, RecFormRel; 882 } 883} 884 885multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 886 string asmbase, string asmstr, InstrItinClass itin, 887 list<dag> pattern> { 888 let BaseName = asmbase in { 889 let Defs = [CARRY] in 890 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 891 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 892 pattern>, RecFormRel; 893 let Defs = [CARRY, CR0] in 894 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 895 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 896 []>, isRecordForm, RecFormRel; 897 } 898 let BaseName = !strconcat(asmbase, "O") in { 899 let Defs = [CARRY, XER] in 900 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 901 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 902 []>, RecFormRel; 903 let Defs = [CARRY, XER, CR0] in 904 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 905 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 906 []>, isRecordForm, RecFormRel; 907 } 908} 909 910multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL, 911 string asmbase, string asmstr, InstrItinClass itin, 912 list<dag> pattern> { 913 let BaseName = asmbase in { 914 def NAME : MForm_2<opcode, OOL, IOL, 915 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 916 pattern>, RecFormRel; 917 let Defs = [CR0] in 918 def _rec : MForm_2<opcode, OOL, IOL, 919 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 920 []>, isRecordForm, RecFormRel; 921 } 922} 923 924multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 925 string asmbase, string asmstr, InstrItinClass itin, 926 list<dag> pattern> { 927 let BaseName = asmbase in { 928 def NAME : MDForm_1<opcode, xo, OOL, IOL, 929 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 930 pattern>, RecFormRel; 931 let Defs = [CR0] in 932 def _rec : MDForm_1<opcode, xo, OOL, IOL, 933 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 934 []>, isRecordForm, RecFormRel; 935 } 936} 937 938multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 939 string asmbase, string asmstr, InstrItinClass itin, 940 list<dag> pattern> { 941 let BaseName = asmbase in { 942 def NAME : MDSForm_1<opcode, xo, OOL, IOL, 943 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 944 pattern>, RecFormRel; 945 let Defs = [CR0] in 946 def _rec : MDSForm_1<opcode, xo, OOL, IOL, 947 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 948 []>, isRecordForm, RecFormRel; 949 } 950} 951 952multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 953 string asmbase, string asmstr, InstrItinClass itin, 954 list<dag> pattern> { 955 let BaseName = asmbase in { 956 let Defs = [CARRY] in 957 def NAME : XSForm_1<opcode, xo, OOL, IOL, 958 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 959 pattern>, RecFormRel; 960 let Defs = [CARRY, CR0] in 961 def _rec : XSForm_1<opcode, xo, OOL, IOL, 962 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 963 []>, isRecordForm, RecFormRel; 964 } 965} 966 967multiclass XSForm_1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 968 string asmbase, string asmstr, InstrItinClass itin, 969 list<dag> pattern> { 970 let BaseName = asmbase in { 971 def NAME : XSForm_1<opcode, xo, OOL, IOL, 972 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 973 pattern>, RecFormRel; 974 let Defs = [CR0] in 975 def _rec : XSForm_1<opcode, xo, OOL, IOL, 976 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 977 []>, isRecordForm, RecFormRel; 978 } 979} 980 981multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 982 string asmbase, string asmstr, InstrItinClass itin, 983 list<dag> pattern> { 984 let BaseName = asmbase in { 985 def NAME : XForm_26<opcode, xo, OOL, IOL, 986 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 987 pattern>, RecFormRel; 988 let Defs = [CR1] in 989 def _rec : XForm_26<opcode, xo, OOL, IOL, 990 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 991 []>, isRecordForm, RecFormRel; 992 } 993} 994 995multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 996 string asmbase, string asmstr, InstrItinClass itin, 997 list<dag> pattern> { 998 let BaseName = asmbase in { 999 def NAME : XForm_28<opcode, xo, OOL, IOL, 1000 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1001 pattern>, RecFormRel; 1002 let Defs = [CR1] in 1003 def _rec : XForm_28<opcode, xo, OOL, IOL, 1004 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1005 []>, isRecordForm, RecFormRel; 1006 } 1007} 1008 1009multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1010 string asmbase, string asmstr, InstrItinClass itin, 1011 list<dag> pattern> { 1012 let BaseName = asmbase in { 1013 def NAME : AForm_1<opcode, xo, OOL, IOL, 1014 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1015 pattern>, RecFormRel; 1016 let Defs = [CR1] in 1017 def _rec : AForm_1<opcode, xo, OOL, IOL, 1018 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1019 []>, isRecordForm, RecFormRel; 1020 } 1021} 1022 1023multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1024 string asmbase, string asmstr, InstrItinClass itin, 1025 list<dag> pattern> { 1026 let BaseName = asmbase in { 1027 def NAME : AForm_2<opcode, xo, OOL, IOL, 1028 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1029 pattern>, RecFormRel; 1030 let Defs = [CR1] in 1031 def _rec : AForm_2<opcode, xo, OOL, IOL, 1032 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1033 []>, isRecordForm, RecFormRel; 1034 } 1035} 1036 1037multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1038 string asmbase, string asmstr, InstrItinClass itin, 1039 list<dag> pattern> { 1040 let BaseName = asmbase in { 1041 def NAME : AForm_3<opcode, xo, OOL, IOL, 1042 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1043 pattern>, RecFormRel; 1044 let Defs = [CR1] in 1045 def _rec : AForm_3<opcode, xo, OOL, IOL, 1046 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1047 []>, isRecordForm, RecFormRel; 1048 } 1049} 1050 1051//===----------------------------------------------------------------------===// 1052// PowerPC Instruction Definitions. 1053 1054// Pseudo instructions: 1055 1056let hasCtrlDep = 1 in { 1057let Defs = [R1], Uses = [R1] in { 1058def ADJCALLSTACKDOWN : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1059 "#ADJCALLSTACKDOWN $amt1 $amt2", 1060 [(callseq_start timm:$amt1, timm:$amt2)]>; 1061def ADJCALLSTACKUP : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1062 "#ADJCALLSTACKUP $amt1 $amt2", 1063 [(callseq_end timm:$amt1, timm:$amt2)]>; 1064} 1065} // hasCtrlDep 1066 1067let Defs = [R1], Uses = [R1] in 1068def DYNALLOC : PPCEmitTimePseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC", 1069 [(set i32:$result, 1070 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; 1071def DYNAREAOFFSET : PPCEmitTimePseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET", 1072 [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 1073// Probed alloca to support stack clash protection. 1074let Defs = [R1], Uses = [R1], hasNoSchedulingInfo = 1 in { 1075def PROBED_ALLOCA_32 : PPCCustomInserterPseudo<(outs gprc:$result), 1076 (ins gprc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_32", 1077 [(set i32:$result, 1078 (PPCprobedalloca i32:$negsize, iaddr:$fpsi))]>; 1079def PREPARE_PROBED_ALLOCA_32 : PPCEmitTimePseudo<(outs 1080 gprc:$fp, gprc:$actual_negsize), 1081 (ins gprc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_32", []>; 1082def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 : PPCEmitTimePseudo<(outs 1083 gprc:$fp, gprc:$actual_negsize), 1084 (ins gprc:$negsize, memri:$fpsi), 1085 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32", []>, 1086 RegConstraint<"$actual_negsize = $negsize">; 1087def PROBED_STACKALLOC_32 : PPCEmitTimePseudo<(outs gprc:$scratch, gprc:$temp), 1088 (ins i64imm:$stacksize), 1089 "#PROBED_STACKALLOC_32", []>; 1090} 1091 1092// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 1093// instruction selection into a branch sequence. 1094let PPC970_Single = 1 in { 1095 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes 1096 // because either operand might become the first operand in an isel, and 1097 // that operand cannot be r0. 1098 def SELECT_CC_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crrc:$cond, 1099 gprc_nor0:$T, gprc_nor0:$F, 1100 i32imm:$BROPC), "#SELECT_CC_I4", 1101 []>; 1102 def SELECT_CC_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crrc:$cond, 1103 g8rc_nox0:$T, g8rc_nox0:$F, 1104 i32imm:$BROPC), "#SELECT_CC_I8", 1105 []>; 1106 def SELECT_CC_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F, 1107 i32imm:$BROPC), "#SELECT_CC_F4", 1108 []>; 1109 def SELECT_CC_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F, 1110 i32imm:$BROPC), "#SELECT_CC_F8", 1111 []>; 1112 def SELECT_CC_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1113 i32imm:$BROPC), "#SELECT_CC_F16", 1114 []>; 1115 def SELECT_CC_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1116 i32imm:$BROPC), "#SELECT_CC_VRRC", 1117 []>; 1118 1119 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition 1120 // register bit directly. 1121 def SELECT_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crbitrc:$cond, 1122 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4", 1123 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>; 1124 def SELECT_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crbitrc:$cond, 1125 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8", 1126 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>; 1127let Predicates = [HasFPU] in { 1128 def SELECT_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crbitrc:$cond, 1129 f4rc:$T, f4rc:$F), "#SELECT_F4", 1130 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>; 1131 def SELECT_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crbitrc:$cond, 1132 f8rc:$T, f8rc:$F), "#SELECT_F8", 1133 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>; 1134 def SELECT_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1135 vrrc:$T, vrrc:$F), "#SELECT_F16", 1136 [(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>; 1137} 1138 def SELECT_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1139 vrrc:$T, vrrc:$F), "#SELECT_VRRC", 1140 [(set v4i32:$dst, 1141 (select i1:$cond, v4i32:$T, v4i32:$F))]>; 1142} 1143 1144// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 1145// scavenge a register for it. 1146let mayStore = 1 in { 1147def SPILL_CR : PPCEmitTimePseudo<(outs), (ins crrc:$cond, memri:$F), 1148 "#SPILL_CR", []>; 1149def SPILL_CRBIT : PPCEmitTimePseudo<(outs), (ins crbitrc:$cond, memri:$F), 1150 "#SPILL_CRBIT", []>; 1151} 1152 1153// RESTORE_CR - Indicate that we're restoring the CR register (previously 1154// spilled), so we'll need to scavenge a register for it. 1155let mayLoad = 1 in { 1156def RESTORE_CR : PPCEmitTimePseudo<(outs crrc:$cond), (ins memri:$F), 1157 "#RESTORE_CR", []>; 1158def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F), 1159 "#RESTORE_CRBIT", []>; 1160} 1161 1162let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in { 1163 let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in 1164 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 1165 [(retflag)]>, Requires<[In32BitMode]>; 1166 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { 1167 let isPredicable = 1 in 1168 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1169 []>; 1170 1171 let isCodeGenOnly = 1 in { 1172 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 1173 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 1174 []>; 1175 1176 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 1177 "bcctr 12, $bi, 0", IIC_BrB, []>; 1178 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 1179 "bcctr 4, $bi, 0", IIC_BrB, []>; 1180 } 1181 } 1182} 1183 1184// Set the float rounding mode. 1185let Uses = [RM], Defs = [RM] in { 1186def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND), 1187 "#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>; 1188 1189def SETRND : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins gprc:$in), 1190 "#SETRND", [(set f64:$FRT, (int_ppc_setrnd gprc :$in))]>; 1191 1192def SETFLM : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FLM), 1193 "#SETFLM", [(set f64:$FRT, (int_ppc_setflm f8rc:$FLM))]>; 1194} 1195 1196let Defs = [LR] in 1197 def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>, 1198 PPC970_Unit_BRU; 1199let Defs = [LR] in 1200 def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>, 1201 PPC970_Unit_BRU; 1202 1203let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1204 hasSideEffects = 0 in { 1205 let isBarrier = 1 in { 1206 let isPredicable = 1 in 1207 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), 1208 "b $dst", IIC_BrB, 1209 [(br bb:$dst)]>; 1210 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst), 1211 "ba $dst", IIC_BrB, []>; 1212 } 1213 1214 // BCC represents an arbitrary conditional branch on a predicate. 1215 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 1216 // a two-value operand where a dag node expects two operands. :( 1217 let isCodeGenOnly = 1 in { 1218 class BCC_class : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), 1219 "b${cond:cc}${cond:pm} ${cond:reg}, $dst" 1220 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>; 1221 def BCC : BCC_class; 1222 1223 // The same as BCC, except that it's not a terminator. Used for introducing 1224 // control flow dependency without creating new blocks. 1225 let isTerminator = 0 in def CTRL_DEP : BCC_class; 1226 1227 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst), 1228 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">; 1229 1230 let isReturn = 1, Uses = [LR, RM] in 1231 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond), 1232 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>; 1233 } 1234 1235 let isCodeGenOnly = 1 in { 1236 let Pattern = [(brcond i1:$bi, bb:$dst)] in 1237 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1238 "bc 12, $bi, $dst">; 1239 1240 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in 1241 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1242 "bc 4, $bi, $dst">; 1243 1244 let isReturn = 1, Uses = [LR, RM] in { 1245 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi), 1246 "bclr 12, $bi, 0", IIC_BrB, []>; 1247 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi), 1248 "bclr 4, $bi, 0", IIC_BrB, []>; 1249 } 1250 } 1251 1252 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in { 1253 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 1254 "bdzlr", IIC_BrB, []>; 1255 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 1256 "bdnzlr", IIC_BrB, []>; 1257 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins), 1258 "bdzlr+", IIC_BrB, []>; 1259 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins), 1260 "bdnzlr+", IIC_BrB, []>; 1261 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins), 1262 "bdzlr-", IIC_BrB, []>; 1263 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins), 1264 "bdnzlr-", IIC_BrB, []>; 1265 } 1266 1267 let Defs = [CTR], Uses = [CTR] in { 1268 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 1269 "bdz $dst">; 1270 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 1271 "bdnz $dst">; 1272 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst), 1273 "bdza $dst">; 1274 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst), 1275 "bdnza $dst">; 1276 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst), 1277 "bdz+ $dst">; 1278 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst), 1279 "bdnz+ $dst">; 1280 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst), 1281 "bdza+ $dst">; 1282 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst), 1283 "bdnza+ $dst">; 1284 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst), 1285 "bdz- $dst">; 1286 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst), 1287 "bdnz- $dst">; 1288 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst), 1289 "bdza- $dst">; 1290 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst), 1291 "bdnza- $dst">; 1292 } 1293} 1294 1295// The unconditional BCL used by the SjLj setjmp code. 1296let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7, 1297 hasSideEffects = 0 in { 1298 let Defs = [LR], Uses = [RM] in { 1299 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst), 1300 "bcl 20, 31, $dst">; 1301 } 1302} 1303 1304let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 1305 // Convenient aliases for call instructions 1306 let Uses = [RM] in { 1307 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func), 1308 "bl $func", IIC_BrB, []>; // See Pat patterns below. 1309 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 1310 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>; 1311 1312 let isCodeGenOnly = 1 in { 1313 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func), 1314 "bl $func", IIC_BrB, []>; 1315 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst), 1316 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">; 1317 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst), 1318 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">; 1319 1320 def BCL : BForm_4<16, 12, 0, 1, (outs), 1321 (ins crbitrc:$bi, condbrtarget:$dst), 1322 "bcl 12, $bi, $dst">; 1323 def BCLn : BForm_4<16, 4, 0, 1, (outs), 1324 (ins crbitrc:$bi, condbrtarget:$dst), 1325 "bcl 4, $bi, $dst">; 1326 def BL_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 1327 (outs), (ins calltarget:$func), 1328 "bl $func\n\tnop", IIC_BrB, []>; 1329 } 1330 } 1331 let Uses = [CTR, RM] in { 1332 let isPredicable = 1 in 1333 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1334 "bctrl", IIC_BrB, [(PPCbctrl)]>, 1335 Requires<[In32BitMode]>; 1336 1337 let isCodeGenOnly = 1 in { 1338 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 1339 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 1340 []>; 1341 1342 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 1343 "bcctrl 12, $bi, 0", IIC_BrB, []>; 1344 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 1345 "bcctrl 4, $bi, 0", IIC_BrB, []>; 1346 } 1347 } 1348 let Uses = [LR, RM] in { 1349 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins), 1350 "blrl", IIC_BrB, []>; 1351 1352 let isCodeGenOnly = 1 in { 1353 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond), 1354 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB, 1355 []>; 1356 1357 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi), 1358 "bclrl 12, $bi, 0", IIC_BrB, []>; 1359 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi), 1360 "bclrl 4, $bi, 0", IIC_BrB, []>; 1361 } 1362 } 1363 let Defs = [CTR], Uses = [CTR, RM] in { 1364 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst), 1365 "bdzl $dst">; 1366 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst), 1367 "bdnzl $dst">; 1368 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst), 1369 "bdzla $dst">; 1370 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst), 1371 "bdnzla $dst">; 1372 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst), 1373 "bdzl+ $dst">; 1374 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst), 1375 "bdnzl+ $dst">; 1376 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst), 1377 "bdzla+ $dst">; 1378 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst), 1379 "bdnzla+ $dst">; 1380 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst), 1381 "bdzl- $dst">; 1382 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst), 1383 "bdnzl- $dst">; 1384 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst), 1385 "bdzla- $dst">; 1386 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst), 1387 "bdnzla- $dst">; 1388 } 1389 let Defs = [CTR], Uses = [CTR, LR, RM] in { 1390 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins), 1391 "bdzlrl", IIC_BrB, []>; 1392 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins), 1393 "bdnzlrl", IIC_BrB, []>; 1394 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins), 1395 "bdzlrl+", IIC_BrB, []>; 1396 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins), 1397 "bdnzlrl+", IIC_BrB, []>; 1398 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins), 1399 "bdzlrl-", IIC_BrB, []>; 1400 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins), 1401 "bdnzlrl-", IIC_BrB, []>; 1402 } 1403} 1404 1405let isCall = 1, PPC970_Unit = 7, Defs = [LR, RM], isCodeGenOnly = 1 in { 1406 // Convenient aliases for call instructions 1407 let Uses = [RM] in { 1408 def BL_RM : IForm<18, 0, 1, (outs), (ins calltarget:$func), 1409 "bl $func", IIC_BrB, []>; // See Pat patterns below. 1410 def BLA_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 1411 "bla $func", IIC_BrB, [(PPCcall_rm (i32 imm:$func))]>; 1412 1413 def BL_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24, 1414 (outs), (ins calltarget:$func), 1415 "bl $func\n\tnop", IIC_BrB, []>; 1416 } 1417 let Uses = [CTR, RM] in { 1418 let isPredicable = 1 in 1419 def BCTRL_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1420 "bctrl", IIC_BrB, [(PPCbctrl_rm)]>, 1421 Requires<[In32BitMode]>; 1422 } 1423} 1424 1425let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1426def TCRETURNdi :PPCEmitTimePseudo< (outs), 1427 (ins calltarget:$dst, i32imm:$offset), 1428 "#TC_RETURNd $dst $offset", 1429 []>; 1430 1431 1432let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1433def TCRETURNai :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 1434 "#TC_RETURNa $func $offset", 1435 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 1436 1437let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1438def TCRETURNri : PPCEmitTimePseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 1439 "#TC_RETURNr $dst $offset", 1440 []>; 1441 1442let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 1443 Defs = [LR, R2], Uses = [CTR, RM], RST = 2 in { 1444 def BCTRL_LWZinto_toc: 1445 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), 1446 (ins memri:$src), "bctrl\n\tlwz 2, $src", IIC_BrB, 1447 [(PPCbctrl_load_toc iaddr:$src)]>, Requires<[In32BitMode]>; 1448 1449} 1450 1451let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 1452 Defs = [LR, R2, RM], Uses = [CTR, RM], RST = 2 in { 1453 def BCTRL_LWZinto_toc_RM: 1454 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), 1455 (ins memri:$src), "bctrl\n\tlwz 2, $src", IIC_BrB, 1456 [(PPCbctrl_load_toc_rm iaddr:$src)]>, Requires<[In32BitMode]>; 1457 1458} 1459 1460let isCodeGenOnly = 1, hasSideEffects = 0 in { 1461 1462let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 1463 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 1464def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1465 []>, Requires<[In32BitMode]>; 1466 1467let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1468 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1469def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 1470 "b $dst", IIC_BrB, 1471 []>; 1472 1473let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1474 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1475def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 1476 "ba $dst", IIC_BrB, 1477 []>; 1478 1479} 1480 1481// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 1482// is not. 1483let hasSideEffects = 1 in { 1484 let Defs = [CTR] in 1485 def EH_SjLj_SetJmp32 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 1486 "#EH_SJLJ_SETJMP32", 1487 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 1488 Requires<[In32BitMode]>; 1489} 1490 1491let hasSideEffects = 1, isBarrier = 1 in { 1492 let isTerminator = 1 in 1493 def EH_SjLj_LongJmp32 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 1494 "#EH_SJLJ_LONGJMP32", 1495 [(PPCeh_sjlj_longjmp addr:$buf)]>, 1496 Requires<[In32BitMode]>; 1497} 1498 1499// This pseudo is never removed from the function, as it serves as 1500// a terminator. Size is set to 0 to prevent the builtin assembler 1501// from emitting it. 1502let isBranch = 1, isTerminator = 1, Size = 0 in { 1503 def EH_SjLj_Setup : PPCEmitTimePseudo<(outs), (ins directbrtarget:$dst), 1504 "#EH_SjLj_Setup\t$dst", []>; 1505} 1506 1507// System call. 1508let PPC970_Unit = 7 in { 1509 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev), 1510 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>; 1511} 1512 1513// Branch history rolling buffer. 1514def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB, 1515 [(PPCclrbhrb)]>, 1516 PPC970_DGroup_Single; 1517// The $dmy argument used for MFBHRBE is not needed; however, including 1518// it avoids automatic generation of PPCFastISel::fastEmit_i(), which 1519// interferes with necessary special handling (see PPCFastISel.cpp). 1520def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD), 1521 (ins u10imm:$imm, u10imm:$dmy), 1522 "mfbhrbe $rD, $imm", IIC_BrB, 1523 [(set i32:$rD, 1524 (PPCmfbhrbe imm:$imm, imm:$dmy))]>, 1525 PPC970_DGroup_First; 1526 1527def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm", 1528 IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>, 1529 PPC970_DGroup_Single; 1530 1531def : InstAlias<"rfebb", (RFEBB 1)>; 1532 1533// DCB* instructions. 1534def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst", 1535 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 1536 PPC970_DGroup_Single; 1537def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst", 1538 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 1539 PPC970_DGroup_Single; 1540def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst", 1541 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 1542 PPC970_DGroup_Single; 1543def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst", 1544 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 1545 PPC970_DGroup_Single; 1546def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst", 1547 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 1548 PPC970_DGroup_Single; 1549 1550def DCBF : DCB_Form_hint<86, (outs), (ins u3imm:$TH, memrr:$dst), 1551 "dcbf $dst, $TH", IIC_LdStDCBF, []>, 1552 PPC970_DGroup_Single; 1553 1554let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { 1555def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst), 1556 "dcbt $dst, $TH", IIC_LdStDCBF, []>, 1557 PPC970_DGroup_Single; 1558def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst), 1559 "dcbtst $dst, $TH", IIC_LdStDCBF, []>, 1560 PPC970_DGroup_Single; 1561} // hasSideEffects = 0 1562 1563def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, memrr:$src), 1564 "icblc $CT, $src", IIC_LdStStore>, Requires<[HasICBT]>; 1565def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, memrr:$src), 1566 "icblq. $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 1567def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src), 1568 "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 1569def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src), 1570 "icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 1571 1572def : Pat<(int_ppc_dcbt xoaddr:$dst), 1573 (DCBT 0, xoaddr:$dst)>; 1574def : Pat<(int_ppc_dcbtst xoaddr:$dst), 1575 (DCBTST 0, xoaddr:$dst)>; 1576def : Pat<(int_ppc_dcbf xoaddr:$dst), 1577 (DCBF 0, xoaddr:$dst)>; 1578def : Pat<(int_ppc_icbt xoaddr:$dst), 1579 (ICBT 0, xoaddr:$dst)>; 1580 1581def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), 1582 (DCBT 0, xoaddr:$dst)>; // data prefetch for loads 1583def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)), 1584 (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores 1585def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)), 1586 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read) 1587 1588def : Pat<(int_ppc_dcbt_with_hint xoaddr:$dst, i32:$TH), 1589 (DCBT i32:$TH, xoaddr:$dst)>; 1590def : Pat<(int_ppc_dcbtst_with_hint xoaddr:$dst, i32:$TH), 1591 (DCBTST i32:$TH, xoaddr:$dst)>; 1592 1593// Atomic operations 1594// FIXME: some of these might be used with constant operands. This will result 1595// in constant materialization instructions that may be redundant. We currently 1596// clean this up in PPCMIPeephole with calls to 1597// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 1598// in the first place. 1599let Defs = [CR0] in { 1600 def ATOMIC_LOAD_ADD_I8 : PPCCustomInserterPseudo< 1601 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8", 1602 [(set i32:$dst, (atomic_load_add_8 ForceXForm:$ptr, i32:$incr))]>; 1603 def ATOMIC_LOAD_SUB_I8 : PPCCustomInserterPseudo< 1604 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8", 1605 [(set i32:$dst, (atomic_load_sub_8 ForceXForm:$ptr, i32:$incr))]>; 1606 def ATOMIC_LOAD_AND_I8 : PPCCustomInserterPseudo< 1607 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8", 1608 [(set i32:$dst, (atomic_load_and_8 ForceXForm:$ptr, i32:$incr))]>; 1609 def ATOMIC_LOAD_OR_I8 : PPCCustomInserterPseudo< 1610 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8", 1611 [(set i32:$dst, (atomic_load_or_8 ForceXForm:$ptr, i32:$incr))]>; 1612 def ATOMIC_LOAD_XOR_I8 : PPCCustomInserterPseudo< 1613 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8", 1614 [(set i32:$dst, (atomic_load_xor_8 ForceXForm:$ptr, i32:$incr))]>; 1615 def ATOMIC_LOAD_NAND_I8 : PPCCustomInserterPseudo< 1616 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8", 1617 [(set i32:$dst, (atomic_load_nand_8 ForceXForm:$ptr, i32:$incr))]>; 1618 def ATOMIC_LOAD_MIN_I8 : PPCCustomInserterPseudo< 1619 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8", 1620 [(set i32:$dst, (atomic_load_min_8 ForceXForm:$ptr, i32:$incr))]>; 1621 def ATOMIC_LOAD_MAX_I8 : PPCCustomInserterPseudo< 1622 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8", 1623 [(set i32:$dst, (atomic_load_max_8 ForceXForm:$ptr, i32:$incr))]>; 1624 def ATOMIC_LOAD_UMIN_I8 : PPCCustomInserterPseudo< 1625 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8", 1626 [(set i32:$dst, (atomic_load_umin_8 ForceXForm:$ptr, i32:$incr))]>; 1627 def ATOMIC_LOAD_UMAX_I8 : PPCCustomInserterPseudo< 1628 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8", 1629 [(set i32:$dst, (atomic_load_umax_8 ForceXForm:$ptr, i32:$incr))]>; 1630 def ATOMIC_LOAD_ADD_I16 : PPCCustomInserterPseudo< 1631 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16", 1632 [(set i32:$dst, (atomic_load_add_16 ForceXForm:$ptr, i32:$incr))]>; 1633 def ATOMIC_LOAD_SUB_I16 : PPCCustomInserterPseudo< 1634 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16", 1635 [(set i32:$dst, (atomic_load_sub_16 ForceXForm:$ptr, i32:$incr))]>; 1636 def ATOMIC_LOAD_AND_I16 : PPCCustomInserterPseudo< 1637 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16", 1638 [(set i32:$dst, (atomic_load_and_16 ForceXForm:$ptr, i32:$incr))]>; 1639 def ATOMIC_LOAD_OR_I16 : PPCCustomInserterPseudo< 1640 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16", 1641 [(set i32:$dst, (atomic_load_or_16 ForceXForm:$ptr, i32:$incr))]>; 1642 def ATOMIC_LOAD_XOR_I16 : PPCCustomInserterPseudo< 1643 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16", 1644 [(set i32:$dst, (atomic_load_xor_16 ForceXForm:$ptr, i32:$incr))]>; 1645 def ATOMIC_LOAD_NAND_I16 : PPCCustomInserterPseudo< 1646 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16", 1647 [(set i32:$dst, (atomic_load_nand_16 ForceXForm:$ptr, i32:$incr))]>; 1648 def ATOMIC_LOAD_MIN_I16 : PPCCustomInserterPseudo< 1649 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16", 1650 [(set i32:$dst, (atomic_load_min_16 ForceXForm:$ptr, i32:$incr))]>; 1651 def ATOMIC_LOAD_MAX_I16 : PPCCustomInserterPseudo< 1652 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16", 1653 [(set i32:$dst, (atomic_load_max_16 ForceXForm:$ptr, i32:$incr))]>; 1654 def ATOMIC_LOAD_UMIN_I16 : PPCCustomInserterPseudo< 1655 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16", 1656 [(set i32:$dst, (atomic_load_umin_16 ForceXForm:$ptr, i32:$incr))]>; 1657 def ATOMIC_LOAD_UMAX_I16 : PPCCustomInserterPseudo< 1658 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16", 1659 [(set i32:$dst, (atomic_load_umax_16 ForceXForm:$ptr, i32:$incr))]>; 1660 def ATOMIC_LOAD_ADD_I32 : PPCCustomInserterPseudo< 1661 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32", 1662 [(set i32:$dst, (atomic_load_add_32 ForceXForm:$ptr, i32:$incr))]>; 1663 def ATOMIC_LOAD_SUB_I32 : PPCCustomInserterPseudo< 1664 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32", 1665 [(set i32:$dst, (atomic_load_sub_32 ForceXForm:$ptr, i32:$incr))]>; 1666 def ATOMIC_LOAD_AND_I32 : PPCCustomInserterPseudo< 1667 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32", 1668 [(set i32:$dst, (atomic_load_and_32 ForceXForm:$ptr, i32:$incr))]>; 1669 def ATOMIC_LOAD_OR_I32 : PPCCustomInserterPseudo< 1670 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32", 1671 [(set i32:$dst, (atomic_load_or_32 ForceXForm:$ptr, i32:$incr))]>; 1672 def ATOMIC_LOAD_XOR_I32 : PPCCustomInserterPseudo< 1673 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32", 1674 [(set i32:$dst, (atomic_load_xor_32 ForceXForm:$ptr, i32:$incr))]>; 1675 def ATOMIC_LOAD_NAND_I32 : PPCCustomInserterPseudo< 1676 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32", 1677 [(set i32:$dst, (atomic_load_nand_32 ForceXForm:$ptr, i32:$incr))]>; 1678 def ATOMIC_LOAD_MIN_I32 : PPCCustomInserterPseudo< 1679 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32", 1680 [(set i32:$dst, (atomic_load_min_32 ForceXForm:$ptr, i32:$incr))]>; 1681 def ATOMIC_LOAD_MAX_I32 : PPCCustomInserterPseudo< 1682 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32", 1683 [(set i32:$dst, (atomic_load_max_32 ForceXForm:$ptr, i32:$incr))]>; 1684 def ATOMIC_LOAD_UMIN_I32 : PPCCustomInserterPseudo< 1685 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32", 1686 [(set i32:$dst, (atomic_load_umin_32 ForceXForm:$ptr, i32:$incr))]>; 1687 def ATOMIC_LOAD_UMAX_I32 : PPCCustomInserterPseudo< 1688 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32", 1689 [(set i32:$dst, (atomic_load_umax_32 ForceXForm:$ptr, i32:$incr))]>; 1690 1691 def ATOMIC_CMP_SWAP_I8 : PPCCustomInserterPseudo< 1692 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8", 1693 [(set i32:$dst, (atomic_cmp_swap_8 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1694 def ATOMIC_CMP_SWAP_I16 : PPCCustomInserterPseudo< 1695 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 1696 [(set i32:$dst, (atomic_cmp_swap_16 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1697 def ATOMIC_CMP_SWAP_I32 : PPCCustomInserterPseudo< 1698 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 1699 [(set i32:$dst, (atomic_cmp_swap_32 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1700 1701 def ATOMIC_SWAP_I8 : PPCCustomInserterPseudo< 1702 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8", 1703 [(set i32:$dst, (atomic_swap_8 ForceXForm:$ptr, i32:$new))]>; 1704 def ATOMIC_SWAP_I16 : PPCCustomInserterPseudo< 1705 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16", 1706 [(set i32:$dst, (atomic_swap_16 ForceXForm:$ptr, i32:$new))]>; 1707 def ATOMIC_SWAP_I32 : PPCCustomInserterPseudo< 1708 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32", 1709 [(set i32:$dst, (atomic_swap_32 ForceXForm:$ptr, i32:$new))]>; 1710} 1711 1712def : Pat<(PPCatomicCmpSwap_8 ForceXForm:$ptr, i32:$old, i32:$new), 1713 (ATOMIC_CMP_SWAP_I8 ForceXForm:$ptr, i32:$old, i32:$new)>; 1714def : Pat<(PPCatomicCmpSwap_16 ForceXForm:$ptr, i32:$old, i32:$new), 1715 (ATOMIC_CMP_SWAP_I16 ForceXForm:$ptr, i32:$old, i32:$new)>; 1716 1717// Instructions to support atomic operations 1718let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 1719def LBARX : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src), 1720 "lbarx $rD, $src", IIC_LdStLWARX, []>, 1721 Requires<[HasPartwordAtomics]>; 1722 1723def LHARX : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src), 1724 "lharx $rD, $src", IIC_LdStLWARX, []>, 1725 Requires<[HasPartwordAtomics]>; 1726 1727def LWARX : XForm_1_memOp<31, 20, (outs gprc:$rD), (ins memrr:$src), 1728 "lwarx $rD, $src", IIC_LdStLWARX, []>; 1729 1730// Instructions to support lock versions of atomics 1731// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 1732def LBARXL : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src), 1733 "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm, 1734 Requires<[HasPartwordAtomics]>; 1735 1736def LHARXL : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src), 1737 "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm, 1738 Requires<[HasPartwordAtomics]>; 1739 1740def LWARXL : XForm_1_memOp<31, 20, (outs gprc:$rD), (ins memrr:$src), 1741 "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm; 1742 1743// The atomic instructions use the destination register as well as the next one 1744// or two registers in order (modulo 31). 1745let hasExtraSrcRegAllocReq = 1 in 1746def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC), 1747 "lwat $rD, $rA, $FC", IIC_LdStLoad>, 1748 Requires<[IsISA3_0]>; 1749} 1750 1751let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { 1752def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$rS, memrr:$dst), 1753 "stbcx. $rS, $dst", IIC_LdStSTWCX, []>, 1754 isRecordForm, Requires<[HasPartwordAtomics]>; 1755 1756def STHCX : XForm_1_memOp<31, 726, (outs), (ins gprc:$rS, memrr:$dst), 1757 "sthcx. $rS, $dst", IIC_LdStSTWCX, []>, 1758 isRecordForm, Requires<[HasPartwordAtomics]>; 1759 1760def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$rS, memrr:$dst), 1761 "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isRecordForm; 1762} 1763 1764let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 1765def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC), 1766 "stwat $rS, $rA, $FC", IIC_LdStStore>, 1767 Requires<[IsISA3_0]>; 1768 1769let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 1770def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>; 1771 1772def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm), 1773 "twi $to, $rA, $imm", IIC_IntTrapW, []>; 1774def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB), 1775 "tw $to, $rA, $rB", IIC_IntTrapW, []>; 1776def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm), 1777 "tdi $to, $rA, $imm", IIC_IntTrapD, []>; 1778def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB), 1779 "td $to, $rA, $rB", IIC_IntTrapD, []>; 1780 1781def POPCNTB : XForm_11<31, 122, (outs gprc:$rA), (ins gprc:$rS), 1782 "popcntb $rA, $rS", IIC_IntGeneral, 1783 [(set i32:$rA, (int_ppc_popcntb i32:$rS))]>; 1784 1785//===----------------------------------------------------------------------===// 1786// PPC32 Load Instructions. 1787// 1788 1789// Unindexed (r+i) Loads. 1790let PPC970_Unit = 2 in { 1791def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src), 1792 "lbz $rD, $src", IIC_LdStLoad, 1793 [(set i32:$rD, (zextloadi8 DForm:$src))]>; 1794def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src), 1795 "lha $rD, $src", IIC_LdStLHA, 1796 [(set i32:$rD, (sextloadi16 DForm:$src))]>, 1797 PPC970_DGroup_Cracked; 1798def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src), 1799 "lhz $rD, $src", IIC_LdStLoad, 1800 [(set i32:$rD, (zextloadi16 DForm:$src))]>; 1801def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src), 1802 "lwz $rD, $src", IIC_LdStLoad, 1803 [(set i32:$rD, (load DForm:$src))]>; 1804 1805let Predicates = [HasFPU] in { 1806def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src), 1807 "lfs $rD, $src", IIC_LdStLFD, 1808 [(set f32:$rD, (load DForm:$src))]>; 1809def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src), 1810 "lfd $rD, $src", IIC_LdStLFD, 1811 [(set f64:$rD, (load DForm:$src))]>; 1812} 1813 1814 1815// Unindexed (r+i) Loads with Update (preinc). 1816let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 1817def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1818 "lbzu $rD, $addr", IIC_LdStLoadUpd, 1819 []>, RegConstraint<"$addr.reg = $ea_result">, 1820 NoEncode<"$ea_result">; 1821 1822def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1823 "lhau $rD, $addr", IIC_LdStLHAU, 1824 []>, RegConstraint<"$addr.reg = $ea_result">, 1825 NoEncode<"$ea_result">; 1826 1827def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1828 "lhzu $rD, $addr", IIC_LdStLoadUpd, 1829 []>, RegConstraint<"$addr.reg = $ea_result">, 1830 NoEncode<"$ea_result">; 1831 1832def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1833 "lwzu $rD, $addr", IIC_LdStLoadUpd, 1834 []>, RegConstraint<"$addr.reg = $ea_result">, 1835 NoEncode<"$ea_result">; 1836 1837let Predicates = [HasFPU] in { 1838def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1839 "lfsu $rD, $addr", IIC_LdStLFDU, 1840 []>, RegConstraint<"$addr.reg = $ea_result">, 1841 NoEncode<"$ea_result">; 1842 1843def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1844 "lfdu $rD, $addr", IIC_LdStLFDU, 1845 []>, RegConstraint<"$addr.reg = $ea_result">, 1846 NoEncode<"$ea_result">; 1847} 1848 1849 1850// Indexed (r+r) Loads with Update (preinc). 1851def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1852 (ins memrr:$addr), 1853 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1854 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1855 NoEncode<"$ea_result">; 1856 1857def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1858 (ins memrr:$addr), 1859 "lhaux $rD, $addr", IIC_LdStLHAUX, 1860 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1861 NoEncode<"$ea_result">; 1862 1863def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1864 (ins memrr:$addr), 1865 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1866 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1867 NoEncode<"$ea_result">; 1868 1869def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1870 (ins memrr:$addr), 1871 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1872 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1873 NoEncode<"$ea_result">; 1874 1875let Predicates = [HasFPU] in { 1876def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), 1877 (ins memrr:$addr), 1878 "lfsux $rD, $addr", IIC_LdStLFDUX, 1879 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1880 NoEncode<"$ea_result">; 1881 1882def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), 1883 (ins memrr:$addr), 1884 "lfdux $rD, $addr", IIC_LdStLFDUX, 1885 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1886 NoEncode<"$ea_result">; 1887} 1888} 1889} 1890 1891// Indexed (r+r) Loads. 1892// 1893let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { 1894def LBZX : XForm_1_memOp<31, 87, (outs gprc:$rD), (ins memrr:$src), 1895 "lbzx $rD, $src", IIC_LdStLoad, 1896 [(set i32:$rD, (zextloadi8 XForm:$src))]>; 1897def LHAX : XForm_1_memOp<31, 343, (outs gprc:$rD), (ins memrr:$src), 1898 "lhax $rD, $src", IIC_LdStLHA, 1899 [(set i32:$rD, (sextloadi16 XForm:$src))]>, 1900 PPC970_DGroup_Cracked; 1901def LHZX : XForm_1_memOp<31, 279, (outs gprc:$rD), (ins memrr:$src), 1902 "lhzx $rD, $src", IIC_LdStLoad, 1903 [(set i32:$rD, (zextloadi16 XForm:$src))]>; 1904def LWZX : XForm_1_memOp<31, 23, (outs gprc:$rD), (ins memrr:$src), 1905 "lwzx $rD, $src", IIC_LdStLoad, 1906 [(set i32:$rD, (load XForm:$src))]>; 1907def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$rD), (ins memrr:$src), 1908 "lhbrx $rD, $src", IIC_LdStLoad, 1909 [(set i32:$rD, (PPClbrx ForceXForm:$src, i16))]>; 1910def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$rD), (ins memrr:$src), 1911 "lwbrx $rD, $src", IIC_LdStLoad, 1912 [(set i32:$rD, (PPClbrx ForceXForm:$src, i32))]>; 1913 1914let Predicates = [HasFPU] in { 1915def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$frD), (ins memrr:$src), 1916 "lfsx $frD, $src", IIC_LdStLFD, 1917 [(set f32:$frD, (load XForm:$src))]>; 1918def LFDX : XForm_25_memOp<31, 599, (outs f8rc:$frD), (ins memrr:$src), 1919 "lfdx $frD, $src", IIC_LdStLFD, 1920 [(set f64:$frD, (load XForm:$src))]>; 1921 1922def LFIWAX : XForm_25_memOp<31, 855, (outs f8rc:$frD), (ins memrr:$src), 1923 "lfiwax $frD, $src", IIC_LdStLFD, 1924 [(set f64:$frD, (PPClfiwax ForceXForm:$src))]>; 1925def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$frD), (ins memrr:$src), 1926 "lfiwzx $frD, $src", IIC_LdStLFD, 1927 [(set f64:$frD, (PPClfiwzx ForceXForm:$src))]>; 1928} 1929} 1930 1931// Load Multiple 1932let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in 1933def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src), 1934 "lmw $rD, $src", IIC_LdStLMW, []>; 1935 1936//===----------------------------------------------------------------------===// 1937// PPC32 Store Instructions. 1938// 1939 1940// Unindexed (r+i) Stores. 1941let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1942def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$dst), 1943 "stb $rS, $dst", IIC_LdStStore, 1944 [(truncstorei8 i32:$rS, DForm:$dst)]>; 1945def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$dst), 1946 "sth $rS, $dst", IIC_LdStStore, 1947 [(truncstorei16 i32:$rS, DForm:$dst)]>; 1948def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$dst), 1949 "stw $rS, $dst", IIC_LdStStore, 1950 [(store i32:$rS, DForm:$dst)]>; 1951let Predicates = [HasFPU] in { 1952def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst), 1953 "stfs $rS, $dst", IIC_LdStSTFD, 1954 [(store f32:$rS, DForm:$dst)]>; 1955def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst), 1956 "stfd $rS, $dst", IIC_LdStSTFD, 1957 [(store f64:$rS, DForm:$dst)]>; 1958} 1959} 1960 1961// Unindexed (r+i) Stores with Update (preinc). 1962let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1963def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1964 "stbu $rS, $dst", IIC_LdStSTU, []>, 1965 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1966def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1967 "sthu $rS, $dst", IIC_LdStSTU, []>, 1968 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1969def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1970 "stwu $rS, $dst", IIC_LdStSTU, []>, 1971 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1972let Predicates = [HasFPU] in { 1973def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst), 1974 "stfsu $rS, $dst", IIC_LdStSTFDU, []>, 1975 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1976def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst), 1977 "stfdu $rS, $dst", IIC_LdStSTFDU, []>, 1978 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1979} 1980} 1981 1982// Patterns to match the pre-inc stores. We can't put the patterns on 1983// the instruction definitions directly as ISel wants the address base 1984// and offset to be separate operands, not a single complex operand. 1985def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1986 (STBU $rS, iaddroff:$ptroff, $ptrreg)>; 1987def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1988 (STHU $rS, iaddroff:$ptroff, $ptrreg)>; 1989def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1990 (STWU $rS, iaddroff:$ptroff, $ptrreg)>; 1991def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1992 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>; 1993def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1994 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>; 1995 1996// Indexed (r+r) Stores. 1997let PPC970_Unit = 2 in { 1998def STBX : XForm_8_memOp<31, 215, (outs), (ins gprc:$rS, memrr:$dst), 1999 "stbx $rS, $dst", IIC_LdStStore, 2000 [(truncstorei8 i32:$rS, XForm:$dst)]>, 2001 PPC970_DGroup_Cracked; 2002def STHX : XForm_8_memOp<31, 407, (outs), (ins gprc:$rS, memrr:$dst), 2003 "sthx $rS, $dst", IIC_LdStStore, 2004 [(truncstorei16 i32:$rS, XForm:$dst)]>, 2005 PPC970_DGroup_Cracked; 2006def STWX : XForm_8_memOp<31, 151, (outs), (ins gprc:$rS, memrr:$dst), 2007 "stwx $rS, $dst", IIC_LdStStore, 2008 [(store i32:$rS, XForm:$dst)]>, 2009 PPC970_DGroup_Cracked; 2010 2011def STHBRX: XForm_8_memOp<31, 918, (outs), (ins gprc:$rS, memrr:$dst), 2012 "sthbrx $rS, $dst", IIC_LdStStore, 2013 [(PPCstbrx i32:$rS, ForceXForm:$dst, i16)]>, 2014 PPC970_DGroup_Cracked; 2015def STWBRX: XForm_8_memOp<31, 662, (outs), (ins gprc:$rS, memrr:$dst), 2016 "stwbrx $rS, $dst", IIC_LdStStore, 2017 [(PPCstbrx i32:$rS, ForceXForm:$dst, i32)]>, 2018 PPC970_DGroup_Cracked; 2019 2020let Predicates = [HasFPU] in { 2021def STFIWX: XForm_28_memOp<31, 983, (outs), (ins f8rc:$frS, memrr:$dst), 2022 "stfiwx $frS, $dst", IIC_LdStSTFD, 2023 [(PPCstfiwx f64:$frS, ForceXForm:$dst)]>; 2024 2025def STFSX : XForm_28_memOp<31, 663, (outs), (ins f4rc:$frS, memrr:$dst), 2026 "stfsx $frS, $dst", IIC_LdStSTFD, 2027 [(store f32:$frS, XForm:$dst)]>; 2028def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$frS, memrr:$dst), 2029 "stfdx $frS, $dst", IIC_LdStSTFD, 2030 [(store f64:$frS, XForm:$dst)]>; 2031} 2032} 2033 2034// Indexed (r+r) Stores with Update (preinc). 2035let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2036def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 2037 (ins gprc:$rS, memrr:$dst), 2038 "stbux $rS, $dst", IIC_LdStSTUX, []>, 2039 RegConstraint<"$dst.ptrreg = $ea_res">, 2040 NoEncode<"$ea_res">, 2041 PPC970_DGroup_Cracked; 2042def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 2043 (ins gprc:$rS, memrr:$dst), 2044 "sthux $rS, $dst", IIC_LdStSTUX, []>, 2045 RegConstraint<"$dst.ptrreg = $ea_res">, 2046 NoEncode<"$ea_res">, 2047 PPC970_DGroup_Cracked; 2048def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 2049 (ins gprc:$rS, memrr:$dst), 2050 "stwux $rS, $dst", IIC_LdStSTUX, []>, 2051 RegConstraint<"$dst.ptrreg = $ea_res">, 2052 NoEncode<"$ea_res">, 2053 PPC970_DGroup_Cracked; 2054let Predicates = [HasFPU] in { 2055def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res), 2056 (ins f4rc:$rS, memrr:$dst), 2057 "stfsux $rS, $dst", IIC_LdStSTFDU, []>, 2058 RegConstraint<"$dst.ptrreg = $ea_res">, 2059 NoEncode<"$ea_res">, 2060 PPC970_DGroup_Cracked; 2061def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res), 2062 (ins f8rc:$rS, memrr:$dst), 2063 "stfdux $rS, $dst", IIC_LdStSTFDU, []>, 2064 RegConstraint<"$dst.ptrreg = $ea_res">, 2065 NoEncode<"$ea_res">, 2066 PPC970_DGroup_Cracked; 2067} 2068} 2069 2070// Patterns to match the pre-inc stores. We can't put the patterns on 2071// the instruction definitions directly as ISel wants the address base 2072// and offset to be separate operands, not a single complex operand. 2073def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2074 (STBUX $rS, $ptrreg, $ptroff)>; 2075def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2076 (STHUX $rS, $ptrreg, $ptroff)>; 2077def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2078 (STWUX $rS, $ptrreg, $ptroff)>; 2079let Predicates = [HasFPU] in { 2080def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2081 (STFSUX $rS, $ptrreg, $ptroff)>; 2082def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2083 (STFDUX $rS, $ptrreg, $ptroff)>; 2084} 2085 2086// Store Multiple 2087let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 2088def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst), 2089 "stmw $rS, $dst", IIC_LdStLMW, []>; 2090 2091def SYNC : XForm_24_sync<31, 598, (outs), (ins u2imm:$L), 2092 "sync $L", IIC_LdStSync, []>; 2093 2094let isCodeGenOnly = 1 in { 2095 def MSYNC : XForm_24_sync<31, 598, (outs), (ins), 2096 "msync", IIC_LdStSync, []> { 2097 let L = 0; 2098 } 2099} 2100 2101// We used to have EIEIO as value but E[0-9A-Z] is a reserved name 2102def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins), 2103 "eieio", IIC_LdStLoad, []>; 2104 2105def PseudoEIEIO : PPCEmitTimePseudo<(outs), (ins), "#PPCEIEIO", 2106 [(int_ppc_eieio)]>; 2107 2108def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2109def : Pat<(int_ppc_iospace_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2110def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2111def : Pat<(int_ppc_iospace_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2112def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2113def : Pat<(int_ppc_iospace_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2114def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2115def : Pat<(int_ppc_iospace_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2116def : Pat<(int_ppc_eieio), (PseudoEIEIO)>; 2117def : Pat<(int_ppc_iospace_eieio), (PseudoEIEIO)>; 2118 2119//===----------------------------------------------------------------------===// 2120// PPC32 Arithmetic Instructions. 2121// 2122 2123let PPC970_Unit = 1 in { // FXU Operations. 2124def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm), 2125 "addi $rD, $rA, $imm", IIC_IntSimple, 2126 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>; 2127let BaseName = "addic" in { 2128let Defs = [CARRY] in 2129def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2130 "addic $rD, $rA, $imm", IIC_IntGeneral, 2131 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>, 2132 RecFormRel, PPC970_DGroup_Cracked; 2133let Defs = [CARRY, CR0] in 2134def ADDIC_rec : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2135 "addic. $rD, $rA, $imm", IIC_IntGeneral, 2136 []>, isRecordForm, RecFormRel; 2137} 2138def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm), 2139 "addis $rD, $rA, $imm", IIC_IntSimple, 2140 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>; 2141let isCodeGenOnly = 1 in 2142def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym), 2143 "la $rD, $sym($rA)", IIC_IntGeneral, 2144 [(set i32:$rD, (add i32:$rA, 2145 (PPClo tglobaladdr:$sym, 0)))]>; 2146def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2147 "mulli $rD, $rA, $imm", IIC_IntMulLI, 2148 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>; 2149let Defs = [CARRY] in 2150def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2151 "subfic $rD, $rA, $imm", IIC_IntGeneral, 2152 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>; 2153 2154let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 2155 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm), 2156 "li $rD, $imm", IIC_IntSimple, 2157 [(set i32:$rD, imm32SExt16:$imm)]>; 2158 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm), 2159 "lis $rD, $imm", IIC_IntSimple, 2160 [(set i32:$rD, imm16ShiftedSExt:$imm)]>; 2161} 2162} 2163 2164def : InstAlias<"li $rD, $imm", (ADDI gprc:$rD, ZERO, s16imm:$imm)>; 2165def : InstAlias<"lis $rD, $imm", (ADDIS gprc:$rD, ZERO, s17imm:$imm)>; 2166 2167let PPC970_Unit = 1 in { // FXU Operations. 2168let Defs = [CR0] in { 2169def ANDI_rec : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2170 "andi. $dst, $src1, $src2", IIC_IntGeneral, 2171 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>, 2172 isRecordForm; 2173def ANDIS_rec : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2174 "andis. $dst, $src1, $src2", IIC_IntGeneral, 2175 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>, 2176 isRecordForm; 2177} 2178def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2179 "ori $dst, $src1, $src2", IIC_IntSimple, 2180 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>; 2181def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2182 "oris $dst, $src1, $src2", IIC_IntSimple, 2183 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>; 2184def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2185 "xori $dst, $src1, $src2", IIC_IntSimple, 2186 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>; 2187def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2188 "xoris $dst, $src1, $src2", IIC_IntSimple, 2189 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>; 2190 2191def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple, 2192 []>; 2193let isCodeGenOnly = 1 in { 2194// The POWER6 and POWER7 have special group-terminating nops. 2195def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins), 2196 "ori 1, 1, 0", IIC_IntSimple, []>; 2197def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins), 2198 "ori 2, 2, 0", IIC_IntSimple, []>; 2199} 2200 2201let isCompare = 1, hasSideEffects = 0 in { 2202 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm), 2203 "cmpwi $crD, $rA, $imm", IIC_IntCompare>; 2204 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2), 2205 "cmplwi $dst, $src1, $src2", IIC_IntCompare>; 2206 def CMPRB : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), 2207 (ins u1imm:$L, gprc:$rA, gprc:$rB), 2208 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 2209 Requires<[IsISA3_0]>; 2210} 2211} 2212 2213let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2214let isCommutable = 1 in { 2215defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2216 "nand", "$rA, $rS, $rB", IIC_IntSimple, 2217 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>; 2218defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2219 "and", "$rA, $rS, $rB", IIC_IntSimple, 2220 [(set i32:$rA, (and i32:$rS, i32:$rB))]>; 2221} // isCommutable 2222defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2223 "andc", "$rA, $rS, $rB", IIC_IntSimple, 2224 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>; 2225let isCommutable = 1 in { 2226defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2227 "or", "$rA, $rS, $rB", IIC_IntSimple, 2228 [(set i32:$rA, (or i32:$rS, i32:$rB))]>; 2229defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2230 "nor", "$rA, $rS, $rB", IIC_IntSimple, 2231 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>; 2232} // isCommutable 2233defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2234 "orc", "$rA, $rS, $rB", IIC_IntSimple, 2235 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>; 2236let isCommutable = 1 in { 2237defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2238 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 2239 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>; 2240defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2241 "xor", "$rA, $rS, $rB", IIC_IntSimple, 2242 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>; 2243} // isCommutable 2244defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2245 "slw", "$rA, $rS, $rB", IIC_IntGeneral, 2246 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>; 2247defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2248 "srw", "$rA, $rS, $rB", IIC_IntGeneral, 2249 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>; 2250defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2251 "sraw", "$rA, $rS, $rB", IIC_IntShift, 2252 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>; 2253} 2254 2255def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>; 2256def : InstAlias<"mr. $rA, $rB", (OR_rec gprc:$rA, gprc:$rB, gprc:$rB)>; 2257 2258def : InstAlias<"not $rA, $rS", (NOR gprc:$rA, gprc:$rS, gprc:$rS)>; 2259def : InstAlias<"not. $rA, $rS", (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS)>; 2260 2261def : InstAlias<"nop", (ORI R0, R0, 0)>; 2262 2263let PPC970_Unit = 1 in { // FXU Operations. 2264let hasSideEffects = 0 in { 2265defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH), 2266 "srawi", "$rA, $rS, $SH", IIC_IntShift, 2267 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>; 2268defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS), 2269 "cntlzw", "$rA, $rS", IIC_IntGeneral, 2270 [(set i32:$rA, (ctlz i32:$rS))]>; 2271defm CNTTZW : XForm_11r<31, 538, (outs gprc:$rA), (ins gprc:$rS), 2272 "cnttzw", "$rA, $rS", IIC_IntGeneral, 2273 [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>; 2274defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS), 2275 "extsb", "$rA, $rS", IIC_IntSimple, 2276 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>; 2277defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS), 2278 "extsh", "$rA, $rS", IIC_IntSimple, 2279 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>; 2280 2281let isCommutable = 1 in 2282def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2283 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 2284 [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>; 2285} 2286let isCompare = 1, hasSideEffects = 0 in { 2287 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 2288 "cmpw $crD, $rA, $rB", IIC_IntCompare>; 2289 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 2290 "cmplw $crD, $rA, $rB", IIC_IntCompare>; 2291} 2292} 2293let PPC970_Unit = 3, Predicates = [HasFPU] in { // FPU Operations. 2294let isCompare = 1, mayRaiseFPException = 1, hasSideEffects = 0 in { 2295 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), 2296 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 2297 def FCMPOS : XForm_17<63, 32, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), 2298 "fcmpo $crD, $fA, $fB", IIC_FPCompare>; 2299 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 2300 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 2301 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 2302 def FCMPOD : XForm_17<63, 32, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 2303 "fcmpo $crD, $fA, $fB", IIC_FPCompare>; 2304 } 2305} 2306 2307def FTDIV: XForm_17<63, 128, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 2308 "ftdiv $crD, $fA, $fB", IIC_FPCompare>; 2309def FTSQRT: XForm_17a<63, 160, (outs crrc:$crD), (ins f8rc:$fB), 2310 "ftsqrt $crD, $fB", IIC_FPCompare, 2311 [(set i32:$crD, (PPCftsqrt f64:$fB))]>; 2312 2313let mayRaiseFPException = 1, hasSideEffects = 0 in { 2314 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2315 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB), 2316 "frin", "$frD, $frB", IIC_FPGeneral, 2317 [(set f64:$frD, (any_fround f64:$frB))]>; 2318 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB), 2319 "frin", "$frD, $frB", IIC_FPGeneral, 2320 [(set f32:$frD, (any_fround f32:$frB))]>; 2321 2322 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2323 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB), 2324 "frip", "$frD, $frB", IIC_FPGeneral, 2325 [(set f64:$frD, (any_fceil f64:$frB))]>; 2326 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB), 2327 "frip", "$frD, $frB", IIC_FPGeneral, 2328 [(set f32:$frD, (any_fceil f32:$frB))]>; 2329 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2330 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB), 2331 "friz", "$frD, $frB", IIC_FPGeneral, 2332 [(set f64:$frD, (any_ftrunc f64:$frB))]>; 2333 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB), 2334 "friz", "$frD, $frB", IIC_FPGeneral, 2335 [(set f32:$frD, (any_ftrunc f32:$frB))]>; 2336 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2337 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB), 2338 "frim", "$frD, $frB", IIC_FPGeneral, 2339 [(set f64:$frD, (any_ffloor f64:$frB))]>; 2340 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB), 2341 "frim", "$frD, $frB", IIC_FPGeneral, 2342 [(set f32:$frD, (any_ffloor f32:$frB))]>; 2343} 2344 2345let Uses = [RM], mayRaiseFPException = 1, hasSideEffects = 0 in { 2346 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB), 2347 "fctiw", "$frD, $frB", IIC_FPGeneral, 2348 []>; 2349 defm FCTIWU : XForm_26r<63, 142, (outs f8rc:$frD), (ins f8rc:$frB), 2350 "fctiwu", "$frD, $frB", IIC_FPGeneral, 2351 []>; 2352 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB), 2353 "fctiwz", "$frD, $frB", IIC_FPGeneral, 2354 [(set f64:$frD, (PPCany_fctiwz f64:$frB))]>; 2355 2356 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB), 2357 "frsp", "$frD, $frB", IIC_FPGeneral, 2358 [(set f32:$frD, (any_fpround f64:$frB))]>; 2359 2360 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB), 2361 "fsqrt", "$frD, $frB", IIC_FPSqrtD, 2362 [(set f64:$frD, (any_fsqrt f64:$frB))]>; 2363 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB), 2364 "fsqrts", "$frD, $frB", IIC_FPSqrtS, 2365 [(set f32:$frD, (any_fsqrt f32:$frB))]>; 2366} 2367} 2368 2369def : Pat<(PPCfsqrt f64:$frA), (FSQRT $frA)>; 2370 2371/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 2372/// often coalesced away and we don't want the dispatch group builder to think 2373/// that they will fill slots (which could cause the load of a LSU reject to 2374/// sneak into a d-group with a store). 2375let hasSideEffects = 0, Predicates = [HasFPU] in 2376defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB), 2377 "fmr", "$frD, $frB", IIC_FPGeneral, 2378 []>, // (set f32:$frD, f32:$frB) 2379 PPC970_Unit_Pseudo; 2380 2381let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 2382// These are artificially split into two different forms, for 4/8 byte FP. 2383defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB), 2384 "fabs", "$frD, $frB", IIC_FPGeneral, 2385 [(set f32:$frD, (fabs f32:$frB))]>; 2386let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2387defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB), 2388 "fabs", "$frD, $frB", IIC_FPGeneral, 2389 [(set f64:$frD, (fabs f64:$frB))]>; 2390defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB), 2391 "fnabs", "$frD, $frB", IIC_FPGeneral, 2392 [(set f32:$frD, (fneg (fabs f32:$frB)))]>; 2393let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2394defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB), 2395 "fnabs", "$frD, $frB", IIC_FPGeneral, 2396 [(set f64:$frD, (fneg (fabs f64:$frB)))]>; 2397defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB), 2398 "fneg", "$frD, $frB", IIC_FPGeneral, 2399 [(set f32:$frD, (fneg f32:$frB))]>; 2400let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2401defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB), 2402 "fneg", "$frD, $frB", IIC_FPGeneral, 2403 [(set f64:$frD, (fneg f64:$frB))]>; 2404 2405defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB), 2406 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 2407 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>; 2408let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2409defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB), 2410 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 2411 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>; 2412 2413// Reciprocal estimates. 2414let mayRaiseFPException = 1 in { 2415defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB), 2416 "fre", "$frD, $frB", IIC_FPGeneral, 2417 [(set f64:$frD, (PPCfre f64:$frB))]>; 2418defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB), 2419 "fres", "$frD, $frB", IIC_FPGeneral, 2420 [(set f32:$frD, (PPCfre f32:$frB))]>; 2421defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB), 2422 "frsqrte", "$frD, $frB", IIC_FPGeneral, 2423 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>; 2424defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB), 2425 "frsqrtes", "$frD, $frB", IIC_FPGeneral, 2426 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>; 2427} 2428} 2429 2430// XL-Form instructions. condition register logical ops. 2431// 2432let hasSideEffects = 0 in 2433def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA), 2434 "mcrf $BF, $BFA", IIC_BrMCR>, 2435 PPC970_DGroup_First, PPC970_Unit_CRU; 2436 2437// FIXME: According to the ISA (section 2.5.1 of version 2.06), the 2438// condition-register logical instructions have preferred forms. Specifically, 2439// it is preferred that the bit specified by the BT field be in the same 2440// condition register as that specified by the bit BB. We might want to account 2441// for this via hinting the register allocator and anti-dep breakers, or we 2442// could constrain the register class to force this constraint and then loosen 2443// it during register allocation via convertToThreeAddress or some similar 2444// mechanism. 2445 2446let isCommutable = 1 in { 2447def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD), 2448 (ins crbitrc:$CRA, crbitrc:$CRB), 2449 "crand $CRD, $CRA, $CRB", IIC_BrCR, 2450 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>; 2451 2452def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD), 2453 (ins crbitrc:$CRA, crbitrc:$CRB), 2454 "crnand $CRD, $CRA, $CRB", IIC_BrCR, 2455 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>; 2456 2457def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD), 2458 (ins crbitrc:$CRA, crbitrc:$CRB), 2459 "cror $CRD, $CRA, $CRB", IIC_BrCR, 2460 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>; 2461 2462def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD), 2463 (ins crbitrc:$CRA, crbitrc:$CRB), 2464 "crxor $CRD, $CRA, $CRB", IIC_BrCR, 2465 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>; 2466 2467def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD), 2468 (ins crbitrc:$CRA, crbitrc:$CRB), 2469 "crnor $CRD, $CRA, $CRB", IIC_BrCR, 2470 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>; 2471 2472def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD), 2473 (ins crbitrc:$CRA, crbitrc:$CRB), 2474 "creqv $CRD, $CRA, $CRB", IIC_BrCR, 2475 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>; 2476} // isCommutable 2477 2478def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD), 2479 (ins crbitrc:$CRA, crbitrc:$CRB), 2480 "crandc $CRD, $CRA, $CRB", IIC_BrCR, 2481 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>; 2482 2483def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD), 2484 (ins crbitrc:$CRA, crbitrc:$CRB), 2485 "crorc $CRD, $CRA, $CRB", IIC_BrCR, 2486 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>; 2487 2488let isCodeGenOnly = 1 in { 2489let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 2490def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins), 2491 "creqv $dst, $dst, $dst", IIC_BrCR, 2492 [(set i1:$dst, 1)]>; 2493 2494def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins), 2495 "crxor $dst, $dst, $dst", IIC_BrCR, 2496 [(set i1:$dst, 0)]>; 2497} 2498 2499let Defs = [CR1EQ], CRD = 6 in { 2500def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 2501 "creqv 6, 6, 6", IIC_BrCR, 2502 [(PPCcr6set)]>; 2503 2504def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 2505 "crxor 6, 6, 6", IIC_BrCR, 2506 [(PPCcr6unset)]>; 2507} 2508} 2509 2510// XFX-Form instructions. Instructions that deal with SPRs. 2511// 2512 2513def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR), 2514 "mfspr $RT, $SPR", IIC_SprMFSPR>; 2515def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT), 2516 "mtspr $SPR, $RT", IIC_SprMTSPR>; 2517 2518def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR), 2519 "mftb $RT, $SPR", IIC_SprMFTB>; 2520 2521def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR), 2522 "mfpmr $RT, $SPR", IIC_SprMFPMR>; 2523 2524def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT), 2525 "mtpmr $SPR, $RT", IIC_SprMTPMR>; 2526 2527 2528// A pseudo-instruction used to implement the read of the 64-bit cycle counter 2529// on a 32-bit target. 2530let hasSideEffects = 1 in 2531def ReadTB : PPCCustomInserterPseudo<(outs gprc:$lo, gprc:$hi), (ins), 2532 "#ReadTB", []>; 2533 2534let Uses = [CTR] in { 2535def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins), 2536 "mfctr $rT", IIC_SprMFSPR>, 2537 PPC970_DGroup_First, PPC970_Unit_FXU; 2538} 2539let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in { 2540def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 2541 "mtctr $rS", IIC_SprMTSPR>, 2542 PPC970_DGroup_First, PPC970_Unit_FXU; 2543} 2544let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in { 2545let Pattern = [(int_set_loop_iterations i32:$rS)] in 2546def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 2547 "mtctr $rS", IIC_SprMTSPR>, 2548 PPC970_DGroup_First, PPC970_Unit_FXU; 2549} 2550 2551let hasSideEffects = 0 in { 2552let Defs = [LR] in { 2553def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS), 2554 "mtlr $rS", IIC_SprMTSPR>, 2555 PPC970_DGroup_First, PPC970_Unit_FXU; 2556} 2557let Uses = [LR] in { 2558def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins), 2559 "mflr $rT", IIC_SprMFSPR>, 2560 PPC970_DGroup_First, PPC970_Unit_FXU; 2561} 2562} 2563 2564let hasSideEffects = 1 in { 2565 def MTUDSCR : XFXForm_7_ext<31, 467, 3, (outs), (ins gprc:$rX), 2566 "mtspr 3, $rX", IIC_SprMTSPR>, 2567 PPC970_DGroup_Single, PPC970_Unit_FXU; 2568 def MFUDSCR : XFXForm_1_ext<31, 339, 3, (outs gprc:$rX), (ins), 2569 "mfspr $rX, 3", IIC_SprMFSPR>, 2570 PPC970_DGroup_First, PPC970_Unit_FXU; 2571} 2572 2573// Disable these alias on AIX since they are not supported. 2574let Predicates = [ModernAs] in { 2575// Aliases for moving to/from dscr to mtspr/mfspr 2576def : InstAlias<"mtudscr $Rx", (MTUDSCR gprc:$Rx)>; 2577def : InstAlias<"mfudscr $Rx", (MFUDSCR gprc:$Rx)>; 2578} 2579 2580let isCodeGenOnly = 1 in { 2581 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed 2582 // like a GPR on the PPC970. As such, copies in and out have the same 2583 // performance characteristics as an OR instruction. 2584 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS), 2585 "mtspr 256, $rS", IIC_IntGeneral>, 2586 PPC970_DGroup_Single, PPC970_Unit_FXU; 2587 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins), 2588 "mfspr $rT, 256", IIC_IntGeneral>, 2589 PPC970_DGroup_First, PPC970_Unit_FXU; 2590 2591 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256, 2592 (outs VRSAVERC:$reg), (ins gprc:$rS), 2593 "mtspr 256, $rS", IIC_IntGeneral>, 2594 PPC970_DGroup_Single, PPC970_Unit_FXU; 2595 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), 2596 (ins VRSAVERC:$reg), 2597 "mfspr $rT, 256", IIC_IntGeneral>, 2598 PPC970_DGroup_First, PPC970_Unit_FXU; 2599} 2600 2601// Aliases for mtvrsave/mfvrsave to mfspr/mtspr. 2602def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>; 2603def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>; 2604 2605let hasSideEffects = 0 in { 2606// mtocrf's input needs to be prepared by shifting by an amount dependent 2607// on the cr register selected. Thus, post-ra anti-dep breaking must not 2608// later change that register assignment. 2609let hasExtraDefRegAllocReq = 1 in { 2610def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST), 2611 "mtocrf $FXM, $ST", IIC_BrMCRX>, 2612 PPC970_DGroup_First, PPC970_Unit_CRU; 2613 2614// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 2615// is dependent on the cr fields being set. 2616def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS), 2617 "mtcrf $FXM, $rS", IIC_BrMCRX>, 2618 PPC970_MicroCode, PPC970_Unit_CRU; 2619} // hasExtraDefRegAllocReq = 1 2620 2621// mfocrf's input needs to be prepared by shifting by an amount dependent 2622// on the cr register selected. Thus, post-ra anti-dep breaking must not 2623// later change that register assignment. 2624let hasExtraSrcRegAllocReq = 1 in { 2625def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM), 2626 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 2627 PPC970_DGroup_First, PPC970_Unit_CRU; 2628 2629// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 2630// is dependent on the cr fields being copied. 2631def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins), 2632 "mfcr $rT", IIC_SprMFCR>, 2633 PPC970_MicroCode, PPC970_Unit_CRU; 2634} // hasExtraSrcRegAllocReq = 1 2635 2636def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins), 2637 "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>; 2638} // hasSideEffects = 0 2639 2640def : InstAlias<"mtcr $rA", (MTCRF 255, gprc:$rA)>; 2641 2642let Predicates = [HasFPU] in { 2643// Custom inserter instruction to perform FADD in round-to-zero mode. 2644let Uses = [RM], mayRaiseFPException = 1 in { 2645 def FADDrtz: PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "", 2646 [(set f64:$FRT, (PPCany_faddrtz f64:$FRA, f64:$FRB))]>; 2647} 2648 2649// The above pseudo gets expanded to make use of the following instructions 2650// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. 2651 2652// When FM is 30/31, we are setting the 62/63 bit of FPSCR, the implicit-def 2653// RM should be set. 2654let hasSideEffects = 1, Defs = [RM] in { 2655def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 2656 "mtfsb0 $FM", IIC_IntMTFSB0, 2657 [(int_ppc_mtfsb0 timm:$FM)]>, 2658 PPC970_DGroup_Single, PPC970_Unit_FPU; 2659def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 2660 "mtfsb1 $FM", IIC_IntMTFSB0, 2661 [(int_ppc_mtfsb1 timm:$FM)]>, 2662 PPC970_DGroup_Single, PPC970_Unit_FPU; 2663} 2664 2665let Defs = [RM], hasSideEffects = 1 in { 2666 let isCodeGenOnly = 1 in 2667 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT), 2668 "mtfsf $FM, $rT", IIC_IntMTFSB0, 2669 [(int_ppc_mtfsf timm:$FM, f64:$rT)]>, 2670 PPC970_DGroup_Single, PPC970_Unit_FPU; 2671} 2672let Uses = [RM], hasSideEffects = 1 in { 2673 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins), 2674 "mffs $rT", IIC_IntMFFS, 2675 [(set f64:$rT, (PPCmffs))]>, 2676 PPC970_DGroup_Single, PPC970_Unit_FPU; 2677 2678 let Defs = [CR1] in 2679 def MFFS_rec : XForm_42<63, 583, (outs f8rc:$rT), (ins), 2680 "mffs. $rT", IIC_IntMFFS, []>, isRecordForm; 2681 2682 def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$rT), (ins), 2683 "mffsce $rT", IIC_IntMFFS, []>, 2684 PPC970_DGroup_Single, PPC970_Unit_FPU; 2685 2686 def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$rT), 2687 (ins f8rc:$FRB), "mffscdrn $rT, $FRB", 2688 IIC_IntMFFS, []>, 2689 PPC970_DGroup_Single, PPC970_Unit_FPU; 2690 2691 def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$rT), 2692 (ins u3imm:$DRM), 2693 "mffscdrni $rT, $DRM", 2694 IIC_IntMFFS, []>, 2695 PPC970_DGroup_Single, PPC970_Unit_FPU; 2696 2697 def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$rT), 2698 (ins f8rc:$FRB), "mffscrn $rT, $FRB", 2699 IIC_IntMFFS, []>, 2700 PPC970_DGroup_Single, PPC970_Unit_FPU; 2701 2702 def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$rT), 2703 (ins u2imm:$RM), "mffscrni $rT, $RM", 2704 IIC_IntMFFS, []>, 2705 PPC970_DGroup_Single, PPC970_Unit_FPU; 2706 2707 def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$rT), (ins), 2708 "mffsl $rT", IIC_IntMFFS, []>, 2709 PPC970_DGroup_Single, PPC970_Unit_FPU; 2710} 2711} 2712 2713let Predicates = [IsISA3_0] in { 2714def MODSW : XForm_8<31, 779, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2715 "modsw $rT, $rA, $rB", IIC_IntDivW, 2716 [(set i32:$rT, (srem i32:$rA, i32:$rB))]>; 2717def MODUW : XForm_8<31, 267, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2718 "moduw $rT, $rA, $rB", IIC_IntDivW, 2719 [(set i32:$rT, (urem i32:$rA, i32:$rB))]>; 2720let hasSideEffects = 1 in 2721def ADDEX : Z23Form_RTAB5_CY2<31, 170, (outs gprc:$rT), 2722 (ins gprc:$rA, gprc:$rB, u2imm:$CY), 2723 "addex $rT, $rA, $rB, $CY", IIC_IntGeneral, []>; 2724} 2725 2726let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2727// XO-Form instructions. Arithmetic instructions that can set overflow bit 2728let isCommutable = 1 in 2729defm ADD4 : XOForm_1rx<31, 266, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2730 "add", "$rT, $rA, $rB", IIC_IntSimple, 2731 [(set i32:$rT, (add i32:$rA, i32:$rB))]>; 2732let isCodeGenOnly = 1 in 2733def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB), 2734 "add $rT, $rA, $rB", IIC_IntSimple, 2735 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>; 2736let isCommutable = 1 in 2737defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2738 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 2739 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>, 2740 PPC970_DGroup_Cracked; 2741 2742defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2743 "divw", "$rT, $rA, $rB", IIC_IntDivW, 2744 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>; 2745defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2746 "divwu", "$rT, $rA, $rB", IIC_IntDivW, 2747 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>; 2748defm DIVWE : XOForm_1rcr<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2749 "divwe", "$rT, $rA, $rB", IIC_IntDivW, 2750 [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>, 2751 Requires<[HasExtDiv]>; 2752defm DIVWEU : XOForm_1rcr<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2753 "divweu", "$rT, $rA, $rB", IIC_IntDivW, 2754 [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>, 2755 Requires<[HasExtDiv]>; 2756let isCommutable = 1 in { 2757defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2758 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW, 2759 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>; 2760defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2761 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU, 2762 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>; 2763defm MULLW : XOForm_1rx<31, 235, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2764 "mullw", "$rT, $rA, $rB", IIC_IntMulHW, 2765 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>; 2766} // isCommutable 2767defm SUBF : XOForm_1rx<31, 40, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2768 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 2769 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>; 2770defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2771 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 2772 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>, 2773 PPC970_DGroup_Cracked; 2774defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA), 2775 "neg", "$rT, $rA", IIC_IntSimple, 2776 [(set i32:$rT, (ineg i32:$rA))]>; 2777let Uses = [CARRY] in { 2778let isCommutable = 1 in 2779defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2780 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 2781 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>; 2782defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA), 2783 "addme", "$rT, $rA", IIC_IntGeneral, 2784 [(set i32:$rT, (adde i32:$rA, -1))]>; 2785defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA), 2786 "addze", "$rT, $rA", IIC_IntGeneral, 2787 [(set i32:$rT, (adde i32:$rA, 0))]>; 2788defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2789 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 2790 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>; 2791defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA), 2792 "subfme", "$rT, $rA", IIC_IntGeneral, 2793 [(set i32:$rT, (sube -1, i32:$rA))]>; 2794defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA), 2795 "subfze", "$rT, $rA", IIC_IntGeneral, 2796 [(set i32:$rT, (sube 0, i32:$rA))]>; 2797} 2798} 2799 2800def : InstAlias<"sub $rA, $rB, $rC", (SUBF gprc:$rA, gprc:$rC, gprc:$rB)>; 2801def : InstAlias<"sub. $rA, $rB, $rC", (SUBF_rec gprc:$rA, gprc:$rC, gprc:$rB)>; 2802def : InstAlias<"subc $rA, $rB, $rC", (SUBFC gprc:$rA, gprc:$rC, gprc:$rB)>; 2803def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC_rec gprc:$rA, gprc:$rC, gprc:$rB)>; 2804 2805// A-Form instructions. Most of the instructions executed in the FPU are of 2806// this type. 2807// 2808let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 2809let mayRaiseFPException = 1, Uses = [RM] in { 2810let isCommutable = 1 in { 2811 defm FMADD : AForm_1r<63, 29, 2812 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2813 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2814 [(set f64:$FRT, (any_fma f64:$FRA, f64:$FRC, f64:$FRB))]>; 2815 defm FMADDS : AForm_1r<59, 29, 2816 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2817 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2818 [(set f32:$FRT, (any_fma f32:$FRA, f32:$FRC, f32:$FRB))]>; 2819 defm FMSUB : AForm_1r<63, 28, 2820 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2821 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2822 [(set f64:$FRT, 2823 (any_fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>; 2824 defm FMSUBS : AForm_1r<59, 28, 2825 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2826 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2827 [(set f32:$FRT, 2828 (any_fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>; 2829 defm FNMADD : AForm_1r<63, 31, 2830 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2831 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2832 [(set f64:$FRT, 2833 (fneg (any_fma f64:$FRA, f64:$FRC, f64:$FRB)))]>; 2834 defm FNMADDS : AForm_1r<59, 31, 2835 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2836 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2837 [(set f32:$FRT, 2838 (fneg (any_fma f32:$FRA, f32:$FRC, f32:$FRB)))]>; 2839 defm FNMSUB : AForm_1r<63, 30, 2840 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2841 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2842 [(set f64:$FRT, (fneg (any_fma f64:$FRA, f64:$FRC, 2843 (fneg f64:$FRB))))]>; 2844 defm FNMSUBS : AForm_1r<59, 30, 2845 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2846 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2847 [(set f32:$FRT, (fneg (any_fma f32:$FRA, f32:$FRC, 2848 (fneg f32:$FRB))))]>; 2849} // isCommutable 2850} 2851// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 2852// having 4 of these, force the comparison to always be an 8-byte double (code 2853// should use an FMRSD if the input comparison value really wants to be a float) 2854// and 4/8 byte forms for the result and operand type.. 2855let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2856defm FSELD : AForm_1r<63, 23, 2857 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2858 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2859 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>; 2860defm FSELS : AForm_1r<63, 23, 2861 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2862 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2863 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>; 2864let Uses = [RM], mayRaiseFPException = 1 in { 2865 let isCommutable = 1 in { 2866 defm FADD : AForm_2r<63, 21, 2867 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2868 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub, 2869 [(set f64:$FRT, (any_fadd f64:$FRA, f64:$FRB))]>; 2870 defm FADDS : AForm_2r<59, 21, 2871 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2872 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral, 2873 [(set f32:$FRT, (any_fadd f32:$FRA, f32:$FRB))]>; 2874 } // isCommutable 2875 defm FDIV : AForm_2r<63, 18, 2876 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2877 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD, 2878 [(set f64:$FRT, (any_fdiv f64:$FRA, f64:$FRB))]>; 2879 defm FDIVS : AForm_2r<59, 18, 2880 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2881 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS, 2882 [(set f32:$FRT, (any_fdiv f32:$FRA, f32:$FRB))]>; 2883 let isCommutable = 1 in { 2884 defm FMUL : AForm_3r<63, 25, 2885 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC), 2886 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused, 2887 [(set f64:$FRT, (any_fmul f64:$FRA, f64:$FRC))]>; 2888 defm FMULS : AForm_3r<59, 25, 2889 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC), 2890 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral, 2891 [(set f32:$FRT, (any_fmul f32:$FRA, f32:$FRC))]>; 2892 } // isCommutable 2893 defm FSUB : AForm_2r<63, 20, 2894 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2895 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub, 2896 [(set f64:$FRT, (any_fsub f64:$FRA, f64:$FRB))]>; 2897 defm FSUBS : AForm_2r<59, 20, 2898 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2899 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral, 2900 [(set f32:$FRT, (any_fsub f32:$FRA, f32:$FRB))]>; 2901 } 2902} 2903 2904let hasSideEffects = 0 in { 2905let PPC970_Unit = 1 in { // FXU Operations. 2906 let isSelect = 1 in 2907 def ISEL : AForm_4<31, 15, 2908 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond), 2909 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 2910 []>; 2911} 2912 2913let PPC970_Unit = 1 in { // FXU Operations. 2914// M-Form instructions. rotate and mask instructions. 2915// 2916let isCommutable = 1 in { 2917// RLWIMI can be commuted if the rotate amount is zero. 2918defm RLWIMI : MForm_2r<20, (outs gprc:$rA), 2919 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB, 2920 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 2921 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 2922 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 2923} 2924let BaseName = "rlwinm" in { 2925def RLWINM : MForm_2<21, 2926 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 2927 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 2928 []>, RecFormRel; 2929let Defs = [CR0] in 2930def RLWINM_rec : MForm_2<21, 2931 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 2932 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 2933 []>, isRecordForm, RecFormRel, PPC970_DGroup_Cracked; 2934} 2935defm RLWNM : MForm_2r<23, (outs gprc:$rA), 2936 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME), 2937 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 2938 []>; 2939} 2940} // hasSideEffects = 0 2941 2942//===----------------------------------------------------------------------===// 2943// PowerPC Instruction Patterns 2944// 2945 2946// Arbitrary immediate support. Implement in terms of LIS/ORI. 2947def : Pat<(i32 imm:$imm), 2948 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 2949 2950// Implement the 'not' operation with the NOR instruction. 2951def i32not : OutPatFrag<(ops node:$in), 2952 (NOR $in, $in)>; 2953def : Pat<(not i32:$in), 2954 (i32not $in)>; 2955 2956// ADD an arbitrary immediate. 2957def : Pat<(add i32:$in, imm:$imm), 2958 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 2959// OR an arbitrary immediate. 2960def : Pat<(or i32:$in, imm:$imm), 2961 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 2962// XOR an arbitrary immediate. 2963def : Pat<(xor i32:$in, imm:$imm), 2964 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 2965// SUBFIC 2966def : Pat<(sub imm32SExt16:$imm, i32:$in), 2967 (SUBFIC $in, imm:$imm)>; 2968 2969// SHL/SRL 2970def : Pat<(shl i32:$in, (i32 imm:$imm)), 2971 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>; 2972def : Pat<(srl i32:$in, (i32 imm:$imm)), 2973 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>; 2974 2975// ROTL 2976def : Pat<(rotl i32:$in, i32:$sh), 2977 (RLWNM $in, $sh, 0, 31)>; 2978def : Pat<(rotl i32:$in, (i32 imm:$imm)), 2979 (RLWINM $in, imm:$imm, 0, 31)>; 2980 2981// RLWNM 2982def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm), 2983 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 2984 2985// Calls 2986def : Pat<(PPCcall (i32 tglobaladdr:$dst)), 2987 (BL tglobaladdr:$dst)>; 2988 2989def : Pat<(PPCcall (i32 texternalsym:$dst)), 2990 (BL texternalsym:$dst)>; 2991 2992def : Pat<(PPCcall_rm (i32 tglobaladdr:$dst)), 2993 (BL_RM tglobaladdr:$dst)>; 2994 2995def : Pat<(PPCcall_rm (i32 texternalsym:$dst)), 2996 (BL_RM texternalsym:$dst)>; 2997 2998// Calls for AIX only 2999def : Pat<(PPCcall (i32 mcsym:$dst)), 3000 (BL mcsym:$dst)>; 3001 3002def : Pat<(PPCcall_nop (i32 mcsym:$dst)), 3003 (BL_NOP mcsym:$dst)>; 3004 3005def : Pat<(PPCcall_nop (i32 texternalsym:$dst)), 3006 (BL_NOP texternalsym:$dst)>; 3007 3008def : Pat<(PPCcall_rm (i32 mcsym:$dst)), 3009 (BL_RM mcsym:$dst)>; 3010 3011def : Pat<(PPCcall_nop_rm (i32 mcsym:$dst)), 3012 (BL_NOP_RM mcsym:$dst)>; 3013 3014def : Pat<(PPCcall_nop_rm (i32 texternalsym:$dst)), 3015 (BL_NOP_RM texternalsym:$dst)>; 3016 3017def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 3018 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 3019 3020def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 3021 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 3022 3023def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 3024 (TCRETURNri CTRRC:$dst, imm:$imm)>; 3025 3026def : Pat<(int_ppc_readflm), (MFFS)>; 3027 3028// Hi and Lo for Darwin Global Addresses. 3029def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 3030def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 3031def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 3032def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 3033def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 3034def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 3035def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 3036def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 3037def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in), 3038 (ADDIS $in, tglobaltlsaddr:$g)>; 3039def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in), 3040 (ADDI $in, tglobaltlsaddr:$g)>; 3041def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)), 3042 (ADDIS $in, tglobaladdr:$g)>; 3043def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)), 3044 (ADDIS $in, tconstpool:$g)>; 3045def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)), 3046 (ADDIS $in, tjumptable:$g)>; 3047def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)), 3048 (ADDIS $in, tblockaddress:$g)>; 3049 3050// Support for thread-local storage. 3051def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT", 3052 [(set i32:$rD, (PPCppc32GOT))]>; 3053 3054// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode. 3055// This uses two output registers, the first as the real output, the second as a 3056// temporary register, used internally in code generation. 3057def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT", 3058 []>, NoEncode<"$rT">; 3059 3060def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc_nor0:$rD), (ins s16imm:$disp, gprc_nor0:$reg), 3061 "#LDgotTprelL32", 3062 [(set i32:$rD, 3063 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>; 3064def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g), 3065 (ADD4TLS $in, tglobaltlsaddr:$g)>; 3066 3067def ADDItlsgdL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3068 "#ADDItlsgdL32", 3069 [(set i32:$rD, 3070 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>; 3071// LR is a true define, while the rest of the Defs are clobbers. R3 is 3072// explicitly defined when this op is created, so not mentioned here. 3073let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3074 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3075def GETtlsADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3076 "GETtlsADDR32", 3077 [(set i32:$rD, 3078 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>; 3079// R3 is explicitly defined when this op is created, so not mentioned here. 3080// The rest of the Defs are the exact set of registers that will be clobbered by 3081// the call. 3082let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3083 Defs = [R0,R4,R5,R11,LR,CR0] in 3084def GETtlsADDR32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle), 3085 "GETtlsADDR32AIX", 3086 [(set i32:$rD, 3087 (PPCgetTlsAddr i32:$offset, i32:$handle))]>; 3088// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR 3089// are true defines while the rest of the Defs are clobbers. 3090let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3091 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3092def ADDItlsgdLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3093 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3094 "#ADDItlsgdLADDR32", 3095 [(set i32:$rD, 3096 (PPCaddiTlsgdLAddr i32:$reg, 3097 tglobaltlsaddr:$disp, 3098 tglobaltlsaddr:$sym))]>; 3099def ADDItlsldL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3100 "#ADDItlsldL32", 3101 [(set i32:$rD, 3102 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>; 3103// This pseudo is expanded to two copies to put the variable offset in R4 and 3104// the region handle in R3 and GETtlsADDR32AIX. 3105def TLSGDAIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle), 3106 "#TLSGDAIX", 3107 [(set i32:$rD, 3108 (PPCTlsgdAIX i32:$offset, i32:$handle))]>; 3109// LR is a true define, while the rest of the Defs are clobbers. R3 is 3110// explicitly defined when this op is created, so not mentioned here. 3111let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3112 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3113def GETtlsldADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3114 "GETtlsldADDR32", 3115 [(set i32:$rD, 3116 (PPCgetTlsldAddr i32:$reg, 3117 tglobaltlsaddr:$sym))]>; 3118// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR 3119// are true defines while the rest of the Defs are clobbers. 3120let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3121 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3122def ADDItlsldLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3123 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3124 "#ADDItlsldLADDR32", 3125 [(set i32:$rD, 3126 (PPCaddiTlsldLAddr i32:$reg, 3127 tglobaltlsaddr:$disp, 3128 tglobaltlsaddr:$sym))]>; 3129def ADDIdtprelL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3130 "#ADDIdtprelL32", 3131 [(set i32:$rD, 3132 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>; 3133def ADDISdtprelHA32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3134 "#ADDISdtprelHA32", 3135 [(set i32:$rD, 3136 (PPCaddisDtprelHA i32:$reg, 3137 tglobaltlsaddr:$disp))]>; 3138 3139// Support for Position-independent code 3140def LWZtoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), 3141 "#LWZtoc", 3142 [(set i32:$rD, 3143 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3144def LWZtocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc_nor0:$reg), 3145 "#LWZtocL", 3146 [(set i32:$rD, 3147 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3148def ADDIStocHA : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp), 3149 "#ADDIStocHA", 3150 [(set i32:$rD, 3151 (PPCtoc_entry i32:$reg, tglobaladdr:$disp))]>; 3152// Local Data Transform 3153def ADDItoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), 3154 "#ADDItoc", 3155 [(set i32:$rD, 3156 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3157 3158// Get Global (GOT) Base Register offset, from the word immediately preceding 3159// the function label. 3160def UpdateGBR : PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>; 3161 3162// Pseudo-instruction marked for deletion. When deleting the instruction would 3163// cause iterator invalidation in MIR transformation passes, this pseudo can be 3164// used instead. It will be removed unconditionally at pre-emit time (prior to 3165// branch selection). 3166def UNENCODED_NOP: PPCEmitTimePseudo<(outs), (ins), "#UNENCODED_NOP", []>; 3167 3168// Standard shifts. These are represented separately from the real shifts above 3169// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 3170// amounts. 3171def : Pat<(sra i32:$rS, i32:$rB), 3172 (SRAW $rS, $rB)>; 3173def : Pat<(srl i32:$rS, i32:$rB), 3174 (SRW $rS, $rB)>; 3175def : Pat<(shl i32:$rS, i32:$rB), 3176 (SLW $rS, $rB)>; 3177 3178def : Pat<(i32 (zextloadi1 DForm:$src)), 3179 (LBZ DForm:$src)>; 3180def : Pat<(i32 (zextloadi1 XForm:$src)), 3181 (LBZX XForm:$src)>; 3182def : Pat<(i32 (extloadi1 DForm:$src)), 3183 (LBZ DForm:$src)>; 3184def : Pat<(i32 (extloadi1 XForm:$src)), 3185 (LBZX XForm:$src)>; 3186def : Pat<(i32 (extloadi8 DForm:$src)), 3187 (LBZ DForm:$src)>; 3188def : Pat<(i32 (extloadi8 XForm:$src)), 3189 (LBZX XForm:$src)>; 3190def : Pat<(i32 (extloadi16 DForm:$src)), 3191 (LHZ DForm:$src)>; 3192def : Pat<(i32 (extloadi16 XForm:$src)), 3193 (LHZX XForm:$src)>; 3194let Predicates = [HasFPU] in { 3195def : Pat<(f64 (extloadf32 DForm:$src)), 3196 (COPY_TO_REGCLASS (LFS DForm:$src), F8RC)>; 3197def : Pat<(f64 (extloadf32 XForm:$src)), 3198 (COPY_TO_REGCLASS (LFSX XForm:$src), F8RC)>; 3199 3200def : Pat<(f64 (any_fpextend f32:$src)), 3201 (COPY_TO_REGCLASS $src, F8RC)>; 3202} 3203 3204// Only seq_cst fences require the heavyweight sync (SYNC 0). 3205// All others can use the lightweight sync (SYNC 1). 3206// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html 3207// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits 3208// versions of Power. 3209def : Pat<(atomic_fence (i64 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3210def : Pat<(atomic_fence (i32 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3211def : Pat<(atomic_fence (timm), (timm)), (SYNC 1)>, Requires<[HasSYNC]>; 3212def : Pat<(atomic_fence (timm), (timm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 3213 3214let Predicates = [HasFPU] in { 3215// Additional fnmsub patterns for custom node 3216def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C), 3217 (FNMSUB $A, $B, $C)>; 3218def : Pat<(PPCfnmsub f32:$A, f32:$B, f32:$C), 3219 (FNMSUBS $A, $B, $C)>; 3220def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)), 3221 (FMSUB $A, $B, $C)>; 3222def : Pat<(fneg (PPCfnmsub f32:$A, f32:$B, f32:$C)), 3223 (FMSUBS $A, $B, $C)>; 3224def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)), 3225 (FNMADD $A, $B, $C)>; 3226def : Pat<(PPCfnmsub f32:$A, f32:$B, (fneg f32:$C)), 3227 (FNMADDS $A, $B, $C)>; 3228 3229// FCOPYSIGN's operand types need not agree. 3230def : Pat<(fcopysign f64:$frB, f32:$frA), 3231 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>; 3232def : Pat<(fcopysign f32:$frB, f64:$frA), 3233 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>; 3234} 3235 3236// XL Compat intrinsics. 3237def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (FMSUB $A, $B, $C)>; 3238def : Pat<(int_ppc_fmsubs f32:$A, f32:$B, f32:$C), (FMSUBS $A, $B, $C)>; 3239def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (FNMADD $A, $B, $C)>; 3240def : Pat<(int_ppc_fnmadds f32:$A, f32:$B, f32:$C), (FNMADDS $A, $B, $C)>; 3241def : Pat<(int_ppc_fre f64:$A), (FRE $A)>; 3242def : Pat<(int_ppc_fres f32:$A), (FRES $A)>; 3243def : Pat<(int_ppc_fnabs f64:$A), (FNABSD $A)>; 3244def : Pat<(int_ppc_fnabss f32:$A), (FNABSS $A)>; 3245 3246include "PPCInstrAltivec.td" 3247include "PPCInstrSPE.td" 3248include "PPCInstr64Bit.td" 3249include "PPCInstrVSX.td" 3250include "PPCInstrHTM.td" 3251 3252def crnot : OutPatFrag<(ops node:$in), 3253 (CRNOR $in, $in)>; 3254def : Pat<(not i1:$in), 3255 (crnot $in)>; 3256 3257// Prefixed instructions may require access to the above defs at a later 3258// time so we include this after the def. 3259include "PPCInstrP10.td" 3260include "PPCInstrMMA.td" 3261 3262// Patterns for arithmetic i1 operations. 3263def : Pat<(add i1:$a, i1:$b), 3264 (CRXOR $a, $b)>; 3265def : Pat<(sub i1:$a, i1:$b), 3266 (CRXOR $a, $b)>; 3267def : Pat<(mul i1:$a, i1:$b), 3268 (CRAND $a, $b)>; 3269 3270// We're sometimes asked to materialize i1 -1, which is just 1 in this case 3271// (-1 is used to mean all bits set). 3272def : Pat<(i1 -1), (CRSET)>; 3273 3274// i1 extensions, implemented in terms of isel. 3275def : Pat<(i32 (zext i1:$in)), 3276 (SELECT_I4 $in, (LI 1), (LI 0))>; 3277def : Pat<(i32 (sext i1:$in)), 3278 (SELECT_I4 $in, (LI -1), (LI 0))>; 3279 3280def : Pat<(i64 (zext i1:$in)), 3281 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3282def : Pat<(i64 (sext i1:$in)), 3283 (SELECT_I8 $in, (LI8 -1), (LI8 0))>; 3284 3285// FIXME: We should choose either a zext or a sext based on other constants 3286// already around. 3287def : Pat<(i32 (anyext i1:$in)), 3288 (SELECT_I4 $in, (LI 1), (LI 0))>; 3289def : Pat<(i64 (anyext i1:$in)), 3290 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3291 3292// match setcc on i1 variables. 3293// CRANDC is: 3294// 1 1 : F 3295// 1 0 : T 3296// 0 1 : F 3297// 0 0 : F 3298// 3299// LT is: 3300// -1 -1 : F 3301// -1 0 : T 3302// 0 -1 : F 3303// 0 0 : F 3304// 3305// ULT is: 3306// 1 1 : F 3307// 1 0 : F 3308// 0 1 : T 3309// 0 0 : F 3310def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)), 3311 (CRANDC $s1, $s2)>; 3312def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)), 3313 (CRANDC $s2, $s1)>; 3314// CRORC is: 3315// 1 1 : T 3316// 1 0 : T 3317// 0 1 : F 3318// 0 0 : T 3319// 3320// LE is: 3321// -1 -1 : T 3322// -1 0 : T 3323// 0 -1 : F 3324// 0 0 : T 3325// 3326// ULE is: 3327// 1 1 : T 3328// 1 0 : F 3329// 0 1 : T 3330// 0 0 : T 3331def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)), 3332 (CRORC $s1, $s2)>; 3333def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), 3334 (CRORC $s2, $s1)>; 3335 3336def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)), 3337 (CREQV $s1, $s2)>; 3338 3339// GE is: 3340// -1 -1 : T 3341// -1 0 : F 3342// 0 -1 : T 3343// 0 0 : T 3344// 3345// UGE is: 3346// 1 1 : T 3347// 1 0 : T 3348// 0 1 : F 3349// 0 0 : T 3350def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), 3351 (CRORC $s2, $s1)>; 3352def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)), 3353 (CRORC $s1, $s2)>; 3354 3355// GT is: 3356// -1 -1 : F 3357// -1 0 : F 3358// 0 -1 : T 3359// 0 0 : F 3360// 3361// UGT is: 3362// 1 1 : F 3363// 1 0 : T 3364// 0 1 : F 3365// 0 0 : F 3366def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)), 3367 (CRANDC $s2, $s1)>; 3368def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)), 3369 (CRANDC $s1, $s2)>; 3370 3371def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)), 3372 (CRXOR $s1, $s2)>; 3373 3374// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE, 3375// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for 3376// floating-point types. 3377 3378multiclass CRNotPat<dag pattern, dag result> { 3379 def : Pat<pattern, (crnot result)>; 3380 def : Pat<(not pattern), result>; 3381 3382 // We can also fold the crnot into an extension: 3383 def : Pat<(i32 (zext pattern)), 3384 (SELECT_I4 result, (LI 0), (LI 1))>; 3385 def : Pat<(i32 (sext pattern)), 3386 (SELECT_I4 result, (LI 0), (LI -1))>; 3387 3388 // We can also fold the crnot into an extension: 3389 def : Pat<(i64 (zext pattern)), 3390 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3391 def : Pat<(i64 (sext pattern)), 3392 (SELECT_I8 result, (LI8 0), (LI8 -1))>; 3393 3394 // FIXME: We should choose either a zext or a sext based on other constants 3395 // already around. 3396 def : Pat<(i32 (anyext pattern)), 3397 (SELECT_I4 result, (LI 0), (LI 1))>; 3398 3399 def : Pat<(i64 (anyext pattern)), 3400 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3401} 3402 3403// FIXME: Because of what seems like a bug in TableGen's type-inference code, 3404// we need to write imm:$imm in the output patterns below, not just $imm, or 3405// else the resulting matcher will not correctly add the immediate operand 3406// (making it a register operand instead). 3407 3408// extended SETCC. 3409multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag, 3410 OutPatFrag rfrag, OutPatFrag rfrag8> { 3411 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))), 3412 (rfrag $s1)>; 3413 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))), 3414 (rfrag8 $s1)>; 3415 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))), 3416 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3417 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))), 3418 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3419 3420 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))), 3421 (rfrag $s1)>; 3422 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))), 3423 (rfrag8 $s1)>; 3424 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))), 3425 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3426 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))), 3427 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3428} 3429 3430// Note that we do all inversions below with i(32|64)not, instead of using 3431// (xori x, 1) because on the A2 nor has single-cycle latency while xori 3432// has 2-cycle latency. 3433 3434defm : ExtSetCCPat<SETEQ, 3435 PatFrag<(ops node:$in, node:$cc), 3436 (setcc $in, 0, $cc)>, 3437 OutPatFrag<(ops node:$in), 3438 (RLWINM (CNTLZW $in), 27, 31, 31)>, 3439 OutPatFrag<(ops node:$in), 3440 (RLDICL (CNTLZD $in), 58, 63)> >; 3441 3442defm : ExtSetCCPat<SETNE, 3443 PatFrag<(ops node:$in, node:$cc), 3444 (setcc $in, 0, $cc)>, 3445 OutPatFrag<(ops node:$in), 3446 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>, 3447 OutPatFrag<(ops node:$in), 3448 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >; 3449 3450defm : ExtSetCCPat<SETLT, 3451 PatFrag<(ops node:$in, node:$cc), 3452 (setcc $in, 0, $cc)>, 3453 OutPatFrag<(ops node:$in), 3454 (RLWINM $in, 1, 31, 31)>, 3455 OutPatFrag<(ops node:$in), 3456 (RLDICL $in, 1, 63)> >; 3457 3458defm : ExtSetCCPat<SETGE, 3459 PatFrag<(ops node:$in, node:$cc), 3460 (setcc $in, 0, $cc)>, 3461 OutPatFrag<(ops node:$in), 3462 (RLWINM (i32not $in), 1, 31, 31)>, 3463 OutPatFrag<(ops node:$in), 3464 (RLDICL (i64not $in), 1, 63)> >; 3465 3466defm : ExtSetCCPat<SETGT, 3467 PatFrag<(ops node:$in, node:$cc), 3468 (setcc $in, 0, $cc)>, 3469 OutPatFrag<(ops node:$in), 3470 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>, 3471 OutPatFrag<(ops node:$in), 3472 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >; 3473 3474defm : ExtSetCCPat<SETLE, 3475 PatFrag<(ops node:$in, node:$cc), 3476 (setcc $in, 0, $cc)>, 3477 OutPatFrag<(ops node:$in), 3478 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>, 3479 OutPatFrag<(ops node:$in), 3480 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >; 3481 3482defm : ExtSetCCPat<SETLT, 3483 PatFrag<(ops node:$in, node:$cc), 3484 (setcc $in, -1, $cc)>, 3485 OutPatFrag<(ops node:$in), 3486 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>, 3487 OutPatFrag<(ops node:$in), 3488 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3489 3490defm : ExtSetCCPat<SETGE, 3491 PatFrag<(ops node:$in, node:$cc), 3492 (setcc $in, -1, $cc)>, 3493 OutPatFrag<(ops node:$in), 3494 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>, 3495 OutPatFrag<(ops node:$in), 3496 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3497 3498defm : ExtSetCCPat<SETGT, 3499 PatFrag<(ops node:$in, node:$cc), 3500 (setcc $in, -1, $cc)>, 3501 OutPatFrag<(ops node:$in), 3502 (RLWINM (i32not $in), 1, 31, 31)>, 3503 OutPatFrag<(ops node:$in), 3504 (RLDICL (i64not $in), 1, 63)> >; 3505 3506defm : ExtSetCCPat<SETLE, 3507 PatFrag<(ops node:$in, node:$cc), 3508 (setcc $in, -1, $cc)>, 3509 OutPatFrag<(ops node:$in), 3510 (RLWINM $in, 1, 31, 31)>, 3511 OutPatFrag<(ops node:$in), 3512 (RLDICL $in, 1, 63)> >; 3513 3514// An extended SETCC with shift amount. 3515multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag, 3516 OutPatFrag rfrag, OutPatFrag rfrag8> { 3517 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3518 (rfrag $s1, $sa)>; 3519 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3520 (rfrag8 $s1, $sa)>; 3521 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3522 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3523 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3524 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3525 3526 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3527 (rfrag $s1, $sa)>; 3528 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3529 (rfrag8 $s1, $sa)>; 3530 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3531 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3532 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3533 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3534} 3535 3536defm : ExtSetCCShiftPat<SETNE, 3537 PatFrag<(ops node:$in, node:$sa, node:$cc), 3538 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3539 OutPatFrag<(ops node:$in, node:$sa), 3540 (RLWNM $in, (SUBFIC $sa, 32), 31, 31)>, 3541 OutPatFrag<(ops node:$in, node:$sa), 3542 (RLDCL $in, (SUBFIC $sa, 64), 63)> >; 3543 3544defm : ExtSetCCShiftPat<SETEQ, 3545 PatFrag<(ops node:$in, node:$sa, node:$cc), 3546 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3547 OutPatFrag<(ops node:$in, node:$sa), 3548 (RLWNM (i32not $in), 3549 (SUBFIC $sa, 32), 31, 31)>, 3550 OutPatFrag<(ops node:$in, node:$sa), 3551 (RLDCL (i64not $in), 3552 (SUBFIC $sa, 64), 63)> >; 3553 3554// SETCC for i32. 3555def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)), 3556 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3557def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)), 3558 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3559def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)), 3560 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3561def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)), 3562 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3563def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)), 3564 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3565def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)), 3566 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3567 3568// For non-equality comparisons, the default code would materialize the 3569// constant, then compare against it, like this: 3570// lis r2, 4660 3571// ori r2, r2, 22136 3572// cmpw cr0, r3, r2 3573// beq cr0,L6 3574// Since we are just comparing for equality, we can emit this instead: 3575// xoris r0,r3,0x1234 3576// cmplwi cr0,r0,0x5678 3577// beq cr0,L6 3578 3579def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)), 3580 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3581 (LO16 imm:$imm)), sub_eq)>; 3582 3583def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)), 3584 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3585def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)), 3586 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3587def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)), 3588 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3589def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)), 3590 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3591def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)), 3592 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3593 3594// SETCC for i64. 3595def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)), 3596 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3597def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)), 3598 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3599def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)), 3600 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3601def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)), 3602 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3603def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)), 3604 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3605def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)), 3606 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3607 3608// For non-equality comparisons, the default code would materialize the 3609// constant, then compare against it, like this: 3610// lis r2, 4660 3611// ori r2, r2, 22136 3612// cmpd cr0, r3, r2 3613// beq cr0,L6 3614// Since we are just comparing for equality, we can emit this instead: 3615// xoris r0,r3,0x1234 3616// cmpldi cr0,r0,0x5678 3617// beq cr0,L6 3618 3619def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)), 3620 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3621 (LO16 imm:$imm)), sub_eq)>; 3622 3623def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)), 3624 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3625def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)), 3626 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3627def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)), 3628 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3629def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)), 3630 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3631def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)), 3632 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3633 3634let Predicates = [IsNotISA3_1] in { 3635// Instantiations of CRNotPat for i32. 3636defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)), 3637 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3638defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)), 3639 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3640defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)), 3641 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3642defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)), 3643 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3644defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)), 3645 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3646defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)), 3647 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3648 3649defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 3650 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3651 (LO16 imm:$imm)), sub_eq)>; 3652 3653defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)), 3654 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3655defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)), 3656 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3657defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)), 3658 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3659defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)), 3660 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3661defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)), 3662 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3663 3664// Instantiations of CRNotPat for i64. 3665defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)), 3666 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3667defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)), 3668 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3669defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)), 3670 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3671defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)), 3672 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3673defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)), 3674 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3675defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)), 3676 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3677 3678defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 3679 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3680 (LO16 imm:$imm)), sub_eq)>; 3681 3682defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)), 3683 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3684defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)), 3685 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3686defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)), 3687 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3688defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)), 3689 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3690defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)), 3691 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3692} 3693 3694multiclass FSetCCPat<SDPatternOperator SetCC, ValueType Ty, I FCmp> { 3695 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 3696 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3697 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 3698 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3699 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 3700 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3701 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 3702 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3703 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)), 3704 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3705 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 3706 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3707 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)), 3708 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 3709 3710 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOLT)), 3711 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3712 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)), 3713 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3714 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOGT)), 3715 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3716 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGT)), 3717 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3718 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOEQ)), 3719 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3720 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETEQ)), 3721 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3722 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUO)), 3723 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 3724} 3725 3726let Predicates = [HasFPU] in { 3727// FCMPU: If either of the operands is a Signaling NaN, then VXSNAN is set. 3728// SETCC for f32. 3729defm : FSetCCPat<any_fsetcc, f32, FCMPUS>; 3730 3731// SETCC for f64. 3732defm : FSetCCPat<any_fsetcc, f64, FCMPUD>; 3733 3734// SETCC for f128. 3735defm : FSetCCPat<any_fsetcc, f128, XSCMPUQP>; 3736 3737// FCMPO: If either of the operands is a Signaling NaN, then VXSNAN is set and, 3738// if neither operand is a Signaling NaN but at least one operand is a Quiet NaN, 3739// then VXVC is set. 3740// SETCCS for f32. 3741defm : FSetCCPat<strict_fsetccs, f32, FCMPOS>; 3742 3743// SETCCS for f64. 3744defm : FSetCCPat<strict_fsetccs, f64, FCMPOD>; 3745 3746// SETCCS for f128. 3747defm : FSetCCPat<strict_fsetccs, f128, XSCMPOQP>; 3748} 3749 3750// This must be in this file because it relies on patterns defined in this file 3751// after the inclusion of the instruction sets. 3752let Predicates = [HasSPE] in { 3753// SETCC for f32. 3754def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOLT)), 3755 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3756def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLT)), 3757 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3758def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOGT)), 3759 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3760def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGT)), 3761 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3762def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOEQ)), 3763 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3764def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETEQ)), 3765 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3766 3767defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUGE)), 3768 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3769defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGE)), 3770 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 3771defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETULE)), 3772 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3773defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLE)), 3774 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 3775defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUNE)), 3776 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3777defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETNE)), 3778 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 3779 3780// SETCC for f64. 3781def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOLT)), 3782 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3783def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLT)), 3784 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3785def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOGT)), 3786 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 3787def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGT)), 3788 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 3789def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOEQ)), 3790 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 3791def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETEQ)), 3792 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 3793 3794defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUGE)), 3795 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3796defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGE)), 3797 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 3798defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETULE)), 3799 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 3800defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLE)), 3801 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 3802defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUNE)), 3803 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 3804defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETNE)), 3805 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 3806} 3807// match select on i1 variables: 3808def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)), 3809 (CROR (CRAND $cond , $tval), 3810 (CRAND (crnot $cond), $fval))>; 3811 3812// match selectcc on i1 variables: 3813// select (lhs == rhs), tval, fval is: 3814// ((lhs == rhs) & tval) | (!(lhs == rhs) & fval) 3815def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)), 3816 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 3817 (CRAND (CRORC $rhs, $lhs), $fval))>; 3818def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)), 3819 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 3820 (CRAND (CRORC $lhs, $rhs), $fval))>; 3821def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)), 3822 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 3823 (CRAND (CRANDC $rhs, $lhs), $fval))>; 3824def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)), 3825 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 3826 (CRAND (CRANDC $lhs, $rhs), $fval))>; 3827def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)), 3828 (CROR (CRAND (CREQV $lhs, $rhs), $tval), 3829 (CRAND (CRXOR $lhs, $rhs), $fval))>; 3830def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)), 3831 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 3832 (CRAND (CRANDC $lhs, $rhs), $fval))>; 3833def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)), 3834 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 3835 (CRAND (CRANDC $rhs, $lhs), $fval))>; 3836def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)), 3837 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 3838 (CRAND (CRORC $lhs, $rhs), $fval))>; 3839def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)), 3840 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 3841 (CRAND (CRORC $rhs, $lhs), $fval))>; 3842def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)), 3843 (CROR (CRAND (CREQV $lhs, $rhs), $fval), 3844 (CRAND (CRXOR $lhs, $rhs), $tval))>; 3845 3846// match selectcc on i1 variables with non-i1 output. 3847def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)), 3848 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 3849def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)), 3850 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 3851def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)), 3852 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 3853def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)), 3854 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 3855def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)), 3856 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>; 3857def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)), 3858 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 3859def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)), 3860 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 3861def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)), 3862 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 3863def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)), 3864 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 3865def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)), 3866 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>; 3867 3868def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)), 3869 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 3870def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)), 3871 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 3872def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)), 3873 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 3874def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)), 3875 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 3876def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)), 3877 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>; 3878def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)), 3879 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 3880def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)), 3881 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 3882def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)), 3883 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 3884def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)), 3885 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 3886def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)), 3887 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>; 3888 3889let Predicates = [HasFPU] in { 3890def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), 3891 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 3892def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), 3893 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 3894def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), 3895 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 3896def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), 3897 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 3898def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), 3899 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>; 3900def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), 3901 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 3902def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)), 3903 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 3904def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), 3905 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 3906def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)), 3907 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 3908def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), 3909 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>; 3910 3911def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), 3912 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 3913def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)), 3914 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 3915def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), 3916 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 3917def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)), 3918 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 3919def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), 3920 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>; 3921def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), 3922 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 3923def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), 3924 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 3925def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), 3926 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 3927def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), 3928 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 3929def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), 3930 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>; 3931} 3932 3933def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLT)), 3934 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 3935def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULT)), 3936 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 3937def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLE)), 3938 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 3939def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULE)), 3940 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 3941def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETEQ)), 3942 (SELECT_F16 (CREQV $lhs, $rhs), $tval, $fval)>; 3943def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGE)), 3944 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 3945def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGE)), 3946 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 3947def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGT)), 3948 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 3949def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGT)), 3950 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 3951def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETNE)), 3952 (SELECT_F16 (CRXOR $lhs, $rhs), $tval, $fval)>; 3953 3954def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)), 3955 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 3956def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)), 3957 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 3958def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)), 3959 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 3960def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)), 3961 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 3962def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)), 3963 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>; 3964def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)), 3965 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 3966def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)), 3967 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 3968def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)), 3969 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 3970def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)), 3971 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 3972def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)), 3973 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>; 3974 3975def ANDI_rec_1_EQ_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 3976 "#ANDI_rec_1_EQ_BIT", 3977 [(set i1:$dst, (trunc (not i32:$in)))]>; 3978def ANDI_rec_1_GT_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 3979 "#ANDI_rec_1_GT_BIT", 3980 [(set i1:$dst, (trunc i32:$in))]>; 3981 3982def ANDI_rec_1_EQ_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 3983 "#ANDI_rec_1_EQ_BIT8", 3984 [(set i1:$dst, (trunc (not i64:$in)))]>; 3985def ANDI_rec_1_GT_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 3986 "#ANDI_rec_1_GT_BIT8", 3987 [(set i1:$dst, (trunc i64:$in))]>; 3988 3989def : Pat<(i1 (not (trunc i32:$in))), 3990 (ANDI_rec_1_EQ_BIT $in)>; 3991def : Pat<(i1 (not (trunc i64:$in))), 3992 (ANDI_rec_1_EQ_BIT8 $in)>; 3993 3994def : Pat<(int_ppc_fsel f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), (FSELD $FRA, $FRC, $FRB)>; 3995def : Pat<(int_ppc_frsqrte f8rc:$frB), (FRSQRTE $frB)>; 3996def : Pat<(int_ppc_frsqrtes f4rc:$frB), (FRSQRTES $frB)>; 3997 3998//===----------------------------------------------------------------------===// 3999// PowerPC Instructions used for assembler/disassembler only 4000// 4001 4002// FIXME: For B=0 or B > 8, the registers following RT are used. 4003// WARNING: Do not add patterns for this instruction without fixing this. 4004def LSWI : XForm_base_r3xo_memOp<31, 597, (outs gprc:$RT), 4005 (ins gprc:$A, u5imm:$B), 4006 "lswi $RT, $A, $B", IIC_LdStLoad, []>; 4007 4008// FIXME: For B=0 or B > 8, the registers following RT are used. 4009// WARNING: Do not add patterns for this instruction without fixing this. 4010def STSWI : XForm_base_r3xo_memOp<31, 725, (outs), 4011 (ins gprc:$RT, gprc:$A, u5imm:$B), 4012 "stswi $RT, $A, $B", IIC_LdStLoad, []>; 4013 4014def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins), 4015 "isync", IIC_SprISYNC, []>; 4016 4017def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src), 4018 "icbi $src", IIC_LdStICBI, []>; 4019 4020def WAIT : XForm_24_sync<31, 30, (outs), (ins u2imm:$L), 4021 "wait $L", IIC_LdStLoad, []>; 4022 4023def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO), 4024 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>; 4025 4026def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR), 4027 "mtsr $SR, $RS", IIC_SprMTSR>; 4028 4029def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR), 4030 "mfsr $RS, $SR", IIC_SprMFSR>; 4031 4032def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB), 4033 "mtsrin $RS, $RB", IIC_SprMTSR>; 4034 4035def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB), 4036 "mfsrin $RS, $RB", IIC_SprMFSR>; 4037 4038def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, u1imm:$L), 4039 "mtmsr $RS, $L", IIC_SprMTMSR>; 4040 4041def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS), 4042 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> { 4043 let L = 0; 4044} 4045 4046def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>, 4047 Requires<[IsBookE]> { 4048 bits<1> E; 4049 4050 let Inst{16} = E; 4051 let Inst{21-30} = 163; 4052} 4053 4054def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B), 4055 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4056def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B), 4057 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4058 4059def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4060def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4061def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4062def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4063 4064def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins), 4065 "mfmsr $RT", IIC_SprMFMSR, []>; 4066 4067def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, u1imm:$L), 4068 "mtmsrd $RS, $L", IIC_SprMTMSRD>; 4069 4070def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA), 4071 "mcrfs $BF, $BFA", IIC_BrMCR>; 4072 4073// All MTFSF variants may change the rounding mode so conservatively set it 4074// as an implicit def for all of them. 4075let Predicates = [HasFPU] in { 4076let Defs = [RM], hasSideEffects = 1 in { 4077let isCodeGenOnly = 1, 4078 Pattern = [(int_ppc_mtfsfi timm:$BF, timm:$U)], W = 0 in 4079def MTFSFIb : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U), 4080 "mtfsfi $BF, $U", IIC_IntMFFS>; 4081def MTFSFI : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, i32imm:$W), 4082 "mtfsfi $BF, $U, $W", IIC_IntMFFS>; 4083let Defs = [CR1] in 4084def MTFSFI_rec : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, u1imm:$W), 4085 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isRecordForm; 4086 4087def MTFSF : XFLForm_1<63, 711, (outs), 4088 (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W), 4089 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>; 4090let Defs = [CR1] in 4091def MTFSF_rec : XFLForm_1<63, 711, (outs), 4092 (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W), 4093 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isRecordForm; 4094} 4095 4096def : InstAlias<"mtfsfi $BF, $U", (MTFSFI u3imm:$BF, u4imm:$U, 0)>; 4097def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec u3imm:$BF, u4imm:$U, 0)>; 4098def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4099def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4100} 4101 4102def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB), 4103 "slbie $RB", IIC_SprSLBIE, []>; 4104 4105def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB), 4106 "slbmte $RS, $RB", IIC_SprSLBMTE, []>; 4107 4108def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB), 4109 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>; 4110 4111def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB), 4112 "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>; 4113 4114def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>; 4115 4116let Defs = [CR0] in 4117def SLBFEE_rec : XForm_26<31, 979, (outs gprc:$RT), (ins gprc:$RB), 4118 "slbfee. $RT, $RB", IIC_SprSLBFEE, []>, isRecordForm; 4119 4120def TLBIA : XForm_0<31, 370, (outs), (ins), 4121 "tlbia", IIC_SprTLBIA, []>; 4122 4123def TLBSYNC : XForm_0<31, 566, (outs), (ins), 4124 "tlbsync", IIC_SprTLBSYNC, []>; 4125 4126def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB), 4127 "tlbiel $RB", IIC_SprTLBIEL, []>; 4128 4129def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB), 4130 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4131def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB), 4132 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4133 4134def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB), 4135 "tlbie $RB,$RS", IIC_SprTLBIE, []>; 4136 4137def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B", 4138 IIC_LdStLoad>, Requires<[IsBookE]>; 4139 4140def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B", 4141 IIC_LdStLoad>, Requires<[IsBookE]>; 4142 4143def TLBRE : XForm_24_eieio<31, 946, (outs), (ins), 4144 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4145 4146def TLBWE : XForm_24_eieio<31, 978, (outs), (ins), 4147 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4148 4149def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS), 4150 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4151 4152def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS), 4153 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4154 4155def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B), 4156 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>, 4157 Requires<[IsPPC4xx]>; 4158def TLBSX2D : XForm_base_r3xo<31, 914, (outs), 4159 (ins gprc:$RST, gprc:$A, gprc:$B), 4160 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>, 4161 Requires<[IsPPC4xx]>, isRecordForm; 4162 4163def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>; 4164 4165def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>, 4166 Requires<[IsBookE]>; 4167def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>, 4168 Requires<[IsBookE]>; 4169 4170def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>, 4171 Requires<[IsE500]>; 4172def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>, 4173 Requires<[IsE500]>; 4174 4175def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR), 4176 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>; 4177def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR), 4178 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>; 4179 4180def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>; 4181def NAP : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>; 4182 4183def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>; 4184 4185def LBZCIX : XForm_base_r3xo_memOp<31, 853, (outs gprc:$RST), 4186 (ins gprc:$A, gprc:$B), 4187 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>; 4188def LHZCIX : XForm_base_r3xo_memOp<31, 821, (outs gprc:$RST), 4189 (ins gprc:$A, gprc:$B), 4190 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>; 4191def LWZCIX : XForm_base_r3xo_memOp<31, 789, (outs gprc:$RST), 4192 (ins gprc:$A, gprc:$B), 4193 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>; 4194def LDCIX : XForm_base_r3xo_memOp<31, 885, (outs gprc:$RST), 4195 (ins gprc:$A, gprc:$B), 4196 "ldcix $RST, $A, $B", IIC_LdStLoad, []>; 4197 4198def STBCIX : XForm_base_r3xo_memOp<31, 981, (outs), 4199 (ins gprc:$RST, gprc:$A, gprc:$B), 4200 "stbcix $RST, $A, $B", IIC_LdStLoad, []>; 4201def STHCIX : XForm_base_r3xo_memOp<31, 949, (outs), 4202 (ins gprc:$RST, gprc:$A, gprc:$B), 4203 "sthcix $RST, $A, $B", IIC_LdStLoad, []>; 4204def STWCIX : XForm_base_r3xo_memOp<31, 917, (outs), 4205 (ins gprc:$RST, gprc:$A, gprc:$B), 4206 "stwcix $RST, $A, $B", IIC_LdStLoad, []>; 4207def STDCIX : XForm_base_r3xo_memOp<31, 1013, (outs), 4208 (ins gprc:$RST, gprc:$A, gprc:$B), 4209 "stdcix $RST, $A, $B", IIC_LdStLoad, []>; 4210 4211// External PID Load Store Instructions 4212 4213def LBEPX : XForm_1<31, 95, (outs gprc:$rD), (ins memrr:$src), 4214 "lbepx $rD, $src", IIC_LdStLoad, []>, 4215 Requires<[IsE500]>; 4216 4217def LFDEPX : XForm_25<31, 607, (outs f8rc:$frD), (ins memrr:$src), 4218 "lfdepx $frD, $src", IIC_LdStLFD, []>, 4219 Requires<[IsE500]>; 4220 4221def LHEPX : XForm_1<31, 287, (outs gprc:$rD), (ins memrr:$src), 4222 "lhepx $rD, $src", IIC_LdStLoad, []>, 4223 Requires<[IsE500]>; 4224 4225def LWEPX : XForm_1<31, 31, (outs gprc:$rD), (ins memrr:$src), 4226 "lwepx $rD, $src", IIC_LdStLoad, []>, 4227 Requires<[IsE500]>; 4228 4229def STBEPX : XForm_8<31, 223, (outs), (ins gprc:$rS, memrr:$dst), 4230 "stbepx $rS, $dst", IIC_LdStStore, []>, 4231 Requires<[IsE500]>; 4232 4233def STFDEPX : XForm_28_memOp<31, 735, (outs), (ins f8rc:$frS, memrr:$dst), 4234 "stfdepx $frS, $dst", IIC_LdStSTFD, []>, 4235 Requires<[IsE500]>; 4236 4237def STHEPX : XForm_8<31, 415, (outs), (ins gprc:$rS, memrr:$dst), 4238 "sthepx $rS, $dst", IIC_LdStStore, []>, 4239 Requires<[IsE500]>; 4240 4241def STWEPX : XForm_8<31, 159, (outs), (ins gprc:$rS, memrr:$dst), 4242 "stwepx $rS, $dst", IIC_LdStStore, []>, 4243 Requires<[IsE500]>; 4244 4245def DCBFEP : DCB_Form<127, 0, (outs), (ins memrr:$dst), "dcbfep $dst", 4246 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4247 4248def DCBSTEP : DCB_Form<63, 0, (outs), (ins memrr:$dst), "dcbstep $dst", 4249 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4250 4251def DCBTEP : DCB_Form_hint<319, (outs), (ins memrr:$dst, u5imm:$TH), 4252 "dcbtep $TH, $dst", IIC_LdStDCBF, []>, 4253 Requires<[IsE500]>; 4254 4255def DCBTSTEP : DCB_Form_hint<255, (outs), (ins memrr:$dst, u5imm:$TH), 4256 "dcbtstep $TH, $dst", IIC_LdStDCBF, []>, 4257 Requires<[IsE500]>; 4258 4259def DCBZEP : DCB_Form<1023, 0, (outs), (ins memrr:$dst), "dcbzep $dst", 4260 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4261 4262def DCBZLEP : DCB_Form<1023, 1, (outs), (ins memrr:$dst), "dcbzlep $dst", 4263 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4264 4265def ICBIEP : XForm_1a<31, 991, (outs), (ins memrr:$src), "icbiep $src", 4266 IIC_LdStICBI, []>, Requires<[IsE500]>; 4267 4268//===----------------------------------------------------------------------===// 4269// PowerPC Assembler Instruction Aliases 4270// 4271 4272// Pseudo-instructions for alternate assembly syntax (never used by codegen). 4273// These are aliases that require C++ handling to convert to the target 4274// instruction, while InstAliases can be handled directly by tblgen. 4275class PPCAsmPseudo<string asm, dag iops> 4276 : Instruction { 4277 let Namespace = "PPC"; 4278 bit PPC64 = 0; // Default value, override with isPPC64 4279 4280 let OutOperandList = (outs); 4281 let InOperandList = iops; 4282 let Pattern = []; 4283 let AsmString = asm; 4284 let isAsmParserOnly = 1; 4285 let isPseudo = 1; 4286 let hasNoSchedulingInfo = 1; 4287} 4288 4289def : InstAlias<"sc", (SC 0)>; 4290 4291def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>; 4292def : InstAlias<"hwsync", (SYNC 0), 0>, Requires<[HasSYNC]>; 4293def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>; 4294def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>; 4295def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>; 4296 4297def : InstAlias<"wait", (WAIT 0)>; 4298def : InstAlias<"waitrsv", (WAIT 1)>; 4299def : InstAlias<"waitimpl", (WAIT 2)>; 4300 4301def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>; 4302 4303def DCBTx : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>; 4304def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>; 4305 4306def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4307def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4308def DCBTT : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>; 4309 4310def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4311def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4312def DCBTSTT : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>; 4313 4314def DCBFx : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>; 4315def DCBFL : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>; 4316def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>; 4317 4318def : Pat<(int_ppc_isync), (ISYNC)>; 4319def : Pat<(int_ppc_dcbfl xoaddr:$dst), 4320 (DCBF 1, xoaddr:$dst)>; 4321def : Pat<(int_ppc_dcbflp xoaddr:$dst), 4322 (DCBF 3, xoaddr:$dst)>; 4323 4324let Predicates = [IsISA3_1] in { 4325 def DCBFPS : PPCAsmPseudo<"dcbfps $dst", (ins memrr:$dst)>; 4326 def DCBSTPS : PPCAsmPseudo<"dcbstps $dst", (ins memrr:$dst)>; 4327 4328 def : Pat<(int_ppc_dcbfps xoaddr:$dst), 4329 (DCBF 4, xoaddr:$dst)>; 4330 def : Pat<(int_ppc_dcbstps xoaddr:$dst), 4331 (DCBF 6, xoaddr:$dst)>; 4332} 4333 4334def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4335def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4336def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4337def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4338 4339def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>; 4340def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>; 4341def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>; 4342 4343def : InstAlias<"xnop", (XORI R0, R0, 0)>; 4344 4345def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>; 4346def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>; 4347 4348//Disable this alias on AIX for now because as does not support them. 4349let Predicates = [ModernAs] in { 4350 4351foreach BR = 0-7 in { 4352 def : InstAlias<"mfbr"#BR#" $Rx", 4353 (MFDCR gprc:$Rx, !add(BR, 0x80))>, 4354 Requires<[IsPPC4xx]>; 4355 def : InstAlias<"mtbr"#BR#" $Rx", 4356 (MTDCR gprc:$Rx, !add(BR, 0x80))>, 4357 Requires<[IsPPC4xx]>; 4358} 4359 4360def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>; 4361def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>; 4362def : InstAlias<"mtudscr $Rx", (MTSPR 3, gprc:$Rx)>; 4363def : InstAlias<"mfudscr $Rx", (MFSPR gprc:$Rx, 3)>; 4364 4365def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>; 4366def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>; 4367 4368def : InstAlias<"mtlr $Rx", (MTSPR 8, gprc:$Rx)>; 4369def : InstAlias<"mflr $Rx", (MFSPR gprc:$Rx, 8)>; 4370 4371def : InstAlias<"mtctr $Rx", (MTSPR 9, gprc:$Rx)>; 4372def : InstAlias<"mfctr $Rx", (MFSPR gprc:$Rx, 9)>; 4373 4374def : InstAlias<"mtuamr $Rx", (MTSPR 13, gprc:$Rx)>; 4375def : InstAlias<"mfuamr $Rx", (MFSPR gprc:$Rx, 13)>; 4376 4377def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>; 4378def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>; 4379 4380def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>; 4381def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>; 4382 4383def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>; 4384def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>; 4385 4386def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>; 4387def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>; 4388 4389def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>; 4390def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>; 4391 4392def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>; 4393def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>; 4394 4395def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>; 4396def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>; 4397 4398def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>; 4399def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>; 4400 4401def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>; 4402def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>; 4403 4404def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>; 4405def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>; 4406 4407foreach SPRG = 4-7 in { 4408 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>, 4409 Requires<[IsBookE]>; 4410 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>, 4411 Requires<[IsBookE]>; 4412 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4413 Requires<[IsBookE]>; 4414 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4415 Requires<[IsBookE]>; 4416} 4417 4418foreach SPRG = 0-3 in { 4419 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>; 4420 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>; 4421 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4422 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4423} 4424 4425def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>; 4426def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>; 4427 4428def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>; 4429def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>; 4430 4431def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>; 4432 4433def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>; 4434def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>; 4435 4436foreach BATR = 0-3 in { 4437 def : InstAlias<"mtdbatu "#BATR#", $Rx", 4438 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>, 4439 Requires<[IsPPC6xx]>; 4440 def : InstAlias<"mfdbatu $Rx, "#BATR, 4441 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>, 4442 Requires<[IsPPC6xx]>; 4443 def : InstAlias<"mtdbatl "#BATR#", $Rx", 4444 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>, 4445 Requires<[IsPPC6xx]>; 4446 def : InstAlias<"mfdbatl $Rx, "#BATR, 4447 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>, 4448 Requires<[IsPPC6xx]>; 4449 def : InstAlias<"mtibatu "#BATR#", $Rx", 4450 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>, 4451 Requires<[IsPPC6xx]>; 4452 def : InstAlias<"mfibatu $Rx, "#BATR, 4453 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>, 4454 Requires<[IsPPC6xx]>; 4455 def : InstAlias<"mtibatl "#BATR#", $Rx", 4456 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>, 4457 Requires<[IsPPC6xx]>; 4458 def : InstAlias<"mfibatl $Rx, "#BATR, 4459 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>, 4460 Requires<[IsPPC6xx]>; 4461} 4462 4463def : InstAlias<"mtppr $RT", (MTSPR 896, gprc:$RT)>; 4464def : InstAlias<"mfppr $RT", (MFSPR gprc:$RT, 896)>; 4465 4466def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4467def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>; 4468 4469def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4470def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>; 4471 4472def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4473def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>; 4474 4475def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>; 4476def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4477 4478def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>; 4479def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4480 4481def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4482def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>; 4483 4484def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4485def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>; 4486 4487def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4488def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>; 4489 4490def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4491def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>; 4492 4493} 4494 4495def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>; 4496 4497def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>, 4498 Requires<[IsPPC4xx]>; 4499def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>, 4500 Requires<[IsPPC4xx]>; 4501def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>, 4502 Requires<[IsPPC4xx]>; 4503def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>, 4504 Requires<[IsPPC4xx]>; 4505 4506def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>; 4507 4508def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm", 4509 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4510def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm", 4511 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4512def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm", 4513 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4514def SUBIC_rec : PPCAsmPseudo<"subic. $rA, $rB, $imm", 4515 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4516 4517def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b", 4518 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4519def EXTLWI_rec : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b", 4520 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4521def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b", 4522 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4523def EXTRWI_rec : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b", 4524 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4525def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b", 4526 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4527def INSLWI_rec : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b", 4528 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4529def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b", 4530 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4531def INSRWI_rec : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b", 4532 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4533def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n", 4534 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4535def ROTRWI_rec : PPCAsmPseudo<"rotrwi. $rA, $rS, $n", 4536 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4537def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n", 4538 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4539def SLWI_rec : PPCAsmPseudo<"slwi. $rA, $rS, $n", 4540 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4541def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n", 4542 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4543def SRWI_rec : PPCAsmPseudo<"srwi. $rA, $rS, $n", 4544 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4545def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n", 4546 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4547def CLRRWI_rec : PPCAsmPseudo<"clrrwi. $rA, $rS, $n", 4548 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4549def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n", 4550 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4551def CLRLSLWI_rec : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n", 4552 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4553 4554def : InstAlias<"isellt $rT, $rA, $rB", 4555 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0LT)>; 4556def : InstAlias<"iselgt $rT, $rA, $rB", 4557 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0GT)>; 4558def : InstAlias<"iseleq $rT, $rA, $rB", 4559 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0EQ)>; 4560 4561def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4562def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4563def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4564def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM_rec gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4565def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4566def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4567 4568def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>; 4569def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW_rec gprc:$rA, gprc:$rS)>; 4570// The POWER variant 4571def : MnemonicAlias<"cntlz", "cntlzw">; 4572def : MnemonicAlias<"cntlz.", "cntlzw.">; 4573 4574def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b", 4575 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4576def EXTLDI_rec : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b", 4577 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4578def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b", 4579 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4580def EXTRDI_rec : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b", 4581 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4582def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b", 4583 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4584def INSRDI_rec : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b", 4585 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4586def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n", 4587 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4588def ROTRDI_rec : PPCAsmPseudo<"rotrdi. $rA, $rS, $n", 4589 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4590def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n", 4591 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4592def SLDI_rec : PPCAsmPseudo<"sldi. $rA, $rS, $n", 4593 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4594def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n", 4595 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4596def SRDI_rec : PPCAsmPseudo<"srdi. $rA, $rS, $n", 4597 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4598def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n", 4599 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4600def CLRRDI_rec : PPCAsmPseudo<"clrrdi. $rA, $rS, $n", 4601 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4602def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n", 4603 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4604def CLRLSLDI_rec : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n", 4605 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4606def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>; 4607 4608def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4609def : InstAlias<"rotldi $rA, $rS, $n", 4610 (RLDICL_32_64 g8rc:$rA, gprc:$rS, u6imm:$n, 0)>; 4611def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4612def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4613def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4614def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4615def : InstAlias<"clrldi $rA, $rS, $n", 4616 (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)>; 4617def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4618def : InstAlias<"lnia $RT", (ADDPCIS g8rc:$RT, 0)>; 4619 4620def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b", 4621 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4622def RLWINMbm_rec : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b", 4623 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4624def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b", 4625 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4626def RLWIMIbm_rec : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b", 4627 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4628def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b", 4629 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4630def RLWNMbm_rec : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b", 4631 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4632 4633// These generic branch instruction forms are used for the assembler parser only. 4634// Defs and Uses are conservative, since we don't know the BO value. 4635let PPC970_Unit = 7, isBranch = 1, hasSideEffects = 0 in { 4636 let Defs = [CTR], Uses = [CTR, RM] in { 4637 def gBC : BForm_3<16, 0, 0, (outs), 4638 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 4639 "bc $bo, $bi, $dst">; 4640 def gBCA : BForm_3<16, 1, 0, (outs), 4641 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 4642 "bca $bo, $bi, $dst">; 4643 let isAsmParserOnly = 1 in { 4644 def gBCat : BForm_3_at<16, 0, 0, (outs), 4645 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 4646 condbrtarget:$dst), 4647 "bc$at $bo, $bi, $dst">; 4648 def gBCAat : BForm_3_at<16, 1, 0, (outs), 4649 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 4650 abscondbrtarget:$dst), 4651 "bca$at $bo, $bi, $dst">; 4652 } // isAsmParserOnly = 1 4653 } 4654 let Defs = [LR, CTR], Uses = [CTR, RM] in { 4655 def gBCL : BForm_3<16, 0, 1, (outs), 4656 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 4657 "bcl $bo, $bi, $dst">; 4658 def gBCLA : BForm_3<16, 1, 1, (outs), 4659 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 4660 "bcla $bo, $bi, $dst">; 4661 let isAsmParserOnly = 1 in { 4662 def gBCLat : BForm_3_at<16, 0, 1, (outs), 4663 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 4664 condbrtarget:$dst), 4665 "bcl$at $bo, $bi, $dst">; 4666 def gBCLAat : BForm_3_at<16, 1, 1, (outs), 4667 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 4668 abscondbrtarget:$dst), 4669 "bcla$at $bo, $bi, $dst">; 4670 } // // isAsmParserOnly = 1 4671 } 4672 let Defs = [CTR], Uses = [CTR, LR, RM] in 4673 def gBCLR : XLForm_2<19, 16, 0, (outs), 4674 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4675 "bclr $bo, $bi, $bh", IIC_BrB, []>; 4676 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4677 def gBCLRL : XLForm_2<19, 16, 1, (outs), 4678 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4679 "bclrl $bo, $bi, $bh", IIC_BrB, []>; 4680 let Defs = [CTR], Uses = [CTR, LR, RM] in 4681 def gBCCTR : XLForm_2<19, 528, 0, (outs), 4682 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4683 "bcctr $bo, $bi, $bh", IIC_BrB, []>; 4684 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4685 def gBCCTRL : XLForm_2<19, 528, 1, (outs), 4686 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4687 "bcctrl $bo, $bi, $bh", IIC_BrB, []>; 4688} 4689 4690multiclass BranchSimpleMnemonicAT<string pm, int at> { 4691 def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi, 4692 condbrtarget:$dst)>; 4693 def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi, 4694 condbrtarget:$dst)>; 4695 def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi, 4696 condbrtarget:$dst)>; 4697 def : InstAlias<"bcla"#pm#" $bo, $bi, $dst", (gBCLAat u5imm:$bo, at, crbitrc:$bi, 4698 condbrtarget:$dst)>; 4699} 4700defm : BranchSimpleMnemonicAT<"+", 3>; 4701defm : BranchSimpleMnemonicAT<"-", 2>; 4702 4703def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>; 4704def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>; 4705def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>; 4706def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>; 4707 4708multiclass BranchSimpleMnemonic1<string name, string pm, int bo> { 4709 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>; 4710 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4711 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>; 4712 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>; 4713 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4714 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>; 4715} 4716multiclass BranchSimpleMnemonic2<string name, string pm, int bo> 4717 : BranchSimpleMnemonic1<name, pm, bo> { 4718 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>; 4719 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>; 4720} 4721defm : BranchSimpleMnemonic2<"t", "", 12>; 4722defm : BranchSimpleMnemonic2<"f", "", 4>; 4723defm : BranchSimpleMnemonic2<"t", "-", 14>; 4724defm : BranchSimpleMnemonic2<"f", "-", 6>; 4725defm : BranchSimpleMnemonic2<"t", "+", 15>; 4726defm : BranchSimpleMnemonic2<"f", "+", 7>; 4727defm : BranchSimpleMnemonic1<"dnzt", "", 8>; 4728defm : BranchSimpleMnemonic1<"dnzf", "", 0>; 4729defm : BranchSimpleMnemonic1<"dzt", "", 10>; 4730defm : BranchSimpleMnemonic1<"dzf", "", 2>; 4731 4732multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> { 4733 def : InstAlias<"b"#name#pm#" $cc, $dst", 4734 (BCC bibo, crrc:$cc, condbrtarget:$dst)>; 4735 def : InstAlias<"b"#name#pm#" $dst", 4736 (BCC bibo, CR0, condbrtarget:$dst)>; 4737 4738 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst", 4739 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4740 def : InstAlias<"b"#name#"a"#pm#" $dst", 4741 (BCCA bibo, CR0, abscondbrtarget:$dst)>; 4742 4743 def : InstAlias<"b"#name#"lr"#pm#" $cc", 4744 (BCCLR bibo, crrc:$cc)>; 4745 def : InstAlias<"b"#name#"lr"#pm, 4746 (BCCLR bibo, CR0)>; 4747 4748 def : InstAlias<"b"#name#"ctr"#pm#" $cc", 4749 (BCCCTR bibo, crrc:$cc)>; 4750 def : InstAlias<"b"#name#"ctr"#pm, 4751 (BCCCTR bibo, CR0)>; 4752 4753 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst", 4754 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>; 4755 def : InstAlias<"b"#name#"l"#pm#" $dst", 4756 (BCCL bibo, CR0, condbrtarget:$dst)>; 4757 4758 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst", 4759 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4760 def : InstAlias<"b"#name#"la"#pm#" $dst", 4761 (BCCLA bibo, CR0, abscondbrtarget:$dst)>; 4762 4763 def : InstAlias<"b"#name#"lrl"#pm#" $cc", 4764 (BCCLRL bibo, crrc:$cc)>; 4765 def : InstAlias<"b"#name#"lrl"#pm, 4766 (BCCLRL bibo, CR0)>; 4767 4768 def : InstAlias<"b"#name#"ctrl"#pm#" $cc", 4769 (BCCCTRL bibo, crrc:$cc)>; 4770 def : InstAlias<"b"#name#"ctrl"#pm, 4771 (BCCCTRL bibo, CR0)>; 4772} 4773multiclass BranchExtendedMnemonic<string name, int bibo> { 4774 defm : BranchExtendedMnemonicPM<name, "", bibo>; 4775 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>; 4776 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>; 4777} 4778defm : BranchExtendedMnemonic<"lt", 12>; 4779defm : BranchExtendedMnemonic<"gt", 44>; 4780defm : BranchExtendedMnemonic<"eq", 76>; 4781defm : BranchExtendedMnemonic<"un", 108>; 4782defm : BranchExtendedMnemonic<"so", 108>; 4783defm : BranchExtendedMnemonic<"ge", 4>; 4784defm : BranchExtendedMnemonic<"nl", 4>; 4785defm : BranchExtendedMnemonic<"le", 36>; 4786defm : BranchExtendedMnemonic<"ng", 36>; 4787defm : BranchExtendedMnemonic<"ne", 68>; 4788defm : BranchExtendedMnemonic<"nu", 100>; 4789defm : BranchExtendedMnemonic<"ns", 100>; 4790 4791def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; 4792def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; 4793def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; 4794def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; 4795def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>; 4796def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; 4797def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>; 4798def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; 4799 4800def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>; 4801def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>; 4802def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>; 4803def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>; 4804def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>; 4805def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 4806def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>; 4807def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 4808 4809def : InstAlias<"trap", (TW 31, R0, R0)>; 4810 4811multiclass TrapExtendedMnemonic<string name, int to> { 4812 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>; 4813 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>; 4814 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>; 4815 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>; 4816} 4817defm : TrapExtendedMnemonic<"lt", 16>; 4818defm : TrapExtendedMnemonic<"le", 20>; 4819defm : TrapExtendedMnemonic<"eq", 4>; 4820defm : TrapExtendedMnemonic<"ge", 12>; 4821defm : TrapExtendedMnemonic<"gt", 8>; 4822defm : TrapExtendedMnemonic<"nl", 12>; 4823defm : TrapExtendedMnemonic<"ne", 24>; 4824defm : TrapExtendedMnemonic<"ng", 20>; 4825defm : TrapExtendedMnemonic<"llt", 2>; 4826defm : TrapExtendedMnemonic<"lle", 6>; 4827defm : TrapExtendedMnemonic<"lge", 5>; 4828defm : TrapExtendedMnemonic<"lgt", 1>; 4829defm : TrapExtendedMnemonic<"lnl", 5>; 4830defm : TrapExtendedMnemonic<"lng", 6>; 4831defm : TrapExtendedMnemonic<"u", 31>; 4832 4833// Atomic loads 4834def : Pat<(atomic_load_8 DForm:$src), (LBZ memri:$src)>; 4835def : Pat<(atomic_load_16 DForm:$src), (LHZ memri:$src)>; 4836def : Pat<(atomic_load_32 DForm:$src), (LWZ memri:$src)>; 4837def : Pat<(atomic_load_8 XForm:$src), (LBZX memrr:$src)>; 4838def : Pat<(atomic_load_16 XForm:$src), (LHZX memrr:$src)>; 4839def : Pat<(atomic_load_32 XForm:$src), (LWZX memrr:$src)>; 4840 4841// Atomic stores 4842def : Pat<(atomic_store_8 DForm:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>; 4843def : Pat<(atomic_store_16 DForm:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>; 4844def : Pat<(atomic_store_32 DForm:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>; 4845def : Pat<(atomic_store_8 XForm:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>; 4846def : Pat<(atomic_store_16 XForm:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>; 4847def : Pat<(atomic_store_32 XForm:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>; 4848 4849let Predicates = [IsISA3_0] in { 4850 4851// Copy-Paste Facility 4852// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to 4853// PASTE for naming consistency. 4854let mayLoad = 1 in 4855def CP_COPY : X_RA5_RB5<31, 774, "copy" , gprc, IIC_LdStCOPY, []>; 4856 4857let mayStore = 1, Defs = [CR0] in 4858def CP_PASTE_rec : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isRecordForm; 4859 4860def : InstAlias<"paste. $RA, $RB", (CP_PASTE_rec gprc:$RA, gprc:$RB, 1)>; 4861def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cpabort", IIC_SprABORT, []>; 4862 4863// Message Synchronize 4864def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>; 4865 4866// Power-Saving Mode Instruction: 4867def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>; 4868 4869def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA), 4870 "setb $RT, $BFA", IIC_IntGeneral>; 4871} // IsISA3_0 4872 4873let Predicates = [IsISA3_0] in { 4874def : Pat<(i32 (int_ppc_cmprb i32:$a, gprc:$b, gprc:$c)), 4875 (i32 (SETB (CMPRB u1imm:$a, $b, $c)))>; 4876} 4877def : Pat<(i32 (int_ppc_mulhw gprc:$a, gprc:$b)), 4878 (i32 (MULHW $a, $b))>; 4879def : Pat<(i32 (int_ppc_mulhwu gprc:$a, gprc:$b)), 4880 (i32 (MULHWU $a, $b))>; 4881def : Pat<(i32 (int_ppc_cmpb gprc:$a, gprc:$b)), 4882 (i32 (CMPB $a, $b))>; 4883 4884def : Pat<(int_ppc_load2r ForceXForm:$ptr), 4885 (LHBRX ForceXForm:$ptr)>; 4886def : Pat<(int_ppc_load4r ForceXForm:$ptr), 4887 (LWBRX ForceXForm:$ptr)>; 4888def : Pat<(int_ppc_store2r gprc:$a, ForceXForm:$ptr), 4889 (STHBRX gprc:$a, ForceXForm:$ptr)>; 4890def : Pat<(int_ppc_store4r gprc:$a, ForceXForm:$ptr), 4891 (STWBRX gprc:$a, ForceXForm:$ptr)>; 4892 4893 4894// Fast 32-bit reverse bits algorithm: 4895// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 4896// n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xAAAAAAAA); 4897// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 4898// n = ((n >> 2) & 0x33333333) | ((n << 2) & 0xCCCCCCCC); 4899// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 4900// n = ((n >> 4) & 0x0F0F0F0F) | ((n << 4) & 0xF0F0F0F0); 4901// Step 4: byte reverse (Suppose n = [B1,B2,B3,B4]): 4902// Step 4.1: Put B4,B2 in the right position (rotate left 3 bytes): 4903// n' = (n rotl 24); After which n' = [B4, B1, B2, B3] 4904// Step 4.2: Insert B3 to the right position: 4905// n' = rlwimi n', n, 8, 8, 15; After which n' = [B4, B3, B2, B3] 4906// Step 4.3: Insert B1 to the right position: 4907// n' = rlwimi n', n, 8, 24, 31; After which n' = [B4, B3, B2, B1] 4908def MaskValues { 4909 dag Lo1 = (ORI (LIS 0x5555), 0x5555); 4910 dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA); 4911 dag Lo2 = (ORI (LIS 0x3333), 0x3333); 4912 dag Hi2 = (ORI (LIS 0xCCCC), 0xCCCC); 4913 dag Lo4 = (ORI (LIS 0x0F0F), 0x0F0F); 4914 dag Hi4 = (ORI (LIS 0xF0F0), 0xF0F0); 4915} 4916 4917def Shift1 { 4918 dag Right = (RLWINM $A, 31, 1, 31); 4919 dag Left = (RLWINM $A, 1, 0, 30); 4920} 4921 4922def Swap1 { 4923 dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1), 4924 (AND Shift1.Left, MaskValues.Hi1)); 4925} 4926 4927def Shift2 { 4928 dag Right = (RLWINM Swap1.Bit, 30, 2, 31); 4929 dag Left = (RLWINM Swap1.Bit, 2, 0, 29); 4930} 4931 4932def Swap2 { 4933 dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2), 4934 (AND Shift2.Left, MaskValues.Hi2)); 4935} 4936 4937def Shift4 { 4938 dag Right = (RLWINM Swap2.Bits, 28, 4, 31); 4939 dag Left = (RLWINM Swap2.Bits, 4, 0, 27); 4940} 4941 4942def Swap4 { 4943 dag Bits = (OR (AND Shift4.Right, MaskValues.Lo4), 4944 (AND Shift4.Left, MaskValues.Hi4)); 4945} 4946 4947def Rotate { 4948 dag Left3Bytes = (RLWINM Swap4.Bits, 24, 0, 31); 4949} 4950 4951def RotateInsertByte3 { 4952 dag Left = (RLWIMI Rotate.Left3Bytes, Swap4.Bits, 8, 8, 15); 4953} 4954 4955def RotateInsertByte1 { 4956 dag Left = (RLWIMI RotateInsertByte3.Left, Swap4.Bits, 8, 24, 31); 4957} 4958 4959// Clear the upper half of the register when in 64-bit mode 4960let Predicates = [In64BitMode] in 4961def : Pat<(i32 (bitreverse i32:$A)), (RLDICL_32 RotateInsertByte1.Left, 0, 32)>; 4962let Predicates = [In32BitMode] in 4963def : Pat<(i32 (bitreverse i32:$A)), RotateInsertByte1.Left>; 4964 4965// Fast 64-bit reverse bits algorithm: 4966// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 4967// n = ((n >> 1) & 0x5555555555555555) | ((n << 1) & 0xAAAAAAAAAAAAAAAA); 4968// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 4969// n = ((n >> 2) & 0x3333333333333333) | ((n << 2) & 0xCCCCCCCCCCCCCCCC); 4970// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 4971// n = ((n >> 4) & 0x0F0F0F0F0F0F0F0F) | ((n << 4) & 0xF0F0F0F0F0F0F0F0); 4972// Step 4: byte reverse (Suppose n = [B0,B1,B2,B3,B4,B5,B6,B7]): 4973// Apply the same byte reverse algorithm mentioned above for the fast 32-bit 4974// reverse to both the high 32 bit and low 32 bit of the 64 bit value. And 4975// then OR them together to get the final result. 4976def MaskValues64 { 4977 dag Lo1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo1, sub_32)); 4978 dag Hi1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi1, sub_32)); 4979 dag Lo2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo2, sub_32)); 4980 dag Hi2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi2, sub_32)); 4981 dag Lo4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo4, sub_32)); 4982 dag Hi4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi4, sub_32)); 4983} 4984 4985def DWMaskValues { 4986 dag Lo1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo1, 32, 31), 0x5555), 0x5555); 4987 dag Hi1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi1, 32, 31), 0xAAAA), 0xAAAA); 4988 dag Lo2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo2, 32, 31), 0x3333), 0x3333); 4989 dag Hi2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi2, 32, 31), 0xCCCC), 0xCCCC); 4990 dag Lo4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo4, 32, 31), 0x0F0F), 0x0F0F); 4991 dag Hi4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi4, 32, 31), 0xF0F0), 0xF0F0); 4992} 4993 4994def DWSwapInByte { 4995 dag Swap1 = (OR8 (AND8 (RLDICL $A, 63, 1), DWMaskValues.Lo1), 4996 (AND8 (RLDICR $A, 1, 62), DWMaskValues.Hi1)); 4997 dag Swap2 = (OR8 (AND8 (RLDICL Swap1, 62, 2), DWMaskValues.Lo2), 4998 (AND8 (RLDICR Swap1, 2, 61), DWMaskValues.Hi2)); 4999 dag Swap4 = (OR8 (AND8 (RLDICL Swap2, 60, 4), DWMaskValues.Lo4), 5000 (AND8 (RLDICR Swap2, 4, 59), DWMaskValues.Hi4)); 5001} 5002 5003// Intra-byte swap is done, now start inter-byte swap. 5004def DWBytes4567 { 5005 dag Word = (i32 (EXTRACT_SUBREG DWSwapInByte.Swap4, sub_32)); 5006} 5007 5008def DWBytes7456 { 5009 dag Word = (RLWINM DWBytes4567.Word, 24, 0, 31); 5010} 5011 5012def DWBytes7656 { 5013 dag Word = (RLWIMI DWBytes7456.Word, DWBytes4567.Word, 8, 8, 15); 5014} 5015 5016// B7 B6 B5 B4 in the right order 5017def DWBytes7654 { 5018 dag Word = (RLWIMI DWBytes7656.Word, DWBytes4567.Word, 8, 24, 31); 5019 dag DWord = 5020 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5021} 5022 5023def DWBytes0123 { 5024 dag Word = (i32 (EXTRACT_SUBREG (RLDICL DWSwapInByte.Swap4, 32, 32), sub_32)); 5025} 5026 5027def DWBytes3012 { 5028 dag Word = (RLWINM DWBytes0123.Word, 24, 0, 31); 5029} 5030 5031def DWBytes3212 { 5032 dag Word = (RLWIMI DWBytes3012.Word, DWBytes0123.Word, 8, 8, 15); 5033} 5034 5035// B3 B2 B1 B0 in the right order 5036def DWBytes3210 { 5037 dag Word = (RLWIMI DWBytes3212.Word, DWBytes0123.Word, 8, 24, 31); 5038 dag DWord = 5039 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5040} 5041 5042// These instructions store a hash computed from the value of the link register 5043// and the value of the stack pointer. 5044let mayStore = 1 in { 5045def HASHST : XForm_XD6_RA5_RB5<31, 722, (outs), 5046 (ins gprc:$RB, memrihash:$D_RA_XD), 5047 "hashst $RB, $D_RA_XD", IIC_IntGeneral, []>; 5048def HASHSTP : XForm_XD6_RA5_RB5<31, 658, (outs), 5049 (ins gprc:$RB, memrihash:$D_RA_XD), 5050 "hashstp $RB, $D_RA_XD", IIC_IntGeneral, []>; 5051} 5052 5053// These instructions check a hash computed from the value of the link register 5054// and the value of the stack pointer. The hasSideEffects flag is needed as the 5055// instruction may TRAP if the hash does not match the hash stored at the 5056// specified address. 5057let mayLoad = 1, hasSideEffects = 1 in { 5058def HASHCHK : XForm_XD6_RA5_RB5<31, 754, (outs), 5059 (ins gprc:$RB, memrihash:$D_RA_XD), 5060 "hashchk $RB, $D_RA_XD", IIC_IntGeneral, []>; 5061def HASHCHKP : XForm_XD6_RA5_RB5<31, 690, (outs), 5062 (ins gprc:$RB, memrihash:$D_RA_XD), 5063 "hashchkp $RB, $D_RA_XD", IIC_IntGeneral, []>; 5064} 5065 5066// Now both high word and low word are reversed, next 5067// swap the high word and low word. 5068def : Pat<(i64 (bitreverse i64:$A)), 5069 (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>; 5070 5071def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A), 5072 (STWCX gprc:$A, ForceXForm:$dst)>; 5073def : Pat<(int_ppc_stbcx ForceXForm:$dst, gprc:$A), 5074 (STBCX gprc:$A, ForceXForm:$dst)>; 5075def : Pat<(int_ppc_trap gprc:$A), 5076 (TWI 24, $A, 0)>; 5077 5078def : Pat<(int_ppc_fcfid f64:$A), 5079 (XSCVSXDDP $A)>; 5080def : Pat<(int_ppc_fcfud f64:$A), 5081 (XSCVUXDDP $A)>; 5082def : Pat<(int_ppc_fctid f64:$A), 5083 (FCTID $A)>; 5084def : Pat<(int_ppc_fctidz f64:$A), 5085 (XSCVDPSXDS $A)>; 5086def : Pat<(int_ppc_fctiw f64:$A), 5087 (FCTIW $A)>; 5088def : Pat<(int_ppc_fctiwz f64:$A), 5089 (XSCVDPSXWS $A)>; 5090def : Pat<(int_ppc_fctudz f64:$A), 5091 (XSCVDPUXDS $A)>; 5092def : Pat<(int_ppc_fctuwz f64:$A), 5093 (XSCVDPUXWS $A)>; 5094 5095def : Pat<(int_ppc_mfmsr), (MFMSR)>; 5096def : Pat<(int_ppc_mftbu), (MFTB 269)>; 5097def : Pat<(i32 (int_ppc_mfspr timm:$SPR)), 5098 (MFSPR $SPR)>; 5099def : Pat<(int_ppc_mtspr timm:$SPR, gprc:$RT), 5100 (MTSPR $SPR, $RT)>; 5101def : Pat<(int_ppc_mtmsr gprc:$RS), 5102 (MTMSR $RS, 0)>; 5103 5104let Predicates = [IsISA2_07] in { 5105 def : Pat<(int_ppc_sthcx ForceXForm:$dst, gprc:$A), 5106 (STHCX gprc:$A, ForceXForm:$dst)>; 5107} 5108def : Pat<(int_ppc_dcbtstt ForceXForm:$dst), 5109 (DCBTST 16, ForceXForm:$dst)>; 5110def : Pat<(int_ppc_dcbtt ForceXForm:$dst), 5111 (DCBT 16, ForceXForm:$dst)>; 5112 5113def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT), 5114 (STFIWX f64:$XT, ForceXForm:$dst)>; 5115