1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the subset of the 32-bit PowerPC instruction set, as used
11// by the PowerPC instruction selector.
12//
13//===----------------------------------------------------------------------===//
14
15include "PPCInstrFormats.td"
16
17//===----------------------------------------------------------------------===//
18// PowerPC specific type constraints.
19//
20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21  SDTCisVT<0, f64>, SDTCisPtrTy<1>
22]>;
23def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24  SDTCisVT<0, f64>, SDTCisPtrTy<1>
25]>;
26
27def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28def SDT_PPCCallSeqEnd   : SDCallSeqEnd<[ SDTCisVT<0, i32>,
29                                         SDTCisVT<1, i32> ]>;
30def SDT_PPCvperm   : SDTypeProfile<1, 3, [
31  SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
32]>;
33
34def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35  SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
36]>;
37
38def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39  SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
40]>;
41
42def SDT_PPClbrx : SDTypeProfile<1, 2, [
43  SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
44]>;
45def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46  SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
47]>;
48
49def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
50  SDTCisPtrTy<0>, SDTCisVT<1, i32>
51]>;
52
53def tocentry32 : Operand<iPTR> {
54  let MIOperandInfo = (ops i32imm:$imm);
55}
56
57def SDT_PPCqvfperm   : SDTypeProfile<1, 3, [
58  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3>
59]>;
60def SDT_PPCqvgpci   : SDTypeProfile<1, 1, [
61  SDTCisVec<0>, SDTCisInt<1>
62]>;
63def SDT_PPCqvaligni   : SDTypeProfile<1, 3, [
64  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>
65]>;
66def SDT_PPCqvesplati   : SDTypeProfile<1, 2, [
67  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>
68]>;
69
70def SDT_PPCqbflt : SDTypeProfile<1, 1, [
71  SDTCisVec<0>, SDTCisVec<1>
72]>;
73
74def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [
75  SDTCisVec<0>, SDTCisPtrTy<1>
76]>;
77
78//===----------------------------------------------------------------------===//
79// PowerPC specific DAG Nodes.
80//
81
82def PPCfre    : SDNode<"PPCISD::FRE",     SDTFPUnaryOp, []>;
83def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
84
85def PPCfcfid  : SDNode<"PPCISD::FCFID",   SDTFPUnaryOp, []>;
86def PPCfcfidu : SDNode<"PPCISD::FCFIDU",  SDTFPUnaryOp, []>;
87def PPCfcfids : SDNode<"PPCISD::FCFIDS",  SDTFPRoundOp, []>;
88def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
89def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
90def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
91def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
92def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
93def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
94                       [SDNPHasChain, SDNPMayStore]>;
95def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
96                       [SDNPHasChain, SDNPMayLoad]>;
97def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
98                       [SDNPHasChain, SDNPMayLoad]>;
99
100// Extract FPSCR (not modeled at the DAG level).
101def PPCmffs   : SDNode<"PPCISD::MFFS",
102                       SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
103
104// Perform FADD in round-to-zero mode.
105def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
106
107
108def PPCfsel   : SDNode<"PPCISD::FSEL",
109   // Type constraint for fsel.
110   SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
111                        SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
112
113def PPChi       : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
114def PPClo       : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
115def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp,
116                         [SDNPMayLoad, SDNPMemOperand]>;
117def PPCvmaddfp  : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
118def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
119
120def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
121
122def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
123def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
124                            [SDNPMayLoad]>;
125def PPCaddTls     : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
126def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
127def PPCaddiTlsgdL   : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
128def PPCgetTlsAddr   : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
129def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR",
130                               SDTypeProfile<1, 3, [
131                                 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
132                                 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
133def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
134def PPCaddiTlsldL   : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
135def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
136def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR",
137                               SDTypeProfile<1, 3, [
138                                 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
139                                 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
140def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;
141def PPCaddiDtprelL   : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
142
143def PPCvperm    : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
144
145def PPCqvfperm   : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>;
146def PPCqvgpci    : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>;
147def PPCqvaligni  : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>;
148def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>;
149
150def PPCqbflt     : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>;
151
152def PPCqvlfsb    : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb,
153                          [SDNPHasChain, SDNPMayLoad]>;
154
155def PPCcmpb     : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>;
156
157// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
158// amounts.  These nodes are generated by the multi-precision shift code.
159def PPCsrl        : SDNode<"PPCISD::SRL"       , SDTIntShiftOp>;
160def PPCsra        : SDNode<"PPCISD::SRA"       , SDTIntShiftOp>;
161def PPCshl        : SDNode<"PPCISD::SHL"       , SDTIntShiftOp>;
162
163// These are target-independent nodes, but have target-specific formats.
164def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
165                           [SDNPHasChain, SDNPOutGlue]>;
166def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_PPCCallSeqEnd,
167                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
168
169def SDT_PPCCall   : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
170def PPCcall  : SDNode<"PPCISD::CALL", SDT_PPCCall,
171                      [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
172                       SDNPVariadic]>;
173def PPCcall_nop  : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
174                          [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
175                           SDNPVariadic]>;
176def PPCmtctr      : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
177                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
178def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
179                      [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
180                       SDNPVariadic]>;
181def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC",
182                               SDTypeProfile<0, 1, []>,
183                               [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
184                                SDNPVariadic]>;
185
186def retflag       : SDNode<"PPCISD::RET_FLAG", SDTNone,
187                           [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
188
189def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
190                        [SDNPHasChain,  SDNPOptInGlue, SDNPVariadic]>;
191
192def PPCeh_sjlj_setjmp  : SDNode<"PPCISD::EH_SJLJ_SETJMP",
193                                SDTypeProfile<1, 1, [SDTCisInt<0>,
194                                                     SDTCisPtrTy<1>]>,
195                                [SDNPHasChain, SDNPSideEffect]>;
196def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
197                                SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
198                                [SDNPHasChain, SDNPSideEffect]>;
199
200def SDT_PPCsc     : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
201def PPCsc         : SDNode<"PPCISD::SC", SDT_PPCsc,
202                           [SDNPHasChain, SDNPSideEffect]>;
203
204def PPCclrbhrb    : SDNode<"PPCISD::CLRBHRB", SDTNone,
205                           [SDNPHasChain, SDNPSideEffect]>;
206def PPCmfbhrbe    : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>;
207def PPCrfebb      : SDNode<"PPCISD::RFEBB", SDT_PPCsc,
208                           [SDNPHasChain, SDNPSideEffect]>;
209
210def PPCvcmp       : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
211def PPCvcmp_o     : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
212
213def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
214                           [SDNPHasChain, SDNPOptInGlue]>;
215
216def PPClbrx       : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
217                           [SDNPHasChain, SDNPMayLoad]>;
218def PPCstbrx      : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
219                           [SDNPHasChain, SDNPMayStore]>;
220
221// Instructions to set/unset CR bit 6 for SVR4 vararg calls
222def PPCcr6set   : SDNode<"PPCISD::CR6SET", SDTNone,
223                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
224def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
225                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
226
227// Instructions to support dynamic alloca.
228def SDTDynOp  : SDTypeProfile<1, 2, []>;
229def SDTDynAreaOp  : SDTypeProfile<1, 1, []>;
230def PPCdynalloc   : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
231def PPCdynareaoffset   : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>;
232
233//===----------------------------------------------------------------------===//
234// PowerPC specific transformation functions and pattern fragments.
235//
236
237def SHL32 : SDNodeXForm<imm, [{
238  // Transformation function: 31 - imm
239  return getI32Imm(31 - N->getZExtValue(), SDLoc(N));
240}]>;
241
242def SRL32 : SDNodeXForm<imm, [{
243  // Transformation function: 32 - imm
244  return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N))
245                           : getI32Imm(0, SDLoc(N));
246}]>;
247
248def LO16 : SDNodeXForm<imm, [{
249  // Transformation function: get the low 16 bits.
250  return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N));
251}]>;
252
253def HI16 : SDNodeXForm<imm, [{
254  // Transformation function: shift the immediate value down into the low bits.
255  return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N));
256}]>;
257
258def HA16 : SDNodeXForm<imm, [{
259  // Transformation function: shift the immediate value down into the low bits.
260  signed int Val = N->getZExtValue();
261  return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N));
262}]>;
263def MB : SDNodeXForm<imm, [{
264  // Transformation function: get the start bit of a mask
265  unsigned mb = 0, me;
266  (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
267  return getI32Imm(mb, SDLoc(N));
268}]>;
269
270def ME : SDNodeXForm<imm, [{
271  // Transformation function: get the end bit of a mask
272  unsigned mb, me = 0;
273  (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
274  return getI32Imm(me, SDLoc(N));
275}]>;
276def maskimm32 : PatLeaf<(imm), [{
277  // maskImm predicate - True if immediate is a run of ones.
278  unsigned mb, me;
279  if (N->getValueType(0) == MVT::i32)
280    return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
281  else
282    return false;
283}]>;
284
285def imm32SExt16  : Operand<i32>, ImmLeaf<i32, [{
286  // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
287  // sign extended field.  Used by instructions like 'addi'.
288  return (int32_t)Imm == (short)Imm;
289}]>;
290def imm64SExt16  : Operand<i64>, ImmLeaf<i64, [{
291  // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
292  // sign extended field.  Used by instructions like 'addi'.
293  return (int64_t)Imm == (short)Imm;
294}]>;
295def immZExt16  : PatLeaf<(imm), [{
296  // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
297  // field.  Used by instructions like 'ori'.
298  return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
299}], LO16>;
300
301// imm16Shifted* - These match immediates where the low 16-bits are zero.  There
302// are two forms: imm16ShiftedSExt and imm16ShiftedZExt.  These two forms are
303// identical in 32-bit mode, but in 64-bit mode, they return true if the
304// immediate fits into a sign/zero extended 32-bit immediate (with the low bits
305// clear).
306def imm16ShiftedZExt : PatLeaf<(imm), [{
307  // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
308  // immediate are set.  Used by instructions like 'xoris'.
309  return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
310}], HI16>;
311
312def imm16ShiftedSExt : PatLeaf<(imm), [{
313  // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
314  // immediate are set.  Used by instructions like 'addis'.  Identical to
315  // imm16ShiftedZExt in 32-bit mode.
316  if (N->getZExtValue() & 0xFFFF) return false;
317  if (N->getValueType(0) == MVT::i32)
318    return true;
319  // For 64-bit, make sure it is sext right.
320  return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
321}], HI16>;
322
323def imm64ZExt32  : Operand<i64>, ImmLeaf<i64, [{
324  // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
325  // zero extended field.
326  return isUInt<32>(Imm);
327}]>;
328
329// Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
330// restricted memrix (4-aligned) constants are alignment sensitive. If these
331// offsets are hidden behind TOC entries than the values of the lower-order
332// bits cannot be checked directly. As a result, we need to also incorporate
333// an alignment check into the relevant patterns.
334
335def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
336  return cast<LoadSDNode>(N)->getAlignment() >= 4;
337}]>;
338def aligned4store : PatFrag<(ops node:$val, node:$ptr),
339                            (store node:$val, node:$ptr), [{
340  return cast<StoreSDNode>(N)->getAlignment() >= 4;
341}]>;
342def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
343  return cast<LoadSDNode>(N)->getAlignment() >= 4;
344}]>;
345def aligned4pre_store : PatFrag<
346                          (ops node:$val, node:$base, node:$offset),
347                          (pre_store node:$val, node:$base, node:$offset), [{
348  return cast<StoreSDNode>(N)->getAlignment() >= 4;
349}]>;
350
351def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
352  return cast<LoadSDNode>(N)->getAlignment() < 4;
353}]>;
354def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
355                              (store node:$val, node:$ptr), [{
356  return cast<StoreSDNode>(N)->getAlignment() < 4;
357}]>;
358def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
359  return cast<LoadSDNode>(N)->getAlignment() < 4;
360}]>;
361
362//===----------------------------------------------------------------------===//
363// PowerPC Flag Definitions.
364
365class isPPC64 { bit PPC64 = 1; }
366class isDOT   { bit RC = 1; }
367
368class RegConstraint<string C> {
369  string Constraints = C;
370}
371class NoEncode<string E> {
372  string DisableEncoding = E;
373}
374
375
376//===----------------------------------------------------------------------===//
377// PowerPC Operand Definitions.
378
379// In the default PowerPC assembler syntax, registers are specified simply
380// by number, so they cannot be distinguished from immediate values (without
381// looking at the opcode).  This means that the default operand matching logic
382// for the asm parser does not work, and we need to specify custom matchers.
383// Since those can only be specified with RegisterOperand classes and not
384// directly on the RegisterClass, all instructions patterns used by the asm
385// parser need to use a RegisterOperand (instead of a RegisterClass) for
386// all their register operands.
387// For this purpose, we define one RegisterOperand for each RegisterClass,
388// using the same name as the class, just in lower case.
389
390def PPCRegGPRCAsmOperand : AsmOperandClass {
391  let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
392}
393def gprc : RegisterOperand<GPRC> {
394  let ParserMatchClass = PPCRegGPRCAsmOperand;
395}
396def PPCRegG8RCAsmOperand : AsmOperandClass {
397  let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
398}
399def g8rc : RegisterOperand<G8RC> {
400  let ParserMatchClass = PPCRegG8RCAsmOperand;
401}
402def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
403  let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
404}
405def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
406  let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
407}
408def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
409  let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
410}
411def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
412  let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
413}
414def PPCRegF8RCAsmOperand : AsmOperandClass {
415  let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
416}
417def f8rc : RegisterOperand<F8RC> {
418  let ParserMatchClass = PPCRegF8RCAsmOperand;
419}
420def PPCRegF4RCAsmOperand : AsmOperandClass {
421  let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
422}
423def f4rc : RegisterOperand<F4RC> {
424  let ParserMatchClass = PPCRegF4RCAsmOperand;
425}
426def PPCRegVRRCAsmOperand : AsmOperandClass {
427  let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
428}
429def vrrc : RegisterOperand<VRRC> {
430  let ParserMatchClass = PPCRegVRRCAsmOperand;
431}
432def PPCRegCRBITRCAsmOperand : AsmOperandClass {
433  let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
434}
435def crbitrc : RegisterOperand<CRBITRC> {
436  let ParserMatchClass = PPCRegCRBITRCAsmOperand;
437}
438def PPCRegCRRCAsmOperand : AsmOperandClass {
439  let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
440}
441def crrc : RegisterOperand<CRRC> {
442  let ParserMatchClass = PPCRegCRRCAsmOperand;
443}
444def crrc0 : RegisterOperand<CRRC0> {
445  let ParserMatchClass = PPCRegCRRCAsmOperand;
446}
447
448def PPCU1ImmAsmOperand : AsmOperandClass {
449  let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
450  let RenderMethod = "addImmOperands";
451}
452def u1imm   : Operand<i32> {
453  let PrintMethod = "printU1ImmOperand";
454  let ParserMatchClass = PPCU1ImmAsmOperand;
455}
456
457def PPCU2ImmAsmOperand : AsmOperandClass {
458  let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
459  let RenderMethod = "addImmOperands";
460}
461def u2imm   : Operand<i32> {
462  let PrintMethod = "printU2ImmOperand";
463  let ParserMatchClass = PPCU2ImmAsmOperand;
464}
465
466def PPCU3ImmAsmOperand : AsmOperandClass {
467  let Name = "U3Imm"; let PredicateMethod = "isU3Imm";
468  let RenderMethod = "addImmOperands";
469}
470def u3imm   : Operand<i32> {
471  let PrintMethod = "printU3ImmOperand";
472  let ParserMatchClass = PPCU3ImmAsmOperand;
473}
474
475def PPCU4ImmAsmOperand : AsmOperandClass {
476  let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
477  let RenderMethod = "addImmOperands";
478}
479def u4imm   : Operand<i32> {
480  let PrintMethod = "printU4ImmOperand";
481  let ParserMatchClass = PPCU4ImmAsmOperand;
482}
483def PPCS5ImmAsmOperand : AsmOperandClass {
484  let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
485  let RenderMethod = "addImmOperands";
486}
487def s5imm   : Operand<i32> {
488  let PrintMethod = "printS5ImmOperand";
489  let ParserMatchClass = PPCS5ImmAsmOperand;
490  let DecoderMethod = "decodeSImmOperand<5>";
491}
492def PPCU5ImmAsmOperand : AsmOperandClass {
493  let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
494  let RenderMethod = "addImmOperands";
495}
496def u5imm   : Operand<i32> {
497  let PrintMethod = "printU5ImmOperand";
498  let ParserMatchClass = PPCU5ImmAsmOperand;
499  let DecoderMethod = "decodeUImmOperand<5>";
500}
501def PPCU6ImmAsmOperand : AsmOperandClass {
502  let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
503  let RenderMethod = "addImmOperands";
504}
505def u6imm   : Operand<i32> {
506  let PrintMethod = "printU6ImmOperand";
507  let ParserMatchClass = PPCU6ImmAsmOperand;
508  let DecoderMethod = "decodeUImmOperand<6>";
509}
510def PPCU10ImmAsmOperand : AsmOperandClass {
511  let Name = "U10Imm"; let PredicateMethod = "isU10Imm";
512  let RenderMethod = "addImmOperands";
513}
514def u10imm  : Operand<i32> {
515  let PrintMethod = "printU10ImmOperand";
516  let ParserMatchClass = PPCU10ImmAsmOperand;
517  let DecoderMethod = "decodeUImmOperand<10>";
518}
519def PPCU12ImmAsmOperand : AsmOperandClass {
520  let Name = "U12Imm"; let PredicateMethod = "isU12Imm";
521  let RenderMethod = "addImmOperands";
522}
523def u12imm  : Operand<i32> {
524  let PrintMethod = "printU12ImmOperand";
525  let ParserMatchClass = PPCU12ImmAsmOperand;
526  let DecoderMethod = "decodeUImmOperand<12>";
527}
528def PPCS16ImmAsmOperand : AsmOperandClass {
529  let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
530  let RenderMethod = "addS16ImmOperands";
531}
532def s16imm  : Operand<i32> {
533  let PrintMethod = "printS16ImmOperand";
534  let EncoderMethod = "getImm16Encoding";
535  let ParserMatchClass = PPCS16ImmAsmOperand;
536  let DecoderMethod = "decodeSImmOperand<16>";
537}
538def PPCU16ImmAsmOperand : AsmOperandClass {
539  let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
540  let RenderMethod = "addU16ImmOperands";
541}
542def u16imm  : Operand<i32> {
543  let PrintMethod = "printU16ImmOperand";
544  let EncoderMethod = "getImm16Encoding";
545  let ParserMatchClass = PPCU16ImmAsmOperand;
546  let DecoderMethod = "decodeUImmOperand<16>";
547}
548def PPCS17ImmAsmOperand : AsmOperandClass {
549  let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
550  let RenderMethod = "addS16ImmOperands";
551}
552def s17imm  : Operand<i32> {
553  // This operand type is used for addis/lis to allow the assembler parser
554  // to accept immediates in the range -65536..65535 for compatibility with
555  // the GNU assembler.  The operand is treated as 16-bit otherwise.
556  let PrintMethod = "printS16ImmOperand";
557  let EncoderMethod = "getImm16Encoding";
558  let ParserMatchClass = PPCS17ImmAsmOperand;
559  let DecoderMethod = "decodeSImmOperand<16>";
560}
561def PPCDirectBrAsmOperand : AsmOperandClass {
562  let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
563  let RenderMethod = "addBranchTargetOperands";
564}
565def directbrtarget : Operand<OtherVT> {
566  let PrintMethod = "printBranchOperand";
567  let EncoderMethod = "getDirectBrEncoding";
568  let ParserMatchClass = PPCDirectBrAsmOperand;
569}
570def absdirectbrtarget : Operand<OtherVT> {
571  let PrintMethod = "printAbsBranchOperand";
572  let EncoderMethod = "getAbsDirectBrEncoding";
573  let ParserMatchClass = PPCDirectBrAsmOperand;
574}
575def PPCCondBrAsmOperand : AsmOperandClass {
576  let Name = "CondBr"; let PredicateMethod = "isCondBr";
577  let RenderMethod = "addBranchTargetOperands";
578}
579def condbrtarget : Operand<OtherVT> {
580  let PrintMethod = "printBranchOperand";
581  let EncoderMethod = "getCondBrEncoding";
582  let ParserMatchClass = PPCCondBrAsmOperand;
583}
584def abscondbrtarget : Operand<OtherVT> {
585  let PrintMethod = "printAbsBranchOperand";
586  let EncoderMethod = "getAbsCondBrEncoding";
587  let ParserMatchClass = PPCCondBrAsmOperand;
588}
589def calltarget : Operand<iPTR> {
590  let PrintMethod = "printBranchOperand";
591  let EncoderMethod = "getDirectBrEncoding";
592  let ParserMatchClass = PPCDirectBrAsmOperand;
593}
594def abscalltarget : Operand<iPTR> {
595  let PrintMethod = "printAbsBranchOperand";
596  let EncoderMethod = "getAbsDirectBrEncoding";
597  let ParserMatchClass = PPCDirectBrAsmOperand;
598}
599def PPCCRBitMaskOperand : AsmOperandClass {
600 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
601}
602def crbitm: Operand<i8> {
603  let PrintMethod = "printcrbitm";
604  let EncoderMethod = "get_crbitm_encoding";
605  let DecoderMethod = "decodeCRBitMOperand";
606  let ParserMatchClass = PPCCRBitMaskOperand;
607}
608// Address operands
609// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
610def PPCRegGxRCNoR0Operand : AsmOperandClass {
611  let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
612}
613def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
614  let ParserMatchClass = PPCRegGxRCNoR0Operand;
615}
616// A version of ptr_rc usable with the asm parser.
617def PPCRegGxRCOperand : AsmOperandClass {
618  let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
619}
620def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
621  let ParserMatchClass = PPCRegGxRCOperand;
622}
623
624def PPCDispRIOperand : AsmOperandClass {
625 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
626 let RenderMethod = "addS16ImmOperands";
627}
628def dispRI : Operand<iPTR> {
629  let ParserMatchClass = PPCDispRIOperand;
630}
631def PPCDispRIXOperand : AsmOperandClass {
632 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
633 let RenderMethod = "addImmOperands";
634}
635def dispRIX : Operand<iPTR> {
636  let ParserMatchClass = PPCDispRIXOperand;
637}
638def PPCDispSPE8Operand : AsmOperandClass {
639 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
640 let RenderMethod = "addImmOperands";
641}
642def dispSPE8 : Operand<iPTR> {
643  let ParserMatchClass = PPCDispSPE8Operand;
644}
645def PPCDispSPE4Operand : AsmOperandClass {
646 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
647 let RenderMethod = "addImmOperands";
648}
649def dispSPE4 : Operand<iPTR> {
650  let ParserMatchClass = PPCDispSPE4Operand;
651}
652def PPCDispSPE2Operand : AsmOperandClass {
653 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
654 let RenderMethod = "addImmOperands";
655}
656def dispSPE2 : Operand<iPTR> {
657  let ParserMatchClass = PPCDispSPE2Operand;
658}
659
660def memri : Operand<iPTR> {
661  let PrintMethod = "printMemRegImm";
662  let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
663  let EncoderMethod = "getMemRIEncoding";
664  let DecoderMethod = "decodeMemRIOperands";
665}
666def memrr : Operand<iPTR> {
667  let PrintMethod = "printMemRegReg";
668  let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
669}
670def memrix : Operand<iPTR> {   // memri where the imm is 4-aligned.
671  let PrintMethod = "printMemRegImm";
672  let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
673  let EncoderMethod = "getMemRIXEncoding";
674  let DecoderMethod = "decodeMemRIXOperands";
675}
676def spe8dis : Operand<iPTR> {   // SPE displacement where the imm is 8-aligned.
677  let PrintMethod = "printMemRegImm";
678  let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
679  let EncoderMethod = "getSPE8DisEncoding";
680}
681def spe4dis : Operand<iPTR> {   // SPE displacement where the imm is 4-aligned.
682  let PrintMethod = "printMemRegImm";
683  let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
684  let EncoderMethod = "getSPE4DisEncoding";
685}
686def spe2dis : Operand<iPTR> {   // SPE displacement where the imm is 2-aligned.
687  let PrintMethod = "printMemRegImm";
688  let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
689  let EncoderMethod = "getSPE2DisEncoding";
690}
691
692// A single-register address. This is used with the SjLj
693// pseudo-instructions.
694def memr : Operand<iPTR> {
695  let MIOperandInfo = (ops ptr_rc:$ptrreg);
696}
697def PPCTLSRegOperand : AsmOperandClass {
698  let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
699  let RenderMethod = "addTLSRegOperands";
700}
701def tlsreg32 : Operand<i32> {
702  let EncoderMethod = "getTLSRegEncoding";
703  let ParserMatchClass = PPCTLSRegOperand;
704}
705def tlsgd32 : Operand<i32> {}
706def tlscall32 : Operand<i32> {
707  let PrintMethod = "printTLSCall";
708  let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
709  let EncoderMethod = "getTLSCallEncoding";
710}
711
712// PowerPC Predicate operand.
713def pred : Operand<OtherVT> {
714  let PrintMethod = "printPredicateOperand";
715  let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
716}
717
718// Define PowerPC specific addressing mode.
719def iaddr  : ComplexPattern<iPTR, 2, "SelectAddrImm",    [], []>;
720def xaddr  : ComplexPattern<iPTR, 2, "SelectAddrIdx",    [], []>;
721def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
722def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4",  [], []>; // "std"
723
724// The address in a single register. This is used with the SjLj
725// pseudo-instructions.
726def addr   : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
727
728/// This is just the offset part of iaddr, used for preinc.
729def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
730
731//===----------------------------------------------------------------------===//
732// PowerPC Instruction Predicate Definitions.
733def In32BitMode  : Predicate<"!PPCSubTarget->isPPC64()">;
734def In64BitMode  : Predicate<"PPCSubTarget->isPPC64()">;
735def IsBookE  : Predicate<"PPCSubTarget->isBookE()">;
736def IsNotBookE  : Predicate<"!PPCSubTarget->isBookE()">;
737def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
738def HasSYNC   : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
739def IsPPC4xx  : Predicate<"PPCSubTarget->isPPC4xx()">;
740def IsPPC6xx  : Predicate<"PPCSubTarget->isPPC6xx()">;
741def IsE500  : Predicate<"PPCSubTarget->isE500()">;
742def HasSPE  : Predicate<"PPCSubTarget->HasSPE()">;
743def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
744def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">;
745def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
746def NaNsFPMath   : Predicate<"!TM.Options.NoNaNsFPMath">;
747def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">;
748def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">;
749
750//===----------------------------------------------------------------------===//
751// PowerPC Multiclass Definitions.
752
753multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
754                    string asmbase, string asmstr, InstrItinClass itin,
755                    list<dag> pattern> {
756  let BaseName = asmbase in {
757    def NAME : XForm_6<opcode, xo, OOL, IOL,
758                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
759                       pattern>, RecFormRel;
760    let Defs = [CR0] in
761    def o    : XForm_6<opcode, xo, OOL, IOL,
762                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
763                       []>, isDOT, RecFormRel;
764  }
765}
766
767multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
768                     string asmbase, string asmstr, InstrItinClass itin,
769                     list<dag> pattern> {
770  let BaseName = asmbase in {
771    let Defs = [CARRY] in
772    def NAME : XForm_6<opcode, xo, OOL, IOL,
773                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
774                       pattern>, RecFormRel;
775    let Defs = [CARRY, CR0] in
776    def o    : XForm_6<opcode, xo, OOL, IOL,
777                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
778                       []>, isDOT, RecFormRel;
779  }
780}
781
782multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
783                      string asmbase, string asmstr, InstrItinClass itin,
784                      list<dag> pattern> {
785  let BaseName = asmbase in {
786    let Defs = [CARRY] in
787    def NAME : XForm_10<opcode, xo, OOL, IOL,
788                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
789                       pattern>, RecFormRel;
790    let Defs = [CARRY, CR0] in
791    def o    : XForm_10<opcode, xo, OOL, IOL,
792                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
793                       []>, isDOT, RecFormRel;
794  }
795}
796
797multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
798                    string asmbase, string asmstr, InstrItinClass itin,
799                    list<dag> pattern> {
800  let BaseName = asmbase in {
801    def NAME : XForm_11<opcode, xo, OOL, IOL,
802                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
803                       pattern>, RecFormRel;
804    let Defs = [CR0] in
805    def o    : XForm_11<opcode, xo, OOL, IOL,
806                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
807                       []>, isDOT, RecFormRel;
808  }
809}
810
811multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
812                    string asmbase, string asmstr, InstrItinClass itin,
813                    list<dag> pattern> {
814  let BaseName = asmbase in {
815    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
816                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
817                       pattern>, RecFormRel;
818    let Defs = [CR0] in
819    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
820                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
821                       []>, isDOT, RecFormRel;
822  }
823}
824
825// Multiclass for instructions for which the non record form is not cracked
826// and the record form is cracked (i.e. divw, mullw, etc.)
827multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
828                      string asmbase, string asmstr, InstrItinClass itin,
829                      list<dag> pattern> {
830  let BaseName = asmbase in {
831    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
832                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
833                       pattern>, RecFormRel;
834    let Defs = [CR0] in
835    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
836                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
837                       []>, isDOT, RecFormRel, PPC970_DGroup_First,
838                       PPC970_DGroup_Cracked;
839  }
840}
841
842multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
843                      string asmbase, string asmstr, InstrItinClass itin,
844                      list<dag> pattern> {
845  let BaseName = asmbase in {
846    let Defs = [CARRY] in
847    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
848                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
849                       pattern>, RecFormRel;
850    let Defs = [CARRY, CR0] in
851    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
852                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
853                       []>, isDOT, RecFormRel;
854  }
855}
856
857multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
858                    string asmbase, string asmstr, InstrItinClass itin,
859                    list<dag> pattern> {
860  let BaseName = asmbase in {
861    def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
862                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
863                       pattern>, RecFormRel;
864    let Defs = [CR0] in
865    def o    : XOForm_3<opcode, xo, oe, OOL, IOL,
866                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
867                       []>, isDOT, RecFormRel;
868  }
869}
870
871multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
872                      string asmbase, string asmstr, InstrItinClass itin,
873                      list<dag> pattern> {
874  let BaseName = asmbase in {
875    let Defs = [CARRY] in
876    def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
877                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
878                       pattern>, RecFormRel;
879    let Defs = [CARRY, CR0] in
880    def o    : XOForm_3<opcode, xo, oe, OOL, IOL,
881                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
882                       []>, isDOT, RecFormRel;
883  }
884}
885
886multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
887                    string asmbase, string asmstr, InstrItinClass itin,
888                    list<dag> pattern> {
889  let BaseName = asmbase in {
890    def NAME : MForm_2<opcode, OOL, IOL,
891                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
892                       pattern>, RecFormRel;
893    let Defs = [CR0] in
894    def o    : MForm_2<opcode, OOL, IOL,
895                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
896                       []>, isDOT, RecFormRel;
897  }
898}
899
900multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
901                    string asmbase, string asmstr, InstrItinClass itin,
902                    list<dag> pattern> {
903  let BaseName = asmbase in {
904    def NAME : MDForm_1<opcode, xo, OOL, IOL,
905                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
906                       pattern>, RecFormRel;
907    let Defs = [CR0] in
908    def o    : MDForm_1<opcode, xo, OOL, IOL,
909                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
910                       []>, isDOT, RecFormRel;
911  }
912}
913
914multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
915                     string asmbase, string asmstr, InstrItinClass itin,
916                     list<dag> pattern> {
917  let BaseName = asmbase in {
918    def NAME : MDSForm_1<opcode, xo, OOL, IOL,
919                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
920                        pattern>, RecFormRel;
921    let Defs = [CR0] in
922    def o    : MDSForm_1<opcode, xo, OOL, IOL,
923                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
924                        []>, isDOT, RecFormRel;
925  }
926}
927
928multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
929                      string asmbase, string asmstr, InstrItinClass itin,
930                      list<dag> pattern> {
931  let BaseName = asmbase in {
932    let Defs = [CARRY] in
933    def NAME : XSForm_1<opcode, xo, OOL, IOL,
934                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
935                       pattern>, RecFormRel;
936    let Defs = [CARRY, CR0] in
937    def o    : XSForm_1<opcode, xo, OOL, IOL,
938                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
939                       []>, isDOT, RecFormRel;
940  }
941}
942
943multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
944                    string asmbase, string asmstr, InstrItinClass itin,
945                    list<dag> pattern> {
946  let BaseName = asmbase in {
947    def NAME : XForm_26<opcode, xo, OOL, IOL,
948                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
949                       pattern>, RecFormRel;
950    let Defs = [CR1] in
951    def o    : XForm_26<opcode, xo, OOL, IOL,
952                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
953                       []>, isDOT, RecFormRel;
954  }
955}
956
957multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
958                    string asmbase, string asmstr, InstrItinClass itin,
959                    list<dag> pattern> {
960  let BaseName = asmbase in {
961    def NAME : XForm_28<opcode, xo, OOL, IOL,
962                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
963                       pattern>, RecFormRel;
964    let Defs = [CR1] in
965    def o    : XForm_28<opcode, xo, OOL, IOL,
966                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
967                       []>, isDOT, RecFormRel;
968  }
969}
970
971multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
972                    string asmbase, string asmstr, InstrItinClass itin,
973                    list<dag> pattern> {
974  let BaseName = asmbase in {
975    def NAME : AForm_1<opcode, xo, OOL, IOL,
976                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
977                       pattern>, RecFormRel;
978    let Defs = [CR1] in
979    def o    : AForm_1<opcode, xo, OOL, IOL,
980                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
981                       []>, isDOT, RecFormRel;
982  }
983}
984
985multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
986                    string asmbase, string asmstr, InstrItinClass itin,
987                    list<dag> pattern> {
988  let BaseName = asmbase in {
989    def NAME : AForm_2<opcode, xo, OOL, IOL,
990                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
991                       pattern>, RecFormRel;
992    let Defs = [CR1] in
993    def o    : AForm_2<opcode, xo, OOL, IOL,
994                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
995                       []>, isDOT, RecFormRel;
996  }
997}
998
999multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
1000                    string asmbase, string asmstr, InstrItinClass itin,
1001                    list<dag> pattern> {
1002  let BaseName = asmbase in {
1003    def NAME : AForm_3<opcode, xo, OOL, IOL,
1004                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1005                       pattern>, RecFormRel;
1006    let Defs = [CR1] in
1007    def o    : AForm_3<opcode, xo, OOL, IOL,
1008                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1009                       []>, isDOT, RecFormRel;
1010  }
1011}
1012
1013//===----------------------------------------------------------------------===//
1014// PowerPC Instruction Definitions.
1015
1016// Pseudo-instructions:
1017
1018let hasCtrlDep = 1 in {
1019let Defs = [R1], Uses = [R1] in {
1020def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
1021                              [(callseq_start timm:$amt)]>;
1022def ADJCALLSTACKUP   : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
1023                              [(callseq_end timm:$amt1, timm:$amt2)]>;
1024}
1025
1026def UPDATE_VRSAVE    : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
1027                              "UPDATE_VRSAVE $rD, $rS", []>;
1028}
1029
1030let Defs = [R1], Uses = [R1] in
1031def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
1032                       [(set i32:$result,
1033                             (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
1034def DYNAREAOFFSET : Pseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET",
1035                       [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>;
1036
1037// SELECT_CC_* - Used to implement the SELECT_CC DAG operation.  Expanded after
1038// instruction selection into a branch sequence.
1039let usesCustomInserter = 1,    // Expanded after instruction selection.
1040    PPC970_Single = 1 in {
1041  // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
1042  // because either operand might become the first operand in an isel, and
1043  // that operand cannot be r0.
1044  def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
1045                              gprc_nor0:$T, gprc_nor0:$F,
1046                              i32imm:$BROPC), "#SELECT_CC_I4",
1047                              []>;
1048  def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
1049                              g8rc_nox0:$T, g8rc_nox0:$F,
1050                              i32imm:$BROPC), "#SELECT_CC_I8",
1051                              []>;
1052  def SELECT_CC_F4  : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1053                              i32imm:$BROPC), "#SELECT_CC_F4",
1054                              []>;
1055  def SELECT_CC_F8  : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
1056                              i32imm:$BROPC), "#SELECT_CC_F8",
1057                              []>;
1058  def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
1059                              i32imm:$BROPC), "#SELECT_CC_VRRC",
1060                              []>;
1061
1062  // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
1063  // register bit directly.
1064  def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
1065                          gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
1066                          [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
1067  def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
1068                          g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
1069                          [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
1070  def SELECT_F4  : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
1071                          f4rc:$T, f4rc:$F), "#SELECT_F4",
1072                          [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
1073  def SELECT_F8  : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
1074                          f8rc:$T, f8rc:$F), "#SELECT_F8",
1075                          [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
1076  def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
1077                          vrrc:$T, vrrc:$F), "#SELECT_VRRC",
1078                          [(set v4i32:$dst,
1079                                (select i1:$cond, v4i32:$T, v4i32:$F))]>;
1080}
1081
1082// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
1083// scavenge a register for it.
1084let mayStore = 1 in {
1085def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
1086                     "#SPILL_CR", []>;
1087def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1088                         "#SPILL_CRBIT", []>;
1089}
1090
1091// RESTORE_CR - Indicate that we're restoring the CR register (previously
1092// spilled), so we'll need to scavenge a register for it.
1093let mayLoad = 1 in {
1094def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1095                     "#RESTORE_CR", []>;
1096def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1097                           "#RESTORE_CRBIT", []>;
1098}
1099
1100let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1101  let isReturn = 1, Uses = [LR, RM] in
1102    def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1103                           [(retflag)]>, Requires<[In32BitMode]>;
1104  let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1105    def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1106                            []>;
1107
1108    let isCodeGenOnly = 1 in {
1109      def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1110                               "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1111                               []>;
1112
1113      def BCCTR :  XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1114                                "bcctr 12, $bi, 0", IIC_BrB, []>;
1115      def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1116                                "bcctr 4, $bi, 0", IIC_BrB, []>;
1117    }
1118  }
1119}
1120
1121let Defs = [LR] in
1122  def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1123                   PPC970_Unit_BRU;
1124let Defs = [LR] in
1125  def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1126                    PPC970_Unit_BRU;
1127
1128let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1129  let isBarrier = 1 in {
1130  def B   : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1131                  "b $dst", IIC_BrB,
1132                  [(br bb:$dst)]>;
1133  def BA  : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1134                  "ba $dst", IIC_BrB, []>;
1135  }
1136
1137  // BCC represents an arbitrary conditional branch on a predicate.
1138  // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1139  // a two-value operand where a dag node expects two operands. :(
1140  let isCodeGenOnly = 1 in {
1141    def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1142                    "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1143                    /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1144    def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1145                     "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1146
1147    let isReturn = 1, Uses = [LR, RM] in
1148    def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1149                           "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1150  }
1151
1152  let isCodeGenOnly = 1 in {
1153    let Pattern = [(brcond i1:$bi, bb:$dst)] in
1154    def BC  : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1155             "bc 12, $bi, $dst">;
1156
1157    let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1158    def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1159             "bc 4, $bi, $dst">;
1160
1161    let isReturn = 1, Uses = [LR, RM] in
1162    def BCLR  : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1163                             "bclr 12, $bi, 0", IIC_BrB, []>;
1164    def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1165                             "bclr 4, $bi, 0", IIC_BrB, []>;
1166  }
1167
1168  let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1169   def BDZLR  : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1170                             "bdzlr", IIC_BrB, []>;
1171   def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1172                             "bdnzlr", IIC_BrB, []>;
1173   def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1174                             "bdzlr+", IIC_BrB, []>;
1175   def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1176                             "bdnzlr+", IIC_BrB, []>;
1177   def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1178                             "bdzlr-", IIC_BrB, []>;
1179   def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1180                             "bdnzlr-", IIC_BrB, []>;
1181  }
1182
1183  let Defs = [CTR], Uses = [CTR] in {
1184    def BDZ  : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1185                       "bdz $dst">;
1186    def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1187                       "bdnz $dst">;
1188    def BDZA  : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1189                        "bdza $dst">;
1190    def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1191                        "bdnza $dst">;
1192    def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1193                       "bdz+ $dst">;
1194    def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1195                       "bdnz+ $dst">;
1196    def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1197                        "bdza+ $dst">;
1198    def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1199                        "bdnza+ $dst">;
1200    def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1201                       "bdz- $dst">;
1202    def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1203                       "bdnz- $dst">;
1204    def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1205                        "bdza- $dst">;
1206    def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1207                        "bdnza- $dst">;
1208  }
1209}
1210
1211// The unconditional BCL used by the SjLj setjmp code.
1212let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1213  let Defs = [LR], Uses = [RM] in {
1214    def BCLalways  : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1215                            "bcl 20, 31, $dst">;
1216  }
1217}
1218
1219let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1220  // Convenient aliases for call instructions
1221  let Uses = [RM] in {
1222    def BL  : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1223                    "bl $func", IIC_BrB, []>;  // See Pat patterns below.
1224    def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1225                    "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1226
1227    let isCodeGenOnly = 1 in {
1228      def BL_TLS  : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1229                          "bl $func", IIC_BrB, []>;
1230      def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1231                       "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1232      def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1233                        "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1234
1235      def BCL  : BForm_4<16, 12, 0, 1, (outs),
1236                         (ins crbitrc:$bi, condbrtarget:$dst),
1237                         "bcl 12, $bi, $dst">;
1238      def BCLn : BForm_4<16, 4, 0, 1, (outs),
1239                         (ins crbitrc:$bi, condbrtarget:$dst),
1240                         "bcl 4, $bi, $dst">;
1241    }
1242  }
1243  let Uses = [CTR, RM] in {
1244    def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1245                             "bctrl", IIC_BrB, [(PPCbctrl)]>,
1246                Requires<[In32BitMode]>;
1247
1248    let isCodeGenOnly = 1 in {
1249      def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1250                                "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1251                                []>;
1252
1253      def BCCTRL  : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1254                                 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1255      def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1256                                 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1257    }
1258  }
1259  let Uses = [LR, RM] in {
1260    def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1261                            "blrl", IIC_BrB, []>;
1262
1263    let isCodeGenOnly = 1 in {
1264      def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1265                              "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1266                              []>;
1267
1268      def BCLRL  : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1269                                "bclrl 12, $bi, 0", IIC_BrB, []>;
1270      def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1271                                "bclrl 4, $bi, 0", IIC_BrB, []>;
1272    }
1273  }
1274  let Defs = [CTR], Uses = [CTR, RM] in {
1275    def BDZL  : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1276                        "bdzl $dst">;
1277    def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1278                        "bdnzl $dst">;
1279    def BDZLA  : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1280                         "bdzla $dst">;
1281    def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1282                         "bdnzla $dst">;
1283    def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1284                        "bdzl+ $dst">;
1285    def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1286                        "bdnzl+ $dst">;
1287    def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1288                         "bdzla+ $dst">;
1289    def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1290                         "bdnzla+ $dst">;
1291    def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1292                        "bdzl- $dst">;
1293    def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1294                        "bdnzl- $dst">;
1295    def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1296                         "bdzla- $dst">;
1297    def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1298                         "bdnzla- $dst">;
1299  }
1300  let Defs = [CTR], Uses = [CTR, LR, RM] in {
1301    def BDZLRL  : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1302                               "bdzlrl", IIC_BrB, []>;
1303    def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1304                               "bdnzlrl", IIC_BrB, []>;
1305    def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1306                               "bdzlrl+", IIC_BrB, []>;
1307    def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1308                               "bdnzlrl+", IIC_BrB, []>;
1309    def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1310                               "bdzlrl-", IIC_BrB, []>;
1311    def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1312                               "bdnzlrl-", IIC_BrB, []>;
1313  }
1314}
1315
1316let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1317def TCRETURNdi :Pseudo< (outs),
1318                        (ins calltarget:$dst, i32imm:$offset),
1319                 "#TC_RETURNd $dst $offset",
1320                 []>;
1321
1322
1323let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1324def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1325                 "#TC_RETURNa $func $offset",
1326                 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1327
1328let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1329def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1330                 "#TC_RETURNr $dst $offset",
1331                 []>;
1332
1333
1334let isCodeGenOnly = 1 in {
1335
1336let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1337    isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM]  in
1338def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1339                            []>, Requires<[In32BitMode]>;
1340
1341let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1342    isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1343def TAILB   : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1344                  "b $dst", IIC_BrB,
1345                  []>;
1346
1347let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1348    isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1349def TAILBA   : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1350                  "ba $dst", IIC_BrB,
1351                  []>;
1352
1353}
1354
1355let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1356  let Defs = [CTR] in
1357  def EH_SjLj_SetJmp32  : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1358                            "#EH_SJLJ_SETJMP32",
1359                            [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1360                          Requires<[In32BitMode]>;
1361  let isTerminator = 1 in
1362  def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1363                            "#EH_SJLJ_LONGJMP32",
1364                            [(PPCeh_sjlj_longjmp addr:$buf)]>,
1365                          Requires<[In32BitMode]>;
1366}
1367
1368let isBranch = 1, isTerminator = 1 in {
1369  def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1370                        "#EH_SjLj_Setup\t$dst", []>;
1371}
1372
1373// System call.
1374let PPC970_Unit = 7 in {
1375  def SC     : SCForm<17, 1, (outs), (ins i32imm:$lev),
1376                      "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1377}
1378
1379// Branch history rolling buffer.
1380def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB,
1381                      [(PPCclrbhrb)]>,
1382                      PPC970_DGroup_Single;
1383// The $dmy argument used for MFBHRBE is not needed; however, including
1384// it avoids automatic generation of PPCFastISel::fastEmit_i(), which
1385// interferes with necessary special handling (see PPCFastISel.cpp).
1386def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD),
1387                         (ins u10imm:$imm, u10imm:$dmy),
1388                         "mfbhrbe $rD, $imm", IIC_BrB,
1389                         [(set i32:$rD,
1390                               (PPCmfbhrbe imm:$imm, imm:$dmy))]>,
1391                         PPC970_DGroup_First;
1392
1393def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm",
1394                     IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>,
1395                     PPC970_DGroup_Single;
1396
1397// DCB* instructions.
1398def DCBA   : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1399                      IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1400                      PPC970_DGroup_Single;
1401def DCBF   : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1402                      IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1403                      PPC970_DGroup_Single;
1404def DCBI   : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1405                      IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1406                      PPC970_DGroup_Single;
1407def DCBST  : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1408                      IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1409                      PPC970_DGroup_Single;
1410def DCBZ   : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1411                      IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1412                      PPC970_DGroup_Single;
1413def DCBZL  : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1414                      IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1415                      PPC970_DGroup_Single;
1416
1417let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in {
1418def DCBT   : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst),
1419                      "dcbt $dst, $TH", IIC_LdStDCBF, []>,
1420                      PPC970_DGroup_Single;
1421def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst),
1422                      "dcbtst $dst, $TH", IIC_LdStDCBF, []>,
1423                      PPC970_DGroup_Single;
1424} // hasSideEffects = 0
1425
1426def ICBT  : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1427                       "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1428
1429def : Pat<(int_ppc_dcbt xoaddr:$dst),
1430          (DCBT 0, xoaddr:$dst)>;
1431def : Pat<(int_ppc_dcbtst xoaddr:$dst),
1432          (DCBTST 0, xoaddr:$dst)>;
1433
1434def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1435          (DCBT 0, xoaddr:$dst)>;   // data prefetch for loads
1436def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1437          (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores
1438def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1439          (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
1440
1441// Atomic operations
1442let usesCustomInserter = 1 in {
1443  let Defs = [CR0] in {
1444    def ATOMIC_LOAD_ADD_I8 : Pseudo<
1445      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1446      [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1447    def ATOMIC_LOAD_SUB_I8 : Pseudo<
1448      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1449      [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1450    def ATOMIC_LOAD_AND_I8 : Pseudo<
1451      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1452      [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1453    def ATOMIC_LOAD_OR_I8 : Pseudo<
1454      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1455      [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1456    def ATOMIC_LOAD_XOR_I8 : Pseudo<
1457      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1458      [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1459    def ATOMIC_LOAD_NAND_I8 : Pseudo<
1460      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1461      [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1462    def ATOMIC_LOAD_ADD_I16 : Pseudo<
1463      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1464      [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1465    def ATOMIC_LOAD_SUB_I16 : Pseudo<
1466      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1467      [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1468    def ATOMIC_LOAD_AND_I16 : Pseudo<
1469      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1470      [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1471    def ATOMIC_LOAD_OR_I16 : Pseudo<
1472      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1473      [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1474    def ATOMIC_LOAD_XOR_I16 : Pseudo<
1475      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1476      [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1477    def ATOMIC_LOAD_NAND_I16 : Pseudo<
1478      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1479      [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1480    def ATOMIC_LOAD_ADD_I32 : Pseudo<
1481      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1482      [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1483    def ATOMIC_LOAD_SUB_I32 : Pseudo<
1484      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1485      [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1486    def ATOMIC_LOAD_AND_I32 : Pseudo<
1487      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1488      [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1489    def ATOMIC_LOAD_OR_I32 : Pseudo<
1490      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1491      [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1492    def ATOMIC_LOAD_XOR_I32 : Pseudo<
1493      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1494      [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1495    def ATOMIC_LOAD_NAND_I32 : Pseudo<
1496      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1497      [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1498
1499    def ATOMIC_CMP_SWAP_I8 : Pseudo<
1500      (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1501      [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1502    def ATOMIC_CMP_SWAP_I16 : Pseudo<
1503      (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1504      [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1505    def ATOMIC_CMP_SWAP_I32 : Pseudo<
1506      (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1507      [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1508
1509    def ATOMIC_SWAP_I8 : Pseudo<
1510      (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1511      [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1512    def ATOMIC_SWAP_I16 : Pseudo<
1513      (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1514      [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1515    def ATOMIC_SWAP_I32 : Pseudo<
1516      (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1517      [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1518  }
1519}
1520
1521// Instructions to support atomic operations
1522let mayLoad = 1, hasSideEffects = 0 in {
1523def LBARX : XForm_1<31,  52, (outs gprc:$rD), (ins memrr:$src),
1524                    "lbarx $rD, $src", IIC_LdStLWARX, []>,
1525                    Requires<[HasPartwordAtomics]>;
1526
1527def LHARX : XForm_1<31,  116, (outs gprc:$rD), (ins memrr:$src),
1528                    "lharx $rD, $src", IIC_LdStLWARX, []>,
1529                    Requires<[HasPartwordAtomics]>;
1530
1531def LWARX : XForm_1<31,  20, (outs gprc:$rD), (ins memrr:$src),
1532                    "lwarx $rD, $src", IIC_LdStLWARX, []>;
1533
1534// Instructions to support lock versions of atomics
1535// (EH=1 - see Power ISA 2.07 Book II 4.4.2)
1536def LBARXL : XForm_1<31,  52, (outs gprc:$rD), (ins memrr:$src),
1537                     "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1538                     Requires<[HasPartwordAtomics]>;
1539
1540def LHARXL : XForm_1<31,  116, (outs gprc:$rD), (ins memrr:$src),
1541                     "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1542                     Requires<[HasPartwordAtomics]>;
1543
1544def LWARXL : XForm_1<31,  20, (outs gprc:$rD), (ins memrr:$src),
1545                     "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT;
1546}
1547
1548let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in {
1549def STBCX : XForm_1<31, 694, (outs), (ins gprc:$rS, memrr:$dst),
1550                    "stbcx. $rS, $dst", IIC_LdStSTWCX, []>,
1551                    isDOT, Requires<[HasPartwordAtomics]>;
1552
1553def STHCX : XForm_1<31, 726, (outs), (ins gprc:$rS, memrr:$dst),
1554                    "sthcx. $rS, $dst", IIC_LdStSTWCX, []>,
1555                    isDOT, Requires<[HasPartwordAtomics]>;
1556
1557def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1558                    "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT;
1559}
1560
1561let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1562def TRAP  : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1563
1564def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1565                     "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1566def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1567                 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1568def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1569                     "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1570def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1571                 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1572
1573//===----------------------------------------------------------------------===//
1574// PPC32 Load Instructions.
1575//
1576
1577// Unindexed (r+i) Loads.
1578let PPC970_Unit = 2 in {
1579def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1580                  "lbz $rD, $src", IIC_LdStLoad,
1581                  [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1582def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1583                  "lha $rD, $src", IIC_LdStLHA,
1584                  [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1585                  PPC970_DGroup_Cracked;
1586def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1587                  "lhz $rD, $src", IIC_LdStLoad,
1588                  [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1589def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1590                  "lwz $rD, $src", IIC_LdStLoad,
1591                  [(set i32:$rD, (load iaddr:$src))]>;
1592
1593def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1594                  "lfs $rD, $src", IIC_LdStLFD,
1595                  [(set f32:$rD, (load iaddr:$src))]>;
1596def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1597                  "lfd $rD, $src", IIC_LdStLFD,
1598                  [(set f64:$rD, (load iaddr:$src))]>;
1599
1600
1601// Unindexed (r+i) Loads with Update (preinc).
1602let mayLoad = 1, hasSideEffects = 0 in {
1603def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1604                   "lbzu $rD, $addr", IIC_LdStLoadUpd,
1605                   []>, RegConstraint<"$addr.reg = $ea_result">,
1606                   NoEncode<"$ea_result">;
1607
1608def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1609                   "lhau $rD, $addr", IIC_LdStLHAU,
1610                   []>, RegConstraint<"$addr.reg = $ea_result">,
1611                   NoEncode<"$ea_result">;
1612
1613def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1614                   "lhzu $rD, $addr", IIC_LdStLoadUpd,
1615                   []>, RegConstraint<"$addr.reg = $ea_result">,
1616                   NoEncode<"$ea_result">;
1617
1618def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1619                   "lwzu $rD, $addr", IIC_LdStLoadUpd,
1620                   []>, RegConstraint<"$addr.reg = $ea_result">,
1621                   NoEncode<"$ea_result">;
1622
1623def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1624                  "lfsu $rD, $addr", IIC_LdStLFDU,
1625                  []>, RegConstraint<"$addr.reg = $ea_result">,
1626                   NoEncode<"$ea_result">;
1627
1628def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1629                  "lfdu $rD, $addr", IIC_LdStLFDU,
1630                  []>, RegConstraint<"$addr.reg = $ea_result">,
1631                   NoEncode<"$ea_result">;
1632
1633
1634// Indexed (r+r) Loads with Update (preinc).
1635def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1636                   (ins memrr:$addr),
1637                   "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1638                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1639                   NoEncode<"$ea_result">;
1640
1641def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1642                   (ins memrr:$addr),
1643                   "lhaux $rD, $addr", IIC_LdStLHAUX,
1644                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1645                   NoEncode<"$ea_result">;
1646
1647def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1648                   (ins memrr:$addr),
1649                   "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1650                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1651                   NoEncode<"$ea_result">;
1652
1653def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1654                   (ins memrr:$addr),
1655                   "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1656                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1657                   NoEncode<"$ea_result">;
1658
1659def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1660                   (ins memrr:$addr),
1661                   "lfsux $rD, $addr", IIC_LdStLFDUX,
1662                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1663                   NoEncode<"$ea_result">;
1664
1665def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1666                   (ins memrr:$addr),
1667                   "lfdux $rD, $addr", IIC_LdStLFDUX,
1668                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1669                   NoEncode<"$ea_result">;
1670}
1671}
1672
1673// Indexed (r+r) Loads.
1674//
1675let PPC970_Unit = 2 in {
1676def LBZX : XForm_1<31,  87, (outs gprc:$rD), (ins memrr:$src),
1677                   "lbzx $rD, $src", IIC_LdStLoad,
1678                   [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1679def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1680                   "lhax $rD, $src", IIC_LdStLHA,
1681                   [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1682                   PPC970_DGroup_Cracked;
1683def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1684                   "lhzx $rD, $src", IIC_LdStLoad,
1685                   [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1686def LWZX : XForm_1<31,  23, (outs gprc:$rD), (ins memrr:$src),
1687                   "lwzx $rD, $src", IIC_LdStLoad,
1688                   [(set i32:$rD, (load xaddr:$src))]>;
1689
1690
1691def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1692                   "lhbrx $rD, $src", IIC_LdStLoad,
1693                   [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1694def LWBRX : XForm_1<31,  534, (outs gprc:$rD), (ins memrr:$src),
1695                   "lwbrx $rD, $src", IIC_LdStLoad,
1696                   [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1697
1698def LFSX   : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1699                      "lfsx $frD, $src", IIC_LdStLFD,
1700                      [(set f32:$frD, (load xaddr:$src))]>;
1701def LFDX   : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1702                      "lfdx $frD, $src", IIC_LdStLFD,
1703                      [(set f64:$frD, (load xaddr:$src))]>;
1704
1705def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1706                      "lfiwax $frD, $src", IIC_LdStLFD,
1707                      [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1708def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1709                      "lfiwzx $frD, $src", IIC_LdStLFD,
1710                      [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1711}
1712
1713// Load Multiple
1714def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1715                  "lmw $rD, $src", IIC_LdStLMW, []>;
1716
1717//===----------------------------------------------------------------------===//
1718// PPC32 Store Instructions.
1719//
1720
1721// Unindexed (r+i) Stores.
1722let PPC970_Unit = 2 in {
1723def STB  : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1724                   "stb $rS, $src", IIC_LdStStore,
1725                   [(truncstorei8 i32:$rS, iaddr:$src)]>;
1726def STH  : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1727                   "sth $rS, $src", IIC_LdStStore,
1728                   [(truncstorei16 i32:$rS, iaddr:$src)]>;
1729def STW  : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1730                   "stw $rS, $src", IIC_LdStStore,
1731                   [(store i32:$rS, iaddr:$src)]>;
1732def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1733                   "stfs $rS, $dst", IIC_LdStSTFD,
1734                   [(store f32:$rS, iaddr:$dst)]>;
1735def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1736                   "stfd $rS, $dst", IIC_LdStSTFD,
1737                   [(store f64:$rS, iaddr:$dst)]>;
1738}
1739
1740// Unindexed (r+i) Stores with Update (preinc).
1741let PPC970_Unit = 2, mayStore = 1 in {
1742def STBU  : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1743                    "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1744                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1745def STHU  : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1746                    "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1747                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1748def STWU  : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1749                    "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1750                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1751def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1752                    "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1753                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1754def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1755                    "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1756                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1757}
1758
1759// Patterns to match the pre-inc stores.  We can't put the patterns on
1760// the instruction definitions directly as ISel wants the address base
1761// and offset to be separate operands, not a single complex operand.
1762def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1763          (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1764def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1765          (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1766def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1767          (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1768def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1769          (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1770def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1771          (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1772
1773// Indexed (r+r) Stores.
1774let PPC970_Unit = 2 in {
1775def STBX  : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1776                   "stbx $rS, $dst", IIC_LdStStore,
1777                   [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1778                   PPC970_DGroup_Cracked;
1779def STHX  : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1780                   "sthx $rS, $dst", IIC_LdStStore,
1781                   [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1782                   PPC970_DGroup_Cracked;
1783def STWX  : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1784                   "stwx $rS, $dst", IIC_LdStStore,
1785                   [(store i32:$rS, xaddr:$dst)]>,
1786                   PPC970_DGroup_Cracked;
1787
1788def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1789                   "sthbrx $rS, $dst", IIC_LdStStore,
1790                   [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1791                   PPC970_DGroup_Cracked;
1792def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1793                   "stwbrx $rS, $dst", IIC_LdStStore,
1794                   [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1795                   PPC970_DGroup_Cracked;
1796
1797def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1798                     "stfiwx $frS, $dst", IIC_LdStSTFD,
1799                     [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1800
1801def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1802                     "stfsx $frS, $dst", IIC_LdStSTFD,
1803                     [(store f32:$frS, xaddr:$dst)]>;
1804def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1805                     "stfdx $frS, $dst", IIC_LdStSTFD,
1806                     [(store f64:$frS, xaddr:$dst)]>;
1807}
1808
1809// Indexed (r+r) Stores with Update (preinc).
1810let PPC970_Unit = 2, mayStore = 1 in {
1811def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1812                    "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1813                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1814                    PPC970_DGroup_Cracked;
1815def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1816                    "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1817                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1818                    PPC970_DGroup_Cracked;
1819def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1820                    "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1821                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1822                    PPC970_DGroup_Cracked;
1823def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1824                    "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1825                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1826                    PPC970_DGroup_Cracked;
1827def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1828                    "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1829                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1830                    PPC970_DGroup_Cracked;
1831}
1832
1833// Patterns to match the pre-inc stores.  We can't put the patterns on
1834// the instruction definitions directly as ISel wants the address base
1835// and offset to be separate operands, not a single complex operand.
1836def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1837          (STBUX $rS, $ptrreg, $ptroff)>;
1838def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1839          (STHUX $rS, $ptrreg, $ptroff)>;
1840def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1841          (STWUX $rS, $ptrreg, $ptroff)>;
1842def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1843          (STFSUX $rS, $ptrreg, $ptroff)>;
1844def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1845          (STFDUX $rS, $ptrreg, $ptroff)>;
1846
1847// Store Multiple
1848def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1849                   "stmw $rS, $dst", IIC_LdStLMW, []>;
1850
1851def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1852                        "sync $L", IIC_LdStSync, []>;
1853
1854let isCodeGenOnly = 1 in {
1855  def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1856                           "msync", IIC_LdStSync, []> {
1857    let L = 0;
1858  }
1859}
1860
1861def : Pat<(int_ppc_sync),   (SYNC 0)>, Requires<[HasSYNC]>;
1862def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
1863def : Pat<(int_ppc_sync),   (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1864def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1865
1866//===----------------------------------------------------------------------===//
1867// PPC32 Arithmetic Instructions.
1868//
1869
1870let PPC970_Unit = 1 in {  // FXU Operations.
1871def ADDI   : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1872                     "addi $rD, $rA, $imm", IIC_IntSimple,
1873                     [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1874let BaseName = "addic" in {
1875let Defs = [CARRY] in
1876def ADDIC  : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1877                     "addic $rD, $rA, $imm", IIC_IntGeneral,
1878                     [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1879                     RecFormRel, PPC970_DGroup_Cracked;
1880let Defs = [CARRY, CR0] in
1881def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1882                     "addic. $rD, $rA, $imm", IIC_IntGeneral,
1883                     []>, isDOT, RecFormRel;
1884}
1885def ADDIS  : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1886                     "addis $rD, $rA, $imm", IIC_IntSimple,
1887                     [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1888let isCodeGenOnly = 1 in
1889def LA     : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1890                     "la $rD, $sym($rA)", IIC_IntGeneral,
1891                     [(set i32:$rD, (add i32:$rA,
1892                                          (PPClo tglobaladdr:$sym, 0)))]>;
1893def MULLI  : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1894                     "mulli $rD, $rA, $imm", IIC_IntMulLI,
1895                     [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1896let Defs = [CARRY] in
1897def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1898                     "subfic $rD, $rA, $imm", IIC_IntGeneral,
1899                     [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1900
1901let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1902  def LI  : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1903                       "li $rD, $imm", IIC_IntSimple,
1904                       [(set i32:$rD, imm32SExt16:$imm)]>;
1905  def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1906                       "lis $rD, $imm", IIC_IntSimple,
1907                       [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1908}
1909}
1910
1911let PPC970_Unit = 1 in {  // FXU Operations.
1912let Defs = [CR0] in {
1913def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1914                    "andi. $dst, $src1, $src2", IIC_IntGeneral,
1915                    [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1916                    isDOT;
1917def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1918                    "andis. $dst, $src1, $src2", IIC_IntGeneral,
1919                    [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1920                    isDOT;
1921}
1922def ORI   : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1923                    "ori $dst, $src1, $src2", IIC_IntSimple,
1924                    [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1925def ORIS  : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1926                    "oris $dst, $src1, $src2", IIC_IntSimple,
1927                    [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1928def XORI  : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1929                    "xori $dst, $src1, $src2", IIC_IntSimple,
1930                    [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1931def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1932                    "xoris $dst, $src1, $src2", IIC_IntSimple,
1933                    [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1934
1935def NOP   : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1936                         []>;
1937let isCodeGenOnly = 1 in {
1938// The POWER6 and POWER7 have special group-terminating nops.
1939def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1940                                        "ori 1, 1, 0", IIC_IntSimple, []>;
1941def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1942                                        "ori 2, 2, 0", IIC_IntSimple, []>;
1943}
1944
1945let isCompare = 1, hasSideEffects = 0 in {
1946  def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1947                          "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1948  def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1949                           "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1950}
1951}
1952
1953let PPC970_Unit = 1, hasSideEffects = 0 in {  // FXU Operations.
1954let isCommutable = 1 in {
1955defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1956                     "nand", "$rA, $rS, $rB", IIC_IntSimple,
1957                     [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1958defm AND  : XForm_6r<31,  28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1959                     "and", "$rA, $rS, $rB", IIC_IntSimple,
1960                     [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1961} // isCommutable
1962defm ANDC : XForm_6r<31,  60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1963                     "andc", "$rA, $rS, $rB", IIC_IntSimple,
1964                     [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1965let isCommutable = 1 in {
1966defm OR   : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1967                     "or", "$rA, $rS, $rB", IIC_IntSimple,
1968                     [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1969defm NOR  : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1970                     "nor", "$rA, $rS, $rB", IIC_IntSimple,
1971                     [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1972} // isCommutable
1973defm ORC  : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1974                     "orc", "$rA, $rS, $rB", IIC_IntSimple,
1975                     [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1976let isCommutable = 1 in {
1977defm EQV  : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1978                     "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1979                     [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1980defm XOR  : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1981                     "xor", "$rA, $rS, $rB", IIC_IntSimple,
1982                     [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1983} // isCommutable
1984defm SLW  : XForm_6r<31,  24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1985                     "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1986                     [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1987defm SRW  : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1988                     "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1989                     [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1990defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1991                      "sraw", "$rA, $rS, $rB", IIC_IntShift,
1992                      [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1993}
1994
1995let PPC970_Unit = 1 in {  // FXU Operations.
1996let hasSideEffects = 0 in {
1997defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1998                        "srawi", "$rA, $rS, $SH", IIC_IntShift,
1999                        [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
2000defm CNTLZW : XForm_11r<31,  26, (outs gprc:$rA), (ins gprc:$rS),
2001                        "cntlzw", "$rA, $rS", IIC_IntGeneral,
2002                        [(set i32:$rA, (ctlz i32:$rS))]>;
2003defm EXTSB  : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
2004                        "extsb", "$rA, $rS", IIC_IntSimple,
2005                        [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
2006defm EXTSH  : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
2007                        "extsh", "$rA, $rS", IIC_IntSimple,
2008                        [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
2009
2010let isCommutable = 1 in
2011def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2012                   "cmpb $rA, $rS, $rB", IIC_IntGeneral,
2013                   [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>;
2014}
2015let isCompare = 1, hasSideEffects = 0 in {
2016  def CMPW   : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
2017                            "cmpw $crD, $rA, $rB", IIC_IntCompare>;
2018  def CMPLW  : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
2019                            "cmplw $crD, $rA, $rB", IIC_IntCompare>;
2020}
2021}
2022let PPC970_Unit = 3 in {  // FPU Operations.
2023//def FCMPO  : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
2024//                      "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
2025let isCompare = 1, hasSideEffects = 0 in {
2026  def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
2027                        "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
2028  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2029  def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
2030                        "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
2031}
2032
2033let Uses = [RM] in {
2034  let hasSideEffects = 0 in {
2035  defm FCTIW  : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
2036                          "fctiw", "$frD, $frB", IIC_FPGeneral,
2037                          []>;
2038  defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
2039                          "fctiwz", "$frD, $frB", IIC_FPGeneral,
2040                          [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
2041
2042  defm FRSP   : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
2043                          "frsp", "$frD, $frB", IIC_FPGeneral,
2044                          [(set f32:$frD, (fround f64:$frB))]>;
2045
2046  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2047  defm FRIND  : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
2048                          "frin", "$frD, $frB", IIC_FPGeneral,
2049                          [(set f64:$frD, (frnd f64:$frB))]>;
2050  defm FRINS  : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
2051                          "frin", "$frD, $frB", IIC_FPGeneral,
2052                          [(set f32:$frD, (frnd f32:$frB))]>;
2053  }
2054
2055  let hasSideEffects = 0 in {
2056  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2057  defm FRIPD  : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
2058                          "frip", "$frD, $frB", IIC_FPGeneral,
2059                          [(set f64:$frD, (fceil f64:$frB))]>;
2060  defm FRIPS  : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
2061                          "frip", "$frD, $frB", IIC_FPGeneral,
2062                          [(set f32:$frD, (fceil f32:$frB))]>;
2063  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2064  defm FRIZD  : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
2065                          "friz", "$frD, $frB", IIC_FPGeneral,
2066                          [(set f64:$frD, (ftrunc f64:$frB))]>;
2067  defm FRIZS  : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
2068                          "friz", "$frD, $frB", IIC_FPGeneral,
2069                          [(set f32:$frD, (ftrunc f32:$frB))]>;
2070  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2071  defm FRIMD  : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
2072                          "frim", "$frD, $frB", IIC_FPGeneral,
2073                          [(set f64:$frD, (ffloor f64:$frB))]>;
2074  defm FRIMS  : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
2075                          "frim", "$frD, $frB", IIC_FPGeneral,
2076                          [(set f32:$frD, (ffloor f32:$frB))]>;
2077
2078  defm FSQRT  : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
2079                          "fsqrt", "$frD, $frB", IIC_FPSqrtD,
2080                          [(set f64:$frD, (fsqrt f64:$frB))]>;
2081  defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
2082                          "fsqrts", "$frD, $frB", IIC_FPSqrtS,
2083                          [(set f32:$frD, (fsqrt f32:$frB))]>;
2084  }
2085  }
2086}
2087
2088/// Note that FMR is defined as pseudo-ops on the PPC970 because they are
2089/// often coalesced away and we don't want the dispatch group builder to think
2090/// that they will fill slots (which could cause the load of a LSU reject to
2091/// sneak into a d-group with a store).
2092let hasSideEffects = 0 in
2093defm FMR   : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
2094                       "fmr", "$frD, $frB", IIC_FPGeneral,
2095                       []>,  // (set f32:$frD, f32:$frB)
2096                       PPC970_Unit_Pseudo;
2097
2098let PPC970_Unit = 3, hasSideEffects = 0 in {  // FPU Operations.
2099// These are artificially split into two different forms, for 4/8 byte FP.
2100defm FABSS  : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
2101                        "fabs", "$frD, $frB", IIC_FPGeneral,
2102                        [(set f32:$frD, (fabs f32:$frB))]>;
2103let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2104defm FABSD  : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
2105                        "fabs", "$frD, $frB", IIC_FPGeneral,
2106                        [(set f64:$frD, (fabs f64:$frB))]>;
2107defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
2108                        "fnabs", "$frD, $frB", IIC_FPGeneral,
2109                        [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
2110let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2111defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
2112                        "fnabs", "$frD, $frB", IIC_FPGeneral,
2113                        [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
2114defm FNEGS  : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
2115                        "fneg", "$frD, $frB", IIC_FPGeneral,
2116                        [(set f32:$frD, (fneg f32:$frB))]>;
2117let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2118defm FNEGD  : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
2119                        "fneg", "$frD, $frB", IIC_FPGeneral,
2120                        [(set f64:$frD, (fneg f64:$frB))]>;
2121
2122defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
2123                        "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2124                        [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
2125let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2126defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
2127                        "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2128                        [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
2129
2130// Reciprocal estimates.
2131defm FRE      : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
2132                          "fre", "$frD, $frB", IIC_FPGeneral,
2133                          [(set f64:$frD, (PPCfre f64:$frB))]>;
2134defm FRES     : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
2135                          "fres", "$frD, $frB", IIC_FPGeneral,
2136                          [(set f32:$frD, (PPCfre f32:$frB))]>;
2137defm FRSQRTE  : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
2138                          "frsqrte", "$frD, $frB", IIC_FPGeneral,
2139                          [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
2140defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
2141                          "frsqrtes", "$frD, $frB", IIC_FPGeneral,
2142                          [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
2143}
2144
2145// XL-Form instructions.  condition register logical ops.
2146//
2147let hasSideEffects = 0 in
2148def MCRF   : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
2149                      "mcrf $BF, $BFA", IIC_BrMCR>,
2150             PPC970_DGroup_First, PPC970_Unit_CRU;
2151
2152// FIXME: According to the ISA (section 2.5.1 of version 2.06), the
2153// condition-register logical instructions have preferred forms. Specifically,
2154// it is preferred that the bit specified by the BT field be in the same
2155// condition register as that specified by the bit BB. We might want to account
2156// for this via hinting the register allocator and anti-dep breakers, or we
2157// could constrain the register class to force this constraint and then loosen
2158// it during register allocation via convertToThreeAddress or some similar
2159// mechanism.
2160
2161let isCommutable = 1 in {
2162def CRAND  : XLForm_1<19, 257, (outs crbitrc:$CRD),
2163                               (ins crbitrc:$CRA, crbitrc:$CRB),
2164                      "crand $CRD, $CRA, $CRB", IIC_BrCR,
2165                      [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2166
2167def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2168                               (ins crbitrc:$CRA, crbitrc:$CRB),
2169                      "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2170                      [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2171
2172def CROR   : XLForm_1<19, 449, (outs crbitrc:$CRD),
2173                               (ins crbitrc:$CRA, crbitrc:$CRB),
2174                      "cror $CRD, $CRA, $CRB", IIC_BrCR,
2175                      [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2176
2177def CRXOR  : XLForm_1<19, 193, (outs crbitrc:$CRD),
2178                               (ins crbitrc:$CRA, crbitrc:$CRB),
2179                      "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2180                      [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2181
2182def CRNOR  : XLForm_1<19, 33, (outs crbitrc:$CRD),
2183                              (ins crbitrc:$CRA, crbitrc:$CRB),
2184                      "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2185                      [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2186
2187def CREQV  : XLForm_1<19, 289, (outs crbitrc:$CRD),
2188                               (ins crbitrc:$CRA, crbitrc:$CRB),
2189                      "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2190                      [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2191} // isCommutable
2192
2193def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2194                               (ins crbitrc:$CRA, crbitrc:$CRB),
2195                      "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2196                      [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2197
2198def CRORC  : XLForm_1<19, 417, (outs crbitrc:$CRD),
2199                               (ins crbitrc:$CRA, crbitrc:$CRB),
2200                      "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2201                      [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2202
2203let isCodeGenOnly = 1 in {
2204def CRSET  : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2205              "creqv $dst, $dst, $dst", IIC_BrCR,
2206              [(set i1:$dst, 1)]>;
2207
2208def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2209              "crxor $dst, $dst, $dst", IIC_BrCR,
2210              [(set i1:$dst, 0)]>;
2211
2212let Defs = [CR1EQ], CRD = 6 in {
2213def CR6SET  : XLForm_1_ext<19, 289, (outs), (ins),
2214              "creqv 6, 6, 6", IIC_BrCR,
2215              [(PPCcr6set)]>;
2216
2217def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2218              "crxor 6, 6, 6", IIC_BrCR,
2219              [(PPCcr6unset)]>;
2220}
2221}
2222
2223// XFX-Form instructions.  Instructions that deal with SPRs.
2224//
2225
2226def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2227                      "mfspr $RT, $SPR", IIC_SprMFSPR>;
2228def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2229                      "mtspr $SPR, $RT", IIC_SprMTSPR>;
2230
2231def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2232                     "mftb $RT, $SPR", IIC_SprMFTB>;
2233
2234// A pseudo-instruction used to implement the read of the 64-bit cycle counter
2235// on a 32-bit target.
2236let hasSideEffects = 1, usesCustomInserter = 1 in
2237def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins),
2238                    "#ReadTB", []>;
2239
2240let Uses = [CTR] in {
2241def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2242                          "mfctr $rT", IIC_SprMFSPR>,
2243            PPC970_DGroup_First, PPC970_Unit_FXU;
2244}
2245let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2246def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2247                          "mtctr $rS", IIC_SprMTSPR>,
2248            PPC970_DGroup_First, PPC970_Unit_FXU;
2249}
2250let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2251let Pattern = [(int_ppc_mtctr i32:$rS)] in
2252def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2253                              "mtctr $rS", IIC_SprMTSPR>,
2254                PPC970_DGroup_First, PPC970_Unit_FXU;
2255}
2256
2257let Defs = [LR] in {
2258def MTLR  : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2259                          "mtlr $rS", IIC_SprMTSPR>,
2260            PPC970_DGroup_First, PPC970_Unit_FXU;
2261}
2262let Uses = [LR] in {
2263def MFLR  : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2264                          "mflr $rT", IIC_SprMFSPR>,
2265            PPC970_DGroup_First, PPC970_Unit_FXU;
2266}
2267
2268let isCodeGenOnly = 1 in {
2269  // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2270  // like a GPR on the PPC970.  As such, copies in and out have the same
2271  // performance characteristics as an OR instruction.
2272  def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2273                               "mtspr 256, $rS", IIC_IntGeneral>,
2274                 PPC970_DGroup_Single, PPC970_Unit_FXU;
2275  def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2276                               "mfspr $rT, 256", IIC_IntGeneral>,
2277                 PPC970_DGroup_First, PPC970_Unit_FXU;
2278
2279  def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2280                                (outs VRSAVERC:$reg), (ins gprc:$rS),
2281                                "mtspr 256, $rS", IIC_IntGeneral>,
2282                  PPC970_DGroup_Single, PPC970_Unit_FXU;
2283  def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2284                                (ins VRSAVERC:$reg),
2285                                "mfspr $rT, 256", IIC_IntGeneral>,
2286                  PPC970_DGroup_First, PPC970_Unit_FXU;
2287}
2288
2289// SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2290// so we'll need to scavenge a register for it.
2291let mayStore = 1 in
2292def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2293                     "#SPILL_VRSAVE", []>;
2294
2295// RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2296// spilled), so we'll need to scavenge a register for it.
2297let mayLoad = 1 in
2298def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2299                     "#RESTORE_VRSAVE", []>;
2300
2301let hasSideEffects = 0 in {
2302// mtocrf's input needs to be prepared by shifting by an amount dependent
2303// on the cr register selected. Thus, post-ra anti-dep breaking must not
2304// later change that register assignment.
2305let hasExtraDefRegAllocReq = 1 in {
2306def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2307                       "mtocrf $FXM, $ST", IIC_BrMCRX>,
2308            PPC970_DGroup_First, PPC970_Unit_CRU;
2309
2310// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that
2311// is dependent on the cr fields being set.
2312def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2313                      "mtcrf $FXM, $rS", IIC_BrMCRX>,
2314            PPC970_MicroCode, PPC970_Unit_CRU;
2315} // hasExtraDefRegAllocReq = 1
2316
2317// mfocrf's input needs to be prepared by shifting by an amount dependent
2318// on the cr register selected. Thus, post-ra anti-dep breaking must not
2319// later change that register assignment.
2320let hasExtraSrcRegAllocReq = 1 in {
2321def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2322                       "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2323            PPC970_DGroup_First, PPC970_Unit_CRU;
2324
2325// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that
2326// is dependent on the cr fields being copied.
2327def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2328                     "mfcr $rT", IIC_SprMFCR>,
2329                     PPC970_MicroCode, PPC970_Unit_CRU;
2330} // hasExtraSrcRegAllocReq = 1
2331} // hasSideEffects = 0
2332
2333// Pseudo instruction to perform FADD in round-to-zero mode.
2334let usesCustomInserter = 1, Uses = [RM] in {
2335  def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2336                      [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2337}
2338
2339// The above pseudo gets expanded to make use of the following instructions
2340// to manipulate FPSCR.  Note that FPSCR is not modeled at the DAG level.
2341let Uses = [RM], Defs = [RM] in {
2342  def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2343                        "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2344               PPC970_DGroup_Single, PPC970_Unit_FPU;
2345  def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2346                        "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2347               PPC970_DGroup_Single, PPC970_Unit_FPU;
2348  let isCodeGenOnly = 1 in
2349  def MTFSFb  : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2350                        "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2351                PPC970_DGroup_Single, PPC970_Unit_FPU;
2352}
2353let Uses = [RM] in {
2354  def MFFS   : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2355                         "mffs $rT", IIC_IntMFFS,
2356                         [(set f64:$rT, (PPCmffs))]>,
2357               PPC970_DGroup_Single, PPC970_Unit_FPU;
2358
2359  let Defs = [CR1] in
2360  def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2361                      "mffs. $rT", IIC_IntMFFS, []>, isDOT;
2362}
2363
2364
2365let PPC970_Unit = 1, hasSideEffects = 0 in {  // FXU Operations.
2366// XO-Form instructions.  Arithmetic instructions that can set overflow bit
2367let isCommutable = 1 in
2368defm ADD4  : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2369                       "add", "$rT, $rA, $rB", IIC_IntSimple,
2370                       [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2371let isCodeGenOnly = 1 in
2372def ADD4TLS  : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2373                       "add $rT, $rA, $rB", IIC_IntSimple,
2374                       [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2375let isCommutable = 1 in
2376defm ADDC  : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2377                        "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2378                        [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2379                        PPC970_DGroup_Cracked;
2380
2381defm DIVW  : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2382                          "divw", "$rT, $rA, $rB", IIC_IntDivW,
2383                          [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>;
2384defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2385                          "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2386                          [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>;
2387def DIVWE : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2388                     "divwe $rT, $rA, $rB", IIC_IntDivW,
2389                     [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>,
2390                     Requires<[HasExtDiv]>;
2391let Defs = [CR0] in
2392def DIVWEo : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2393                      "divwe. $rT, $rA, $rB", IIC_IntDivW,
2394                      []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2395                      Requires<[HasExtDiv]>;
2396def DIVWEU : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2397                      "divweu $rT, $rA, $rB", IIC_IntDivW,
2398                      [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>,
2399                      Requires<[HasExtDiv]>;
2400let Defs = [CR0] in
2401def DIVWEUo : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2402                       "divweu. $rT, $rA, $rB", IIC_IntDivW,
2403                       []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2404                       Requires<[HasExtDiv]>;
2405let isCommutable = 1 in {
2406defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2407                       "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2408                       [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2409defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2410                       "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2411                       [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2412defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2413                       "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2414                       [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2415} // isCommutable
2416defm SUBF  : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2417                       "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2418                       [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2419defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2420                        "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2421                        [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2422                        PPC970_DGroup_Cracked;
2423defm NEG    : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2424                        "neg", "$rT, $rA", IIC_IntSimple,
2425                        [(set i32:$rT, (ineg i32:$rA))]>;
2426let Uses = [CARRY] in {
2427let isCommutable = 1 in
2428defm ADDE  : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2429                        "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2430                        [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2431defm ADDME  : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2432                         "addme", "$rT, $rA", IIC_IntGeneral,
2433                         [(set i32:$rT, (adde i32:$rA, -1))]>;
2434defm ADDZE  : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2435                         "addze", "$rT, $rA", IIC_IntGeneral,
2436                         [(set i32:$rT, (adde i32:$rA, 0))]>;
2437defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2438                        "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2439                        [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2440defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2441                         "subfme", "$rT, $rA", IIC_IntGeneral,
2442                         [(set i32:$rT, (sube -1, i32:$rA))]>;
2443defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2444                         "subfze", "$rT, $rA", IIC_IntGeneral,
2445                         [(set i32:$rT, (sube 0, i32:$rA))]>;
2446}
2447}
2448
2449// A-Form instructions.  Most of the instructions executed in the FPU are of
2450// this type.
2451//
2452let PPC970_Unit = 3, hasSideEffects = 0 in {  // FPU Operations.
2453let Uses = [RM] in {
2454let isCommutable = 1 in {
2455  defm FMADD : AForm_1r<63, 29,
2456                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2457                      "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2458                      [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2459  defm FMADDS : AForm_1r<59, 29,
2460                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2461                      "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2462                      [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2463  defm FMSUB : AForm_1r<63, 28,
2464                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2465                      "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2466                      [(set f64:$FRT,
2467                            (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2468  defm FMSUBS : AForm_1r<59, 28,
2469                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2470                      "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2471                      [(set f32:$FRT,
2472                            (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2473  defm FNMADD : AForm_1r<63, 31,
2474                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2475                      "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2476                      [(set f64:$FRT,
2477                            (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2478  defm FNMADDS : AForm_1r<59, 31,
2479                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2480                      "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2481                      [(set f32:$FRT,
2482                            (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2483  defm FNMSUB : AForm_1r<63, 30,
2484                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2485                      "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2486                      [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2487                                                 (fneg f64:$FRB))))]>;
2488  defm FNMSUBS : AForm_1r<59, 30,
2489                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2490                      "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2491                      [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2492                                                 (fneg f32:$FRB))))]>;
2493} // isCommutable
2494}
2495// FSEL is artificially split into 4 and 8-byte forms for the result.  To avoid
2496// having 4 of these, force the comparison to always be an 8-byte double (code
2497// should use an FMRSD if the input comparison value really wants to be a float)
2498// and 4/8 byte forms for the result and operand type..
2499let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2500defm FSELD : AForm_1r<63, 23,
2501                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2502                      "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2503                      [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2504defm FSELS : AForm_1r<63, 23,
2505                      (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2506                      "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2507                      [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2508let Uses = [RM] in {
2509  let isCommutable = 1 in {
2510  defm FADD  : AForm_2r<63, 21,
2511                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2512                        "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2513                        [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2514  defm FADDS : AForm_2r<59, 21,
2515                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2516                        "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2517                        [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2518  } // isCommutable
2519  defm FDIV  : AForm_2r<63, 18,
2520                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2521                        "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2522                        [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2523  defm FDIVS : AForm_2r<59, 18,
2524                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2525                        "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2526                        [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2527  let isCommutable = 1 in {
2528  defm FMUL  : AForm_3r<63, 25,
2529                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2530                        "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2531                        [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2532  defm FMULS : AForm_3r<59, 25,
2533                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2534                        "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2535                        [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2536  } // isCommutable
2537  defm FSUB  : AForm_2r<63, 20,
2538                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2539                        "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2540                        [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2541  defm FSUBS : AForm_2r<59, 20,
2542                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2543                        "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2544                        [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2545  }
2546}
2547
2548let hasSideEffects = 0 in {
2549let PPC970_Unit = 1 in {  // FXU Operations.
2550  let isSelect = 1 in
2551  def ISEL  : AForm_4<31, 15,
2552                     (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2553                     "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
2554                     []>;
2555}
2556
2557let PPC970_Unit = 1 in {  // FXU Operations.
2558// M-Form instructions.  rotate and mask instructions.
2559//
2560let isCommutable = 1 in {
2561// RLWIMI can be commuted if the rotate amount is zero.
2562defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2563                       (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2564                       u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2565                       IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2566                       RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2567}
2568let BaseName = "rlwinm" in {
2569def RLWINM : MForm_2<21,
2570                     (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2571                     "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2572                     []>, RecFormRel;
2573let Defs = [CR0] in
2574def RLWINMo : MForm_2<21,
2575                      (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2576                      "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2577                      []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2578}
2579defm RLWNM  : MForm_2r<23, (outs gprc:$rA),
2580                       (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2581                       "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2582                       []>;
2583}
2584} // hasSideEffects = 0
2585
2586//===----------------------------------------------------------------------===//
2587// PowerPC Instruction Patterns
2588//
2589
2590// Arbitrary immediate support.  Implement in terms of LIS/ORI.
2591def : Pat<(i32 imm:$imm),
2592          (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2593
2594// Implement the 'not' operation with the NOR instruction.
2595def i32not : OutPatFrag<(ops node:$in),
2596                        (NOR $in, $in)>;
2597def        : Pat<(not i32:$in),
2598                 (i32not $in)>;
2599
2600// ADD an arbitrary immediate.
2601def : Pat<(add i32:$in, imm:$imm),
2602          (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2603// OR an arbitrary immediate.
2604def : Pat<(or i32:$in, imm:$imm),
2605          (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2606// XOR an arbitrary immediate.
2607def : Pat<(xor i32:$in, imm:$imm),
2608          (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2609// SUBFIC
2610def : Pat<(sub imm32SExt16:$imm, i32:$in),
2611          (SUBFIC $in, imm:$imm)>;
2612
2613// SHL/SRL
2614def : Pat<(shl i32:$in, (i32 imm:$imm)),
2615          (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2616def : Pat<(srl i32:$in, (i32 imm:$imm)),
2617          (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2618
2619// ROTL
2620def : Pat<(rotl i32:$in, i32:$sh),
2621          (RLWNM $in, $sh, 0, 31)>;
2622def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2623          (RLWINM $in, imm:$imm, 0, 31)>;
2624
2625// RLWNM
2626def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2627          (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2628
2629// Calls
2630def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2631          (BL tglobaladdr:$dst)>;
2632def : Pat<(PPCcall (i32 texternalsym:$dst)),
2633          (BL texternalsym:$dst)>;
2634
2635def : Pat<(PPCtc_return (i32 tglobaladdr:$dst),  imm:$imm),
2636          (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2637
2638def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2639          (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2640
2641def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2642          (TCRETURNri CTRRC:$dst, imm:$imm)>;
2643
2644
2645
2646// Hi and Lo for Darwin Global Addresses.
2647def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2648def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2649def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2650def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2651def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2652def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2653def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2654def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2655def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2656          (ADDIS $in, tglobaltlsaddr:$g)>;
2657def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2658          (ADDI $in, tglobaltlsaddr:$g)>;
2659def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2660          (ADDIS $in, tglobaladdr:$g)>;
2661def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2662          (ADDIS $in, tconstpool:$g)>;
2663def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2664          (ADDIS $in, tjumptable:$g)>;
2665def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2666          (ADDIS $in, tblockaddress:$g)>;
2667
2668// Support for thread-local storage.
2669def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2670                [(set i32:$rD, (PPCppc32GOT))]>;
2671
2672// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2673// This uses two output registers, the first as the real output, the second as a
2674// temporary register, used internally in code generation.
2675def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2676                []>, NoEncode<"$rT">;
2677
2678def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2679                           "#LDgotTprelL32",
2680                           [(set i32:$rD,
2681                             (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2682def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2683          (ADD4TLS $in, tglobaltlsaddr:$g)>;
2684
2685def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2686                         "#ADDItlsgdL32",
2687                         [(set i32:$rD,
2688                           (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2689// LR is a true define, while the rest of the Defs are clobbers.  R3 is
2690// explicitly defined when this op is created, so not mentioned here.
2691let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2692    Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2693def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2694                          "GETtlsADDR32",
2695                          [(set i32:$rD,
2696                            (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2697// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded.  R3 and LR
2698// are true defines while the rest of the Defs are clobbers.
2699let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2700    Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2701def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD),
2702                              (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2703                              "#ADDItlsgdLADDR32",
2704                              [(set i32:$rD,
2705                                (PPCaddiTlsgdLAddr i32:$reg,
2706                                                   tglobaltlsaddr:$disp,
2707                                                   tglobaltlsaddr:$sym))]>;
2708def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2709                          "#ADDItlsldL32",
2710                          [(set i32:$rD,
2711                            (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2712// LR is a true define, while the rest of the Defs are clobbers.  R3 is
2713// explicitly defined when this op is created, so not mentioned here.
2714let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2715    Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2716def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2717                            "GETtlsldADDR32",
2718                            [(set i32:$rD,
2719                              (PPCgetTlsldAddr i32:$reg,
2720                                               tglobaltlsaddr:$sym))]>;
2721// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded.  R3 and LR
2722// are true defines while the rest of the Defs are clobbers.
2723let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2724    Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2725def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD),
2726                              (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2727                              "#ADDItlsldLADDR32",
2728                              [(set i32:$rD,
2729                                (PPCaddiTlsldLAddr i32:$reg,
2730                                                   tglobaltlsaddr:$disp,
2731                                                   tglobaltlsaddr:$sym))]>;
2732def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2733                           "#ADDIdtprelL32",
2734                           [(set i32:$rD,
2735                             (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2736def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2737                            "#ADDISdtprelHA32",
2738                            [(set i32:$rD,
2739                              (PPCaddisDtprelHA i32:$reg,
2740                                                tglobaltlsaddr:$disp))]>;
2741
2742// Support for Position-independent code
2743def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2744                   "#LWZtoc",
2745                   [(set i32:$rD,
2746                      (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2747// Get Global (GOT) Base Register offset, from the word immediately preceding
2748// the function label.
2749def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2750
2751
2752// Standard shifts.  These are represented separately from the real shifts above
2753// so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2754// amounts.
2755def : Pat<(sra i32:$rS, i32:$rB),
2756          (SRAW $rS, $rB)>;
2757def : Pat<(srl i32:$rS, i32:$rB),
2758          (SRW $rS, $rB)>;
2759def : Pat<(shl i32:$rS, i32:$rB),
2760          (SLW $rS, $rB)>;
2761
2762def : Pat<(zextloadi1 iaddr:$src),
2763          (LBZ iaddr:$src)>;
2764def : Pat<(zextloadi1 xaddr:$src),
2765          (LBZX xaddr:$src)>;
2766def : Pat<(extloadi1 iaddr:$src),
2767          (LBZ iaddr:$src)>;
2768def : Pat<(extloadi1 xaddr:$src),
2769          (LBZX xaddr:$src)>;
2770def : Pat<(extloadi8 iaddr:$src),
2771          (LBZ iaddr:$src)>;
2772def : Pat<(extloadi8 xaddr:$src),
2773          (LBZX xaddr:$src)>;
2774def : Pat<(extloadi16 iaddr:$src),
2775          (LHZ iaddr:$src)>;
2776def : Pat<(extloadi16 xaddr:$src),
2777          (LHZX xaddr:$src)>;
2778def : Pat<(f64 (extloadf32 iaddr:$src)),
2779          (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2780def : Pat<(f64 (extloadf32 xaddr:$src)),
2781          (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2782
2783def : Pat<(f64 (fextend f32:$src)),
2784          (COPY_TO_REGCLASS $src, F8RC)>;
2785
2786// Only seq_cst fences require the heavyweight sync (SYNC 0).
2787// All others can use the lightweight sync (SYNC 1).
2788// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
2789// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
2790// versions of Power.
2791def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2792def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2793def : Pat<(atomic_fence (imm),   (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
2794def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2795
2796// Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2797def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2798          (FNMSUB $A, $C, $B)>;
2799def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2800          (FNMSUB $A, $C, $B)>;
2801def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2802          (FNMSUBS $A, $C, $B)>;
2803def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2804          (FNMSUBS $A, $C, $B)>;
2805
2806// FCOPYSIGN's operand types need not agree.
2807def : Pat<(fcopysign f64:$frB, f32:$frA),
2808          (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2809def : Pat<(fcopysign f32:$frB, f64:$frA),
2810          (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2811
2812include "PPCInstrAltivec.td"
2813include "PPCInstrSPE.td"
2814include "PPCInstr64Bit.td"
2815include "PPCInstrVSX.td"
2816include "PPCInstrQPX.td"
2817include "PPCInstrHTM.td"
2818
2819def crnot : OutPatFrag<(ops node:$in),
2820                       (CRNOR $in, $in)>;
2821def       : Pat<(not i1:$in),
2822                (crnot $in)>;
2823
2824// Patterns for arithmetic i1 operations.
2825def : Pat<(add i1:$a, i1:$b),
2826          (CRXOR $a, $b)>;
2827def : Pat<(sub i1:$a, i1:$b),
2828          (CRXOR $a, $b)>;
2829def : Pat<(mul i1:$a, i1:$b),
2830          (CRAND $a, $b)>;
2831
2832// We're sometimes asked to materialize i1 -1, which is just 1 in this case
2833// (-1 is used to mean all bits set).
2834def : Pat<(i1 -1), (CRSET)>;
2835
2836// i1 extensions, implemented in terms of isel.
2837def : Pat<(i32 (zext i1:$in)),
2838          (SELECT_I4 $in, (LI 1), (LI 0))>;
2839def : Pat<(i32 (sext i1:$in)),
2840          (SELECT_I4 $in, (LI -1), (LI 0))>;
2841
2842def : Pat<(i64 (zext i1:$in)),
2843          (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2844def : Pat<(i64 (sext i1:$in)),
2845          (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2846
2847// FIXME: We should choose either a zext or a sext based on other constants
2848// already around.
2849def : Pat<(i32 (anyext i1:$in)),
2850          (SELECT_I4 $in, (LI 1), (LI 0))>;
2851def : Pat<(i64 (anyext i1:$in)),
2852          (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2853
2854// match setcc on i1 variables.
2855// CRANDC is:
2856//   1 1 : F
2857//   1 0 : T
2858//   0 1 : F
2859//   0 0 : F
2860//
2861// LT is:
2862//  -1 -1  : F
2863//  -1  0  : T
2864//   0 -1  : F
2865//   0  0  : F
2866//
2867// ULT is:
2868//   1 1 : F
2869//   1 0 : F
2870//   0 1 : T
2871//   0 0 : F
2872def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2873          (CRANDC $s1, $s2)>;
2874def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2875          (CRANDC $s2, $s1)>;
2876// CRORC is:
2877//   1 1 : T
2878//   1 0 : T
2879//   0 1 : F
2880//   0 0 : T
2881//
2882// LE is:
2883//  -1 -1 : T
2884//  -1  0 : T
2885//   0 -1 : F
2886//   0  0 : T
2887//
2888// ULE is:
2889//   1 1 : T
2890//   1 0 : F
2891//   0 1 : T
2892//   0 0 : T
2893def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2894          (CRORC $s1, $s2)>;
2895def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2896          (CRORC $s2, $s1)>;
2897
2898def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2899          (CREQV $s1, $s2)>;
2900
2901// GE is:
2902//  -1 -1 : T
2903//  -1  0 : F
2904//   0 -1 : T
2905//   0  0 : T
2906//
2907// UGE is:
2908//   1 1 : T
2909//   1 0 : T
2910//   0 1 : F
2911//   0 0 : T
2912def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2913          (CRORC $s2, $s1)>;
2914def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2915          (CRORC $s1, $s2)>;
2916
2917// GT is:
2918//  -1 -1 : F
2919//  -1  0 : F
2920//   0 -1 : T
2921//   0  0 : F
2922//
2923// UGT is:
2924//  1 1 : F
2925//  1 0 : T
2926//  0 1 : F
2927//  0 0 : F
2928def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2929          (CRANDC $s2, $s1)>;
2930def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2931          (CRANDC $s1, $s2)>;
2932
2933def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2934          (CRXOR $s1, $s2)>;
2935
2936// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2937// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2938// floating-point types.
2939
2940multiclass CRNotPat<dag pattern, dag result> {
2941  def : Pat<pattern, (crnot result)>;
2942  def : Pat<(not pattern), result>;
2943
2944  // We can also fold the crnot into an extension:
2945  def : Pat<(i32 (zext pattern)),
2946            (SELECT_I4 result, (LI 0), (LI 1))>;
2947  def : Pat<(i32 (sext pattern)),
2948            (SELECT_I4 result, (LI 0), (LI -1))>;
2949
2950  // We can also fold the crnot into an extension:
2951  def : Pat<(i64 (zext pattern)),
2952            (SELECT_I8 result, (LI8 0), (LI8 1))>;
2953  def : Pat<(i64 (sext pattern)),
2954            (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2955
2956  // FIXME: We should choose either a zext or a sext based on other constants
2957  // already around.
2958  def : Pat<(i32 (anyext pattern)),
2959            (SELECT_I4 result, (LI 0), (LI 1))>;
2960
2961  def : Pat<(i64 (anyext pattern)),
2962            (SELECT_I8 result, (LI8 0), (LI8 1))>;
2963}
2964
2965// FIXME: Because of what seems like a bug in TableGen's type-inference code,
2966// we need to write imm:$imm in the output patterns below, not just $imm, or
2967// else the resulting matcher will not correctly add the immediate operand
2968// (making it a register operand instead).
2969
2970// extended SETCC.
2971multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2972                       OutPatFrag rfrag, OutPatFrag rfrag8> {
2973  def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2974            (rfrag $s1)>;
2975  def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2976            (rfrag8 $s1)>;
2977  def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2978            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2979  def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2980            (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2981
2982  def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2983            (rfrag $s1)>;
2984  def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2985            (rfrag8 $s1)>;
2986  def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2987            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2988  def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2989            (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2990}
2991
2992// Note that we do all inversions below with i(32|64)not, instead of using
2993// (xori x, 1) because on the A2 nor has single-cycle latency while xori
2994// has 2-cycle latency.
2995
2996defm : ExtSetCCPat<SETEQ,
2997                   PatFrag<(ops node:$in, node:$cc),
2998                           (setcc $in, 0, $cc)>,
2999                   OutPatFrag<(ops node:$in),
3000                              (RLWINM (CNTLZW $in), 27, 31, 31)>,
3001                   OutPatFrag<(ops node:$in),
3002                              (RLDICL (CNTLZD $in), 58, 63)> >;
3003
3004defm : ExtSetCCPat<SETNE,
3005                   PatFrag<(ops node:$in, node:$cc),
3006                           (setcc $in, 0, $cc)>,
3007                   OutPatFrag<(ops node:$in),
3008                              (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
3009                   OutPatFrag<(ops node:$in),
3010                              (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
3011
3012defm : ExtSetCCPat<SETLT,
3013                   PatFrag<(ops node:$in, node:$cc),
3014                           (setcc $in, 0, $cc)>,
3015                   OutPatFrag<(ops node:$in),
3016                              (RLWINM $in, 1, 31, 31)>,
3017                   OutPatFrag<(ops node:$in),
3018                              (RLDICL $in, 1, 63)> >;
3019
3020defm : ExtSetCCPat<SETGE,
3021                   PatFrag<(ops node:$in, node:$cc),
3022                           (setcc $in, 0, $cc)>,
3023                   OutPatFrag<(ops node:$in),
3024                              (RLWINM (i32not $in), 1, 31, 31)>,
3025                   OutPatFrag<(ops node:$in),
3026                              (RLDICL (i64not $in), 1, 63)> >;
3027
3028defm : ExtSetCCPat<SETGT,
3029                   PatFrag<(ops node:$in, node:$cc),
3030                           (setcc $in, 0, $cc)>,
3031                   OutPatFrag<(ops node:$in),
3032                              (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
3033                   OutPatFrag<(ops node:$in),
3034                              (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
3035
3036defm : ExtSetCCPat<SETLE,
3037                   PatFrag<(ops node:$in, node:$cc),
3038                           (setcc $in, 0, $cc)>,
3039                   OutPatFrag<(ops node:$in),
3040                              (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
3041                   OutPatFrag<(ops node:$in),
3042                              (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
3043
3044defm : ExtSetCCPat<SETLT,
3045                   PatFrag<(ops node:$in, node:$cc),
3046                           (setcc $in, -1, $cc)>,
3047                   OutPatFrag<(ops node:$in),
3048                              (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
3049                   OutPatFrag<(ops node:$in),
3050                              (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3051
3052defm : ExtSetCCPat<SETGE,
3053                   PatFrag<(ops node:$in, node:$cc),
3054                           (setcc $in, -1, $cc)>,
3055                   OutPatFrag<(ops node:$in),
3056                              (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
3057                   OutPatFrag<(ops node:$in),
3058                              (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3059
3060defm : ExtSetCCPat<SETGT,
3061                   PatFrag<(ops node:$in, node:$cc),
3062                           (setcc $in, -1, $cc)>,
3063                   OutPatFrag<(ops node:$in),
3064                              (RLWINM (i32not $in), 1, 31, 31)>,
3065                   OutPatFrag<(ops node:$in),
3066                              (RLDICL (i64not $in), 1, 63)> >;
3067
3068defm : ExtSetCCPat<SETLE,
3069                   PatFrag<(ops node:$in, node:$cc),
3070                           (setcc $in, -1, $cc)>,
3071                   OutPatFrag<(ops node:$in),
3072                              (RLWINM $in, 1, 31, 31)>,
3073                   OutPatFrag<(ops node:$in),
3074                              (RLDICL $in, 1, 63)> >;
3075
3076// SETCC for i32.
3077def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
3078          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3079def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
3080          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3081def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
3082          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3083def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
3084          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3085def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
3086          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3087def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
3088          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3089
3090// For non-equality comparisons, the default code would materialize the
3091// constant, then compare against it, like this:
3092//   lis r2, 4660
3093//   ori r2, r2, 22136
3094//   cmpw cr0, r3, r2
3095//   beq cr0,L6
3096// Since we are just comparing for equality, we can emit this instead:
3097//   xoris r0,r3,0x1234
3098//   cmplwi cr0,r0,0x5678
3099//   beq cr0,L6
3100
3101def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
3102          (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3103                                  (LO16 imm:$imm)), sub_eq)>;
3104
3105defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
3106                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3107defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
3108                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3109defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
3110                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3111defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
3112                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3113defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
3114                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3115defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
3116                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3117
3118defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
3119                (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3120                                        (LO16 imm:$imm)), sub_eq)>;
3121
3122def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
3123          (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3124def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
3125          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3126def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
3127          (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3128def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
3129          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3130def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
3131          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3132
3133defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
3134                (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3135defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
3136                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3137defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
3138                (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3139defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
3140                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3141defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
3142                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3143
3144// SETCC for i64.
3145def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
3146          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3147def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
3148          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3149def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
3150          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3151def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
3152          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3153def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
3154          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3155def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
3156          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3157
3158// For non-equality comparisons, the default code would materialize the
3159// constant, then compare against it, like this:
3160//   lis r2, 4660
3161//   ori r2, r2, 22136
3162//   cmpd cr0, r3, r2
3163//   beq cr0,L6
3164// Since we are just comparing for equality, we can emit this instead:
3165//   xoris r0,r3,0x1234
3166//   cmpldi cr0,r0,0x5678
3167//   beq cr0,L6
3168
3169def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
3170          (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3171                                  (LO16 imm:$imm)), sub_eq)>;
3172
3173defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3174                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3175defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
3176                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3177defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
3178                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3179defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
3180                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3181defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
3182                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3183defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
3184                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3185
3186defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
3187                (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3188                                        (LO16 imm:$imm)), sub_eq)>;
3189
3190def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
3191          (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3192def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3193          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3194def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3195          (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3196def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
3197          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3198def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
3199          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3200
3201defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3202                (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3203defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
3204                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3205defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
3206                (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3207defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
3208                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3209defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
3210                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3211
3212// SETCC for f32.
3213def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
3214          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3215def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
3216          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3217def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
3218          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3219def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
3220          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3221def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
3222          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3223def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
3224          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3225def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
3226          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3227
3228defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3229                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3230defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
3231                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3232defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
3233                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3234defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
3235                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3236defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
3237                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3238defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
3239                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3240defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
3241                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3242
3243// SETCC for f64.
3244def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
3245          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3246def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
3247          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3248def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
3249          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3250def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
3251          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3252def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
3253          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3254def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
3255          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3256def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
3257          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3258
3259defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3260                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3261defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
3262                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3263defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
3264                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3265defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
3266                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3267defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
3268                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3269defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
3270                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3271defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
3272                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3273
3274// match select on i1 variables:
3275def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
3276          (CROR (CRAND        $cond , $tval),
3277                (CRAND (crnot $cond), $fval))>;
3278
3279// match selectcc on i1 variables:
3280//   select (lhs == rhs), tval, fval is:
3281//   ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
3282def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
3283           (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3284                 (CRAND (CRORC  $rhs, $lhs), $fval))>;
3285def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)),
3286           (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3287                 (CRAND (CRORC  $lhs, $rhs), $fval))>;
3288def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
3289           (CROR (CRAND (CRORC  $lhs, $rhs), $tval),
3290                 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3291def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)),
3292           (CROR (CRAND (CRORC  $rhs, $lhs), $tval),
3293                 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3294def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
3295           (CROR (CRAND (CREQV $lhs, $rhs), $tval),
3296                 (CRAND (CRXOR $lhs, $rhs), $fval))>;
3297def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
3298           (CROR (CRAND (CRORC  $rhs, $lhs), $tval),
3299                 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3300def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)),
3301           (CROR (CRAND (CRORC  $lhs, $rhs), $tval),
3302                 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3303def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
3304           (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3305                 (CRAND (CRORC  $lhs, $rhs), $fval))>;
3306def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)),
3307           (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3308                 (CRAND (CRORC  $rhs, $lhs), $fval))>;
3309def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
3310           (CROR (CRAND (CREQV $lhs, $rhs), $fval),
3311                 (CRAND (CRXOR $lhs, $rhs), $tval))>;
3312
3313// match selectcc on i1 variables with non-i1 output.
3314def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3315          (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3316def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)),
3317          (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3318def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3319          (SELECT_I4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3320def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)),
3321          (SELECT_I4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3322def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3323          (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3324def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3325          (SELECT_I4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3326def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)),
3327          (SELECT_I4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3328def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3329          (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3330def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)),
3331          (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3332def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3333          (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3334
3335def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3336          (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3337def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)),
3338          (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3339def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3340          (SELECT_I8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3341def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)),
3342          (SELECT_I8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3343def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3344          (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3345def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3346          (SELECT_I8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3347def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)),
3348          (SELECT_I8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3349def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3350          (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3351def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)),
3352          (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3353def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3354          (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3355
3356def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3357          (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3358def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
3359          (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3360def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3361          (SELECT_F4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3362def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),
3363          (SELECT_F4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3364def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3365          (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3366def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3367          (SELECT_F4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3368def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
3369          (SELECT_F4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3370def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3371          (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3372def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
3373          (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3374def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3375          (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3376
3377def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3378          (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3379def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
3380          (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3381def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3382          (SELECT_F8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3383def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)),
3384          (SELECT_F8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3385def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3386          (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3387def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3388          (SELECT_F8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3389def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
3390          (SELECT_F8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3391def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3392          (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3393def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
3394          (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3395def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3396          (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3397
3398def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3399          (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3400def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)),
3401          (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3402def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3403          (SELECT_VRRC (CRORC  $lhs, $rhs), $tval, $fval)>;
3404def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)),
3405          (SELECT_VRRC (CRORC  $rhs, $lhs), $tval, $fval)>;
3406def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3407          (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3408def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3409          (SELECT_VRRC (CRORC  $rhs, $lhs), $tval, $fval)>;
3410def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)),
3411          (SELECT_VRRC (CRORC  $lhs, $rhs), $tval, $fval)>;
3412def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3413          (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3414def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)),
3415          (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3416def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3417          (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3418
3419let usesCustomInserter = 1 in {
3420def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3421                             "#ANDIo_1_EQ_BIT",
3422                             [(set i1:$dst, (trunc (not i32:$in)))]>;
3423def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3424                             "#ANDIo_1_GT_BIT",
3425                             [(set i1:$dst, (trunc i32:$in))]>;
3426
3427def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3428                              "#ANDIo_1_EQ_BIT8",
3429                              [(set i1:$dst, (trunc (not i64:$in)))]>;
3430def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3431                              "#ANDIo_1_GT_BIT8",
3432                              [(set i1:$dst, (trunc i64:$in))]>;
3433}
3434
3435def : Pat<(i1 (not (trunc i32:$in))),
3436           (ANDIo_1_EQ_BIT $in)>;
3437def : Pat<(i1 (not (trunc i64:$in))),
3438           (ANDIo_1_EQ_BIT8 $in)>;
3439
3440//===----------------------------------------------------------------------===//
3441// PowerPC Instructions used for assembler/disassembler only
3442//
3443
3444// FIXME: For B=0 or B > 8, the registers following RT are used.
3445// WARNING: Do not add patterns for this instruction without fixing this.
3446def LSWI  : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3447                            "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3448
3449// FIXME: For B=0 or B > 8, the registers following RT are used.
3450// WARNING: Do not add patterns for this instruction without fixing this.
3451def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3452                            "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3453
3454def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3455                         "isync", IIC_SprISYNC, []>;
3456
3457def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3458                    "icbi $src", IIC_LdStICBI, []>;
3459
3460// We used to have EIEIO as value but E[0-9A-Z] is a reserved name
3461def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3462                           "eieio", IIC_LdStLoad, []>;
3463
3464def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3465                         "wait $L", IIC_LdStLoad, []>;
3466
3467def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3468                         "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3469
3470def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3471            "mtsr $SR, $RS", IIC_SprMTSR>;
3472
3473def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3474            "mfsr $RS, $SR", IIC_SprMFSR>;
3475
3476def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3477            "mtsrin $RS, $RB", IIC_SprMTSR>;
3478
3479def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3480            "mfsrin $RS, $RB", IIC_SprMFSR>;
3481
3482def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3483                    "mtmsr $RS, $L", IIC_SprMTMSR>;
3484
3485def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3486                    "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3487  let L = 0;
3488}
3489
3490def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3491              Requires<[IsBookE]> {
3492  bits<1> E;
3493
3494  let Inst{16} = E;
3495  let Inst{21-30} = 163;
3496}
3497
3498def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3499               "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3500def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3501               "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3502
3503def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3504def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3505def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3506def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3507
3508def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3509                  "mfmsr $RT", IIC_SprMFMSR, []>;
3510
3511def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3512                    "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3513
3514def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
3515                     "mcrfs $BF, $BFA", IIC_BrMCR>;
3516
3517def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3518                      "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
3519
3520def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3521                       "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
3522
3523def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
3524def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
3525
3526def MTFSF : XFLForm_1<63, 711, (outs),
3527                      (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3528                      "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
3529def MTFSFo : XFLForm_1<63, 711, (outs),
3530                       (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3531                       "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
3532
3533def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3534def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3535
3536def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3537                        "slbie $RB", IIC_SprSLBIE, []>;
3538
3539def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3540                    "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3541
3542def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3543                       "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3544
3545def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3546
3547def TLBIA : XForm_0<31, 370, (outs), (ins),
3548                        "tlbia", IIC_SprTLBIA, []>;
3549
3550def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3551                        "tlbsync", IIC_SprTLBSYNC, []>;
3552
3553def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3554                          "tlbiel $RB", IIC_SprTLBIEL, []>;
3555
3556def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3557                          "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3558def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3559                          "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3560
3561def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3562                          "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3563
3564def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3565                IIC_LdStLoad>, Requires<[IsBookE]>;
3566
3567def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3568                IIC_LdStLoad>, Requires<[IsBookE]>;
3569
3570def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3571                           "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3572
3573def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3574                           "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3575
3576def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3577               "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3578
3579def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3580               "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3581
3582def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3583                             "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3584                             Requires<[IsPPC4xx]>;
3585def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3586                              (ins gprc:$RST, gprc:$A, gprc:$B),
3587                              "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3588                              Requires<[IsPPC4xx]>, isDOT;
3589
3590def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3591
3592def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3593                  Requires<[IsBookE]>;
3594def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3595                   Requires<[IsBookE]>;
3596
3597def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3598                   Requires<[IsE500]>;
3599def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3600                    Requires<[IsE500]>;
3601
3602def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3603                      "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3604def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3605                      "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3606
3607def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
3608
3609def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3610                             "lbzcix $RST, $A, $B", IIC_LdStLoad, []>;
3611def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3612                             "lhzcix $RST, $A, $B", IIC_LdStLoad, []>;
3613def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3614                             "lwzcix $RST, $A, $B", IIC_LdStLoad, []>;
3615def LDCIX :  XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3616                             "ldcix $RST, $A, $B", IIC_LdStLoad, []>;
3617
3618def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3619                             "stbcix $RST, $A, $B", IIC_LdStLoad, []>;
3620def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3621                             "sthcix $RST, $A, $B", IIC_LdStLoad, []>;
3622def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3623                             "stwcix $RST, $A, $B", IIC_LdStLoad, []>;
3624def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3625                             "stdcix $RST, $A, $B", IIC_LdStLoad, []>;
3626
3627//===----------------------------------------------------------------------===//
3628// PowerPC Assembler Instruction Aliases
3629//
3630
3631// Pseudo-instructions for alternate assembly syntax (never used by codegen).
3632// These are aliases that require C++ handling to convert to the target
3633// instruction, while InstAliases can be handled directly by tblgen.
3634class PPCAsmPseudo<string asm, dag iops>
3635  : Instruction {
3636  let Namespace = "PPC";
3637  bit PPC64 = 0;  // Default value, override with isPPC64
3638
3639  let OutOperandList = (outs);
3640  let InOperandList = iops;
3641  let Pattern = [];
3642  let AsmString = asm;
3643  let isAsmParserOnly = 1;
3644  let isPseudo = 1;
3645}
3646
3647def : InstAlias<"sc", (SC 0)>;
3648
3649def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
3650def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>;
3651def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
3652def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
3653
3654def : InstAlias<"wait", (WAIT 0)>;
3655def : InstAlias<"waitrsv", (WAIT 1)>;
3656def : InstAlias<"waitimpl", (WAIT 2)>;
3657
3658def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3659
3660def DCBTx   : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>;
3661def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>;
3662
3663def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3664def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3665def DCBTT  : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>;
3666
3667def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3668def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3669def DCBTSTT  : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>;
3670
3671def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3672def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3673def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3674def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3675
3676def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3677def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3678
3679def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3680def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3681
3682def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3683def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3684
3685def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3686def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3687
3688def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3689def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3690
3691def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3692def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3693
3694def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3695def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3696
3697def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3698def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3699
3700def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3701def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3702
3703def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3704def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3705
3706def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3707def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3708
3709def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3710def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3711
3712def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3713def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3714
3715def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3716def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3717
3718def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3719def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3720def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3721
3722def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3723def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3724
3725def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3726def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3727def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3728def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3729
3730def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3731
3732def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3733def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3734
3735def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3736def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3737
3738def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3739
3740foreach BATR = 0-3 in {
3741    def : InstAlias<"mtdbatu "#BATR#", $Rx",
3742                    (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3743                    Requires<[IsPPC6xx]>;
3744    def : InstAlias<"mfdbatu $Rx, "#BATR,
3745                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3746                    Requires<[IsPPC6xx]>;
3747    def : InstAlias<"mtdbatl "#BATR#", $Rx",
3748                    (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3749                    Requires<[IsPPC6xx]>;
3750    def : InstAlias<"mfdbatl $Rx, "#BATR,
3751                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3752                    Requires<[IsPPC6xx]>;
3753    def : InstAlias<"mtibatu "#BATR#", $Rx",
3754                    (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3755                    Requires<[IsPPC6xx]>;
3756    def : InstAlias<"mfibatu $Rx, "#BATR,
3757                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3758                    Requires<[IsPPC6xx]>;
3759    def : InstAlias<"mtibatl "#BATR#", $Rx",
3760                    (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3761                    Requires<[IsPPC6xx]>;
3762    def : InstAlias<"mfibatl $Rx, "#BATR,
3763                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3764                    Requires<[IsPPC6xx]>;
3765}
3766
3767foreach BR = 0-7 in {
3768    def : InstAlias<"mfbr"#BR#" $Rx",
3769                    (MFDCR gprc:$Rx, !add(BR, 0x80))>,
3770                    Requires<[IsPPC4xx]>;
3771    def : InstAlias<"mtbr"#BR#" $Rx",
3772                    (MTDCR gprc:$Rx, !add(BR, 0x80))>,
3773                    Requires<[IsPPC4xx]>;
3774}
3775
3776def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3777def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
3778
3779def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3780def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
3781
3782def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3783def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
3784
3785def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3786def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
3787
3788def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
3789def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
3790
3791def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3792def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
3793
3794def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3795
3796def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3797                        (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3798def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3799                         (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3800def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3801                         (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3802def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3803                          (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3804
3805def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3806def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3807def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3808def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3809
3810def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3811def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3812
3813def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
3814def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
3815
3816foreach SPRG = 0-3 in {
3817  def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
3818  def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
3819  def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3820  def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3821}
3822foreach SPRG = 4-7 in {
3823  def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
3824                  Requires<[IsBookE]>;
3825  def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
3826                  Requires<[IsBookE]>;
3827  def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3828                  Requires<[IsBookE]>;
3829  def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3830                  Requires<[IsBookE]>;
3831}
3832
3833def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3834
3835def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3836def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3837
3838def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3839
3840def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3841def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3842
3843def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3844def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3845def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3846def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3847
3848def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3849
3850def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
3851                Requires<[IsPPC4xx]>;
3852def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
3853                Requires<[IsPPC4xx]>;
3854def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
3855                Requires<[IsPPC4xx]>;
3856def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
3857                Requires<[IsPPC4xx]>;
3858
3859def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3860                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3861def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3862                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3863def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3864                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3865def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3866                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3867def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3868                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3869def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3870                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3871def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3872                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3873def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3874                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3875def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3876                          (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3877def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3878                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3879def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3880                        (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3881def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3882                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3883def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3884                        (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3885def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3886                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3887def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3888                          (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3889def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3890                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3891def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3892                            (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3893def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3894                             (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3895
3896def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3897def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3898def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3899def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3900def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3901def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3902
3903def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
3904def : InstAlias<"cntlzw. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>;
3905// The POWER variant
3906def : MnemonicAlias<"cntlz",  "cntlzw">;
3907def : MnemonicAlias<"cntlz.", "cntlzw.">;
3908
3909def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3910                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3911def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3912                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3913def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3914                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3915def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3916                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3917def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3918                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3919def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3920                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3921def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3922                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3923def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3924                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3925def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3926                        (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3927def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3928                         (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3929def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3930                        (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3931def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3932                         (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3933def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3934                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3935def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3936                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3937def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3938                            (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3939def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3940                             (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3941
3942def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3943def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3944def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3945def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3946def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3947def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3948
3949def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b",
3950                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3951def RLWINMobm : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b",
3952                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3953def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b",
3954                           (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3955def RLWIMIobm : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b",
3956                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3957def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b",
3958                          (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3959def RLWNMobm : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b",
3960                           (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3961
3962// These generic branch instruction forms are used for the assembler parser only.
3963// Defs and Uses are conservative, since we don't know the BO value.
3964let PPC970_Unit = 7 in {
3965  let Defs = [CTR], Uses = [CTR, RM] in {
3966    def gBC : BForm_3<16, 0, 0, (outs),
3967                      (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3968                      "bc $bo, $bi, $dst">;
3969    def gBCA : BForm_3<16, 1, 0, (outs),
3970                       (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3971                       "bca $bo, $bi, $dst">;
3972  }
3973  let Defs = [LR, CTR], Uses = [CTR, RM] in {
3974    def gBCL : BForm_3<16, 0, 1, (outs),
3975                       (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3976                       "bcl $bo, $bi, $dst">;
3977    def gBCLA : BForm_3<16, 1, 1, (outs),
3978                        (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3979                        "bcla $bo, $bi, $dst">;
3980  }
3981  let Defs = [CTR], Uses = [CTR, LR, RM] in
3982    def gBCLR : XLForm_2<19, 16, 0, (outs),
3983                         (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3984                         "bclr $bo, $bi, $bh", IIC_BrB, []>;
3985  let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3986    def gBCLRL : XLForm_2<19, 16, 1, (outs),
3987                          (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3988                          "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3989  let Defs = [CTR], Uses = [CTR, LR, RM] in
3990    def gBCCTR : XLForm_2<19, 528, 0, (outs),
3991                          (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3992                          "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3993  let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3994    def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3995                           (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3996                           "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3997}
3998def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3999def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
4000def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
4001def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
4002
4003multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
4004  def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
4005  def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
4006  def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
4007  def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
4008  def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
4009  def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
4010}
4011multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
4012  : BranchSimpleMnemonic1<name, pm, bo> {
4013  def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
4014  def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
4015}
4016defm : BranchSimpleMnemonic2<"t", "", 12>;
4017defm : BranchSimpleMnemonic2<"f", "", 4>;
4018defm : BranchSimpleMnemonic2<"t", "-", 14>;
4019defm : BranchSimpleMnemonic2<"f", "-", 6>;
4020defm : BranchSimpleMnemonic2<"t", "+", 15>;
4021defm : BranchSimpleMnemonic2<"f", "+", 7>;
4022defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
4023defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
4024defm : BranchSimpleMnemonic1<"dzt", "", 10>;
4025defm : BranchSimpleMnemonic1<"dzf", "", 2>;
4026
4027multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
4028  def : InstAlias<"b"#name#pm#" $cc, $dst",
4029                  (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
4030  def : InstAlias<"b"#name#pm#" $dst",
4031                  (BCC bibo, CR0, condbrtarget:$dst)>;
4032
4033  def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
4034                  (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
4035  def : InstAlias<"b"#name#"a"#pm#" $dst",
4036                  (BCCA bibo, CR0, abscondbrtarget:$dst)>;
4037
4038  def : InstAlias<"b"#name#"lr"#pm#" $cc",
4039                  (BCCLR bibo, crrc:$cc)>;
4040  def : InstAlias<"b"#name#"lr"#pm,
4041                  (BCCLR bibo, CR0)>;
4042
4043  def : InstAlias<"b"#name#"ctr"#pm#" $cc",
4044                  (BCCCTR bibo, crrc:$cc)>;
4045  def : InstAlias<"b"#name#"ctr"#pm,
4046                  (BCCCTR bibo, CR0)>;
4047
4048  def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
4049                  (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
4050  def : InstAlias<"b"#name#"l"#pm#" $dst",
4051                  (BCCL bibo, CR0, condbrtarget:$dst)>;
4052
4053  def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
4054                  (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
4055  def : InstAlias<"b"#name#"la"#pm#" $dst",
4056                  (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
4057
4058  def : InstAlias<"b"#name#"lrl"#pm#" $cc",
4059                  (BCCLRL bibo, crrc:$cc)>;
4060  def : InstAlias<"b"#name#"lrl"#pm,
4061                  (BCCLRL bibo, CR0)>;
4062
4063  def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
4064                  (BCCCTRL bibo, crrc:$cc)>;
4065  def : InstAlias<"b"#name#"ctrl"#pm,
4066                  (BCCCTRL bibo, CR0)>;
4067}
4068multiclass BranchExtendedMnemonic<string name, int bibo> {
4069  defm : BranchExtendedMnemonicPM<name, "", bibo>;
4070  defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
4071  defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
4072}
4073defm : BranchExtendedMnemonic<"lt", 12>;
4074defm : BranchExtendedMnemonic<"gt", 44>;
4075defm : BranchExtendedMnemonic<"eq", 76>;
4076defm : BranchExtendedMnemonic<"un", 108>;
4077defm : BranchExtendedMnemonic<"so", 108>;
4078defm : BranchExtendedMnemonic<"ge", 4>;
4079defm : BranchExtendedMnemonic<"nl", 4>;
4080defm : BranchExtendedMnemonic<"le", 36>;
4081defm : BranchExtendedMnemonic<"ng", 36>;
4082defm : BranchExtendedMnemonic<"ne", 68>;
4083defm : BranchExtendedMnemonic<"nu", 100>;
4084defm : BranchExtendedMnemonic<"ns", 100>;
4085
4086def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
4087def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
4088def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
4089def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
4090def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
4091def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
4092def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
4093def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
4094
4095def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
4096def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
4097def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
4098def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
4099def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
4100def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
4101def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
4102def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
4103
4104multiclass TrapExtendedMnemonic<string name, int to> {
4105  def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
4106  def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
4107  def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
4108  def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
4109}
4110defm : TrapExtendedMnemonic<"lt", 16>;
4111defm : TrapExtendedMnemonic<"le", 20>;
4112defm : TrapExtendedMnemonic<"eq", 4>;
4113defm : TrapExtendedMnemonic<"ge", 12>;
4114defm : TrapExtendedMnemonic<"gt", 8>;
4115defm : TrapExtendedMnemonic<"nl", 12>;
4116defm : TrapExtendedMnemonic<"ne", 24>;
4117defm : TrapExtendedMnemonic<"ng", 20>;
4118defm : TrapExtendedMnemonic<"llt", 2>;
4119defm : TrapExtendedMnemonic<"lle", 6>;
4120defm : TrapExtendedMnemonic<"lge", 5>;
4121defm : TrapExtendedMnemonic<"lgt", 1>;
4122defm : TrapExtendedMnemonic<"lnl", 5>;
4123defm : TrapExtendedMnemonic<"lng", 6>;
4124defm : TrapExtendedMnemonic<"u", 31>;
4125
4126// Atomic loads
4127def : Pat<(atomic_load_8  iaddr:$src), (LBZ  memri:$src)>;
4128def : Pat<(atomic_load_16 iaddr:$src), (LHZ  memri:$src)>;
4129def : Pat<(atomic_load_32 iaddr:$src), (LWZ  memri:$src)>;
4130def : Pat<(atomic_load_8  xaddr:$src), (LBZX memrr:$src)>;
4131def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
4132def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
4133
4134// Atomic stores
4135def : Pat<(atomic_store_8  iaddr:$ptr, i32:$val), (STB  gprc:$val, memri:$ptr)>;
4136def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH  gprc:$val, memri:$ptr)>;
4137def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW  gprc:$val, memri:$ptr)>;
4138def : Pat<(atomic_store_8  xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
4139def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
4140def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;
4141