1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subset of the 32-bit PowerPC instruction set, as used 11// by the PowerPC instruction selector. 12// 13//===----------------------------------------------------------------------===// 14 15include "PPCInstrFormats.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC specific type constraints. 19// 20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 21 SDTCisVT<0, f64>, SDTCisPtrTy<1> 22]>; 23def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 24def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 25 SDTCisVT<1, i32> ]>; 26def SDT_PPCvperm : SDTypeProfile<1, 3, [ 27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 28]>; 29 30def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 32]>; 33 34def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 36]>; 37 38def SDT_PPClbrx : SDTypeProfile<1, 2, [ 39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 40]>; 41def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 43]>; 44 45def SDT_PPClarx : SDTypeProfile<1, 1, [ 46 SDTCisInt<0>, SDTCisPtrTy<1> 47]>; 48def SDT_PPCstcx : SDTypeProfile<0, 2, [ 49 SDTCisInt<0>, SDTCisPtrTy<1> 50]>; 51 52def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 53 SDTCisPtrTy<0>, SDTCisVT<1, i32> 54]>; 55 56def SDT_PPCnop : SDTypeProfile<0, 0, []>; 57 58//===----------------------------------------------------------------------===// 59// PowerPC specific DAG Nodes. 60// 61 62def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>; 63def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 64def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 65def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 66 [SDNPHasChain, SDNPMayStore]>; 67 68// This sequence is used for long double->int conversions. It changes the 69// bits in the FPSCR which is not modelled. 70def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 71 [SDNPOutGlue]>; 72def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>, 73 [SDNPInGlue, SDNPOutGlue]>; 74def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>, 75 [SDNPInGlue, SDNPOutGlue]>; 76def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, 77 [SDNPInGlue, SDNPOutGlue]>; 78def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3, 79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>, 80 SDTCisVT<3, f64>]>, 81 [SDNPInGlue]>; 82 83def PPCfsel : SDNode<"PPCISD::FSEL", 84 // Type constraint for fsel. 85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 87 88def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 89def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 90def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>; 91def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 92def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 93 94def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 95def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 96 [SDNPMayLoad]>; 97def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 98def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 99def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 100def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 101def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 102def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 103def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 104def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp, 105 [SDNPHasChain]>; 106def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 107 108def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 109 110// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 111// amounts. These nodes are generated by the multi-precision shift code. 112def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 113def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 114def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 115 116def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>; 117def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, 118 [SDNPHasChain, SDNPMayStore]>; 119 120// These are target-independent nodes, but have target-specific formats. 121def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 122 [SDNPHasChain, SDNPOutGlue]>; 123def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 124 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 125 126def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 127def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall, 128 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 129 SDNPVariadic]>; 130def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall, 131 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 132 SDNPVariadic]>; 133def PPCcall_nop_SVR4 : SDNode<"PPCISD::CALL_NOP_SVR4", SDT_PPCCall, 134 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 135 SDNPVariadic]>; 136def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInGlue, SDNPOutGlue]>; 137def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>, 138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 139def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>, 140 [SDNPHasChain, SDNPSideEffect, 141 SDNPInGlue, SDNPOutGlue]>; 142def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>, 143 [SDNPHasChain, SDNPSideEffect, 144 SDNPInGlue, SDNPOutGlue]>; 145def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 147def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone, 148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 149 SDNPVariadic]>; 150 151def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone, 152 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 153 SDNPVariadic]>; 154 155def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 156 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 157 158def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 159 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 160 161def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 162def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>; 163 164def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 165 [SDNPHasChain, SDNPOptInGlue]>; 166 167def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 168 [SDNPHasChain, SDNPMayLoad]>; 169def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 170 [SDNPHasChain, SDNPMayStore]>; 171 172// Instructions to set/unset CR bit 6 for SVR4 vararg calls 173def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 174 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 175def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 176 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 177 178// Instructions to support atomic operations 179def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx, 180 [SDNPHasChain, SDNPMayLoad]>; 181def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx, 182 [SDNPHasChain, SDNPMayStore]>; 183 184// Instructions to support medium and large code model 185def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>; 186def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>; 187def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>; 188 189 190// Instructions to support dynamic alloca. 191def SDTDynOp : SDTypeProfile<1, 2, []>; 192def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 193 194//===----------------------------------------------------------------------===// 195// PowerPC specific transformation functions and pattern fragments. 196// 197 198def SHL32 : SDNodeXForm<imm, [{ 199 // Transformation function: 31 - imm 200 return getI32Imm(31 - N->getZExtValue()); 201}]>; 202 203def SRL32 : SDNodeXForm<imm, [{ 204 // Transformation function: 32 - imm 205 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0); 206}]>; 207 208def LO16 : SDNodeXForm<imm, [{ 209 // Transformation function: get the low 16 bits. 210 return getI32Imm((unsigned short)N->getZExtValue()); 211}]>; 212 213def HI16 : SDNodeXForm<imm, [{ 214 // Transformation function: shift the immediate value down into the low bits. 215 return getI32Imm((unsigned)N->getZExtValue() >> 16); 216}]>; 217 218def HA16 : SDNodeXForm<imm, [{ 219 // Transformation function: shift the immediate value down into the low bits. 220 signed int Val = N->getZExtValue(); 221 return getI32Imm((Val - (signed short)Val) >> 16); 222}]>; 223def MB : SDNodeXForm<imm, [{ 224 // Transformation function: get the start bit of a mask 225 unsigned mb = 0, me; 226 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 227 return getI32Imm(mb); 228}]>; 229 230def ME : SDNodeXForm<imm, [{ 231 // Transformation function: get the end bit of a mask 232 unsigned mb, me = 0; 233 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 234 return getI32Imm(me); 235}]>; 236def maskimm32 : PatLeaf<(imm), [{ 237 // maskImm predicate - True if immediate is a run of ones. 238 unsigned mb, me; 239 if (N->getValueType(0) == MVT::i32) 240 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 241 else 242 return false; 243}]>; 244 245def immSExt16 : PatLeaf<(imm), [{ 246 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended 247 // field. Used by instructions like 'addi'. 248 if (N->getValueType(0) == MVT::i32) 249 return (int32_t)N->getZExtValue() == (short)N->getZExtValue(); 250 else 251 return (int64_t)N->getZExtValue() == (short)N->getZExtValue(); 252}]>; 253def immZExt16 : PatLeaf<(imm), [{ 254 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 255 // field. Used by instructions like 'ori'. 256 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 257}], LO16>; 258 259// imm16Shifted* - These match immediates where the low 16-bits are zero. There 260// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 261// identical in 32-bit mode, but in 64-bit mode, they return true if the 262// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 263// clear). 264def imm16ShiftedZExt : PatLeaf<(imm), [{ 265 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 266 // immediate are set. Used by instructions like 'xoris'. 267 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 268}], HI16>; 269 270def imm16ShiftedSExt : PatLeaf<(imm), [{ 271 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 272 // immediate are set. Used by instructions like 'addis'. Identical to 273 // imm16ShiftedZExt in 32-bit mode. 274 if (N->getZExtValue() & 0xFFFF) return false; 275 if (N->getValueType(0) == MVT::i32) 276 return true; 277 // For 64-bit, make sure it is sext right. 278 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 279}], HI16>; 280 281// Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require 282// restricted memrix (offset/4) constants are alignment sensitive. If these 283// offsets are hidden behind TOC entries than the values of the lower-order 284// bits cannot be checked directly. As a result, we need to also incorporate 285// an alignment check into the relevant patterns. 286 287def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 288 return cast<LoadSDNode>(N)->getAlignment() >= 4; 289}]>; 290def aligned4store : PatFrag<(ops node:$val, node:$ptr), 291 (store node:$val, node:$ptr), [{ 292 return cast<StoreSDNode>(N)->getAlignment() >= 4; 293}]>; 294def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 295 return cast<LoadSDNode>(N)->getAlignment() >= 4; 296}]>; 297def aligned4pre_store : PatFrag< 298 (ops node:$val, node:$base, node:$offset), 299 (pre_store node:$val, node:$base, node:$offset), [{ 300 return cast<StoreSDNode>(N)->getAlignment() >= 4; 301}]>; 302 303def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 304 return cast<LoadSDNode>(N)->getAlignment() < 4; 305}]>; 306def unaligned4store : PatFrag<(ops node:$val, node:$ptr), 307 (store node:$val, node:$ptr), [{ 308 return cast<StoreSDNode>(N)->getAlignment() < 4; 309}]>; 310def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 311 return cast<LoadSDNode>(N)->getAlignment() < 4; 312}]>; 313 314//===----------------------------------------------------------------------===// 315// PowerPC Flag Definitions. 316 317class isPPC64 { bit PPC64 = 1; } 318class isDOT { 319 list<Register> Defs = [CR0]; 320 bit RC = 1; 321} 322 323class RegConstraint<string C> { 324 string Constraints = C; 325} 326class NoEncode<string E> { 327 string DisableEncoding = E; 328} 329 330 331//===----------------------------------------------------------------------===// 332// PowerPC Operand Definitions. 333 334def s5imm : Operand<i32> { 335 let PrintMethod = "printS5ImmOperand"; 336} 337def u5imm : Operand<i32> { 338 let PrintMethod = "printU5ImmOperand"; 339} 340def u6imm : Operand<i32> { 341 let PrintMethod = "printU6ImmOperand"; 342} 343def s16imm : Operand<i32> { 344 let PrintMethod = "printS16ImmOperand"; 345} 346def u16imm : Operand<i32> { 347 let PrintMethod = "printU16ImmOperand"; 348} 349def directbrtarget : Operand<OtherVT> { 350 let PrintMethod = "printBranchOperand"; 351 let EncoderMethod = "getDirectBrEncoding"; 352} 353def condbrtarget : Operand<OtherVT> { 354 let PrintMethod = "printBranchOperand"; 355 let EncoderMethod = "getCondBrEncoding"; 356} 357def calltarget : Operand<iPTR> { 358 let EncoderMethod = "getDirectBrEncoding"; 359} 360def aaddr : Operand<iPTR> { 361 let PrintMethod = "printAbsAddrOperand"; 362} 363def symbolHi: Operand<i32> { 364 let PrintMethod = "printSymbolHi"; 365 let EncoderMethod = "getHA16Encoding"; 366} 367def symbolLo: Operand<i32> { 368 let PrintMethod = "printSymbolLo"; 369 let EncoderMethod = "getLO16Encoding"; 370} 371def crbitm: Operand<i8> { 372 let PrintMethod = "printcrbitm"; 373 let EncoderMethod = "get_crbitm_encoding"; 374} 375// Address operands 376// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode). 377def ptr_rc_nor0 : PointerLikeRegClass<1>; 378 379def memri : Operand<iPTR> { 380 let PrintMethod = "printMemRegImm"; 381 let MIOperandInfo = (ops symbolLo:$imm, ptr_rc_nor0:$reg); 382 let EncoderMethod = "getMemRIEncoding"; 383} 384def memrr : Operand<iPTR> { 385 let PrintMethod = "printMemRegReg"; 386 let MIOperandInfo = (ops ptr_rc_nor0:$offreg, ptr_rc:$ptrreg); 387} 388def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits. 389 let PrintMethod = "printMemRegImmShifted"; 390 let MIOperandInfo = (ops symbolLo:$imm, ptr_rc_nor0:$reg); 391 let EncoderMethod = "getMemRIXEncoding"; 392} 393 394// PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg 395// that doesn't matter. 396def pred : PredicateOperand<OtherVT, (ops imm, CRRC), 397 (ops (i32 20), (i32 zero_reg))> { 398 let PrintMethod = "printPredicateOperand"; 399} 400 401// Define PowerPC specific addressing mode. 402def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; 403def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; 404def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 405def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std" 406 407/// This is just the offset part of iaddr, used for preinc. 408def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 409def xaddroff : ComplexPattern<iPTR, 1, "SelectAddrIdxOffs", [], []>; 410 411//===----------------------------------------------------------------------===// 412// PowerPC Instruction Predicate Definitions. 413def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">; 414def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">; 415def IsBookE : Predicate<"PPCSubTarget.isBookE()">; 416 417//===----------------------------------------------------------------------===// 418// PowerPC Instruction Definitions. 419 420// Pseudo-instructions: 421 422let hasCtrlDep = 1 in { 423let Defs = [R1], Uses = [R1] in { 424def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt", 425 [(callseq_start timm:$amt)]>; 426def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2", 427 [(callseq_end timm:$amt1, timm:$amt2)]>; 428} 429 430def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS), 431 "UPDATE_VRSAVE $rD, $rS", []>; 432} 433 434let Defs = [R1], Uses = [R1] in 435def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "#DYNALLOC", 436 [(set GPRC:$result, 437 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>; 438 439// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 440// instruction selection into a branch sequence. 441let usesCustomInserter = 1, // Expanded after instruction selection. 442 PPC970_Single = 1 in { 443 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F, 444 i32imm:$BROPC), "#SELECT_CC_I4", 445 []>; 446 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F, 447 i32imm:$BROPC), "#SELECT_CC_I8", 448 []>; 449 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F, 450 i32imm:$BROPC), "#SELECT_CC_F4", 451 []>; 452 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F, 453 i32imm:$BROPC), "#SELECT_CC_F8", 454 []>; 455 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F, 456 i32imm:$BROPC), "#SELECT_CC_VRRC", 457 []>; 458} 459 460// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 461// scavenge a register for it. 462let mayStore = 1 in 463def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F), 464 "#SPILL_CR", []>; 465 466// RESTORE_CR - Indicate that we're restoring the CR register (previously 467// spilled), so we'll need to scavenge a register for it. 468let mayLoad = 1 in 469def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F), 470 "#RESTORE_CR", []>; 471 472let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 473 let isCodeGenOnly = 1, isReturn = 1, Uses = [LR, RM] in 474 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p), 475 "b${p:cc}lr ${p:reg}", BrB, 476 [(retflag)]>; 477 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in 478 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>; 479} 480 481let Defs = [LR] in 482 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>, 483 PPC970_Unit_BRU; 484 485let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 486 let isBarrier = 1 in { 487 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), 488 "b $dst", BrB, 489 [(br bb:$dst)]>; 490 } 491 492 // BCC represents an arbitrary conditional branch on a predicate. 493 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 494 // a two-value operand where a dag node expects two operands. :( 495 let isCodeGenOnly = 1 in 496 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), 497 "b${cond:cc} ${cond:reg}, $dst" 498 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>; 499 500 let Defs = [CTR], Uses = [CTR] in { 501 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 502 "bdz $dst">; 503 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 504 "bdnz $dst">; 505 } 506} 507 508// Darwin ABI Calls. 509let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 510 // Convenient aliases for call instructions 511 let Uses = [RM] in { 512 def BL_Darwin : IForm<18, 0, 1, 513 (outs), (ins calltarget:$func), 514 "bl $func", BrB, []>; // See Pat patterns below. 515 def BLA_Darwin : IForm<18, 1, 1, 516 (outs), (ins aaddr:$func), 517 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>; 518 } 519 let Uses = [CTR, RM] in { 520 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 521 (outs), (ins), 522 "bctrl", BrB, 523 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>; 524 } 525} 526 527// SVR4 ABI Calls. 528let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 529 // Convenient aliases for call instructions 530 let Uses = [RM] in { 531 def BL_SVR4 : IForm<18, 0, 1, 532 (outs), (ins calltarget:$func), 533 "bl $func", BrB, []>; // See Pat patterns below. 534 def BLA_SVR4 : IForm<18, 1, 1, 535 (outs), (ins aaddr:$func), 536 "bla $func", BrB, 537 [(PPCcall_SVR4 (i32 imm:$func))]>; 538 } 539 let Uses = [CTR, RM] in { 540 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1, 541 (outs), (ins), 542 "bctrl", BrB, 543 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>; 544 } 545} 546 547 548let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 549def TCRETURNdi :Pseudo< (outs), 550 (ins calltarget:$dst, i32imm:$offset), 551 "#TC_RETURNd $dst $offset", 552 []>; 553 554 555let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 556def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset), 557 "#TC_RETURNa $func $offset", 558 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 559 560let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 561def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 562 "#TC_RETURNr $dst $offset", 563 []>; 564 565 566let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 567 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 568def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 569 Requires<[In32BitMode]>; 570 571 572 573let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 574 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 575def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 576 "b $dst", BrB, 577 []>; 578 579 580let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 581 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 582def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 583 "ba $dst", BrB, 584 []>; 585 586 587// DCB* instructions. 588def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), 589 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 590 PPC970_DGroup_Single; 591def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), 592 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, 593 PPC970_DGroup_Single; 594def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), 595 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 596 PPC970_DGroup_Single; 597def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), 598 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 599 PPC970_DGroup_Single; 600def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), 601 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>, 602 PPC970_DGroup_Single; 603def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), 604 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>, 605 PPC970_DGroup_Single; 606def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), 607 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 608 PPC970_DGroup_Single; 609def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), 610 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 611 PPC970_DGroup_Single; 612 613def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), 614 (DCBT xoaddr:$dst)>; 615 616// Atomic operations 617let usesCustomInserter = 1 in { 618 let Defs = [CR0] in { 619 def ATOMIC_LOAD_ADD_I8 : Pseudo< 620 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I8", 621 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>; 622 def ATOMIC_LOAD_SUB_I8 : Pseudo< 623 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I8", 624 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>; 625 def ATOMIC_LOAD_AND_I8 : Pseudo< 626 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I8", 627 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>; 628 def ATOMIC_LOAD_OR_I8 : Pseudo< 629 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I8", 630 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>; 631 def ATOMIC_LOAD_XOR_I8 : Pseudo< 632 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "ATOMIC_LOAD_XOR_I8", 633 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>; 634 def ATOMIC_LOAD_NAND_I8 : Pseudo< 635 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I8", 636 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>; 637 def ATOMIC_LOAD_ADD_I16 : Pseudo< 638 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I16", 639 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>; 640 def ATOMIC_LOAD_SUB_I16 : Pseudo< 641 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I16", 642 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>; 643 def ATOMIC_LOAD_AND_I16 : Pseudo< 644 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I16", 645 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>; 646 def ATOMIC_LOAD_OR_I16 : Pseudo< 647 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I16", 648 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>; 649 def ATOMIC_LOAD_XOR_I16 : Pseudo< 650 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I16", 651 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>; 652 def ATOMIC_LOAD_NAND_I16 : Pseudo< 653 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I16", 654 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>; 655 def ATOMIC_LOAD_ADD_I32 : Pseudo< 656 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I32", 657 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>; 658 def ATOMIC_LOAD_SUB_I32 : Pseudo< 659 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I32", 660 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>; 661 def ATOMIC_LOAD_AND_I32 : Pseudo< 662 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I32", 663 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>; 664 def ATOMIC_LOAD_OR_I32 : Pseudo< 665 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I32", 666 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>; 667 def ATOMIC_LOAD_XOR_I32 : Pseudo< 668 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I32", 669 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>; 670 def ATOMIC_LOAD_NAND_I32 : Pseudo< 671 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I32", 672 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>; 673 674 def ATOMIC_CMP_SWAP_I8 : Pseudo< 675 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I8", 676 [(set GPRC:$dst, 677 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 678 def ATOMIC_CMP_SWAP_I16 : Pseudo< 679 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 680 [(set GPRC:$dst, 681 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 682 def ATOMIC_CMP_SWAP_I32 : Pseudo< 683 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 684 [(set GPRC:$dst, 685 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>; 686 687 def ATOMIC_SWAP_I8 : Pseudo< 688 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_i8", 689 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>; 690 def ATOMIC_SWAP_I16 : Pseudo< 691 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I16", 692 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>; 693 def ATOMIC_SWAP_I32 : Pseudo< 694 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I32", 695 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>; 696 } 697} 698 699// Instructions to support atomic operations 700def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src), 701 "lwarx $rD, $src", LdStLWARX, 702 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>; 703 704let Defs = [CR0] in 705def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst), 706 "stwcx. $rS, $dst", LdStSTWCX, 707 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>, 708 isDOT; 709 710let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 711def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>; 712 713//===----------------------------------------------------------------------===// 714// PPC32 Load Instructions. 715// 716 717// Unindexed (r+i) Loads. 718let canFoldAsLoad = 1, PPC970_Unit = 2 in { 719def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src), 720 "lbz $rD, $src", LdStLoad, 721 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>; 722def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src), 723 "lha $rD, $src", LdStLHA, 724 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>, 725 PPC970_DGroup_Cracked; 726def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src), 727 "lhz $rD, $src", LdStLoad, 728 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>; 729def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src), 730 "lwz $rD, $src", LdStLoad, 731 [(set GPRC:$rD, (load iaddr:$src))]>; 732 733def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src), 734 "lfs $rD, $src", LdStLFD, 735 [(set F4RC:$rD, (load iaddr:$src))]>; 736def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src), 737 "lfd $rD, $src", LdStLFD, 738 [(set F8RC:$rD, (load iaddr:$src))]>; 739 740 741// Unindexed (r+i) Loads with Update (preinc). 742let mayLoad = 1 in { 743def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 744 "lbzu $rD, $addr", LdStLoadUpd, 745 []>, RegConstraint<"$addr.reg = $ea_result">, 746 NoEncode<"$ea_result">; 747 748def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 749 "lhau $rD, $addr", LdStLHAU, 750 []>, RegConstraint<"$addr.reg = $ea_result">, 751 NoEncode<"$ea_result">; 752 753def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 754 "lhzu $rD, $addr", LdStLoadUpd, 755 []>, RegConstraint<"$addr.reg = $ea_result">, 756 NoEncode<"$ea_result">; 757 758def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 759 "lwzu $rD, $addr", LdStLoadUpd, 760 []>, RegConstraint<"$addr.reg = $ea_result">, 761 NoEncode<"$ea_result">; 762 763def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 764 "lfsu $rD, $addr", LdStLFDU, 765 []>, RegConstraint<"$addr.reg = $ea_result">, 766 NoEncode<"$ea_result">; 767 768def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 769 "lfdu $rD, $addr", LdStLFDU, 770 []>, RegConstraint<"$addr.reg = $ea_result">, 771 NoEncode<"$ea_result">; 772 773 774// Indexed (r+r) Loads with Update (preinc). 775def LBZUX : XForm_1<31, 119, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), 776 (ins memrr:$addr), 777 "lbzux $rD, $addr", LdStLoadUpd, 778 []>, RegConstraint<"$addr.offreg = $ea_result">, 779 NoEncode<"$ea_result">; 780 781def LHAUX : XForm_1<31, 375, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), 782 (ins memrr:$addr), 783 "lhaux $rD, $addr", LdStLHAU, 784 []>, RegConstraint<"$addr.offreg = $ea_result">, 785 NoEncode<"$ea_result">; 786 787def LHZUX : XForm_1<31, 311, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), 788 (ins memrr:$addr), 789 "lhzux $rD, $addr", LdStLoadUpd, 790 []>, RegConstraint<"$addr.offreg = $ea_result">, 791 NoEncode<"$ea_result">; 792 793def LWZUX : XForm_1<31, 55, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), 794 (ins memrr:$addr), 795 "lwzux $rD, $addr", LdStLoadUpd, 796 []>, RegConstraint<"$addr.offreg = $ea_result">, 797 NoEncode<"$ea_result">; 798 799def LFSUX : XForm_1<31, 567, (outs F4RC:$rD, ptr_rc_nor0:$ea_result), 800 (ins memrr:$addr), 801 "lfsux $rD, $addr", LdStLFDU, 802 []>, RegConstraint<"$addr.offreg = $ea_result">, 803 NoEncode<"$ea_result">; 804 805def LFDUX : XForm_1<31, 631, (outs F8RC:$rD, ptr_rc_nor0:$ea_result), 806 (ins memrr:$addr), 807 "lfdux $rD, $addr", LdStLFDU, 808 []>, RegConstraint<"$addr.offreg = $ea_result">, 809 NoEncode<"$ea_result">; 810} 811} 812 813// Indexed (r+r) Loads. 814// 815let canFoldAsLoad = 1, PPC970_Unit = 2 in { 816def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src), 817 "lbzx $rD, $src", LdStLoad, 818 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>; 819def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src), 820 "lhax $rD, $src", LdStLHA, 821 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>, 822 PPC970_DGroup_Cracked; 823def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src), 824 "lhzx $rD, $src", LdStLoad, 825 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>; 826def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src), 827 "lwzx $rD, $src", LdStLoad, 828 [(set GPRC:$rD, (load xaddr:$src))]>; 829 830 831def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src), 832 "lhbrx $rD, $src", LdStLoad, 833 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>; 834def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src), 835 "lwbrx $rD, $src", LdStLoad, 836 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>; 837 838def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src), 839 "lfsx $frD, $src", LdStLFD, 840 [(set F4RC:$frD, (load xaddr:$src))]>; 841def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src), 842 "lfdx $frD, $src", LdStLFD, 843 [(set F8RC:$frD, (load xaddr:$src))]>; 844} 845 846//===----------------------------------------------------------------------===// 847// PPC32 Store Instructions. 848// 849 850// Unindexed (r+i) Stores. 851let PPC970_Unit = 2 in { 852def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src), 853 "stb $rS, $src", LdStStore, 854 [(truncstorei8 GPRC:$rS, iaddr:$src)]>; 855def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src), 856 "sth $rS, $src", LdStStore, 857 [(truncstorei16 GPRC:$rS, iaddr:$src)]>; 858def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src), 859 "stw $rS, $src", LdStStore, 860 [(store GPRC:$rS, iaddr:$src)]>; 861def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst), 862 "stfs $rS, $dst", LdStSTFD, 863 [(store F4RC:$rS, iaddr:$dst)]>; 864def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst), 865 "stfd $rS, $dst", LdStSTFD, 866 [(store F8RC:$rS, iaddr:$dst)]>; 867} 868 869// Unindexed (r+i) Stores with Update (preinc). 870let PPC970_Unit = 2, mayStore = 1 in { 871def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst), 872 "stbu $rS, $dst", LdStStoreUpd, []>, 873 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 874def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst), 875 "sthu $rS, $dst", LdStStoreUpd, []>, 876 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 877def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst), 878 "stwu $rS, $dst", LdStStoreUpd, []>, 879 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 880def STFSU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memri:$dst), 881 "stfsu $rS, $dst", LdStSTFDU, []>, 882 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 883def STFDU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memri:$dst), 884 "stfdu $rS, $dst", LdStSTFDU, []>, 885 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 886} 887 888// Patterns to match the pre-inc stores. We can't put the patterns on 889// the instruction definitions directly as ISel wants the address base 890// and offset to be separate operands, not a single complex operand. 891def : Pat<(pre_truncsti8 GPRC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff), 892 (STBU GPRC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>; 893def : Pat<(pre_truncsti16 GPRC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff), 894 (STHU GPRC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>; 895def : Pat<(pre_store GPRC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff), 896 (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>; 897def : Pat<(pre_store F4RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff), 898 (STFSU F4RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>; 899def : Pat<(pre_store F8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff), 900 (STFDU F8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>; 901 902// Indexed (r+r) Stores. 903let PPC970_Unit = 2 in { 904def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst), 905 "stbx $rS, $dst", LdStStore, 906 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>, 907 PPC970_DGroup_Cracked; 908def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst), 909 "sthx $rS, $dst", LdStStore, 910 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>, 911 PPC970_DGroup_Cracked; 912def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst), 913 "stwx $rS, $dst", LdStStore, 914 [(store GPRC:$rS, xaddr:$dst)]>, 915 PPC970_DGroup_Cracked; 916 917def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst), 918 "sthbrx $rS, $dst", LdStStore, 919 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>, 920 PPC970_DGroup_Cracked; 921def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst), 922 "stwbrx $rS, $dst", LdStStore, 923 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>, 924 PPC970_DGroup_Cracked; 925 926def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst), 927 "stfiwx $frS, $dst", LdStSTFD, 928 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>; 929 930def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst), 931 "stfsx $frS, $dst", LdStSTFD, 932 [(store F4RC:$frS, xaddr:$dst)]>; 933def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst), 934 "stfdx $frS, $dst", LdStSTFD, 935 [(store F8RC:$frS, xaddr:$dst)]>; 936} 937 938// Indexed (r+r) Stores with Update (preinc). 939let PPC970_Unit = 2, mayStore = 1 in { 940def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst), 941 "stbux $rS, $dst", LdStStoreUpd, []>, 942 RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">, 943 PPC970_DGroup_Cracked; 944def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst), 945 "sthux $rS, $dst", LdStStoreUpd, []>, 946 RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">, 947 PPC970_DGroup_Cracked; 948def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst), 949 "stwux $rS, $dst", LdStStoreUpd, []>, 950 RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">, 951 PPC970_DGroup_Cracked; 952def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memrr:$dst), 953 "stfsux $rS, $dst", LdStSTFDU, []>, 954 RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">, 955 PPC970_DGroup_Cracked; 956def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memrr:$dst), 957 "stfdux $rS, $dst", LdStSTFDU, []>, 958 RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">, 959 PPC970_DGroup_Cracked; 960} 961 962// Patterns to match the pre-inc stores. We can't put the patterns on 963// the instruction definitions directly as ISel wants the address base 964// and offset to be separate operands, not a single complex operand. 965def : Pat<(pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff), 966 (STBUX GPRC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>; 967def : Pat<(pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff), 968 (STHUX GPRC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>; 969def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff), 970 (STWUX GPRC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>; 971def : Pat<(pre_store F4RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff), 972 (STFSUX F4RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>; 973def : Pat<(pre_store F8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff), 974 (STFDUX F8RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>; 975 976def SYNC : XForm_24_sync<31, 598, (outs), (ins), 977 "sync", LdStSync, 978 [(int_ppc_sync)]>; 979 980//===----------------------------------------------------------------------===// 981// PPC32 Arithmetic Instructions. 982// 983 984let PPC970_Unit = 1 in { // FXU Operations. 985def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, s16imm:$imm), 986 "addi $rD, $rA, $imm", IntSimple, 987 [(set GPRC:$rD, (add GPRC_NOR0:$rA, immSExt16:$imm))]>; 988def ADDIL : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolLo:$imm), 989 "addi $rD, $rA, $imm", IntSimple, 990 [(set GPRC:$rD, (add GPRC_NOR0:$rA, immSExt16:$imm))]>; 991let Defs = [CARRY] in { 992def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 993 "addic $rD, $rA, $imm", IntGeneral, 994 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>, 995 PPC970_DGroup_Cracked; 996def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 997 "addic. $rD, $rA, $imm", IntGeneral, 998 []>; 999} 1000def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolHi:$imm), 1001 "addis $rD, $rA, $imm", IntSimple, 1002 [(set GPRC:$rD, (add GPRC_NOR0:$rA, 1003 imm16ShiftedSExt:$imm))]>; 1004def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolLo:$sym), 1005 "la $rD, $sym($rA)", IntGeneral, 1006 [(set GPRC:$rD, (add GPRC_NOR0:$rA, 1007 (PPClo tglobaladdr:$sym, 0)))]>; 1008def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 1009 "mulli $rD, $rA, $imm", IntMulLI, 1010 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; 1011let Defs = [CARRY] in { 1012def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), 1013 "subfic $rD, $rA, $imm", IntGeneral, 1014 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>; 1015} 1016 1017let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 1018 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm), 1019 "li $rD, $imm", IntSimple, 1020 [(set GPRC:$rD, immSExt16:$imm)]>; 1021 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm), 1022 "lis $rD, $imm", IntSimple, 1023 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>; 1024} 1025} 1026 1027let PPC970_Unit = 1 in { // FXU Operations. 1028def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1029 "andi. $dst, $src1, $src2", IntGeneral, 1030 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>, 1031 isDOT; 1032def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1033 "andis. $dst, $src1, $src2", IntGeneral, 1034 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>, 1035 isDOT; 1036def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1037 "ori $dst, $src1, $src2", IntSimple, 1038 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>; 1039def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1040 "oris $dst, $src1, $src2", IntSimple, 1041 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>; 1042def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1043 "xori $dst, $src1, $src2", IntSimple, 1044 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>; 1045def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1046 "xoris $dst, $src1, $src2", IntSimple, 1047 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>; 1048def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple, 1049 []>; 1050def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm), 1051 "cmpwi $crD, $rA, $imm", IntCompare>; 1052def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2), 1053 "cmplwi $dst, $src1, $src2", IntCompare>; 1054} 1055 1056 1057let PPC970_Unit = 1 in { // FXU Operations. 1058def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1059 "nand $rA, $rS, $rB", IntSimple, 1060 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>; 1061def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1062 "and $rA, $rS, $rB", IntSimple, 1063 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; 1064def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1065 "andc $rA, $rS, $rB", IntSimple, 1066 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; 1067def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1068 "or $rA, $rS, $rB", IntSimple, 1069 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; 1070def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1071 "nor $rA, $rS, $rB", IntSimple, 1072 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>; 1073def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1074 "orc $rA, $rS, $rB", IntSimple, 1075 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>; 1076def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1077 "eqv $rA, $rS, $rB", IntSimple, 1078 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>; 1079def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1080 "xor $rA, $rS, $rB", IntSimple, 1081 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>; 1082def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1083 "slw $rA, $rS, $rB", IntGeneral, 1084 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>; 1085def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1086 "srw $rA, $rS, $rB", IntGeneral, 1087 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>; 1088let Defs = [CARRY] in { 1089def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB), 1090 "sraw $rA, $rS, $rB", IntShift, 1091 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>; 1092} 1093} 1094 1095let PPC970_Unit = 1 in { // FXU Operations. 1096let Defs = [CARRY] in { 1097def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH), 1098 "srawi $rA, $rS, $SH", IntShift, 1099 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>; 1100} 1101def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS), 1102 "cntlzw $rA, $rS", IntGeneral, 1103 [(set GPRC:$rA, (ctlz GPRC:$rS))]>; 1104def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS), 1105 "extsb $rA, $rS", IntSimple, 1106 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>; 1107def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS), 1108 "extsh $rA, $rS", IntSimple, 1109 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>; 1110 1111def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 1112 "cmpw $crD, $rA, $rB", IntCompare>; 1113def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB), 1114 "cmplw $crD, $rA, $rB", IntCompare>; 1115} 1116let PPC970_Unit = 3 in { // FPU Operations. 1117//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), 1118// "fcmpo $crD, $fA, $fB", FPCompare>; 1119def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB), 1120 "fcmpu $crD, $fA, $fB", FPCompare>; 1121def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB), 1122 "fcmpu $crD, $fA, $fB", FPCompare>; 1123 1124let Uses = [RM] in { 1125 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB), 1126 "fctiwz $frD, $frB", FPGeneral, 1127 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>; 1128 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB), 1129 "frsp $frD, $frB", FPGeneral, 1130 [(set F4RC:$frD, (fround F8RC:$frB))]>; 1131 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB), 1132 "fsqrt $frD, $frB", FPSqrt, 1133 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>; 1134 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB), 1135 "fsqrts $frD, $frB", FPSqrt, 1136 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>; 1137 } 1138} 1139 1140/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 1141/// often coalesced away and we don't want the dispatch group builder to think 1142/// that they will fill slots (which could cause the load of a LSU reject to 1143/// sneak into a d-group with a store). 1144def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB), 1145 "fmr $frD, $frB", FPGeneral, 1146 []>, // (set F4RC:$frD, F4RC:$frB) 1147 PPC970_Unit_Pseudo; 1148 1149let PPC970_Unit = 3 in { // FPU Operations. 1150// These are artificially split into two different forms, for 4/8 byte FP. 1151def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB), 1152 "fabs $frD, $frB", FPGeneral, 1153 [(set F4RC:$frD, (fabs F4RC:$frB))]>; 1154def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB), 1155 "fabs $frD, $frB", FPGeneral, 1156 [(set F8RC:$frD, (fabs F8RC:$frB))]>; 1157def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB), 1158 "fnabs $frD, $frB", FPGeneral, 1159 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>; 1160def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB), 1161 "fnabs $frD, $frB", FPGeneral, 1162 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>; 1163def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB), 1164 "fneg $frD, $frB", FPGeneral, 1165 [(set F4RC:$frD, (fneg F4RC:$frB))]>; 1166def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB), 1167 "fneg $frD, $frB", FPGeneral, 1168 [(set F8RC:$frD, (fneg F8RC:$frB))]>; 1169} 1170 1171 1172// XL-Form instructions. condition register logical ops. 1173// 1174def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA), 1175 "mcrf $BF, $BFA", BrMCR>, 1176 PPC970_DGroup_First, PPC970_Unit_CRU; 1177 1178def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD), 1179 (ins CRBITRC:$CRA, CRBITRC:$CRB), 1180 "creqv $CRD, $CRA, $CRB", BrCR, 1181 []>; 1182 1183def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD), 1184 (ins CRBITRC:$CRA, CRBITRC:$CRB), 1185 "cror $CRD, $CRA, $CRB", BrCR, 1186 []>; 1187 1188def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins), 1189 "creqv $dst, $dst, $dst", BrCR, 1190 []>; 1191 1192def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins), 1193 "crxor $dst, $dst, $dst", BrCR, 1194 []>; 1195 1196let Defs = [CR1EQ], CRD = 6 in { 1197def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 1198 "creqv 6, 6, 6", BrCR, 1199 [(PPCcr6set)]>; 1200 1201def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 1202 "crxor 6, 6, 6", BrCR, 1203 [(PPCcr6unset)]>; 1204} 1205 1206// XFX-Form instructions. Instructions that deal with SPRs. 1207// 1208let Uses = [CTR] in { 1209def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins), 1210 "mfctr $rT", SprMFSPR>, 1211 PPC970_DGroup_First, PPC970_Unit_FXU; 1212} 1213let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in { 1214def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS), 1215 "mtctr $rS", SprMTSPR>, 1216 PPC970_DGroup_First, PPC970_Unit_FXU; 1217} 1218 1219let Defs = [LR] in { 1220def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS), 1221 "mtlr $rS", SprMTSPR>, 1222 PPC970_DGroup_First, PPC970_Unit_FXU; 1223} 1224let Uses = [LR] in { 1225def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins), 1226 "mflr $rT", SprMFSPR>, 1227 PPC970_DGroup_First, PPC970_Unit_FXU; 1228} 1229 1230// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like 1231// a GPR on the PPC970. As such, copies in and out have the same performance 1232// characteristics as an OR instruction. 1233def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS), 1234 "mtspr 256, $rS", IntGeneral>, 1235 PPC970_DGroup_Single, PPC970_Unit_FXU; 1236def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins), 1237 "mfspr $rT, 256", IntGeneral>, 1238 PPC970_DGroup_First, PPC970_Unit_FXU; 1239 1240def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS), 1241 "mtcrf $FXM, $rS", BrMCRX>, 1242 PPC970_MicroCode, PPC970_Unit_CRU; 1243 1244// This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters; 1245// declaring that here gives the local register allocator problems with this: 1246// vreg = MCRF CR0 1247// MFCR <kill of whatever preg got assigned to vreg> 1248// while not declaring it breaks DeadMachineInstructionElimination. 1249// As it turns out, in all cases where we currently use this, 1250// we're only interested in one subregister of it. Represent this in the 1251// instruction to keep the register allocator from becoming confused. 1252// 1253// FIXME: Make this a real Pseudo instruction when the JIT switches to MC. 1254def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), 1255 "#MFCRpseud", SprMFCR>, 1256 PPC970_MicroCode, PPC970_Unit_CRU; 1257 1258def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), 1259 "mfcr $rT", SprMFCR>, 1260 PPC970_MicroCode, PPC970_Unit_CRU; 1261 1262def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), 1263 "mfocrf $rT, $FXM", SprMFCR>, 1264 PPC970_DGroup_First, PPC970_Unit_CRU; 1265 1266// Instructions to manipulate FPSCR. Only long double handling uses these. 1267// FPSCR is not modelled; we use the SDNode Flag to keep things in order. 1268 1269let Uses = [RM], Defs = [RM] in { 1270 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 1271 "mtfsb0 $FM", IntMTFSB0, 1272 [(PPCmtfsb0 (i32 imm:$FM))]>, 1273 PPC970_DGroup_Single, PPC970_Unit_FPU; 1274 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 1275 "mtfsb1 $FM", IntMTFSB0, 1276 [(PPCmtfsb1 (i32 imm:$FM))]>, 1277 PPC970_DGroup_Single, PPC970_Unit_FPU; 1278 // MTFSF does not actually produce an FP result. We pretend it copies 1279 // input reg B to the output. If we didn't do this it would look like the 1280 // instruction had no outputs (because we aren't modelling the FPSCR) and 1281 // it would be deleted. 1282 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA), 1283 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB), 1284 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0, 1285 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM), 1286 F8RC:$rT, F8RC:$FRB))]>, 1287 PPC970_DGroup_Single, PPC970_Unit_FPU; 1288} 1289let Uses = [RM] in { 1290 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins), 1291 "mffs $rT", IntMFFS, 1292 [(set F8RC:$rT, (PPCmffs))]>, 1293 PPC970_DGroup_Single, PPC970_Unit_FPU; 1294 def FADDrtz: AForm_2<63, 21, 1295 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1296 "fadd $FRT, $FRA, $FRB", FPAddSub, 1297 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>, 1298 PPC970_DGroup_Single, PPC970_Unit_FPU; 1299} 1300 1301 1302let PPC970_Unit = 1 in { // FXU Operations. 1303 1304// XO-Form instructions. Arithmetic instructions that can set overflow bit 1305// 1306def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1307 "add $rT, $rA, $rB", IntSimple, 1308 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>; 1309let Defs = [CARRY] in { 1310def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1311 "addc $rT, $rA, $rB", IntGeneral, 1312 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>, 1313 PPC970_DGroup_Cracked; 1314} 1315def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1316 "divw $rT, $rA, $rB", IntDivW, 1317 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>, 1318 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1319def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1320 "divwu $rT, $rA, $rB", IntDivW, 1321 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>, 1322 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1323def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1324 "mulhw $rT, $rA, $rB", IntMulHW, 1325 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>; 1326def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1327 "mulhwu $rT, $rA, $rB", IntMulHWU, 1328 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>; 1329def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1330 "mullw $rT, $rA, $rB", IntMulHW, 1331 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>; 1332def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1333 "subf $rT, $rA, $rB", IntGeneral, 1334 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>; 1335let Defs = [CARRY] in { 1336def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1337 "subfc $rT, $rA, $rB", IntGeneral, 1338 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>, 1339 PPC970_DGroup_Cracked; 1340} 1341def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1342 "neg $rT, $rA", IntSimple, 1343 [(set GPRC:$rT, (ineg GPRC:$rA))]>; 1344let Uses = [CARRY], Defs = [CARRY] in { 1345def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1346 "adde $rT, $rA, $rB", IntGeneral, 1347 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>; 1348def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1349 "addme $rT, $rA", IntGeneral, 1350 [(set GPRC:$rT, (adde GPRC:$rA, -1))]>; 1351def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1352 "addze $rT, $rA", IntGeneral, 1353 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>; 1354def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB), 1355 "subfe $rT, $rA, $rB", IntGeneral, 1356 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>; 1357def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1358 "subfme $rT, $rA", IntGeneral, 1359 [(set GPRC:$rT, (sube -1, GPRC:$rA))]>; 1360def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA), 1361 "subfze $rT, $rA", IntGeneral, 1362 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>; 1363} 1364} 1365 1366// A-Form instructions. Most of the instructions executed in the FPU are of 1367// this type. 1368// 1369let PPC970_Unit = 3 in { // FPU Operations. 1370let Uses = [RM] in { 1371 def FMADD : AForm_1<63, 29, 1372 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1373 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1374 [(set F8RC:$FRT, 1375 (fma F8RC:$FRA, F8RC:$FRC, F8RC:$FRB))]>; 1376 def FMADDS : AForm_1<59, 29, 1377 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1378 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 1379 [(set F4RC:$FRT, 1380 (fma F4RC:$FRA, F4RC:$FRC, F4RC:$FRB))]>; 1381 def FMSUB : AForm_1<63, 28, 1382 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1383 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused, 1384 [(set F8RC:$FRT, 1385 (fma F8RC:$FRA, F8RC:$FRC, (fneg F8RC:$FRB)))]>; 1386 def FMSUBS : AForm_1<59, 28, 1387 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1388 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 1389 [(set F4RC:$FRT, 1390 (fma F4RC:$FRA, F4RC:$FRC, (fneg F4RC:$FRB)))]>; 1391 def FNMADD : AForm_1<63, 31, 1392 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1393 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused, 1394 [(set F8RC:$FRT, 1395 (fneg (fma F8RC:$FRA, F8RC:$FRC, F8RC:$FRB)))]>; 1396 def FNMADDS : AForm_1<59, 31, 1397 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1398 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral, 1399 [(set F4RC:$FRT, 1400 (fneg (fma F4RC:$FRA, F4RC:$FRC, F4RC:$FRB)))]>; 1401 def FNMSUB : AForm_1<63, 30, 1402 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1403 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused, 1404 [(set F8RC:$FRT, (fneg (fma F8RC:$FRA, F8RC:$FRC, 1405 (fneg F8RC:$FRB))))]>; 1406 def FNMSUBS : AForm_1<59, 30, 1407 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1408 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, 1409 [(set F4RC:$FRT, (fneg (fma F4RC:$FRA, F4RC:$FRC, 1410 (fneg F4RC:$FRB))))]>; 1411} 1412// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 1413// having 4 of these, force the comparison to always be an 8-byte double (code 1414// should use an FMRSD if the input comparison value really wants to be a float) 1415// and 4/8 byte forms for the result and operand type.. 1416def FSELD : AForm_1<63, 23, 1417 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), 1418 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1419 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>; 1420def FSELS : AForm_1<63, 23, 1421 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB), 1422 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral, 1423 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>; 1424let Uses = [RM] in { 1425 def FADD : AForm_2<63, 21, 1426 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1427 "fadd $FRT, $FRA, $FRB", FPAddSub, 1428 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>; 1429 def FADDS : AForm_2<59, 21, 1430 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1431 "fadds $FRT, $FRA, $FRB", FPGeneral, 1432 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>; 1433 def FDIV : AForm_2<63, 18, 1434 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1435 "fdiv $FRT, $FRA, $FRB", FPDivD, 1436 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>; 1437 def FDIVS : AForm_2<59, 18, 1438 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1439 "fdivs $FRT, $FRA, $FRB", FPDivS, 1440 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>; 1441 def FMUL : AForm_3<63, 25, 1442 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC), 1443 "fmul $FRT, $FRA, $FRC", FPFused, 1444 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRC))]>; 1445 def FMULS : AForm_3<59, 25, 1446 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC), 1447 "fmuls $FRT, $FRA, $FRC", FPGeneral, 1448 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRC))]>; 1449 def FSUB : AForm_2<63, 20, 1450 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), 1451 "fsub $FRT, $FRA, $FRB", FPAddSub, 1452 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>; 1453 def FSUBS : AForm_2<59, 20, 1454 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), 1455 "fsubs $FRT, $FRA, $FRB", FPGeneral, 1456 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>; 1457 } 1458} 1459 1460let PPC970_Unit = 1 in { // FXU Operations. 1461 def ISEL : AForm_4<31, 15, 1462 (outs GPRC:$rT), (ins GPRC_NOR0:$rA, GPRC:$rB, pred:$cond), 1463 "isel $rT, $rA, $rB, $cond", IntGeneral, 1464 []>; 1465} 1466 1467let PPC970_Unit = 1 in { // FXU Operations. 1468// M-Form instructions. rotate and mask instructions. 1469// 1470let isCommutable = 1 in { 1471// RLWIMI can be commuted if the rotate amount is zero. 1472def RLWIMI : MForm_2<20, 1473 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 1474 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate, 1475 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">, 1476 NoEncode<"$rSi">; 1477} 1478def RLWINM : MForm_2<21, 1479 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1480 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 1481 []>; 1482def RLWINMo : MForm_2<21, 1483 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 1484 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral, 1485 []>, isDOT, PPC970_DGroup_Cracked; 1486def RLWNM : MForm_2<23, 1487 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME), 1488 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral, 1489 []>; 1490} 1491 1492 1493//===----------------------------------------------------------------------===// 1494// PowerPC Instruction Patterns 1495// 1496 1497// Arbitrary immediate support. Implement in terms of LIS/ORI. 1498def : Pat<(i32 imm:$imm), 1499 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 1500 1501// Implement the 'not' operation with the NOR instruction. 1502def NOT : Pat<(not GPRC:$in), 1503 (NOR GPRC:$in, GPRC:$in)>; 1504 1505// ADD an arbitrary immediate. 1506def : Pat<(add GPRC:$in, imm:$imm), 1507 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 1508// OR an arbitrary immediate. 1509def : Pat<(or GPRC:$in, imm:$imm), 1510 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1511// XOR an arbitrary immediate. 1512def : Pat<(xor GPRC:$in, imm:$imm), 1513 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 1514// SUBFIC 1515def : Pat<(sub immSExt16:$imm, GPRC:$in), 1516 (SUBFIC GPRC:$in, imm:$imm)>; 1517 1518// SHL/SRL 1519def : Pat<(shl GPRC:$in, (i32 imm:$imm)), 1520 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>; 1521def : Pat<(srl GPRC:$in, (i32 imm:$imm)), 1522 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>; 1523 1524// ROTL 1525def : Pat<(rotl GPRC:$in, GPRC:$sh), 1526 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>; 1527def : Pat<(rotl GPRC:$in, (i32 imm:$imm)), 1528 (RLWINM GPRC:$in, imm:$imm, 0, 31)>; 1529 1530// RLWNM 1531def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm), 1532 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 1533 1534// Calls 1535def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)), 1536 (BL_Darwin tglobaladdr:$dst)>; 1537def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)), 1538 (BL_Darwin texternalsym:$dst)>; 1539def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)), 1540 (BL_SVR4 tglobaladdr:$dst)>; 1541def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)), 1542 (BL_SVR4 texternalsym:$dst)>; 1543 1544 1545def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 1546 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 1547 1548def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 1549 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 1550 1551def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 1552 (TCRETURNri CTRRC:$dst, imm:$imm)>; 1553 1554 1555 1556// Hi and Lo for Darwin Global Addresses. 1557def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 1558def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 1559def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 1560def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 1561def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 1562def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 1563def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 1564def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 1565def : Pat<(PPChi tglobaltlsaddr:$g, GPRC:$in), 1566 (ADDIS GPRC:$in, tglobaltlsaddr:$g)>; 1567def : Pat<(PPClo tglobaltlsaddr:$g, GPRC:$in), 1568 (ADDIL GPRC:$in, tglobaltlsaddr:$g)>; 1569def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)), 1570 (ADDIS GPRC:$in, tglobaladdr:$g)>; 1571def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)), 1572 (ADDIS GPRC:$in, tconstpool:$g)>; 1573def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)), 1574 (ADDIS GPRC:$in, tjumptable:$g)>; 1575def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)), 1576 (ADDIS GPRC:$in, tblockaddress:$g)>; 1577 1578// Standard shifts. These are represented separately from the real shifts above 1579// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 1580// amounts. 1581def : Pat<(sra GPRC:$rS, GPRC:$rB), 1582 (SRAW GPRC:$rS, GPRC:$rB)>; 1583def : Pat<(srl GPRC:$rS, GPRC:$rB), 1584 (SRW GPRC:$rS, GPRC:$rB)>; 1585def : Pat<(shl GPRC:$rS, GPRC:$rB), 1586 (SLW GPRC:$rS, GPRC:$rB)>; 1587 1588def : Pat<(zextloadi1 iaddr:$src), 1589 (LBZ iaddr:$src)>; 1590def : Pat<(zextloadi1 xaddr:$src), 1591 (LBZX xaddr:$src)>; 1592def : Pat<(extloadi1 iaddr:$src), 1593 (LBZ iaddr:$src)>; 1594def : Pat<(extloadi1 xaddr:$src), 1595 (LBZX xaddr:$src)>; 1596def : Pat<(extloadi8 iaddr:$src), 1597 (LBZ iaddr:$src)>; 1598def : Pat<(extloadi8 xaddr:$src), 1599 (LBZX xaddr:$src)>; 1600def : Pat<(extloadi16 iaddr:$src), 1601 (LHZ iaddr:$src)>; 1602def : Pat<(extloadi16 xaddr:$src), 1603 (LHZX xaddr:$src)>; 1604def : Pat<(f64 (extloadf32 iaddr:$src)), 1605 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>; 1606def : Pat<(f64 (extloadf32 xaddr:$src)), 1607 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>; 1608 1609def : Pat<(f64 (fextend F4RC:$src)), 1610 (COPY_TO_REGCLASS F4RC:$src, F8RC)>; 1611 1612// Memory barriers 1613def : Pat<(membarrier (i32 imm /*ll*/), 1614 (i32 imm /*ls*/), 1615 (i32 imm /*sl*/), 1616 (i32 imm /*ss*/), 1617 (i32 imm /*device*/)), 1618 (SYNC)>; 1619 1620def : Pat<(atomic_fence (imm), (imm)), (SYNC)>; 1621 1622include "PPCInstrAltivec.td" 1623include "PPCInstr64Bit.td" 1624