1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 15 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 16 17 #include "PPC.h" 18 #include "PPCRegisterInfo.h" 19 #include "llvm/Target/TargetInstrInfo.h" 20 21 #define GET_INSTRINFO_HEADER 22 #include "PPCGenInstrInfo.inc" 23 24 namespace llvm { 25 26 /// PPCII - This namespace holds all of the PowerPC target-specific 27 /// per-instruction flags. These must match the corresponding definitions in 28 /// PPC.td and PPCInstrFormats.td. 29 namespace PPCII { 30 enum { 31 // PPC970 Instruction Flags. These flags describe the characteristics of the 32 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 33 // raw machine instructions. 34 35 /// PPC970_First - This instruction starts a new dispatch group, so it will 36 /// always be the first one in the group. 37 PPC970_First = 0x1, 38 39 /// PPC970_Single - This instruction starts a new dispatch group and 40 /// terminates it, so it will be the sole instruction in the group. 41 PPC970_Single = 0x2, 42 43 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 44 /// two dispatch pipes to be available to issue. 45 PPC970_Cracked = 0x4, 46 47 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 48 /// an instruction is issued to. 49 PPC970_Shift = 3, 50 PPC970_Mask = 0x07 << PPC970_Shift 51 }; 52 enum PPC970_Unit { 53 /// These are the various PPC970 execution unit pipelines. Each instruction 54 /// is one of these. 55 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 56 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 57 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 58 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 59 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 60 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 61 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 62 PPC970_BRU = 7 << PPC970_Shift // Branch Unit 63 }; 64 65 enum { 66 /// Shift count to bypass PPC970 flags 67 NewDef_Shift = 6, 68 69 /// The VSX instruction that uses VSX register (vs0-vs63), instead of VMX 70 /// register (v0-v31). 71 UseVSXReg = 0x1 << NewDef_Shift 72 }; 73 } // end namespace PPCII 74 75 class PPCSubtarget; 76 class PPCInstrInfo : public PPCGenInstrInfo { 77 PPCSubtarget &Subtarget; 78 const PPCRegisterInfo RI; 79 80 bool StoreRegToStackSlot(MachineFunction &MF, 81 unsigned SrcReg, bool isKill, int FrameIdx, 82 const TargetRegisterClass *RC, 83 SmallVectorImpl<MachineInstr*> &NewMIs, 84 bool &NonRI, bool &SpillsVRS) const; 85 bool LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, 86 unsigned DestReg, int FrameIdx, 87 const TargetRegisterClass *RC, 88 SmallVectorImpl<MachineInstr *> &NewMIs, 89 bool &NonRI, bool &SpillsVRS) const; 90 virtual void anchor(); 91 92 protected: 93 /// Commutes the operands in the given instruction. 94 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2. 95 /// 96 /// Do not call this method for a non-commutable instruction or for 97 /// non-commutable pair of operand indices OpIdx1 and OpIdx2. 98 /// Even though the instruction is commutable, the method may still 99 /// fail to commute the operands, null pointer is returned in such cases. 100 /// 101 /// For example, we can commute rlwimi instructions, but only if the 102 /// rotate amt is zero. We also have to munge the immediates a bit. 103 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 104 unsigned OpIdx1, 105 unsigned OpIdx2) const override; 106 107 public: 108 explicit PPCInstrInfo(PPCSubtarget &STI); 109 110 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 111 /// such, whenever a client has an instance of instruction info, it should 112 /// always be able to get register info as well (through this method). 113 /// 114 const PPCRegisterInfo &getRegisterInfo() const { return RI; } 115 116 ScheduleHazardRecognizer * 117 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 118 const ScheduleDAG *DAG) const override; 119 ScheduleHazardRecognizer * 120 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 121 const ScheduleDAG *DAG) const override; 122 123 unsigned getInstrLatency(const InstrItineraryData *ItinData, 124 const MachineInstr &MI, 125 unsigned *PredCost = nullptr) const override; 126 127 int getOperandLatency(const InstrItineraryData *ItinData, 128 const MachineInstr &DefMI, unsigned DefIdx, 129 const MachineInstr &UseMI, 130 unsigned UseIdx) const override; 131 int getOperandLatency(const InstrItineraryData *ItinData, 132 SDNode *DefNode, unsigned DefIdx, 133 SDNode *UseNode, unsigned UseIdx) const override { 134 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, 135 UseNode, UseIdx); 136 } 137 138 bool hasLowDefLatency(const TargetSchedModel &SchedModel, 139 const MachineInstr &DefMI, 140 unsigned DefIdx) const override { 141 // Machine LICM should hoist all instructions in low-register-pressure 142 // situations; none are sufficiently free to justify leaving in a loop 143 // body. 144 return false; 145 } 146 147 bool useMachineCombiner() const override { 148 return true; 149 } 150 151 /// Return true when there is potentially a faster code sequence 152 /// for an instruction chain ending in <Root>. All potential patterns are 153 /// output in the <Pattern> array. 154 bool getMachineCombinerPatterns( 155 MachineInstr &Root, 156 SmallVectorImpl<MachineCombinerPattern> &P) const override; 157 158 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override; 159 160 bool isCoalescableExtInstr(const MachineInstr &MI, 161 unsigned &SrcReg, unsigned &DstReg, 162 unsigned &SubIdx) const override; 163 unsigned isLoadFromStackSlot(const MachineInstr &MI, 164 int &FrameIndex) const override; 165 bool isReallyTriviallyReMaterializable(const MachineInstr &MI, 166 AliasAnalysis *AA) const override; 167 unsigned isStoreToStackSlot(const MachineInstr &MI, 168 int &FrameIndex) const override; 169 170 bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, 171 unsigned &SrcOpIdx2) const override; 172 173 void insertNoop(MachineBasicBlock &MBB, 174 MachineBasicBlock::iterator MI) const override; 175 176 177 // Branch analysis. 178 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 179 MachineBasicBlock *&FBB, 180 SmallVectorImpl<MachineOperand> &Cond, 181 bool AllowModify) const override; 182 unsigned removeBranch(MachineBasicBlock &MBB, 183 int *BytesRemoved = nullptr) const override; 184 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 185 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 186 const DebugLoc &DL, 187 int *BytesAdded = nullptr) const override; 188 189 // Select analysis. 190 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 191 unsigned, unsigned, int &, int &, int &) const override; 192 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 193 const DebugLoc &DL, unsigned DstReg, 194 ArrayRef<MachineOperand> Cond, unsigned TrueReg, 195 unsigned FalseReg) const override; 196 197 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 198 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, 199 bool KillSrc) const override; 200 201 void storeRegToStackSlot(MachineBasicBlock &MBB, 202 MachineBasicBlock::iterator MBBI, 203 unsigned SrcReg, bool isKill, int FrameIndex, 204 const TargetRegisterClass *RC, 205 const TargetRegisterInfo *TRI) const override; 206 207 void loadRegFromStackSlot(MachineBasicBlock &MBB, 208 MachineBasicBlock::iterator MBBI, 209 unsigned DestReg, int FrameIndex, 210 const TargetRegisterClass *RC, 211 const TargetRegisterInfo *TRI) const override; 212 213 bool 214 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 215 216 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, 217 MachineRegisterInfo *MRI) const override; 218 219 // If conversion by predication (only supported by some branch instructions). 220 // All of the profitability checks always return true; it is always 221 // profitable to use the predicated branches. 222 bool isProfitableToIfCvt(MachineBasicBlock &MBB, 223 unsigned NumCycles, unsigned ExtraPredCycles, 224 BranchProbability Probability) const override { 225 return true; 226 } 227 228 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 229 unsigned NumT, unsigned ExtraT, 230 MachineBasicBlock &FMBB, 231 unsigned NumF, unsigned ExtraF, 232 BranchProbability Probability) const override; 233 234 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 235 BranchProbability Probability) const override { 236 return true; 237 } 238 239 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 240 MachineBasicBlock &FMBB) const override { 241 return false; 242 } 243 244 // Predication support. 245 bool isPredicated(const MachineInstr &MI) const override; 246 247 bool isUnpredicatedTerminator(const MachineInstr &MI) const override; 248 249 bool PredicateInstruction(MachineInstr &MI, 250 ArrayRef<MachineOperand> Pred) const override; 251 252 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 253 ArrayRef<MachineOperand> Pred2) const override; 254 255 bool DefinesPredicate(MachineInstr &MI, 256 std::vector<MachineOperand> &Pred) const override; 257 258 bool isPredicable(const MachineInstr &MI) const override; 259 260 // Comparison optimization. 261 262 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, 263 unsigned &SrcReg2, int &Mask, int &Value) const override; 264 265 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, 266 unsigned SrcReg2, int Mask, int Value, 267 const MachineRegisterInfo *MRI) const override; 268 269 /// GetInstSize - Return the number of bytes of code the specified 270 /// instruction may be. This returns the maximum number of bytes. 271 /// 272 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 273 274 void getNoop(MCInst &NopInst) const override; 275 276 std::pair<unsigned, unsigned> 277 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 278 279 ArrayRef<std::pair<unsigned, const char *>> 280 getSerializableDirectMachineOperandTargetFlags() const override; 281 282 ArrayRef<std::pair<unsigned, const char *>> 283 getSerializableBitmaskMachineOperandTargetFlags() const override; 284 285 // Lower pseudo instructions after register allocation. 286 bool expandPostRAPseudo(MachineInstr &MI) const override; 287 288 static bool isVFRegister(unsigned Reg) { 289 return Reg >= PPC::VF0 && Reg <= PPC::VF31; 290 } 291 static bool isVRRegister(unsigned Reg) { 292 return Reg >= PPC::V0 && Reg <= PPC::V31; 293 } 294 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const; 295 static int getRecordFormOpcode(unsigned Opcode); 296 297 bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, 298 const unsigned PhiDepth) const; 299 300 /// Return true if the output of the instruction is always a sign-extended, 301 /// i.e. 0 to 31-th bits are same as 32-th bit. 302 bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const { 303 return isSignOrZeroExtended(MI, true, depth); 304 } 305 306 /// Return true if the output of the instruction is always zero-extended, 307 /// i.e. 0 to 31-th bits are all zeros 308 bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const { 309 return isSignOrZeroExtended(MI, false, depth); 310 } 311 }; 312 313 } 314 315 #endif 316