1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef POWERPC_INSTRUCTIONINFO_H 15 #define POWERPC_INSTRUCTIONINFO_H 16 17 #include "PPC.h" 18 #include "PPCRegisterInfo.h" 19 #include "llvm/Target/TargetInstrInfo.h" 20 21 #define GET_INSTRINFO_HEADER 22 #include "PPCGenInstrInfo.inc" 23 24 namespace llvm { 25 26 /// PPCII - This namespace holds all of the PowerPC target-specific 27 /// per-instruction flags. These must match the corresponding definitions in 28 /// PPC.td and PPCInstrFormats.td. 29 namespace PPCII { 30 enum { 31 // PPC970 Instruction Flags. These flags describe the characteristics of the 32 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 33 // raw machine instructions. 34 35 /// PPC970_First - This instruction starts a new dispatch group, so it will 36 /// always be the first one in the group. 37 PPC970_First = 0x1, 38 39 /// PPC970_Single - This instruction starts a new dispatch group and 40 /// terminates it, so it will be the sole instruction in the group. 41 PPC970_Single = 0x2, 42 43 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 44 /// two dispatch pipes to be available to issue. 45 PPC970_Cracked = 0x4, 46 47 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 48 /// an instruction is issued to. 49 PPC970_Shift = 3, 50 PPC970_Mask = 0x07 << PPC970_Shift 51 }; 52 enum PPC970_Unit { 53 /// These are the various PPC970 execution unit pipelines. Each instruction 54 /// is one of these. 55 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 56 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 57 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 58 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 59 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 60 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 61 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 62 PPC970_BRU = 7 << PPC970_Shift // Branch Unit 63 }; 64 } // end namespace PPCII 65 66 67 class PPCInstrInfo : public PPCGenInstrInfo { 68 PPCTargetMachine &TM; 69 const PPCRegisterInfo RI; 70 71 bool StoreRegToStackSlot(MachineFunction &MF, 72 unsigned SrcReg, bool isKill, int FrameIdx, 73 const TargetRegisterClass *RC, 74 SmallVectorImpl<MachineInstr*> &NewMIs, 75 bool &NonRI, bool &SpillsVRS) const; 76 bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, 77 unsigned DestReg, int FrameIdx, 78 const TargetRegisterClass *RC, 79 SmallVectorImpl<MachineInstr*> &NewMIs, 80 bool &NonRI, bool &SpillsVRS) const; 81 virtual void anchor(); 82 public: 83 explicit PPCInstrInfo(PPCTargetMachine &TM); 84 85 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 86 /// such, whenever a client has an instance of instruction info, it should 87 /// always be able to get register info as well (through this method). 88 /// 89 virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; } 90 91 ScheduleHazardRecognizer * 92 CreateTargetHazardRecognizer(const TargetMachine *TM, 93 const ScheduleDAG *DAG) const; 94 ScheduleHazardRecognizer * 95 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 96 const ScheduleDAG *DAG) const; 97 98 virtual 99 int getOperandLatency(const InstrItineraryData *ItinData, 100 const MachineInstr *DefMI, unsigned DefIdx, 101 const MachineInstr *UseMI, unsigned UseIdx) const; 102 virtual 103 int getOperandLatency(const InstrItineraryData *ItinData, 104 SDNode *DefNode, unsigned DefIdx, 105 SDNode *UseNode, unsigned UseIdx) const { 106 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, 107 UseNode, UseIdx); 108 } 109 110 bool isCoalescableExtInstr(const MachineInstr &MI, 111 unsigned &SrcReg, unsigned &DstReg, 112 unsigned &SubIdx) const; 113 unsigned isLoadFromStackSlot(const MachineInstr *MI, 114 int &FrameIndex) const; 115 unsigned isStoreToStackSlot(const MachineInstr *MI, 116 int &FrameIndex) const; 117 118 // commuteInstruction - We can commute rlwimi instructions, but only if the 119 // rotate amt is zero. We also have to munge the immediates a bit. 120 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 121 122 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 123 unsigned &SrcOpIdx2) const; 124 125 virtual void insertNoop(MachineBasicBlock &MBB, 126 MachineBasicBlock::iterator MI) const; 127 128 129 // Branch analysis. 130 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 131 MachineBasicBlock *&FBB, 132 SmallVectorImpl<MachineOperand> &Cond, 133 bool AllowModify) const; 134 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 135 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 136 MachineBasicBlock *FBB, 137 const SmallVectorImpl<MachineOperand> &Cond, 138 DebugLoc DL) const; 139 140 // Select analysis. 141 virtual bool canInsertSelect(const MachineBasicBlock&, 142 const SmallVectorImpl<MachineOperand> &Cond, 143 unsigned, unsigned, int&, int&, int&) const; 144 virtual void insertSelect(MachineBasicBlock &MBB, 145 MachineBasicBlock::iterator MI, DebugLoc DL, 146 unsigned DstReg, 147 const SmallVectorImpl<MachineOperand> &Cond, 148 unsigned TrueReg, unsigned FalseReg) const; 149 150 virtual void copyPhysReg(MachineBasicBlock &MBB, 151 MachineBasicBlock::iterator I, DebugLoc DL, 152 unsigned DestReg, unsigned SrcReg, 153 bool KillSrc) const; 154 155 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 156 MachineBasicBlock::iterator MBBI, 157 unsigned SrcReg, bool isKill, int FrameIndex, 158 const TargetRegisterClass *RC, 159 const TargetRegisterInfo *TRI) const; 160 161 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 162 MachineBasicBlock::iterator MBBI, 163 unsigned DestReg, int FrameIndex, 164 const TargetRegisterClass *RC, 165 const TargetRegisterInfo *TRI) const; 166 167 virtual 168 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 169 170 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 171 unsigned Reg, MachineRegisterInfo *MRI) const; 172 173 // If conversion by predication (only supported by some branch instructions). 174 // All of the profitability checks always return true; it is always 175 // profitable to use the predicated branches. 176 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, 177 unsigned NumCycles, unsigned ExtraPredCycles, 178 const BranchProbability &Probability) const { 179 return true; 180 } 181 182 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 183 unsigned NumT, unsigned ExtraT, 184 MachineBasicBlock &FMBB, 185 unsigned NumF, unsigned ExtraF, 186 const BranchProbability &Probability) const; 187 188 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, 189 unsigned NumCycles, 190 const BranchProbability 191 &Probability) const { 192 return true; 193 } 194 195 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 196 MachineBasicBlock &FMBB) const { 197 return false; 198 } 199 200 // Predication support. 201 bool isPredicated(const MachineInstr *MI) const; 202 203 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 204 205 virtual 206 bool PredicateInstruction(MachineInstr *MI, 207 const SmallVectorImpl<MachineOperand> &Pred) const; 208 209 virtual 210 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 211 const SmallVectorImpl<MachineOperand> &Pred2) const; 212 213 virtual bool DefinesPredicate(MachineInstr *MI, 214 std::vector<MachineOperand> &Pred) const; 215 216 virtual bool isPredicable(MachineInstr *MI) const; 217 218 // Comparison optimization. 219 220 221 virtual bool analyzeCompare(const MachineInstr *MI, 222 unsigned &SrcReg, unsigned &SrcReg2, 223 int &Mask, int &Value) const; 224 225 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, 226 unsigned SrcReg, unsigned SrcReg2, 227 int Mask, int Value, 228 const MachineRegisterInfo *MRI) const; 229 230 /// GetInstSize - Return the number of bytes of code the specified 231 /// instruction may be. This returns the maximum number of bytes. 232 /// 233 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 234 }; 235 236 } 237 238 #endif 239