1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the PowerPC implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 14 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 15 16 #include "PPCRegisterInfo.h" 17 #include "llvm/CodeGen/TargetInstrInfo.h" 18 19 #define GET_INSTRINFO_HEADER 20 #include "PPCGenInstrInfo.inc" 21 22 namespace llvm { 23 24 /// PPCII - This namespace holds all of the PowerPC target-specific 25 /// per-instruction flags. These must match the corresponding definitions in 26 /// PPC.td and PPCInstrFormats.td. 27 namespace PPCII { 28 enum { 29 // PPC970 Instruction Flags. These flags describe the characteristics of the 30 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 31 // raw machine instructions. 32 33 /// PPC970_First - This instruction starts a new dispatch group, so it will 34 /// always be the first one in the group. 35 PPC970_First = 0x1, 36 37 /// PPC970_Single - This instruction starts a new dispatch group and 38 /// terminates it, so it will be the sole instruction in the group. 39 PPC970_Single = 0x2, 40 41 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 42 /// two dispatch pipes to be available to issue. 43 PPC970_Cracked = 0x4, 44 45 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 46 /// an instruction is issued to. 47 PPC970_Shift = 3, 48 PPC970_Mask = 0x07 << PPC970_Shift 49 }; 50 enum PPC970_Unit { 51 /// These are the various PPC970 execution unit pipelines. Each instruction 52 /// is one of these. 53 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 54 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 55 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 56 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 57 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 58 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 59 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 60 PPC970_BRU = 7 << PPC970_Shift // Branch Unit 61 }; 62 63 enum { 64 /// Shift count to bypass PPC970 flags 65 NewDef_Shift = 6, 66 67 /// This instruction is an X-Form memory operation. 68 XFormMemOp = 0x1 << NewDef_Shift, 69 /// This instruction is prefixed. 70 Prefixed = 0x1 << (NewDef_Shift+1) 71 }; 72 } // end namespace PPCII 73 74 // Instructions that have an immediate form might be convertible to that 75 // form if the correct input is a result of a load immediate. In order to 76 // know whether the transformation is special, we might need to know some 77 // of the details of the two forms. 78 struct ImmInstrInfo { 79 // Is the immediate field in the immediate form signed or unsigned? 80 uint64_t SignedImm : 1; 81 // Does the immediate need to be a multiple of some value? 82 uint64_t ImmMustBeMultipleOf : 5; 83 // Is R0/X0 treated specially by the original r+r instruction? 84 // If so, in which operand? 85 uint64_t ZeroIsSpecialOrig : 3; 86 // Is R0/X0 treated specially by the new r+i instruction? 87 // If so, in which operand? 88 uint64_t ZeroIsSpecialNew : 3; 89 // Is the operation commutative? 90 uint64_t IsCommutative : 1; 91 // The operand number to check for add-immediate def. 92 uint64_t OpNoForForwarding : 3; 93 // The operand number for the immediate. 94 uint64_t ImmOpNo : 3; 95 // The opcode of the new instruction. 96 uint64_t ImmOpcode : 16; 97 // The size of the immediate. 98 uint64_t ImmWidth : 5; 99 // The immediate should be truncated to N bits. 100 uint64_t TruncateImmTo : 5; 101 // Is the instruction summing the operand 102 uint64_t IsSummingOperands : 1; 103 }; 104 105 // Information required to convert an instruction to just a materialized 106 // immediate. 107 struct LoadImmediateInfo { 108 unsigned Imm : 16; 109 unsigned Is64Bit : 1; 110 unsigned SetCR : 1; 111 }; 112 113 // Index into the OpcodesForSpill array. 114 enum SpillOpcodeKey { 115 SOK_Int4Spill, 116 SOK_Int8Spill, 117 SOK_Float8Spill, 118 SOK_Float4Spill, 119 SOK_CRSpill, 120 SOK_CRBitSpill, 121 SOK_VRVectorSpill, 122 SOK_VSXVectorSpill, 123 SOK_VectorFloat8Spill, 124 SOK_VectorFloat4Spill, 125 SOK_VRSaveSpill, 126 SOK_QuadFloat8Spill, 127 SOK_QuadFloat4Spill, 128 SOK_QuadBitSpill, 129 SOK_SpillToVSR, 130 SOK_SPESpill, 131 SOK_LastOpcodeSpill // This must be last on the enum. 132 }; 133 134 // Define list of load and store spill opcodes. 135 #define Pwr8LoadOpcodes \ 136 { \ 137 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 138 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \ 139 PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb, \ 140 PPC::SPILLTOVSR_LD, PPC::EVLDD \ 141 } 142 143 #define Pwr9LoadOpcodes \ 144 { \ 145 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 146 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \ 147 PPC::DFLOADf32, PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, \ 148 PPC::QVLFDXb, PPC::SPILLTOVSR_LD \ 149 } 150 151 #define Pwr8StoreOpcodes \ 152 { \ 153 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 154 PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, PPC::SPILL_VRSAVE, \ 155 PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb, PPC::SPILLTOVSR_ST, \ 156 PPC::EVSTDD \ 157 } 158 159 #define Pwr9StoreOpcodes \ 160 { \ 161 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 162 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \ 163 PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb, \ 164 PPC::SPILLTOVSR_ST \ 165 } 166 167 // Initialize arrays for load and store spill opcodes on supported subtargets. 168 #define StoreOpcodesForSpill \ 169 { Pwr8StoreOpcodes, Pwr9StoreOpcodes } 170 #define LoadOpcodesForSpill \ 171 { Pwr8LoadOpcodes, Pwr9LoadOpcodes } 172 173 class PPCSubtarget; 174 class PPCInstrInfo : public PPCGenInstrInfo { 175 PPCSubtarget &Subtarget; 176 const PPCRegisterInfo RI; 177 const unsigned StoreSpillOpcodesArray[2][SOK_LastOpcodeSpill] = 178 StoreOpcodesForSpill; 179 const unsigned LoadSpillOpcodesArray[2][SOK_LastOpcodeSpill] = 180 LoadOpcodesForSpill; 181 182 void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, 183 int FrameIdx, const TargetRegisterClass *RC, 184 SmallVectorImpl<MachineInstr *> &NewMIs) const; 185 void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, 186 unsigned DestReg, int FrameIdx, 187 const TargetRegisterClass *RC, 188 SmallVectorImpl<MachineInstr *> &NewMIs) const; 189 190 // Replace the instruction with single LI if possible. \p DefMI must be LI or 191 // LI8. 192 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI, 193 unsigned OpNoForForwarding, MachineInstr **KilledDef) const; 194 // If the inst is x-form and has imm-form and one of its operand is produced 195 // by a LI, put the imm into the inst directly and remove the LI if possible. 196 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III, 197 unsigned ConstantOpNo, 198 MachineInstr &DefMI) const; 199 // If the inst is x-form and has imm-form and one of its operand is produced 200 // by an add-immediate, try to transform it when possible. 201 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III, 202 unsigned ConstantOpNo, MachineInstr &DefMI, 203 bool KillDefMI) const; 204 // Try to find that, if the instruction 'MI' contains any operand that 205 // could be forwarded from some inst that feeds it. If yes, return the 206 // Def of that operand. And OpNoForForwarding is the operand index in 207 // the 'MI' for that 'Def'. If we see another use of this Def between 208 // the Def and the MI, SeenIntermediateUse becomes 'true'. 209 MachineInstr *getForwardingDefMI(MachineInstr &MI, 210 unsigned &OpNoForForwarding, 211 bool &SeenIntermediateUse) const; 212 213 // Can the user MI have it's source at index \p OpNoForForwarding 214 // forwarded from an add-immediate that feeds it? 215 bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III, 216 unsigned OpNoForForwarding) const; 217 bool isDefMIElgibleForForwarding(MachineInstr &DefMI, 218 const ImmInstrInfo &III, 219 MachineOperand *&ImmMO, 220 MachineOperand *&RegMO) const; 221 bool isImmElgibleForForwarding(const MachineOperand &ImmMO, 222 const MachineInstr &DefMI, 223 const ImmInstrInfo &III, 224 int64_t &Imm) const; 225 bool isRegElgibleForForwarding(const MachineOperand &RegMO, 226 const MachineInstr &DefMI, 227 const MachineInstr &MI, bool KillDefMI, 228 bool &IsFwdFeederRegKilled) const; 229 unsigned getSpillTarget() const; 230 const unsigned *getStoreOpcodesForSpillArray() const; 231 const unsigned *getLoadOpcodesForSpillArray() const; 232 int16_t getFMAOpIdxInfo(unsigned Opcode) const; 233 void reassociateFMA(MachineInstr &Root, MachineCombinerPattern Pattern, 234 SmallVectorImpl<MachineInstr *> &InsInstrs, 235 SmallVectorImpl<MachineInstr *> &DelInstrs, 236 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const; 237 virtual void anchor(); 238 239 protected: 240 /// Commutes the operands in the given instruction. 241 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2. 242 /// 243 /// Do not call this method for a non-commutable instruction or for 244 /// non-commutable pair of operand indices OpIdx1 and OpIdx2. 245 /// Even though the instruction is commutable, the method may still 246 /// fail to commute the operands, null pointer is returned in such cases. 247 /// 248 /// For example, we can commute rlwimi instructions, but only if the 249 /// rotate amt is zero. We also have to munge the immediates a bit. 250 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 251 unsigned OpIdx1, 252 unsigned OpIdx2) const override; 253 254 public: 255 explicit PPCInstrInfo(PPCSubtarget &STI); 256 257 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 258 /// such, whenever a client has an instance of instruction info, it should 259 /// always be able to get register info as well (through this method). 260 /// 261 const PPCRegisterInfo &getRegisterInfo() const { return RI; } 262 263 bool isXFormMemOp(unsigned Opcode) const { 264 return get(Opcode).TSFlags & PPCII::XFormMemOp; 265 } 266 bool isPrefixed(unsigned Opcode) const { 267 return get(Opcode).TSFlags & PPCII::Prefixed; 268 } 269 270 static bool isSameClassPhysRegCopy(unsigned Opcode) { 271 unsigned CopyOpcodes[] = 272 { PPC::OR, PPC::OR8, PPC::FMR, PPC::VOR, PPC::XXLOR, PPC::XXLORf, 273 PPC::XSCPSGNDP, PPC::MCRF, PPC::QVFMR, PPC::QVFMRs, PPC::QVFMRb, 274 PPC::CROR, PPC::EVOR, -1U }; 275 for (int i = 0; CopyOpcodes[i] != -1U; i++) 276 if (Opcode == CopyOpcodes[i]) 277 return true; 278 return false; 279 } 280 281 ScheduleHazardRecognizer * 282 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 283 const ScheduleDAG *DAG) const override; 284 ScheduleHazardRecognizer * 285 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 286 const ScheduleDAG *DAG) const override; 287 288 unsigned getInstrLatency(const InstrItineraryData *ItinData, 289 const MachineInstr &MI, 290 unsigned *PredCost = nullptr) const override; 291 292 int getOperandLatency(const InstrItineraryData *ItinData, 293 const MachineInstr &DefMI, unsigned DefIdx, 294 const MachineInstr &UseMI, 295 unsigned UseIdx) const override; 296 int getOperandLatency(const InstrItineraryData *ItinData, 297 SDNode *DefNode, unsigned DefIdx, 298 SDNode *UseNode, unsigned UseIdx) const override { 299 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, 300 UseNode, UseIdx); 301 } 302 303 bool hasLowDefLatency(const TargetSchedModel &SchedModel, 304 const MachineInstr &DefMI, 305 unsigned DefIdx) const override { 306 // Machine LICM should hoist all instructions in low-register-pressure 307 // situations; none are sufficiently free to justify leaving in a loop 308 // body. 309 return false; 310 } 311 312 bool useMachineCombiner() const override { 313 return true; 314 } 315 316 /// When getMachineCombinerPatterns() finds patterns, this function generates 317 /// the instructions that could replace the original code sequence 318 void genAlternativeCodeSequence( 319 MachineInstr &Root, MachineCombinerPattern Pattern, 320 SmallVectorImpl<MachineInstr *> &InsInstrs, 321 SmallVectorImpl<MachineInstr *> &DelInstrs, 322 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override; 323 324 /// Return true when there is potentially a faster code sequence for a fma 325 /// chain ending in \p Root. All potential patterns are output in the \p 326 /// P array. 327 bool getFMAPatterns(MachineInstr &Root, 328 SmallVectorImpl<MachineCombinerPattern> &P) const; 329 330 /// Return true when there is potentially a faster code sequence 331 /// for an instruction chain ending in <Root>. All potential patterns are 332 /// output in the <Pattern> array. 333 bool getMachineCombinerPatterns( 334 MachineInstr &Root, 335 SmallVectorImpl<MachineCombinerPattern> &P) const override; 336 337 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override; 338 339 /// On PowerPC, we try to reassociate FMA chain which will increase 340 /// instruction size. Set extension resource length limit to 1 for edge case. 341 /// Resource Length is calculated by scaled resource usage in getCycles(). 342 /// Because of the division in getCycles(), it returns different cycles due to 343 /// legacy scaled resource usage. So new resource length may be same with 344 /// legacy or 1 bigger than legacy. 345 /// We need to execlude the 1 bigger case even the resource length is not 346 /// perserved for more FMA chain reassociations on PowerPC. 347 int getExtendResourceLenLimit() const override { return 1; } 348 349 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, 350 MachineInstr &NewMI1, 351 MachineInstr &NewMI2) const override; 352 353 void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const override; 354 355 bool isCoalescableExtInstr(const MachineInstr &MI, 356 Register &SrcReg, Register &DstReg, 357 unsigned &SubIdx) const override; 358 unsigned isLoadFromStackSlot(const MachineInstr &MI, 359 int &FrameIndex) const override; 360 bool isReallyTriviallyReMaterializable(const MachineInstr &MI, 361 AAResults *AA) const override; 362 unsigned isStoreToStackSlot(const MachineInstr &MI, 363 int &FrameIndex) const override; 364 365 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 366 unsigned &SrcOpIdx2) const override; 367 368 void insertNoop(MachineBasicBlock &MBB, 369 MachineBasicBlock::iterator MI) const override; 370 371 372 // Branch analysis. 373 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 374 MachineBasicBlock *&FBB, 375 SmallVectorImpl<MachineOperand> &Cond, 376 bool AllowModify) const override; 377 unsigned removeBranch(MachineBasicBlock &MBB, 378 int *BytesRemoved = nullptr) const override; 379 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 380 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 381 const DebugLoc &DL, 382 int *BytesAdded = nullptr) const override; 383 384 // Select analysis. 385 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 386 Register, Register, Register, int &, int &, 387 int &) const override; 388 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 389 const DebugLoc &DL, Register DstReg, 390 ArrayRef<MachineOperand> Cond, Register TrueReg, 391 Register FalseReg) const override; 392 393 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 394 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 395 bool KillSrc) const override; 396 397 void storeRegToStackSlot(MachineBasicBlock &MBB, 398 MachineBasicBlock::iterator MBBI, 399 Register SrcReg, bool isKill, int FrameIndex, 400 const TargetRegisterClass *RC, 401 const TargetRegisterInfo *TRI) const override; 402 403 // Emits a register spill without updating the register class for vector 404 // registers. This ensures that when we spill a vector register the 405 // element order in the register is the same as it was in memory. 406 void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, 407 MachineBasicBlock::iterator MBBI, 408 unsigned SrcReg, bool isKill, int FrameIndex, 409 const TargetRegisterClass *RC, 410 const TargetRegisterInfo *TRI) const; 411 412 void loadRegFromStackSlot(MachineBasicBlock &MBB, 413 MachineBasicBlock::iterator MBBI, 414 Register DestReg, int FrameIndex, 415 const TargetRegisterClass *RC, 416 const TargetRegisterInfo *TRI) const override; 417 418 // Emits a register reload without updating the register class for vector 419 // registers. This ensures that when we reload a vector register the 420 // element order in the register is the same as it was in memory. 421 void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, 422 MachineBasicBlock::iterator MBBI, 423 unsigned DestReg, int FrameIndex, 424 const TargetRegisterClass *RC, 425 const TargetRegisterInfo *TRI) const; 426 427 unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const; 428 429 unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const; 430 431 bool 432 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 433 434 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, 435 MachineRegisterInfo *MRI) const override; 436 437 bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, 438 Register Reg) const; 439 440 // If conversion by predication (only supported by some branch instructions). 441 // All of the profitability checks always return true; it is always 442 // profitable to use the predicated branches. 443 bool isProfitableToIfCvt(MachineBasicBlock &MBB, 444 unsigned NumCycles, unsigned ExtraPredCycles, 445 BranchProbability Probability) const override { 446 return true; 447 } 448 449 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 450 unsigned NumT, unsigned ExtraT, 451 MachineBasicBlock &FMBB, 452 unsigned NumF, unsigned ExtraF, 453 BranchProbability Probability) const override; 454 455 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 456 BranchProbability Probability) const override { 457 return true; 458 } 459 460 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 461 MachineBasicBlock &FMBB) const override { 462 return false; 463 } 464 465 // Predication support. 466 bool isPredicated(const MachineInstr &MI) const override; 467 468 bool PredicateInstruction(MachineInstr &MI, 469 ArrayRef<MachineOperand> Pred) const override; 470 471 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 472 ArrayRef<MachineOperand> Pred2) const override; 473 474 bool DefinesPredicate(MachineInstr &MI, 475 std::vector<MachineOperand> &Pred) const override; 476 477 // Comparison optimization. 478 479 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 480 Register &SrcReg2, int &Mask, int &Value) const override; 481 482 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 483 Register SrcReg2, int Mask, int Value, 484 const MachineRegisterInfo *MRI) const override; 485 486 487 /// Return true if get the base operand, byte offset of an instruction and 488 /// the memory width. Width is the size of memory that is being 489 /// loaded/stored (e.g. 1, 2, 4, 8). 490 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, 491 const MachineOperand *&BaseOp, 492 int64_t &Offset, unsigned &Width, 493 const TargetRegisterInfo *TRI) const; 494 495 /// Return true if two MIs access different memory addresses and false 496 /// otherwise 497 bool 498 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 499 const MachineInstr &MIb) const override; 500 501 /// GetInstSize - Return the number of bytes of code the specified 502 /// instruction may be. This returns the maximum number of bytes. 503 /// 504 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 505 506 void getNoop(MCInst &NopInst) const override; 507 508 std::pair<unsigned, unsigned> 509 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 510 511 ArrayRef<std::pair<unsigned, const char *>> 512 getSerializableDirectMachineOperandTargetFlags() const override; 513 514 ArrayRef<std::pair<unsigned, const char *>> 515 getSerializableBitmaskMachineOperandTargetFlags() const override; 516 517 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction. 518 bool expandVSXMemPseudo(MachineInstr &MI) const; 519 520 // Lower pseudo instructions after register allocation. 521 bool expandPostRAPseudo(MachineInstr &MI) const override; 522 523 static bool isVFRegister(unsigned Reg) { 524 return Reg >= PPC::VF0 && Reg <= PPC::VF31; 525 } 526 static bool isVRRegister(unsigned Reg) { 527 return Reg >= PPC::V0 && Reg <= PPC::V31; 528 } 529 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const; 530 static int getRecordFormOpcode(unsigned Opcode); 531 532 bool isTOCSaveMI(const MachineInstr &MI) const; 533 534 bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, 535 const unsigned PhiDepth) const; 536 537 /// Return true if the output of the instruction is always a sign-extended, 538 /// i.e. 0 to 31-th bits are same as 32-th bit. 539 bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const { 540 return isSignOrZeroExtended(MI, true, depth); 541 } 542 543 /// Return true if the output of the instruction is always zero-extended, 544 /// i.e. 0 to 31-th bits are all zeros 545 bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const { 546 return isSignOrZeroExtended(MI, false, depth); 547 } 548 549 bool convertToImmediateForm(MachineInstr &MI, 550 MachineInstr **KilledDef = nullptr) const; 551 bool foldFrameOffset(MachineInstr &MI) const; 552 bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const; 553 bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const; 554 bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, 555 unsigned &XFormOpcode, 556 int64_t &OffsetOfImmInstr, 557 ImmInstrInfo &III) const; 558 bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, 559 MachineInstr *&ADDIMI, int64_t &OffsetAddi, 560 int64_t OffsetImm) const; 561 562 /// Fixup killed/dead flag for register \p RegNo between instructions [\p 563 /// StartMI, \p EndMI]. Some PostRA transformations may violate register 564 /// killed/dead flags semantics, this function can be called to fix up. Before 565 /// calling this function, 566 /// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI. 567 /// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI) 568 /// and possible definition for \p RegNo is \p StartMI or \p EndMI. 569 /// 3. Ensure that all instructions between [\p StartMI, \p EndMI] are in same 570 /// basic block. 571 void fixupIsDeadOrKill(MachineInstr &StartMI, MachineInstr &EndMI, 572 unsigned RegNo) const; 573 void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const; 574 void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, 575 int64_t Imm) const; 576 577 bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, 578 bool PostRA) const; 579 580 // In PostRA phase, try to find instruction defines \p Reg before \p MI. 581 // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist. 582 MachineInstr *getDefMIPostRA(unsigned Reg, MachineInstr &MI, 583 bool &SeenIntermediateUse) const; 584 585 /// getRegNumForOperand - some operands use different numbering schemes 586 /// for the same registers. For example, a VSX instruction may have any of 587 /// vs0-vs63 allocated whereas an Altivec instruction could only have 588 /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual 589 /// register number needed for the opcode/operand number combination. 590 /// The operand number argument will be useful when we need to extend this 591 /// to instructions that use both Altivec and VSX numbering (for different 592 /// operands). 593 static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, 594 unsigned OpNo) { 595 int16_t regClass = Desc.OpInfo[OpNo].RegClass; 596 switch (regClass) { 597 // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31, 598 // VSX32-VSX63 during encoding/disassembling 599 case PPC::VSSRCRegClassID: 600 case PPC::VSFRCRegClassID: 601 if (isVFRegister(Reg)) 602 return PPC::VSX32 + (Reg - PPC::VF0); 603 break; 604 // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31, 605 // VSX32-VSX63 during encoding/disassembling 606 case PPC::VSRCRegClassID: 607 if (isVRRegister(Reg)) 608 return PPC::VSX32 + (Reg - PPC::V0); 609 break; 610 // Other RegClass doesn't need mapping 611 default: 612 break; 613 } 614 return Reg; 615 } 616 617 /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero). 618 bool isBDNZ(unsigned Opcode) const; 619 620 /// Find the hardware loop instruction used to set-up the specified loop. 621 /// On PPC, we have two instructions used to set-up the hardware loop 622 /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8) 623 /// instructions to indicate the end of a loop. 624 MachineInstr * 625 findLoopInstr(MachineBasicBlock &PreHeader, 626 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const; 627 628 /// Analyze loop L, which must be a single-basic-block loop, and if the 629 /// conditions can be understood enough produce a PipelinerLoopInfo object. 630 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo> 631 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override; 632 }; 633 634 } 635 636 #endif 637