1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the PowerPC implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 14 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 15 16 #include "PPCRegisterInfo.h" 17 #include "llvm/CodeGen/TargetInstrInfo.h" 18 19 #define GET_INSTRINFO_HEADER 20 #include "PPCGenInstrInfo.inc" 21 22 namespace llvm { 23 24 /// PPCII - This namespace holds all of the PowerPC target-specific 25 /// per-instruction flags. These must match the corresponding definitions in 26 /// PPC.td and PPCInstrFormats.td. 27 namespace PPCII { 28 enum { 29 // PPC970 Instruction Flags. These flags describe the characteristics of the 30 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 31 // raw machine instructions. 32 33 /// PPC970_First - This instruction starts a new dispatch group, so it will 34 /// always be the first one in the group. 35 PPC970_First = 0x1, 36 37 /// PPC970_Single - This instruction starts a new dispatch group and 38 /// terminates it, so it will be the sole instruction in the group. 39 PPC970_Single = 0x2, 40 41 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 42 /// two dispatch pipes to be available to issue. 43 PPC970_Cracked = 0x4, 44 45 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 46 /// an instruction is issued to. 47 PPC970_Shift = 3, 48 PPC970_Mask = 0x07 << PPC970_Shift 49 }; 50 enum PPC970_Unit { 51 /// These are the various PPC970 execution unit pipelines. Each instruction 52 /// is one of these. 53 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 54 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 55 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 56 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 57 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 58 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 59 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 60 PPC970_BRU = 7 << PPC970_Shift // Branch Unit 61 }; 62 63 enum { 64 /// Shift count to bypass PPC970 flags 65 NewDef_Shift = 6, 66 67 /// This instruction is an X-Form memory operation. 68 XFormMemOp = 0x1 << NewDef_Shift, 69 /// This instruction is prefixed. 70 Prefixed = 0x1 << (NewDef_Shift+1) 71 }; 72 } // end namespace PPCII 73 74 // Instructions that have an immediate form might be convertible to that 75 // form if the correct input is a result of a load immediate. In order to 76 // know whether the transformation is special, we might need to know some 77 // of the details of the two forms. 78 struct ImmInstrInfo { 79 // Is the immediate field in the immediate form signed or unsigned? 80 uint64_t SignedImm : 1; 81 // Does the immediate need to be a multiple of some value? 82 uint64_t ImmMustBeMultipleOf : 5; 83 // Is R0/X0 treated specially by the original r+r instruction? 84 // If so, in which operand? 85 uint64_t ZeroIsSpecialOrig : 3; 86 // Is R0/X0 treated specially by the new r+i instruction? 87 // If so, in which operand? 88 uint64_t ZeroIsSpecialNew : 3; 89 // Is the operation commutative? 90 uint64_t IsCommutative : 1; 91 // The operand number to check for add-immediate def. 92 uint64_t OpNoForForwarding : 3; 93 // The operand number for the immediate. 94 uint64_t ImmOpNo : 3; 95 // The opcode of the new instruction. 96 uint64_t ImmOpcode : 16; 97 // The size of the immediate. 98 uint64_t ImmWidth : 5; 99 // The immediate should be truncated to N bits. 100 uint64_t TruncateImmTo : 5; 101 // Is the instruction summing the operand 102 uint64_t IsSummingOperands : 1; 103 }; 104 105 // Information required to convert an instruction to just a materialized 106 // immediate. 107 struct LoadImmediateInfo { 108 unsigned Imm : 16; 109 unsigned Is64Bit : 1; 110 unsigned SetCR : 1; 111 }; 112 113 // Index into the OpcodesForSpill array. 114 enum SpillOpcodeKey { 115 SOK_Int4Spill, 116 SOK_Int8Spill, 117 SOK_Float8Spill, 118 SOK_Float4Spill, 119 SOK_CRSpill, 120 SOK_CRBitSpill, 121 SOK_VRVectorSpill, 122 SOK_VSXVectorSpill, 123 SOK_VectorFloat8Spill, 124 SOK_VectorFloat4Spill, 125 SOK_VRSaveSpill, 126 SOK_QuadFloat8Spill, 127 SOK_QuadFloat4Spill, 128 SOK_QuadBitSpill, 129 SOK_SpillToVSR, 130 SOK_SPESpill, 131 SOK_LastOpcodeSpill // This must be last on the enum. 132 }; 133 134 // Define list of load and store spill opcodes. 135 #define Pwr8LoadOpcodes \ 136 { \ 137 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 138 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \ 139 PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb, \ 140 PPC::SPILLTOVSR_LD, PPC::EVLDD \ 141 } 142 143 #define Pwr9LoadOpcodes \ 144 { \ 145 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 146 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \ 147 PPC::DFLOADf32, PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, \ 148 PPC::QVLFDXb, PPC::SPILLTOVSR_LD \ 149 } 150 151 #define Pwr8StoreOpcodes \ 152 { \ 153 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 154 PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, PPC::SPILL_VRSAVE, \ 155 PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb, PPC::SPILLTOVSR_ST, \ 156 PPC::EVSTDD \ 157 } 158 159 #define Pwr9StoreOpcodes \ 160 { \ 161 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 162 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \ 163 PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb, \ 164 PPC::SPILLTOVSR_ST \ 165 } 166 167 // Initialize arrays for load and store spill opcodes on supported subtargets. 168 #define StoreOpcodesForSpill \ 169 { Pwr8StoreOpcodes, Pwr9StoreOpcodes } 170 #define LoadOpcodesForSpill \ 171 { Pwr8LoadOpcodes, Pwr9LoadOpcodes } 172 173 class PPCSubtarget; 174 class PPCInstrInfo : public PPCGenInstrInfo { 175 PPCSubtarget &Subtarget; 176 const PPCRegisterInfo RI; 177 const unsigned StoreSpillOpcodesArray[2][SOK_LastOpcodeSpill] = 178 StoreOpcodesForSpill; 179 const unsigned LoadSpillOpcodesArray[2][SOK_LastOpcodeSpill] = 180 LoadOpcodesForSpill; 181 182 void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, 183 int FrameIdx, const TargetRegisterClass *RC, 184 SmallVectorImpl<MachineInstr *> &NewMIs) const; 185 void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, 186 unsigned DestReg, int FrameIdx, 187 const TargetRegisterClass *RC, 188 SmallVectorImpl<MachineInstr *> &NewMIs) const; 189 190 // If the inst has imm-form and one of its operand is produced by a LI, 191 // put the imm into the inst directly and remove the LI if possible. 192 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III, 193 unsigned ConstantOpNo, MachineInstr &DefMI, 194 int64_t Imm) const; 195 // If the inst has imm-form and one of its operand is produced by an 196 // add-immediate, try to transform it when possible. 197 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III, 198 unsigned ConstantOpNo, MachineInstr &DefMI, 199 bool KillDefMI) const; 200 // Try to find that, if the instruction 'MI' contains any operand that 201 // could be forwarded from some inst that feeds it. If yes, return the 202 // Def of that operand. And OpNoForForwarding is the operand index in 203 // the 'MI' for that 'Def'. If we see another use of this Def between 204 // the Def and the MI, SeenIntermediateUse becomes 'true'. 205 MachineInstr *getForwardingDefMI(MachineInstr &MI, 206 unsigned &OpNoForForwarding, 207 bool &SeenIntermediateUse) const; 208 209 // Can the user MI have it's source at index \p OpNoForForwarding 210 // forwarded from an add-immediate that feeds it? 211 bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III, 212 unsigned OpNoForForwarding) const; 213 bool isDefMIElgibleForForwarding(MachineInstr &DefMI, 214 const ImmInstrInfo &III, 215 MachineOperand *&ImmMO, 216 MachineOperand *&RegMO) const; 217 bool isImmElgibleForForwarding(const MachineOperand &ImmMO, 218 const MachineInstr &DefMI, 219 const ImmInstrInfo &III, 220 int64_t &Imm) const; 221 bool isRegElgibleForForwarding(const MachineOperand &RegMO, 222 const MachineInstr &DefMI, 223 const MachineInstr &MI, bool KillDefMI, 224 bool &IsFwdFeederRegKilled) const; 225 unsigned getSpillTarget() const; 226 const unsigned *getStoreOpcodesForSpillArray() const; 227 const unsigned *getLoadOpcodesForSpillArray() const; 228 virtual void anchor(); 229 230 protected: 231 /// Commutes the operands in the given instruction. 232 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2. 233 /// 234 /// Do not call this method for a non-commutable instruction or for 235 /// non-commutable pair of operand indices OpIdx1 and OpIdx2. 236 /// Even though the instruction is commutable, the method may still 237 /// fail to commute the operands, null pointer is returned in such cases. 238 /// 239 /// For example, we can commute rlwimi instructions, but only if the 240 /// rotate amt is zero. We also have to munge the immediates a bit. 241 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 242 unsigned OpIdx1, 243 unsigned OpIdx2) const override; 244 245 public: 246 explicit PPCInstrInfo(PPCSubtarget &STI); 247 248 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 249 /// such, whenever a client has an instance of instruction info, it should 250 /// always be able to get register info as well (through this method). 251 /// 252 const PPCRegisterInfo &getRegisterInfo() const { return RI; } 253 254 bool isXFormMemOp(unsigned Opcode) const { 255 return get(Opcode).TSFlags & PPCII::XFormMemOp; 256 } 257 bool isPrefixed(unsigned Opcode) const { 258 return get(Opcode).TSFlags & PPCII::Prefixed; 259 } 260 261 static bool isSameClassPhysRegCopy(unsigned Opcode) { 262 unsigned CopyOpcodes[] = 263 { PPC::OR, PPC::OR8, PPC::FMR, PPC::VOR, PPC::XXLOR, PPC::XXLORf, 264 PPC::XSCPSGNDP, PPC::MCRF, PPC::QVFMR, PPC::QVFMRs, PPC::QVFMRb, 265 PPC::CROR, PPC::EVOR, -1U }; 266 for (int i = 0; CopyOpcodes[i] != -1U; i++) 267 if (Opcode == CopyOpcodes[i]) 268 return true; 269 return false; 270 } 271 272 ScheduleHazardRecognizer * 273 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 274 const ScheduleDAG *DAG) const override; 275 ScheduleHazardRecognizer * 276 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 277 const ScheduleDAG *DAG) const override; 278 279 unsigned getInstrLatency(const InstrItineraryData *ItinData, 280 const MachineInstr &MI, 281 unsigned *PredCost = nullptr) const override; 282 283 int getOperandLatency(const InstrItineraryData *ItinData, 284 const MachineInstr &DefMI, unsigned DefIdx, 285 const MachineInstr &UseMI, 286 unsigned UseIdx) const override; 287 int getOperandLatency(const InstrItineraryData *ItinData, 288 SDNode *DefNode, unsigned DefIdx, 289 SDNode *UseNode, unsigned UseIdx) const override { 290 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, 291 UseNode, UseIdx); 292 } 293 294 bool hasLowDefLatency(const TargetSchedModel &SchedModel, 295 const MachineInstr &DefMI, 296 unsigned DefIdx) const override { 297 // Machine LICM should hoist all instructions in low-register-pressure 298 // situations; none are sufficiently free to justify leaving in a loop 299 // body. 300 return false; 301 } 302 303 bool useMachineCombiner() const override { 304 return true; 305 } 306 307 /// Return true when there is potentially a faster code sequence 308 /// for an instruction chain ending in <Root>. All potential patterns are 309 /// output in the <Pattern> array. 310 bool getMachineCombinerPatterns( 311 MachineInstr &Root, 312 SmallVectorImpl<MachineCombinerPattern> &P) const override; 313 314 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override; 315 316 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, 317 MachineInstr &NewMI1, 318 MachineInstr &NewMI2) const override; 319 320 void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const override; 321 322 bool isCoalescableExtInstr(const MachineInstr &MI, 323 Register &SrcReg, Register &DstReg, 324 unsigned &SubIdx) const override; 325 unsigned isLoadFromStackSlot(const MachineInstr &MI, 326 int &FrameIndex) const override; 327 bool isReallyTriviallyReMaterializable(const MachineInstr &MI, 328 AAResults *AA) const override; 329 unsigned isStoreToStackSlot(const MachineInstr &MI, 330 int &FrameIndex) const override; 331 332 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 333 unsigned &SrcOpIdx2) const override; 334 335 void insertNoop(MachineBasicBlock &MBB, 336 MachineBasicBlock::iterator MI) const override; 337 338 339 // Branch analysis. 340 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 341 MachineBasicBlock *&FBB, 342 SmallVectorImpl<MachineOperand> &Cond, 343 bool AllowModify) const override; 344 unsigned removeBranch(MachineBasicBlock &MBB, 345 int *BytesRemoved = nullptr) const override; 346 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 347 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 348 const DebugLoc &DL, 349 int *BytesAdded = nullptr) const override; 350 351 // Select analysis. 352 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 353 Register, Register, Register, int &, int &, 354 int &) const override; 355 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 356 const DebugLoc &DL, Register DstReg, 357 ArrayRef<MachineOperand> Cond, Register TrueReg, 358 Register FalseReg) const override; 359 360 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 361 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 362 bool KillSrc) const override; 363 364 void storeRegToStackSlot(MachineBasicBlock &MBB, 365 MachineBasicBlock::iterator MBBI, 366 Register SrcReg, bool isKill, int FrameIndex, 367 const TargetRegisterClass *RC, 368 const TargetRegisterInfo *TRI) const override; 369 370 // Emits a register spill without updating the register class for vector 371 // registers. This ensures that when we spill a vector register the 372 // element order in the register is the same as it was in memory. 373 void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, 374 MachineBasicBlock::iterator MBBI, 375 unsigned SrcReg, bool isKill, int FrameIndex, 376 const TargetRegisterClass *RC, 377 const TargetRegisterInfo *TRI) const; 378 379 void loadRegFromStackSlot(MachineBasicBlock &MBB, 380 MachineBasicBlock::iterator MBBI, 381 Register DestReg, int FrameIndex, 382 const TargetRegisterClass *RC, 383 const TargetRegisterInfo *TRI) const override; 384 385 // Emits a register reload without updating the register class for vector 386 // registers. This ensures that when we reload a vector register the 387 // element order in the register is the same as it was in memory. 388 void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, 389 MachineBasicBlock::iterator MBBI, 390 unsigned DestReg, int FrameIndex, 391 const TargetRegisterClass *RC, 392 const TargetRegisterInfo *TRI) const; 393 394 unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const; 395 396 unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const; 397 398 bool 399 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 400 401 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, 402 MachineRegisterInfo *MRI) const override; 403 404 bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, 405 Register Reg) const; 406 407 // If conversion by predication (only supported by some branch instructions). 408 // All of the profitability checks always return true; it is always 409 // profitable to use the predicated branches. 410 bool isProfitableToIfCvt(MachineBasicBlock &MBB, 411 unsigned NumCycles, unsigned ExtraPredCycles, 412 BranchProbability Probability) const override { 413 return true; 414 } 415 416 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 417 unsigned NumT, unsigned ExtraT, 418 MachineBasicBlock &FMBB, 419 unsigned NumF, unsigned ExtraF, 420 BranchProbability Probability) const override; 421 422 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 423 BranchProbability Probability) const override { 424 return true; 425 } 426 427 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 428 MachineBasicBlock &FMBB) const override { 429 return false; 430 } 431 432 // Predication support. 433 bool isPredicated(const MachineInstr &MI) const override; 434 435 bool PredicateInstruction(MachineInstr &MI, 436 ArrayRef<MachineOperand> Pred) const override; 437 438 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 439 ArrayRef<MachineOperand> Pred2) const override; 440 441 bool DefinesPredicate(MachineInstr &MI, 442 std::vector<MachineOperand> &Pred) const override; 443 444 // Comparison optimization. 445 446 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 447 Register &SrcReg2, int &Mask, int &Value) const override; 448 449 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 450 Register SrcReg2, int Mask, int Value, 451 const MachineRegisterInfo *MRI) const override; 452 453 454 /// Return true if get the base operand, byte offset of an instruction and 455 /// the memory width. Width is the size of memory that is being 456 /// loaded/stored (e.g. 1, 2, 4, 8). 457 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, 458 const MachineOperand *&BaseOp, 459 int64_t &Offset, unsigned &Width, 460 const TargetRegisterInfo *TRI) const; 461 462 /// Return true if two MIs access different memory addresses and false 463 /// otherwise 464 bool 465 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 466 const MachineInstr &MIb) const override; 467 468 /// GetInstSize - Return the number of bytes of code the specified 469 /// instruction may be. This returns the maximum number of bytes. 470 /// 471 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 472 473 void getNoop(MCInst &NopInst) const override; 474 475 std::pair<unsigned, unsigned> 476 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 477 478 ArrayRef<std::pair<unsigned, const char *>> 479 getSerializableDirectMachineOperandTargetFlags() const override; 480 481 ArrayRef<std::pair<unsigned, const char *>> 482 getSerializableBitmaskMachineOperandTargetFlags() const override; 483 484 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction. 485 bool expandVSXMemPseudo(MachineInstr &MI) const; 486 487 // Lower pseudo instructions after register allocation. 488 bool expandPostRAPseudo(MachineInstr &MI) const override; 489 490 static bool isVFRegister(unsigned Reg) { 491 return Reg >= PPC::VF0 && Reg <= PPC::VF31; 492 } 493 static bool isVRRegister(unsigned Reg) { 494 return Reg >= PPC::V0 && Reg <= PPC::V31; 495 } 496 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const; 497 static int getRecordFormOpcode(unsigned Opcode); 498 499 bool isTOCSaveMI(const MachineInstr &MI) const; 500 501 bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, 502 const unsigned PhiDepth) const; 503 504 /// Return true if the output of the instruction is always a sign-extended, 505 /// i.e. 0 to 31-th bits are same as 32-th bit. 506 bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const { 507 return isSignOrZeroExtended(MI, true, depth); 508 } 509 510 /// Return true if the output of the instruction is always zero-extended, 511 /// i.e. 0 to 31-th bits are all zeros 512 bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const { 513 return isSignOrZeroExtended(MI, false, depth); 514 } 515 516 bool convertToImmediateForm(MachineInstr &MI, 517 MachineInstr **KilledDef = nullptr) const; 518 bool foldFrameOffset(MachineInstr &MI) const; 519 bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const; 520 bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const; 521 bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, 522 unsigned &XFormOpcode, 523 int64_t &OffsetOfImmInstr, 524 ImmInstrInfo &III) const; 525 bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, 526 MachineInstr *&ADDIMI, int64_t &OffsetAddi, 527 int64_t OffsetImm) const; 528 529 /// Fixup killed/dead flag for register \p RegNo between instructions [\p 530 /// StartMI, \p EndMI]. Some PostRA transformations may violate register 531 /// killed/dead flags semantics, this function can be called to fix up. Before 532 /// calling this function, 533 /// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI. 534 /// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI) 535 /// and possible definition for \p RegNo is \p StartMI or \p EndMI. 536 /// 3. Ensure that all instructions between [\p StartMI, \p EndMI] are in same 537 /// basic block. 538 void fixupIsDeadOrKill(MachineInstr &StartMI, MachineInstr &EndMI, 539 unsigned RegNo) const; 540 void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const; 541 void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, 542 int64_t Imm) const; 543 544 bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, 545 bool PostRA) const; 546 547 // In PostRA phase, try to find instruction defines \p Reg before \p MI. 548 // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist. 549 MachineInstr *getDefMIPostRA(unsigned Reg, MachineInstr &MI, 550 bool &SeenIntermediateUse) const; 551 552 /// getRegNumForOperand - some operands use different numbering schemes 553 /// for the same registers. For example, a VSX instruction may have any of 554 /// vs0-vs63 allocated whereas an Altivec instruction could only have 555 /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual 556 /// register number needed for the opcode/operand number combination. 557 /// The operand number argument will be useful when we need to extend this 558 /// to instructions that use both Altivec and VSX numbering (for different 559 /// operands). 560 static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, 561 unsigned OpNo) { 562 int16_t regClass = Desc.OpInfo[OpNo].RegClass; 563 switch (regClass) { 564 // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31, 565 // VSX32-VSX63 during encoding/disassembling 566 case PPC::VSSRCRegClassID: 567 case PPC::VSFRCRegClassID: 568 if (isVFRegister(Reg)) 569 return PPC::VSX32 + (Reg - PPC::VF0); 570 break; 571 // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31, 572 // VSX32-VSX63 during encoding/disassembling 573 case PPC::VSRCRegClassID: 574 if (isVRRegister(Reg)) 575 return PPC::VSX32 + (Reg - PPC::V0); 576 break; 577 // Other RegClass doesn't need mapping 578 default: 579 break; 580 } 581 return Reg; 582 } 583 584 /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero). 585 bool isBDNZ(unsigned Opcode) const; 586 587 /// Find the hardware loop instruction used to set-up the specified loop. 588 /// On PPC, we have two instructions used to set-up the hardware loop 589 /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8) 590 /// instructions to indicate the end of a loop. 591 MachineInstr * 592 findLoopInstr(MachineBasicBlock &PreHeader, 593 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const; 594 595 /// Analyze loop L, which must be a single-basic-block loop, and if the 596 /// conditions can be understood enough produce a PipelinerLoopInfo object. 597 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo> 598 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override; 599 }; 600 601 } 602 603 #endif 604