1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the PowerPC implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 14 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 15 16 #include "PPCRegisterInfo.h" 17 #include "llvm/CodeGen/TargetInstrInfo.h" 18 19 #define GET_INSTRINFO_HEADER 20 #include "PPCGenInstrInfo.inc" 21 22 namespace llvm { 23 24 /// PPCII - This namespace holds all of the PowerPC target-specific 25 /// per-instruction flags. These must match the corresponding definitions in 26 /// PPC.td and PPCInstrFormats.td. 27 namespace PPCII { 28 enum { 29 // PPC970 Instruction Flags. These flags describe the characteristics of the 30 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 31 // raw machine instructions. 32 33 /// PPC970_First - This instruction starts a new dispatch group, so it will 34 /// always be the first one in the group. 35 PPC970_First = 0x1, 36 37 /// PPC970_Single - This instruction starts a new dispatch group and 38 /// terminates it, so it will be the sole instruction in the group. 39 PPC970_Single = 0x2, 40 41 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 42 /// two dispatch pipes to be available to issue. 43 PPC970_Cracked = 0x4, 44 45 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 46 /// an instruction is issued to. 47 PPC970_Shift = 3, 48 PPC970_Mask = 0x07 << PPC970_Shift 49 }; 50 enum PPC970_Unit { 51 /// These are the various PPC970 execution unit pipelines. Each instruction 52 /// is one of these. 53 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 54 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 55 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 56 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 57 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 58 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 59 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 60 PPC970_BRU = 7 << PPC970_Shift // Branch Unit 61 }; 62 63 enum { 64 /// Shift count to bypass PPC970 flags 65 NewDef_Shift = 6, 66 67 /// This instruction is an X-Form memory operation. 68 XFormMemOp = 0x1 << NewDef_Shift, 69 /// This instruction is prefixed. 70 Prefixed = 0x1 << (NewDef_Shift+1) 71 }; 72 } // end namespace PPCII 73 74 // Instructions that have an immediate form might be convertible to that 75 // form if the correct input is a result of a load immediate. In order to 76 // know whether the transformation is special, we might need to know some 77 // of the details of the two forms. 78 struct ImmInstrInfo { 79 // Is the immediate field in the immediate form signed or unsigned? 80 uint64_t SignedImm : 1; 81 // Does the immediate need to be a multiple of some value? 82 uint64_t ImmMustBeMultipleOf : 5; 83 // Is R0/X0 treated specially by the original r+r instruction? 84 // If so, in which operand? 85 uint64_t ZeroIsSpecialOrig : 3; 86 // Is R0/X0 treated specially by the new r+i instruction? 87 // If so, in which operand? 88 uint64_t ZeroIsSpecialNew : 3; 89 // Is the operation commutative? 90 uint64_t IsCommutative : 1; 91 // The operand number to check for add-immediate def. 92 uint64_t OpNoForForwarding : 3; 93 // The operand number for the immediate. 94 uint64_t ImmOpNo : 3; 95 // The opcode of the new instruction. 96 uint64_t ImmOpcode : 16; 97 // The size of the immediate. 98 uint64_t ImmWidth : 5; 99 // The immediate should be truncated to N bits. 100 uint64_t TruncateImmTo : 5; 101 // Is the instruction summing the operand 102 uint64_t IsSummingOperands : 1; 103 }; 104 105 // Information required to convert an instruction to just a materialized 106 // immediate. 107 struct LoadImmediateInfo { 108 unsigned Imm : 16; 109 unsigned Is64Bit : 1; 110 unsigned SetCR : 1; 111 }; 112 113 // Index into the OpcodesForSpill array. 114 enum SpillOpcodeKey { 115 SOK_Int4Spill, 116 SOK_Int8Spill, 117 SOK_Float8Spill, 118 SOK_Float4Spill, 119 SOK_CRSpill, 120 SOK_CRBitSpill, 121 SOK_VRVectorSpill, 122 SOK_VSXVectorSpill, 123 SOK_VectorFloat8Spill, 124 SOK_VectorFloat4Spill, 125 SOK_VRSaveSpill, 126 SOK_SpillToVSR, 127 SOK_SPESpill, 128 SOK_LastOpcodeSpill // This must be last on the enum. 129 }; 130 131 // Define list of load and store spill opcodes. 132 #define Pwr8LoadOpcodes \ 133 { \ 134 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 135 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \ 136 PPC::RESTORE_VRSAVE, PPC::SPILLTOVSR_LD, PPC::EVLDD \ 137 } 138 139 #define Pwr9LoadOpcodes \ 140 { \ 141 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 142 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \ 143 PPC::DFLOADf32, PPC::RESTORE_VRSAVE, PPC::SPILLTOVSR_LD \ 144 } 145 146 #define Pwr8StoreOpcodes \ 147 { \ 148 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 149 PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, PPC::SPILL_VRSAVE, \ 150 PPC::SPILLTOVSR_ST, PPC::EVSTDD \ 151 } 152 153 #define Pwr9StoreOpcodes \ 154 { \ 155 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 156 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \ 157 PPC::SPILL_VRSAVE, PPC::SPILLTOVSR_ST \ 158 } 159 160 // Initialize arrays for load and store spill opcodes on supported subtargets. 161 #define StoreOpcodesForSpill \ 162 { Pwr8StoreOpcodes, Pwr9StoreOpcodes } 163 #define LoadOpcodesForSpill \ 164 { Pwr8LoadOpcodes, Pwr9LoadOpcodes } 165 166 class PPCSubtarget; 167 class PPCInstrInfo : public PPCGenInstrInfo { 168 PPCSubtarget &Subtarget; 169 const PPCRegisterInfo RI; 170 const unsigned StoreSpillOpcodesArray[2][SOK_LastOpcodeSpill] = 171 StoreOpcodesForSpill; 172 const unsigned LoadSpillOpcodesArray[2][SOK_LastOpcodeSpill] = 173 LoadOpcodesForSpill; 174 175 void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, 176 int FrameIdx, const TargetRegisterClass *RC, 177 SmallVectorImpl<MachineInstr *> &NewMIs) const; 178 void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, 179 unsigned DestReg, int FrameIdx, 180 const TargetRegisterClass *RC, 181 SmallVectorImpl<MachineInstr *> &NewMIs) const; 182 183 // Replace the instruction with single LI if possible. \p DefMI must be LI or 184 // LI8. 185 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI, 186 unsigned OpNoForForwarding, MachineInstr **KilledDef) const; 187 // If the inst is imm-form and its register operand is produced by a ADDI, put 188 // the imm into the inst directly and remove the ADDI if possible. 189 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI, 190 unsigned OpNoForForwarding) const; 191 // If the inst is x-form and has imm-form and one of its operand is produced 192 // by a LI, put the imm into the inst directly and remove the LI if possible. 193 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III, 194 unsigned ConstantOpNo, 195 MachineInstr &DefMI) const; 196 // If the inst is x-form and has imm-form and one of its operand is produced 197 // by an add-immediate, try to transform it when possible. 198 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III, 199 unsigned ConstantOpNo, MachineInstr &DefMI, 200 bool KillDefMI) const; 201 // Try to find that, if the instruction 'MI' contains any operand that 202 // could be forwarded from some inst that feeds it. If yes, return the 203 // Def of that operand. And OpNoForForwarding is the operand index in 204 // the 'MI' for that 'Def'. If we see another use of this Def between 205 // the Def and the MI, SeenIntermediateUse becomes 'true'. 206 MachineInstr *getForwardingDefMI(MachineInstr &MI, 207 unsigned &OpNoForForwarding, 208 bool &SeenIntermediateUse) const; 209 210 // Can the user MI have it's source at index \p OpNoForForwarding 211 // forwarded from an add-immediate that feeds it? 212 bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III, 213 unsigned OpNoForForwarding) const; 214 bool isDefMIElgibleForForwarding(MachineInstr &DefMI, 215 const ImmInstrInfo &III, 216 MachineOperand *&ImmMO, 217 MachineOperand *&RegMO) const; 218 bool isImmElgibleForForwarding(const MachineOperand &ImmMO, 219 const MachineInstr &DefMI, 220 const ImmInstrInfo &III, 221 int64_t &Imm, 222 int64_t BaseImm = 0) const; 223 bool isRegElgibleForForwarding(const MachineOperand &RegMO, 224 const MachineInstr &DefMI, 225 const MachineInstr &MI, bool KillDefMI, 226 bool &IsFwdFeederRegKilled) const; 227 unsigned getSpillTarget() const; 228 const unsigned *getStoreOpcodesForSpillArray() const; 229 const unsigned *getLoadOpcodesForSpillArray() const; 230 int16_t getFMAOpIdxInfo(unsigned Opcode) const; 231 void reassociateFMA(MachineInstr &Root, MachineCombinerPattern Pattern, 232 SmallVectorImpl<MachineInstr *> &InsInstrs, 233 SmallVectorImpl<MachineInstr *> &DelInstrs, 234 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const; 235 virtual void anchor(); 236 237 protected: 238 /// Commutes the operands in the given instruction. 239 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2. 240 /// 241 /// Do not call this method for a non-commutable instruction or for 242 /// non-commutable pair of operand indices OpIdx1 and OpIdx2. 243 /// Even though the instruction is commutable, the method may still 244 /// fail to commute the operands, null pointer is returned in such cases. 245 /// 246 /// For example, we can commute rlwimi instructions, but only if the 247 /// rotate amt is zero. We also have to munge the immediates a bit. 248 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 249 unsigned OpIdx1, 250 unsigned OpIdx2) const override; 251 252 public: 253 explicit PPCInstrInfo(PPCSubtarget &STI); 254 255 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 256 /// such, whenever a client has an instance of instruction info, it should 257 /// always be able to get register info as well (through this method). 258 /// 259 const PPCRegisterInfo &getRegisterInfo() const { return RI; } 260 261 bool isXFormMemOp(unsigned Opcode) const { 262 return get(Opcode).TSFlags & PPCII::XFormMemOp; 263 } 264 bool isPrefixed(unsigned Opcode) const { 265 return get(Opcode).TSFlags & PPCII::Prefixed; 266 } 267 268 static bool isSameClassPhysRegCopy(unsigned Opcode) { 269 unsigned CopyOpcodes[] = {PPC::OR, PPC::OR8, PPC::FMR, 270 PPC::VOR, PPC::XXLOR, PPC::XXLORf, 271 PPC::XSCPSGNDP, PPC::MCRF, PPC::CROR, 272 PPC::EVOR, -1U}; 273 for (int i = 0; CopyOpcodes[i] != -1U; i++) 274 if (Opcode == CopyOpcodes[i]) 275 return true; 276 return false; 277 } 278 279 ScheduleHazardRecognizer * 280 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 281 const ScheduleDAG *DAG) const override; 282 ScheduleHazardRecognizer * 283 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 284 const ScheduleDAG *DAG) const override; 285 286 unsigned getInstrLatency(const InstrItineraryData *ItinData, 287 const MachineInstr &MI, 288 unsigned *PredCost = nullptr) const override; 289 290 int getOperandLatency(const InstrItineraryData *ItinData, 291 const MachineInstr &DefMI, unsigned DefIdx, 292 const MachineInstr &UseMI, 293 unsigned UseIdx) const override; 294 int getOperandLatency(const InstrItineraryData *ItinData, 295 SDNode *DefNode, unsigned DefIdx, 296 SDNode *UseNode, unsigned UseIdx) const override { 297 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, 298 UseNode, UseIdx); 299 } 300 301 bool hasLowDefLatency(const TargetSchedModel &SchedModel, 302 const MachineInstr &DefMI, 303 unsigned DefIdx) const override { 304 // Machine LICM should hoist all instructions in low-register-pressure 305 // situations; none are sufficiently free to justify leaving in a loop 306 // body. 307 return false; 308 } 309 310 bool useMachineCombiner() const override { 311 return true; 312 } 313 314 /// When getMachineCombinerPatterns() finds patterns, this function generates 315 /// the instructions that could replace the original code sequence 316 void genAlternativeCodeSequence( 317 MachineInstr &Root, MachineCombinerPattern Pattern, 318 SmallVectorImpl<MachineInstr *> &InsInstrs, 319 SmallVectorImpl<MachineInstr *> &DelInstrs, 320 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override; 321 322 /// Return true when there is potentially a faster code sequence for a fma 323 /// chain ending in \p Root. All potential patterns are output in the \p 324 /// P array. 325 bool getFMAPatterns(MachineInstr &Root, 326 SmallVectorImpl<MachineCombinerPattern> &P) const; 327 328 /// Return true when there is potentially a faster code sequence 329 /// for an instruction chain ending in <Root>. All potential patterns are 330 /// output in the <Pattern> array. 331 bool getMachineCombinerPatterns( 332 MachineInstr &Root, 333 SmallVectorImpl<MachineCombinerPattern> &P) const override; 334 335 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override; 336 337 /// On PowerPC, we try to reassociate FMA chain which will increase 338 /// instruction size. Set extension resource length limit to 1 for edge case. 339 /// Resource Length is calculated by scaled resource usage in getCycles(). 340 /// Because of the division in getCycles(), it returns different cycles due to 341 /// legacy scaled resource usage. So new resource length may be same with 342 /// legacy or 1 bigger than legacy. 343 /// We need to execlude the 1 bigger case even the resource length is not 344 /// perserved for more FMA chain reassociations on PowerPC. 345 int getExtendResourceLenLimit() const override { return 1; } 346 347 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, 348 MachineInstr &NewMI1, 349 MachineInstr &NewMI2) const override; 350 351 void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const override; 352 353 bool isCoalescableExtInstr(const MachineInstr &MI, 354 Register &SrcReg, Register &DstReg, 355 unsigned &SubIdx) const override; 356 unsigned isLoadFromStackSlot(const MachineInstr &MI, 357 int &FrameIndex) const override; 358 bool isReallyTriviallyReMaterializable(const MachineInstr &MI, 359 AAResults *AA) const override; 360 unsigned isStoreToStackSlot(const MachineInstr &MI, 361 int &FrameIndex) const override; 362 363 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 364 unsigned &SrcOpIdx2) const override; 365 366 void insertNoop(MachineBasicBlock &MBB, 367 MachineBasicBlock::iterator MI) const override; 368 369 370 // Branch analysis. 371 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 372 MachineBasicBlock *&FBB, 373 SmallVectorImpl<MachineOperand> &Cond, 374 bool AllowModify) const override; 375 unsigned removeBranch(MachineBasicBlock &MBB, 376 int *BytesRemoved = nullptr) const override; 377 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 378 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 379 const DebugLoc &DL, 380 int *BytesAdded = nullptr) const override; 381 382 // Select analysis. 383 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 384 Register, Register, Register, int &, int &, 385 int &) const override; 386 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 387 const DebugLoc &DL, Register DstReg, 388 ArrayRef<MachineOperand> Cond, Register TrueReg, 389 Register FalseReg) const override; 390 391 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 392 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 393 bool KillSrc) const override; 394 395 void storeRegToStackSlot(MachineBasicBlock &MBB, 396 MachineBasicBlock::iterator MBBI, 397 Register SrcReg, bool isKill, int FrameIndex, 398 const TargetRegisterClass *RC, 399 const TargetRegisterInfo *TRI) const override; 400 401 // Emits a register spill without updating the register class for vector 402 // registers. This ensures that when we spill a vector register the 403 // element order in the register is the same as it was in memory. 404 void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, 405 MachineBasicBlock::iterator MBBI, 406 unsigned SrcReg, bool isKill, int FrameIndex, 407 const TargetRegisterClass *RC, 408 const TargetRegisterInfo *TRI) const; 409 410 void loadRegFromStackSlot(MachineBasicBlock &MBB, 411 MachineBasicBlock::iterator MBBI, 412 Register DestReg, int FrameIndex, 413 const TargetRegisterClass *RC, 414 const TargetRegisterInfo *TRI) const override; 415 416 // Emits a register reload without updating the register class for vector 417 // registers. This ensures that when we reload a vector register the 418 // element order in the register is the same as it was in memory. 419 void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, 420 MachineBasicBlock::iterator MBBI, 421 unsigned DestReg, int FrameIndex, 422 const TargetRegisterClass *RC, 423 const TargetRegisterInfo *TRI) const; 424 425 unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const; 426 427 unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const; 428 429 bool 430 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 431 432 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, 433 MachineRegisterInfo *MRI) const override; 434 435 bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, 436 Register Reg) const; 437 438 // If conversion by predication (only supported by some branch instructions). 439 // All of the profitability checks always return true; it is always 440 // profitable to use the predicated branches. 441 bool isProfitableToIfCvt(MachineBasicBlock &MBB, 442 unsigned NumCycles, unsigned ExtraPredCycles, 443 BranchProbability Probability) const override { 444 return true; 445 } 446 447 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 448 unsigned NumT, unsigned ExtraT, 449 MachineBasicBlock &FMBB, 450 unsigned NumF, unsigned ExtraF, 451 BranchProbability Probability) const override; 452 453 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 454 BranchProbability Probability) const override { 455 return true; 456 } 457 458 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 459 MachineBasicBlock &FMBB) const override { 460 return false; 461 } 462 463 // Predication support. 464 bool isPredicated(const MachineInstr &MI) const override; 465 466 bool isSchedulingBoundary(const MachineInstr &MI, 467 const MachineBasicBlock *MBB, 468 const MachineFunction &MF) const override; 469 470 bool PredicateInstruction(MachineInstr &MI, 471 ArrayRef<MachineOperand> Pred) const override; 472 473 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 474 ArrayRef<MachineOperand> Pred2) const override; 475 476 bool DefinesPredicate(MachineInstr &MI, 477 std::vector<MachineOperand> &Pred) const override; 478 479 // Comparison optimization. 480 481 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 482 Register &SrcReg2, int &Mask, int &Value) const override; 483 484 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 485 Register SrcReg2, int Mask, int Value, 486 const MachineRegisterInfo *MRI) const override; 487 488 489 /// Return true if get the base operand, byte offset of an instruction and 490 /// the memory width. Width is the size of memory that is being 491 /// loaded/stored (e.g. 1, 2, 4, 8). 492 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, 493 const MachineOperand *&BaseOp, 494 int64_t &Offset, unsigned &Width, 495 const TargetRegisterInfo *TRI) const; 496 497 /// Return true if two MIs access different memory addresses and false 498 /// otherwise 499 bool 500 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 501 const MachineInstr &MIb) const override; 502 503 /// GetInstSize - Return the number of bytes of code the specified 504 /// instruction may be. This returns the maximum number of bytes. 505 /// 506 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 507 508 void getNoop(MCInst &NopInst) const override; 509 510 std::pair<unsigned, unsigned> 511 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 512 513 ArrayRef<std::pair<unsigned, const char *>> 514 getSerializableDirectMachineOperandTargetFlags() const override; 515 516 ArrayRef<std::pair<unsigned, const char *>> 517 getSerializableBitmaskMachineOperandTargetFlags() const override; 518 519 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction. 520 bool expandVSXMemPseudo(MachineInstr &MI) const; 521 522 // Lower pseudo instructions after register allocation. 523 bool expandPostRAPseudo(MachineInstr &MI) const override; 524 525 static bool isVFRegister(unsigned Reg) { 526 return Reg >= PPC::VF0 && Reg <= PPC::VF31; 527 } 528 static bool isVRRegister(unsigned Reg) { 529 return Reg >= PPC::V0 && Reg <= PPC::V31; 530 } 531 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const; 532 static int getRecordFormOpcode(unsigned Opcode); 533 534 bool isTOCSaveMI(const MachineInstr &MI) const; 535 536 bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, 537 const unsigned PhiDepth) const; 538 539 /// Return true if the output of the instruction is always a sign-extended, 540 /// i.e. 0 to 31-th bits are same as 32-th bit. 541 bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const { 542 return isSignOrZeroExtended(MI, true, depth); 543 } 544 545 /// Return true if the output of the instruction is always zero-extended, 546 /// i.e. 0 to 31-th bits are all zeros 547 bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const { 548 return isSignOrZeroExtended(MI, false, depth); 549 } 550 551 bool convertToImmediateForm(MachineInstr &MI, 552 MachineInstr **KilledDef = nullptr) const; 553 bool foldFrameOffset(MachineInstr &MI) const; 554 bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const; 555 bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const; 556 bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, 557 unsigned &XFormOpcode, 558 int64_t &OffsetOfImmInstr, 559 ImmInstrInfo &III) const; 560 bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, 561 MachineInstr *&ADDIMI, int64_t &OffsetAddi, 562 int64_t OffsetImm) const; 563 564 /// Fixup killed/dead flag for register \p RegNo between instructions [\p 565 /// StartMI, \p EndMI]. Some pre-RA or post-RA transformations may violate 566 /// register killed/dead flags semantics, this function can be called to fix 567 /// up. Before calling this function, 568 /// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI. 569 /// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI) 570 /// and possible definition for \p RegNo is \p StartMI or \p EndMI. For 571 /// pre-RA cases, definition may be \p StartMI through COPY, \p StartMI 572 /// will be adjust to true definition. 573 /// 3. We can do accurate fixup for the case when all instructions between 574 /// [\p StartMI, \p EndMI] are in same basic block. 575 /// 4. For the case when \p StartMI and \p EndMI are not in same basic block, 576 /// we conservatively clear kill flag for all uses of \p RegNo for pre-RA 577 /// and for post-RA, we give an assertion as without reaching definition 578 /// analysis post-RA, \p StartMI and \p EndMI are hard to keep right. 579 void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI, 580 unsigned RegNo) const; 581 void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const; 582 void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, 583 int64_t Imm) const; 584 585 bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, 586 bool PostRA) const; 587 588 // In PostRA phase, try to find instruction defines \p Reg before \p MI. 589 // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist. 590 MachineInstr *getDefMIPostRA(unsigned Reg, MachineInstr &MI, 591 bool &SeenIntermediateUse) const; 592 593 /// getRegNumForOperand - some operands use different numbering schemes 594 /// for the same registers. For example, a VSX instruction may have any of 595 /// vs0-vs63 allocated whereas an Altivec instruction could only have 596 /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual 597 /// register number needed for the opcode/operand number combination. 598 /// The operand number argument will be useful when we need to extend this 599 /// to instructions that use both Altivec and VSX numbering (for different 600 /// operands). 601 static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, 602 unsigned OpNo) { 603 int16_t regClass = Desc.OpInfo[OpNo].RegClass; 604 switch (regClass) { 605 // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31, 606 // VSX32-VSX63 during encoding/disassembling 607 case PPC::VSSRCRegClassID: 608 case PPC::VSFRCRegClassID: 609 if (isVFRegister(Reg)) 610 return PPC::VSX32 + (Reg - PPC::VF0); 611 break; 612 // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31, 613 // VSX32-VSX63 during encoding/disassembling 614 case PPC::VSRCRegClassID: 615 if (isVRRegister(Reg)) 616 return PPC::VSX32 + (Reg - PPC::V0); 617 break; 618 // Other RegClass doesn't need mapping 619 default: 620 break; 621 } 622 return Reg; 623 } 624 625 /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero). 626 bool isBDNZ(unsigned Opcode) const; 627 628 /// Find the hardware loop instruction used to set-up the specified loop. 629 /// On PPC, we have two instructions used to set-up the hardware loop 630 /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8) 631 /// instructions to indicate the end of a loop. 632 MachineInstr * 633 findLoopInstr(MachineBasicBlock &PreHeader, 634 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const; 635 636 /// Analyze loop L, which must be a single-basic-block loop, and if the 637 /// conditions can be understood enough produce a PipelinerLoopInfo object. 638 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo> 639 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override; 640 }; 641 642 } 643 644 #endif 645