1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the PowerPC implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 14 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 15 16 #include "PPCRegisterInfo.h" 17 #include "llvm/CodeGen/TargetInstrInfo.h" 18 19 #define GET_INSTRINFO_HEADER 20 #include "PPCGenInstrInfo.inc" 21 22 namespace llvm { 23 24 /// PPCII - This namespace holds all of the PowerPC target-specific 25 /// per-instruction flags. These must match the corresponding definitions in 26 /// PPC.td and PPCInstrFormats.td. 27 namespace PPCII { 28 enum { 29 // PPC970 Instruction Flags. These flags describe the characteristics of the 30 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 31 // raw machine instructions. 32 33 /// PPC970_First - This instruction starts a new dispatch group, so it will 34 /// always be the first one in the group. 35 PPC970_First = 0x1, 36 37 /// PPC970_Single - This instruction starts a new dispatch group and 38 /// terminates it, so it will be the sole instruction in the group. 39 PPC970_Single = 0x2, 40 41 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 42 /// two dispatch pipes to be available to issue. 43 PPC970_Cracked = 0x4, 44 45 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 46 /// an instruction is issued to. 47 PPC970_Shift = 3, 48 PPC970_Mask = 0x07 << PPC970_Shift 49 }; 50 enum PPC970_Unit { 51 /// These are the various PPC970 execution unit pipelines. Each instruction 52 /// is one of these. 53 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 54 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 55 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 56 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 57 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 58 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 59 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 60 PPC970_BRU = 7 << PPC970_Shift // Branch Unit 61 }; 62 63 enum { 64 /// Shift count to bypass PPC970 flags 65 NewDef_Shift = 6, 66 67 /// This instruction is an X-Form memory operation. 68 XFormMemOp = 0x1 << NewDef_Shift, 69 /// This instruction is prefixed. 70 Prefixed = 0x1 << (NewDef_Shift+1) 71 }; 72 } // end namespace PPCII 73 74 // Instructions that have an immediate form might be convertible to that 75 // form if the correct input is a result of a load immediate. In order to 76 // know whether the transformation is special, we might need to know some 77 // of the details of the two forms. 78 struct ImmInstrInfo { 79 // Is the immediate field in the immediate form signed or unsigned? 80 uint64_t SignedImm : 1; 81 // Does the immediate need to be a multiple of some value? 82 uint64_t ImmMustBeMultipleOf : 5; 83 // Is R0/X0 treated specially by the original r+r instruction? 84 // If so, in which operand? 85 uint64_t ZeroIsSpecialOrig : 3; 86 // Is R0/X0 treated specially by the new r+i instruction? 87 // If so, in which operand? 88 uint64_t ZeroIsSpecialNew : 3; 89 // Is the operation commutative? 90 uint64_t IsCommutative : 1; 91 // The operand number to check for add-immediate def. 92 uint64_t OpNoForForwarding : 3; 93 // The operand number for the immediate. 94 uint64_t ImmOpNo : 3; 95 // The opcode of the new instruction. 96 uint64_t ImmOpcode : 16; 97 // The size of the immediate. 98 uint64_t ImmWidth : 5; 99 // The immediate should be truncated to N bits. 100 uint64_t TruncateImmTo : 5; 101 // Is the instruction summing the operand 102 uint64_t IsSummingOperands : 1; 103 }; 104 105 // Information required to convert an instruction to just a materialized 106 // immediate. 107 struct LoadImmediateInfo { 108 unsigned Imm : 16; 109 unsigned Is64Bit : 1; 110 unsigned SetCR : 1; 111 }; 112 113 class PPCSubtarget; 114 class PPCInstrInfo : public PPCGenInstrInfo { 115 PPCSubtarget &Subtarget; 116 const PPCRegisterInfo RI; 117 118 void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, 119 int FrameIdx, const TargetRegisterClass *RC, 120 SmallVectorImpl<MachineInstr *> &NewMIs) const; 121 void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, 122 unsigned DestReg, int FrameIdx, 123 const TargetRegisterClass *RC, 124 SmallVectorImpl<MachineInstr *> &NewMIs) const; 125 126 // If the inst has imm-form and one of its operand is produced by a LI, 127 // put the imm into the inst directly and remove the LI if possible. 128 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III, 129 unsigned ConstantOpNo, MachineInstr &DefMI, 130 int64_t Imm) const; 131 // If the inst has imm-form and one of its operand is produced by an 132 // add-immediate, try to transform it when possible. 133 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III, 134 unsigned ConstantOpNo, MachineInstr &DefMI, 135 bool KillDefMI) const; 136 // Try to find that, if the instruction 'MI' contains any operand that 137 // could be forwarded from some inst that feeds it. If yes, return the 138 // Def of that operand. And OpNoForForwarding is the operand index in 139 // the 'MI' for that 'Def'. If we see another use of this Def between 140 // the Def and the MI, SeenIntermediateUse becomes 'true'. 141 MachineInstr *getForwardingDefMI(MachineInstr &MI, 142 unsigned &OpNoForForwarding, 143 bool &SeenIntermediateUse) const; 144 145 // Can the user MI have it's source at index \p OpNoForForwarding 146 // forwarded from an add-immediate that feeds it? 147 bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III, 148 unsigned OpNoForForwarding) const; 149 bool isDefMIElgibleForForwarding(MachineInstr &DefMI, 150 const ImmInstrInfo &III, 151 MachineOperand *&ImmMO, 152 MachineOperand *&RegMO) const; 153 bool isImmElgibleForForwarding(const MachineOperand &ImmMO, 154 const MachineInstr &DefMI, 155 const ImmInstrInfo &III, 156 int64_t &Imm) const; 157 bool isRegElgibleForForwarding(const MachineOperand &RegMO, 158 const MachineInstr &DefMI, 159 const MachineInstr &MI, bool KillDefMI, 160 bool &IsFwdFeederRegKilled) const; 161 const unsigned *getStoreOpcodesForSpillArray() const; 162 const unsigned *getLoadOpcodesForSpillArray() const; 163 virtual void anchor(); 164 165 protected: 166 /// Commutes the operands in the given instruction. 167 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2. 168 /// 169 /// Do not call this method for a non-commutable instruction or for 170 /// non-commutable pair of operand indices OpIdx1 and OpIdx2. 171 /// Even though the instruction is commutable, the method may still 172 /// fail to commute the operands, null pointer is returned in such cases. 173 /// 174 /// For example, we can commute rlwimi instructions, but only if the 175 /// rotate amt is zero. We also have to munge the immediates a bit. 176 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 177 unsigned OpIdx1, 178 unsigned OpIdx2) const override; 179 180 public: 181 explicit PPCInstrInfo(PPCSubtarget &STI); 182 183 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 184 /// such, whenever a client has an instance of instruction info, it should 185 /// always be able to get register info as well (through this method). 186 /// 187 const PPCRegisterInfo &getRegisterInfo() const { return RI; } 188 189 bool isXFormMemOp(unsigned Opcode) const { 190 return get(Opcode).TSFlags & PPCII::XFormMemOp; 191 } 192 bool isPrefixed(unsigned Opcode) const { 193 return get(Opcode).TSFlags & PPCII::Prefixed; 194 } 195 196 static bool isSameClassPhysRegCopy(unsigned Opcode) { 197 unsigned CopyOpcodes[] = 198 { PPC::OR, PPC::OR8, PPC::FMR, PPC::VOR, PPC::XXLOR, PPC::XXLORf, 199 PPC::XSCPSGNDP, PPC::MCRF, PPC::QVFMR, PPC::QVFMRs, PPC::QVFMRb, 200 PPC::CROR, PPC::EVOR, -1U }; 201 for (int i = 0; CopyOpcodes[i] != -1U; i++) 202 if (Opcode == CopyOpcodes[i]) 203 return true; 204 return false; 205 } 206 207 ScheduleHazardRecognizer * 208 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 209 const ScheduleDAG *DAG) const override; 210 ScheduleHazardRecognizer * 211 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 212 const ScheduleDAG *DAG) const override; 213 214 unsigned getInstrLatency(const InstrItineraryData *ItinData, 215 const MachineInstr &MI, 216 unsigned *PredCost = nullptr) const override; 217 218 int getOperandLatency(const InstrItineraryData *ItinData, 219 const MachineInstr &DefMI, unsigned DefIdx, 220 const MachineInstr &UseMI, 221 unsigned UseIdx) const override; 222 int getOperandLatency(const InstrItineraryData *ItinData, 223 SDNode *DefNode, unsigned DefIdx, 224 SDNode *UseNode, unsigned UseIdx) const override { 225 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, 226 UseNode, UseIdx); 227 } 228 229 bool hasLowDefLatency(const TargetSchedModel &SchedModel, 230 const MachineInstr &DefMI, 231 unsigned DefIdx) const override { 232 // Machine LICM should hoist all instructions in low-register-pressure 233 // situations; none are sufficiently free to justify leaving in a loop 234 // body. 235 return false; 236 } 237 238 bool useMachineCombiner() const override { 239 return true; 240 } 241 242 /// Return true when there is potentially a faster code sequence 243 /// for an instruction chain ending in <Root>. All potential patterns are 244 /// output in the <Pattern> array. 245 bool getMachineCombinerPatterns( 246 MachineInstr &Root, 247 SmallVectorImpl<MachineCombinerPattern> &P) const override; 248 249 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override; 250 251 bool isCoalescableExtInstr(const MachineInstr &MI, 252 unsigned &SrcReg, unsigned &DstReg, 253 unsigned &SubIdx) const override; 254 unsigned isLoadFromStackSlot(const MachineInstr &MI, 255 int &FrameIndex) const override; 256 bool isReallyTriviallyReMaterializable(const MachineInstr &MI, 257 AAResults *AA) const override; 258 unsigned isStoreToStackSlot(const MachineInstr &MI, 259 int &FrameIndex) const override; 260 261 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 262 unsigned &SrcOpIdx2) const override; 263 264 void insertNoop(MachineBasicBlock &MBB, 265 MachineBasicBlock::iterator MI) const override; 266 267 268 // Branch analysis. 269 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 270 MachineBasicBlock *&FBB, 271 SmallVectorImpl<MachineOperand> &Cond, 272 bool AllowModify) const override; 273 unsigned removeBranch(MachineBasicBlock &MBB, 274 int *BytesRemoved = nullptr) const override; 275 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 276 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 277 const DebugLoc &DL, 278 int *BytesAdded = nullptr) const override; 279 280 // Select analysis. 281 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 282 unsigned, unsigned, unsigned, int &, int &, 283 int &) const override; 284 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 285 const DebugLoc &DL, unsigned DstReg, 286 ArrayRef<MachineOperand> Cond, unsigned TrueReg, 287 unsigned FalseReg) const override; 288 289 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 290 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 291 bool KillSrc) const override; 292 293 void storeRegToStackSlot(MachineBasicBlock &MBB, 294 MachineBasicBlock::iterator MBBI, 295 Register SrcReg, bool isKill, int FrameIndex, 296 const TargetRegisterClass *RC, 297 const TargetRegisterInfo *TRI) const override; 298 299 void loadRegFromStackSlot(MachineBasicBlock &MBB, 300 MachineBasicBlock::iterator MBBI, 301 Register DestReg, int FrameIndex, 302 const TargetRegisterClass *RC, 303 const TargetRegisterInfo *TRI) const override; 304 305 unsigned getStoreOpcodeForSpill(unsigned Reg, 306 const TargetRegisterClass *RC = nullptr) const; 307 308 unsigned getLoadOpcodeForSpill(unsigned Reg, 309 const TargetRegisterClass *RC = nullptr) const; 310 311 bool 312 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 313 314 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, 315 MachineRegisterInfo *MRI) const override; 316 317 // If conversion by predication (only supported by some branch instructions). 318 // All of the profitability checks always return true; it is always 319 // profitable to use the predicated branches. 320 bool isProfitableToIfCvt(MachineBasicBlock &MBB, 321 unsigned NumCycles, unsigned ExtraPredCycles, 322 BranchProbability Probability) const override { 323 return true; 324 } 325 326 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 327 unsigned NumT, unsigned ExtraT, 328 MachineBasicBlock &FMBB, 329 unsigned NumF, unsigned ExtraF, 330 BranchProbability Probability) const override; 331 332 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 333 BranchProbability Probability) const override { 334 return true; 335 } 336 337 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 338 MachineBasicBlock &FMBB) const override { 339 return false; 340 } 341 342 // Predication support. 343 bool isPredicated(const MachineInstr &MI) const override; 344 345 bool isUnpredicatedTerminator(const MachineInstr &MI) const override; 346 347 bool PredicateInstruction(MachineInstr &MI, 348 ArrayRef<MachineOperand> Pred) const override; 349 350 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 351 ArrayRef<MachineOperand> Pred2) const override; 352 353 bool DefinesPredicate(MachineInstr &MI, 354 std::vector<MachineOperand> &Pred) const override; 355 356 // Comparison optimization. 357 358 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, 359 unsigned &SrcReg2, int &Mask, int &Value) const override; 360 361 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, 362 unsigned SrcReg2, int Mask, int Value, 363 const MachineRegisterInfo *MRI) const override; 364 365 366 /// Return true if get the base operand, byte offset of an instruction and 367 /// the memory width. Width is the size of memory that is being 368 /// loaded/stored (e.g. 1, 2, 4, 8). 369 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, 370 const MachineOperand *&BaseOp, 371 int64_t &Offset, unsigned &Width, 372 const TargetRegisterInfo *TRI) const; 373 374 /// Return true if two MIs access different memory addresses and false 375 /// otherwise 376 bool 377 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 378 const MachineInstr &MIb) const override; 379 380 /// GetInstSize - Return the number of bytes of code the specified 381 /// instruction may be. This returns the maximum number of bytes. 382 /// 383 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 384 385 void getNoop(MCInst &NopInst) const override; 386 387 std::pair<unsigned, unsigned> 388 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 389 390 ArrayRef<std::pair<unsigned, const char *>> 391 getSerializableDirectMachineOperandTargetFlags() const override; 392 393 ArrayRef<std::pair<unsigned, const char *>> 394 getSerializableBitmaskMachineOperandTargetFlags() const override; 395 396 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction. 397 bool expandVSXMemPseudo(MachineInstr &MI) const; 398 399 // Lower pseudo instructions after register allocation. 400 bool expandPostRAPseudo(MachineInstr &MI) const override; 401 402 static bool isVFRegister(unsigned Reg) { 403 return Reg >= PPC::VF0 && Reg <= PPC::VF31; 404 } 405 static bool isVRRegister(unsigned Reg) { 406 return Reg >= PPC::V0 && Reg <= PPC::V31; 407 } 408 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const; 409 static int getRecordFormOpcode(unsigned Opcode); 410 411 bool isTOCSaveMI(const MachineInstr &MI) const; 412 413 bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, 414 const unsigned PhiDepth) const; 415 416 /// Return true if the output of the instruction is always a sign-extended, 417 /// i.e. 0 to 31-th bits are same as 32-th bit. 418 bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const { 419 return isSignOrZeroExtended(MI, true, depth); 420 } 421 422 /// Return true if the output of the instruction is always zero-extended, 423 /// i.e. 0 to 31-th bits are all zeros 424 bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const { 425 return isSignOrZeroExtended(MI, false, depth); 426 } 427 428 bool convertToImmediateForm(MachineInstr &MI, 429 MachineInstr **KilledDef = nullptr) const; 430 bool foldFrameOffset(MachineInstr &MI) const; 431 bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const; 432 bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const; 433 bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, 434 unsigned &XFormOpcode, 435 int64_t &OffsetOfImmInstr, 436 ImmInstrInfo &III) const; 437 bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, 438 MachineInstr *&ADDIMI, int64_t &OffsetAddi, 439 int64_t OffsetImm) const; 440 441 /// Fixup killed/dead flag for register \p RegNo between instructions [\p 442 /// StartMI, \p EndMI]. Some PostRA transformations may violate register 443 /// killed/dead flags semantics, this function can be called to fix up. Before 444 /// calling this function, 445 /// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI. 446 /// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI) 447 /// and possible definition for \p RegNo is \p StartMI or \p EndMI. 448 /// 3. Ensure that all instructions between [\p StartMI, \p EndMI] are in same 449 /// basic block. 450 void fixupIsDeadOrKill(MachineInstr &StartMI, MachineInstr &EndMI, 451 unsigned RegNo) const; 452 void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const; 453 void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, 454 int64_t Imm) const; 455 456 bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, 457 bool PostRA) const; 458 459 // In PostRA phase, try to find instruction defines \p Reg before \p MI. 460 // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist. 461 MachineInstr *getDefMIPostRA(unsigned Reg, MachineInstr &MI, 462 bool &SeenIntermediateUse) const; 463 464 /// getRegNumForOperand - some operands use different numbering schemes 465 /// for the same registers. For example, a VSX instruction may have any of 466 /// vs0-vs63 allocated whereas an Altivec instruction could only have 467 /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual 468 /// register number needed for the opcode/operand number combination. 469 /// The operand number argument will be useful when we need to extend this 470 /// to instructions that use both Altivec and VSX numbering (for different 471 /// operands). 472 static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, 473 unsigned OpNo) { 474 int16_t regClass = Desc.OpInfo[OpNo].RegClass; 475 switch (regClass) { 476 // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31, 477 // VSX32-VSX63 during encoding/disassembling 478 case PPC::VSSRCRegClassID: 479 case PPC::VSFRCRegClassID: 480 if (isVFRegister(Reg)) 481 return PPC::VSX32 + (Reg - PPC::VF0); 482 break; 483 // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31, 484 // VSX32-VSX63 during encoding/disassembling 485 case PPC::VSRCRegClassID: 486 if (isVRRegister(Reg)) 487 return PPC::VSX32 + (Reg - PPC::V0); 488 break; 489 // Other RegClass doesn't need mapping 490 default: 491 break; 492 } 493 return Reg; 494 } 495 496 /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero). 497 bool isBDNZ(unsigned Opcode) const; 498 499 /// Find the hardware loop instruction used to set-up the specified loop. 500 /// On PPC, we have two instructions used to set-up the hardware loop 501 /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8) 502 /// instructions to indicate the end of a loop. 503 MachineInstr * 504 findLoopInstr(MachineBasicBlock &PreHeader, 505 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const; 506 507 /// Analyze loop L, which must be a single-basic-block loop, and if the 508 /// conditions can be understood enough produce a PipelinerLoopInfo object. 509 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo> 510 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override; 511 }; 512 513 } 514 515 #endif 516