1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the PowerPC implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 14 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 15 16 #include "PPCRegisterInfo.h" 17 #include "llvm/CodeGen/TargetInstrInfo.h" 18 19 #define GET_INSTRINFO_HEADER 20 #include "PPCGenInstrInfo.inc" 21 22 namespace llvm { 23 24 /// PPCII - This namespace holds all of the PowerPC target-specific 25 /// per-instruction flags. These must match the corresponding definitions in 26 /// PPC.td and PPCInstrFormats.td. 27 namespace PPCII { 28 enum { 29 // PPC970 Instruction Flags. These flags describe the characteristics of the 30 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 31 // raw machine instructions. 32 33 /// PPC970_First - This instruction starts a new dispatch group, so it will 34 /// always be the first one in the group. 35 PPC970_First = 0x1, 36 37 /// PPC970_Single - This instruction starts a new dispatch group and 38 /// terminates it, so it will be the sole instruction in the group. 39 PPC970_Single = 0x2, 40 41 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 42 /// two dispatch pipes to be available to issue. 43 PPC970_Cracked = 0x4, 44 45 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 46 /// an instruction is issued to. 47 PPC970_Shift = 3, 48 PPC970_Mask = 0x07 << PPC970_Shift 49 }; 50 enum PPC970_Unit { 51 /// These are the various PPC970 execution unit pipelines. Each instruction 52 /// is one of these. 53 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 54 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 55 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 56 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 57 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 58 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 59 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 60 PPC970_BRU = 7 << PPC970_Shift // Branch Unit 61 }; 62 63 enum { 64 /// Shift count to bypass PPC970 flags 65 NewDef_Shift = 6, 66 67 /// This instruction is an X-Form memory operation. 68 XFormMemOp = 0x1 << NewDef_Shift, 69 /// This instruction is prefixed. 70 Prefixed = 0x1 << (NewDef_Shift+1) 71 }; 72 } // end namespace PPCII 73 74 // Instructions that have an immediate form might be convertible to that 75 // form if the correct input is a result of a load immediate. In order to 76 // know whether the transformation is special, we might need to know some 77 // of the details of the two forms. 78 struct ImmInstrInfo { 79 // Is the immediate field in the immediate form signed or unsigned? 80 uint64_t SignedImm : 1; 81 // Does the immediate need to be a multiple of some value? 82 uint64_t ImmMustBeMultipleOf : 5; 83 // Is R0/X0 treated specially by the original r+r instruction? 84 // If so, in which operand? 85 uint64_t ZeroIsSpecialOrig : 3; 86 // Is R0/X0 treated specially by the new r+i instruction? 87 // If so, in which operand? 88 uint64_t ZeroIsSpecialNew : 3; 89 // Is the operation commutative? 90 uint64_t IsCommutative : 1; 91 // The operand number to check for add-immediate def. 92 uint64_t OpNoForForwarding : 3; 93 // The operand number for the immediate. 94 uint64_t ImmOpNo : 3; 95 // The opcode of the new instruction. 96 uint64_t ImmOpcode : 16; 97 // The size of the immediate. 98 uint64_t ImmWidth : 5; 99 // The immediate should be truncated to N bits. 100 uint64_t TruncateImmTo : 5; 101 // Is the instruction summing the operand 102 uint64_t IsSummingOperands : 1; 103 }; 104 105 // Information required to convert an instruction to just a materialized 106 // immediate. 107 struct LoadImmediateInfo { 108 unsigned Imm : 16; 109 unsigned Is64Bit : 1; 110 unsigned SetCR : 1; 111 }; 112 113 // Index into the OpcodesForSpill array. 114 enum SpillOpcodeKey { 115 SOK_Int4Spill, 116 SOK_Int8Spill, 117 SOK_Float8Spill, 118 SOK_Float4Spill, 119 SOK_CRSpill, 120 SOK_CRBitSpill, 121 SOK_VRVectorSpill, 122 SOK_VSXVectorSpill, 123 SOK_VectorFloat8Spill, 124 SOK_VectorFloat4Spill, 125 SOK_VRSaveSpill, 126 SOK_QuadFloat8Spill, 127 SOK_QuadFloat4Spill, 128 SOK_QuadBitSpill, 129 SOK_SpillToVSR, 130 SOK_SPESpill, 131 SOK_LastOpcodeSpill // This must be last on the enum. 132 }; 133 134 // Define list of load and store spill opcodes. 135 #define Pwr8LoadOpcodes \ 136 { \ 137 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 138 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \ 139 PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb, \ 140 PPC::SPILLTOVSR_LD, PPC::EVLDD \ 141 } 142 143 #define Pwr9LoadOpcodes \ 144 { \ 145 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 146 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \ 147 PPC::DFLOADf32, PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, \ 148 PPC::QVLFDXb, PPC::SPILLTOVSR_LD \ 149 } 150 151 #define Pwr8StoreOpcodes \ 152 { \ 153 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 154 PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, PPC::SPILL_VRSAVE, \ 155 PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb, PPC::SPILLTOVSR_ST, \ 156 PPC::EVSTDD \ 157 } 158 159 #define Pwr9StoreOpcodes \ 160 { \ 161 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 162 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \ 163 PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb, \ 164 PPC::SPILLTOVSR_ST \ 165 } 166 167 // Initialize arrays for load and store spill opcodes on supported subtargets. 168 #define StoreOpcodesForSpill \ 169 { Pwr8StoreOpcodes, Pwr9StoreOpcodes } 170 #define LoadOpcodesForSpill \ 171 { Pwr8LoadOpcodes, Pwr9LoadOpcodes } 172 173 class PPCSubtarget; 174 class PPCInstrInfo : public PPCGenInstrInfo { 175 PPCSubtarget &Subtarget; 176 const PPCRegisterInfo RI; 177 const unsigned StoreSpillOpcodesArray[2][SOK_LastOpcodeSpill] = 178 StoreOpcodesForSpill; 179 const unsigned LoadSpillOpcodesArray[2][SOK_LastOpcodeSpill] = 180 LoadOpcodesForSpill; 181 182 void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, 183 int FrameIdx, const TargetRegisterClass *RC, 184 SmallVectorImpl<MachineInstr *> &NewMIs) const; 185 void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, 186 unsigned DestReg, int FrameIdx, 187 const TargetRegisterClass *RC, 188 SmallVectorImpl<MachineInstr *> &NewMIs) const; 189 190 // Replace the instruction with single LI if possible. \p DefMI must be LI or 191 // LI8. 192 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI, 193 unsigned OpNoForForwarding, MachineInstr **KilledDef) const; 194 // If the inst is x-form and has imm-form and one of its operand is produced 195 // by a LI, put the imm into the inst directly and remove the LI if possible. 196 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III, 197 unsigned ConstantOpNo, 198 MachineInstr &DefMI) const; 199 // If the inst is x-form and has imm-form and one of its operand is produced 200 // by an add-immediate, try to transform it when possible. 201 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III, 202 unsigned ConstantOpNo, MachineInstr &DefMI, 203 bool KillDefMI) const; 204 // Try to find that, if the instruction 'MI' contains any operand that 205 // could be forwarded from some inst that feeds it. If yes, return the 206 // Def of that operand. And OpNoForForwarding is the operand index in 207 // the 'MI' for that 'Def'. If we see another use of this Def between 208 // the Def and the MI, SeenIntermediateUse becomes 'true'. 209 MachineInstr *getForwardingDefMI(MachineInstr &MI, 210 unsigned &OpNoForForwarding, 211 bool &SeenIntermediateUse) const; 212 213 // Can the user MI have it's source at index \p OpNoForForwarding 214 // forwarded from an add-immediate that feeds it? 215 bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III, 216 unsigned OpNoForForwarding) const; 217 bool isDefMIElgibleForForwarding(MachineInstr &DefMI, 218 const ImmInstrInfo &III, 219 MachineOperand *&ImmMO, 220 MachineOperand *&RegMO) const; 221 bool isImmElgibleForForwarding(const MachineOperand &ImmMO, 222 const MachineInstr &DefMI, 223 const ImmInstrInfo &III, 224 int64_t &Imm) const; 225 bool isRegElgibleForForwarding(const MachineOperand &RegMO, 226 const MachineInstr &DefMI, 227 const MachineInstr &MI, bool KillDefMI, 228 bool &IsFwdFeederRegKilled) const; 229 unsigned getSpillTarget() const; 230 const unsigned *getStoreOpcodesForSpillArray() const; 231 const unsigned *getLoadOpcodesForSpillArray() const; 232 virtual void anchor(); 233 234 protected: 235 /// Commutes the operands in the given instruction. 236 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2. 237 /// 238 /// Do not call this method for a non-commutable instruction or for 239 /// non-commutable pair of operand indices OpIdx1 and OpIdx2. 240 /// Even though the instruction is commutable, the method may still 241 /// fail to commute the operands, null pointer is returned in such cases. 242 /// 243 /// For example, we can commute rlwimi instructions, but only if the 244 /// rotate amt is zero. We also have to munge the immediates a bit. 245 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 246 unsigned OpIdx1, 247 unsigned OpIdx2) const override; 248 249 public: 250 explicit PPCInstrInfo(PPCSubtarget &STI); 251 252 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 253 /// such, whenever a client has an instance of instruction info, it should 254 /// always be able to get register info as well (through this method). 255 /// 256 const PPCRegisterInfo &getRegisterInfo() const { return RI; } 257 258 bool isXFormMemOp(unsigned Opcode) const { 259 return get(Opcode).TSFlags & PPCII::XFormMemOp; 260 } 261 bool isPrefixed(unsigned Opcode) const { 262 return get(Opcode).TSFlags & PPCII::Prefixed; 263 } 264 265 static bool isSameClassPhysRegCopy(unsigned Opcode) { 266 unsigned CopyOpcodes[] = 267 { PPC::OR, PPC::OR8, PPC::FMR, PPC::VOR, PPC::XXLOR, PPC::XXLORf, 268 PPC::XSCPSGNDP, PPC::MCRF, PPC::QVFMR, PPC::QVFMRs, PPC::QVFMRb, 269 PPC::CROR, PPC::EVOR, -1U }; 270 for (int i = 0; CopyOpcodes[i] != -1U; i++) 271 if (Opcode == CopyOpcodes[i]) 272 return true; 273 return false; 274 } 275 276 ScheduleHazardRecognizer * 277 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 278 const ScheduleDAG *DAG) const override; 279 ScheduleHazardRecognizer * 280 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 281 const ScheduleDAG *DAG) const override; 282 283 unsigned getInstrLatency(const InstrItineraryData *ItinData, 284 const MachineInstr &MI, 285 unsigned *PredCost = nullptr) const override; 286 287 int getOperandLatency(const InstrItineraryData *ItinData, 288 const MachineInstr &DefMI, unsigned DefIdx, 289 const MachineInstr &UseMI, 290 unsigned UseIdx) const override; 291 int getOperandLatency(const InstrItineraryData *ItinData, 292 SDNode *DefNode, unsigned DefIdx, 293 SDNode *UseNode, unsigned UseIdx) const override { 294 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, 295 UseNode, UseIdx); 296 } 297 298 bool hasLowDefLatency(const TargetSchedModel &SchedModel, 299 const MachineInstr &DefMI, 300 unsigned DefIdx) const override { 301 // Machine LICM should hoist all instructions in low-register-pressure 302 // situations; none are sufficiently free to justify leaving in a loop 303 // body. 304 return false; 305 } 306 307 bool useMachineCombiner() const override { 308 return true; 309 } 310 311 /// Return true when there is potentially a faster code sequence 312 /// for an instruction chain ending in <Root>. All potential patterns are 313 /// output in the <Pattern> array. 314 bool getMachineCombinerPatterns( 315 MachineInstr &Root, 316 SmallVectorImpl<MachineCombinerPattern> &P) const override; 317 318 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override; 319 320 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, 321 MachineInstr &NewMI1, 322 MachineInstr &NewMI2) const override; 323 324 void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const override; 325 326 bool isCoalescableExtInstr(const MachineInstr &MI, 327 Register &SrcReg, Register &DstReg, 328 unsigned &SubIdx) const override; 329 unsigned isLoadFromStackSlot(const MachineInstr &MI, 330 int &FrameIndex) const override; 331 bool isReallyTriviallyReMaterializable(const MachineInstr &MI, 332 AAResults *AA) const override; 333 unsigned isStoreToStackSlot(const MachineInstr &MI, 334 int &FrameIndex) const override; 335 336 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 337 unsigned &SrcOpIdx2) const override; 338 339 void insertNoop(MachineBasicBlock &MBB, 340 MachineBasicBlock::iterator MI) const override; 341 342 343 // Branch analysis. 344 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 345 MachineBasicBlock *&FBB, 346 SmallVectorImpl<MachineOperand> &Cond, 347 bool AllowModify) const override; 348 unsigned removeBranch(MachineBasicBlock &MBB, 349 int *BytesRemoved = nullptr) const override; 350 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 351 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 352 const DebugLoc &DL, 353 int *BytesAdded = nullptr) const override; 354 355 // Select analysis. 356 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 357 Register, Register, Register, int &, int &, 358 int &) const override; 359 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 360 const DebugLoc &DL, Register DstReg, 361 ArrayRef<MachineOperand> Cond, Register TrueReg, 362 Register FalseReg) const override; 363 364 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 365 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 366 bool KillSrc) const override; 367 368 void storeRegToStackSlot(MachineBasicBlock &MBB, 369 MachineBasicBlock::iterator MBBI, 370 Register SrcReg, bool isKill, int FrameIndex, 371 const TargetRegisterClass *RC, 372 const TargetRegisterInfo *TRI) const override; 373 374 // Emits a register spill without updating the register class for vector 375 // registers. This ensures that when we spill a vector register the 376 // element order in the register is the same as it was in memory. 377 void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, 378 MachineBasicBlock::iterator MBBI, 379 unsigned SrcReg, bool isKill, int FrameIndex, 380 const TargetRegisterClass *RC, 381 const TargetRegisterInfo *TRI) const; 382 383 void loadRegFromStackSlot(MachineBasicBlock &MBB, 384 MachineBasicBlock::iterator MBBI, 385 Register DestReg, int FrameIndex, 386 const TargetRegisterClass *RC, 387 const TargetRegisterInfo *TRI) const override; 388 389 // Emits a register reload without updating the register class for vector 390 // registers. This ensures that when we reload a vector register the 391 // element order in the register is the same as it was in memory. 392 void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, 393 MachineBasicBlock::iterator MBBI, 394 unsigned DestReg, int FrameIndex, 395 const TargetRegisterClass *RC, 396 const TargetRegisterInfo *TRI) const; 397 398 unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const; 399 400 unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const; 401 402 bool 403 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 404 405 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, 406 MachineRegisterInfo *MRI) const override; 407 408 bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, 409 Register Reg) const; 410 411 // If conversion by predication (only supported by some branch instructions). 412 // All of the profitability checks always return true; it is always 413 // profitable to use the predicated branches. 414 bool isProfitableToIfCvt(MachineBasicBlock &MBB, 415 unsigned NumCycles, unsigned ExtraPredCycles, 416 BranchProbability Probability) const override { 417 return true; 418 } 419 420 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 421 unsigned NumT, unsigned ExtraT, 422 MachineBasicBlock &FMBB, 423 unsigned NumF, unsigned ExtraF, 424 BranchProbability Probability) const override; 425 426 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 427 BranchProbability Probability) const override { 428 return true; 429 } 430 431 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 432 MachineBasicBlock &FMBB) const override { 433 return false; 434 } 435 436 // Predication support. 437 bool isPredicated(const MachineInstr &MI) const override; 438 439 bool PredicateInstruction(MachineInstr &MI, 440 ArrayRef<MachineOperand> Pred) const override; 441 442 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 443 ArrayRef<MachineOperand> Pred2) const override; 444 445 bool DefinesPredicate(MachineInstr &MI, 446 std::vector<MachineOperand> &Pred) const override; 447 448 // Comparison optimization. 449 450 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 451 Register &SrcReg2, int &Mask, int &Value) const override; 452 453 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 454 Register SrcReg2, int Mask, int Value, 455 const MachineRegisterInfo *MRI) const override; 456 457 458 /// Return true if get the base operand, byte offset of an instruction and 459 /// the memory width. Width is the size of memory that is being 460 /// loaded/stored (e.g. 1, 2, 4, 8). 461 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, 462 const MachineOperand *&BaseOp, 463 int64_t &Offset, unsigned &Width, 464 const TargetRegisterInfo *TRI) const; 465 466 /// Return true if two MIs access different memory addresses and false 467 /// otherwise 468 bool 469 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 470 const MachineInstr &MIb) const override; 471 472 /// GetInstSize - Return the number of bytes of code the specified 473 /// instruction may be. This returns the maximum number of bytes. 474 /// 475 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 476 477 void getNoop(MCInst &NopInst) const override; 478 479 std::pair<unsigned, unsigned> 480 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 481 482 ArrayRef<std::pair<unsigned, const char *>> 483 getSerializableDirectMachineOperandTargetFlags() const override; 484 485 ArrayRef<std::pair<unsigned, const char *>> 486 getSerializableBitmaskMachineOperandTargetFlags() const override; 487 488 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction. 489 bool expandVSXMemPseudo(MachineInstr &MI) const; 490 491 // Lower pseudo instructions after register allocation. 492 bool expandPostRAPseudo(MachineInstr &MI) const override; 493 494 static bool isVFRegister(unsigned Reg) { 495 return Reg >= PPC::VF0 && Reg <= PPC::VF31; 496 } 497 static bool isVRRegister(unsigned Reg) { 498 return Reg >= PPC::V0 && Reg <= PPC::V31; 499 } 500 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const; 501 static int getRecordFormOpcode(unsigned Opcode); 502 503 bool isTOCSaveMI(const MachineInstr &MI) const; 504 505 bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, 506 const unsigned PhiDepth) const; 507 508 /// Return true if the output of the instruction is always a sign-extended, 509 /// i.e. 0 to 31-th bits are same as 32-th bit. 510 bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const { 511 return isSignOrZeroExtended(MI, true, depth); 512 } 513 514 /// Return true if the output of the instruction is always zero-extended, 515 /// i.e. 0 to 31-th bits are all zeros 516 bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const { 517 return isSignOrZeroExtended(MI, false, depth); 518 } 519 520 bool convertToImmediateForm(MachineInstr &MI, 521 MachineInstr **KilledDef = nullptr) const; 522 bool foldFrameOffset(MachineInstr &MI) const; 523 bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const; 524 bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const; 525 bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, 526 unsigned &XFormOpcode, 527 int64_t &OffsetOfImmInstr, 528 ImmInstrInfo &III) const; 529 bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, 530 MachineInstr *&ADDIMI, int64_t &OffsetAddi, 531 int64_t OffsetImm) const; 532 533 /// Fixup killed/dead flag for register \p RegNo between instructions [\p 534 /// StartMI, \p EndMI]. Some PostRA transformations may violate register 535 /// killed/dead flags semantics, this function can be called to fix up. Before 536 /// calling this function, 537 /// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI. 538 /// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI) 539 /// and possible definition for \p RegNo is \p StartMI or \p EndMI. 540 /// 3. Ensure that all instructions between [\p StartMI, \p EndMI] are in same 541 /// basic block. 542 void fixupIsDeadOrKill(MachineInstr &StartMI, MachineInstr &EndMI, 543 unsigned RegNo) const; 544 void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const; 545 void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, 546 int64_t Imm) const; 547 548 bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, 549 bool PostRA) const; 550 551 // In PostRA phase, try to find instruction defines \p Reg before \p MI. 552 // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist. 553 MachineInstr *getDefMIPostRA(unsigned Reg, MachineInstr &MI, 554 bool &SeenIntermediateUse) const; 555 556 /// getRegNumForOperand - some operands use different numbering schemes 557 /// for the same registers. For example, a VSX instruction may have any of 558 /// vs0-vs63 allocated whereas an Altivec instruction could only have 559 /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual 560 /// register number needed for the opcode/operand number combination. 561 /// The operand number argument will be useful when we need to extend this 562 /// to instructions that use both Altivec and VSX numbering (for different 563 /// operands). 564 static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, 565 unsigned OpNo) { 566 int16_t regClass = Desc.OpInfo[OpNo].RegClass; 567 switch (regClass) { 568 // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31, 569 // VSX32-VSX63 during encoding/disassembling 570 case PPC::VSSRCRegClassID: 571 case PPC::VSFRCRegClassID: 572 if (isVFRegister(Reg)) 573 return PPC::VSX32 + (Reg - PPC::VF0); 574 break; 575 // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31, 576 // VSX32-VSX63 during encoding/disassembling 577 case PPC::VSRCRegClassID: 578 if (isVRRegister(Reg)) 579 return PPC::VSX32 + (Reg - PPC::V0); 580 break; 581 // Other RegClass doesn't need mapping 582 default: 583 break; 584 } 585 return Reg; 586 } 587 588 /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero). 589 bool isBDNZ(unsigned Opcode) const; 590 591 /// Find the hardware loop instruction used to set-up the specified loop. 592 /// On PPC, we have two instructions used to set-up the hardware loop 593 /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8) 594 /// instructions to indicate the end of a loop. 595 MachineInstr * 596 findLoopInstr(MachineBasicBlock &PreHeader, 597 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const; 598 599 /// Analyze loop L, which must be a single-basic-block loop, and if the 600 /// conditions can be understood enough produce a PipelinerLoopInfo object. 601 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo> 602 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override; 603 }; 604 605 } 606 607 #endif 608