1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCInstrInfo.h" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCMachineFunctionInfo.h" 18 #include "PPCTargetMachine.h" 19 #include "PPCHazardRecognizers.h" 20 #include "MCTargetDesc/PPCPredicates.h" 21 #include "llvm/CodeGen/MachineFrameInfo.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineMemOperand.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/CodeGen/PseudoSourceValue.h" 26 #include "llvm/MC/MCAsmInfo.h" 27 #include "llvm/Support/CommandLine.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include "llvm/Support/raw_ostream.h" 31 #include "llvm/ADT/STLExtras.h" 32 33 #define GET_INSTRINFO_CTOR 34 #include "PPCGenInstrInfo.inc" 35 36 namespace llvm { 37 extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. 38 extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. 39 } 40 41 using namespace llvm; 42 43 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) 44 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 45 TM(tm), RI(*TM.getSubtargetImpl(), *this) {} 46 47 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for 48 /// this target when scheduling the DAG. 49 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer( 50 const TargetMachine *TM, 51 const ScheduleDAG *DAG) const { 52 // Should use subtarget info to pick the right hazard recognizer. For 53 // now, always return a PPC970 recognizer. 54 const TargetInstrInfo *TII = TM->getInstrInfo(); 55 assert(TII && "No InstrInfo?"); 56 57 unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective(); 58 if (Directive == PPC::DIR_440) { 59 const InstrItineraryData *II = TM->getInstrItineraryData(); 60 return new PPCHazardRecognizer440(II, DAG); 61 } 62 else { 63 return new PPCHazardRecognizer970(*TII); 64 } 65 } 66 67 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 68 int &FrameIndex) const { 69 switch (MI->getOpcode()) { 70 default: break; 71 case PPC::LD: 72 case PPC::LWZ: 73 case PPC::LFS: 74 case PPC::LFD: 75 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 76 MI->getOperand(2).isFI()) { 77 FrameIndex = MI->getOperand(2).getIndex(); 78 return MI->getOperand(0).getReg(); 79 } 80 break; 81 } 82 return 0; 83 } 84 85 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 86 int &FrameIndex) const { 87 switch (MI->getOpcode()) { 88 default: break; 89 case PPC::STD: 90 case PPC::STW: 91 case PPC::STFS: 92 case PPC::STFD: 93 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 94 MI->getOperand(2).isFI()) { 95 FrameIndex = MI->getOperand(2).getIndex(); 96 return MI->getOperand(0).getReg(); 97 } 98 break; 99 } 100 return 0; 101 } 102 103 // commuteInstruction - We can commute rlwimi instructions, but only if the 104 // rotate amt is zero. We also have to munge the immediates a bit. 105 MachineInstr * 106 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 107 MachineFunction &MF = *MI->getParent()->getParent(); 108 109 // Normal instructions can be commuted the obvious way. 110 if (MI->getOpcode() != PPC::RLWIMI) 111 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 112 113 // Cannot commute if it has a non-zero rotate count. 114 if (MI->getOperand(3).getImm() != 0) 115 return 0; 116 117 // If we have a zero rotate count, we have: 118 // M = mask(MB,ME) 119 // Op0 = (Op1 & ~M) | (Op2 & M) 120 // Change this to: 121 // M = mask((ME+1)&31, (MB-1)&31) 122 // Op0 = (Op2 & ~M) | (Op1 & M) 123 124 // Swap op1/op2 125 unsigned Reg0 = MI->getOperand(0).getReg(); 126 unsigned Reg1 = MI->getOperand(1).getReg(); 127 unsigned Reg2 = MI->getOperand(2).getReg(); 128 bool Reg1IsKill = MI->getOperand(1).isKill(); 129 bool Reg2IsKill = MI->getOperand(2).isKill(); 130 bool ChangeReg0 = false; 131 // If machine instrs are no longer in two-address forms, update 132 // destination register as well. 133 if (Reg0 == Reg1) { 134 // Must be two address instruction! 135 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) && 136 "Expecting a two-address instruction!"); 137 Reg2IsKill = false; 138 ChangeReg0 = true; 139 } 140 141 // Masks. 142 unsigned MB = MI->getOperand(4).getImm(); 143 unsigned ME = MI->getOperand(5).getImm(); 144 145 if (NewMI) { 146 // Create a new instruction. 147 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); 148 bool Reg0IsDead = MI->getOperand(0).isDead(); 149 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 150 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) 151 .addReg(Reg2, getKillRegState(Reg2IsKill)) 152 .addReg(Reg1, getKillRegState(Reg1IsKill)) 153 .addImm((ME+1) & 31) 154 .addImm((MB-1) & 31); 155 } 156 157 if (ChangeReg0) 158 MI->getOperand(0).setReg(Reg2); 159 MI->getOperand(2).setReg(Reg1); 160 MI->getOperand(1).setReg(Reg2); 161 MI->getOperand(2).setIsKill(Reg1IsKill); 162 MI->getOperand(1).setIsKill(Reg2IsKill); 163 164 // Swap the mask around. 165 MI->getOperand(4).setImm((ME+1) & 31); 166 MI->getOperand(5).setImm((MB-1) & 31); 167 return MI; 168 } 169 170 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, 171 MachineBasicBlock::iterator MI) const { 172 DebugLoc DL; 173 BuildMI(MBB, MI, DL, get(PPC::NOP)); 174 } 175 176 177 // Branch analysis. 178 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 179 MachineBasicBlock *&FBB, 180 SmallVectorImpl<MachineOperand> &Cond, 181 bool AllowModify) const { 182 // If the block has no terminators, it just falls into the block after it. 183 MachineBasicBlock::iterator I = MBB.end(); 184 if (I == MBB.begin()) 185 return false; 186 --I; 187 while (I->isDebugValue()) { 188 if (I == MBB.begin()) 189 return false; 190 --I; 191 } 192 if (!isUnpredicatedTerminator(I)) 193 return false; 194 195 // Get the last instruction in the block. 196 MachineInstr *LastInst = I; 197 198 // If there is only one terminator instruction, process it. 199 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 200 if (LastInst->getOpcode() == PPC::B) { 201 if (!LastInst->getOperand(0).isMBB()) 202 return true; 203 TBB = LastInst->getOperand(0).getMBB(); 204 return false; 205 } else if (LastInst->getOpcode() == PPC::BCC) { 206 if (!LastInst->getOperand(2).isMBB()) 207 return true; 208 // Block ends with fall-through condbranch. 209 TBB = LastInst->getOperand(2).getMBB(); 210 Cond.push_back(LastInst->getOperand(0)); 211 Cond.push_back(LastInst->getOperand(1)); 212 return false; 213 } 214 // Otherwise, don't know what this is. 215 return true; 216 } 217 218 // Get the instruction before it if it's a terminator. 219 MachineInstr *SecondLastInst = I; 220 221 // If there are three terminators, we don't know what sort of block this is. 222 if (SecondLastInst && I != MBB.begin() && 223 isUnpredicatedTerminator(--I)) 224 return true; 225 226 // If the block ends with PPC::B and PPC:BCC, handle it. 227 if (SecondLastInst->getOpcode() == PPC::BCC && 228 LastInst->getOpcode() == PPC::B) { 229 if (!SecondLastInst->getOperand(2).isMBB() || 230 !LastInst->getOperand(0).isMBB()) 231 return true; 232 TBB = SecondLastInst->getOperand(2).getMBB(); 233 Cond.push_back(SecondLastInst->getOperand(0)); 234 Cond.push_back(SecondLastInst->getOperand(1)); 235 FBB = LastInst->getOperand(0).getMBB(); 236 return false; 237 } 238 239 // If the block ends with two PPC:Bs, handle it. The second one is not 240 // executed, so remove it. 241 if (SecondLastInst->getOpcode() == PPC::B && 242 LastInst->getOpcode() == PPC::B) { 243 if (!SecondLastInst->getOperand(0).isMBB()) 244 return true; 245 TBB = SecondLastInst->getOperand(0).getMBB(); 246 I = LastInst; 247 if (AllowModify) 248 I->eraseFromParent(); 249 return false; 250 } 251 252 // Otherwise, can't handle this. 253 return true; 254 } 255 256 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 257 MachineBasicBlock::iterator I = MBB.end(); 258 if (I == MBB.begin()) return 0; 259 --I; 260 while (I->isDebugValue()) { 261 if (I == MBB.begin()) 262 return 0; 263 --I; 264 } 265 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC) 266 return 0; 267 268 // Remove the branch. 269 I->eraseFromParent(); 270 271 I = MBB.end(); 272 273 if (I == MBB.begin()) return 1; 274 --I; 275 if (I->getOpcode() != PPC::BCC) 276 return 1; 277 278 // Remove the branch. 279 I->eraseFromParent(); 280 return 2; 281 } 282 283 unsigned 284 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 285 MachineBasicBlock *FBB, 286 const SmallVectorImpl<MachineOperand> &Cond, 287 DebugLoc DL) const { 288 // Shouldn't be a fall through. 289 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 290 assert((Cond.size() == 2 || Cond.size() == 0) && 291 "PPC branch conditions have two components!"); 292 293 // One-way branch. 294 if (FBB == 0) { 295 if (Cond.empty()) // Unconditional branch 296 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); 297 else // Conditional branch 298 BuildMI(&MBB, DL, get(PPC::BCC)) 299 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 300 return 1; 301 } 302 303 // Two-way Conditional Branch. 304 BuildMI(&MBB, DL, get(PPC::BCC)) 305 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 306 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); 307 return 2; 308 } 309 310 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 311 MachineBasicBlock::iterator I, DebugLoc DL, 312 unsigned DestReg, unsigned SrcReg, 313 bool KillSrc) const { 314 unsigned Opc; 315 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) 316 Opc = PPC::OR; 317 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) 318 Opc = PPC::OR8; 319 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) 320 Opc = PPC::FMR; 321 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) 322 Opc = PPC::MCRF; 323 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) 324 Opc = PPC::VOR; 325 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) 326 Opc = PPC::CROR; 327 else 328 llvm_unreachable("Impossible reg-to-reg copy"); 329 330 const MCInstrDesc &MCID = get(Opc); 331 if (MCID.getNumOperands() == 3) 332 BuildMI(MBB, I, DL, MCID, DestReg) 333 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); 334 else 335 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); 336 } 337 338 bool 339 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, 340 unsigned SrcReg, bool isKill, 341 int FrameIdx, 342 const TargetRegisterClass *RC, 343 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 344 DebugLoc DL; 345 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) { 346 if (SrcReg != PPC::LR) { 347 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 348 .addReg(SrcReg, 349 getKillRegState(isKill)), 350 FrameIdx)); 351 } else { 352 // FIXME: this spills LR immediately to memory in one step. To do this, 353 // we use R11, which we know cannot be used in the prolog/epilog. This is 354 // a hack. 355 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11)); 356 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 357 .addReg(PPC::R11, 358 getKillRegState(isKill)), 359 FrameIdx)); 360 } 361 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) { 362 if (SrcReg != PPC::LR8) { 363 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 364 .addReg(SrcReg, 365 getKillRegState(isKill)), 366 FrameIdx)); 367 } else { 368 // FIXME: this spills LR immediately to memory in one step. To do this, 369 // we use R11, which we know cannot be used in the prolog/epilog. This is 370 // a hack. 371 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11)); 372 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 373 .addReg(PPC::X11, 374 getKillRegState(isKill)), 375 FrameIdx)); 376 } 377 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) { 378 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) 379 .addReg(SrcReg, 380 getKillRegState(isKill)), 381 FrameIdx)); 382 } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) { 383 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) 384 .addReg(SrcReg, 385 getKillRegState(isKill)), 386 FrameIdx)); 387 } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) { 388 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || 389 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { 390 // FIXME (64-bit): Enable 391 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) 392 .addReg(SrcReg, 393 getKillRegState(isKill)), 394 FrameIdx)); 395 return true; 396 } else { 397 // FIXME: We need a scatch reg here. The trouble with using R0 is that 398 // it's possible for the stack frame to be so big the save location is 399 // out of range of immediate offsets, necessitating another register. 400 // We hack this on Darwin by reserving R2. It's probably broken on Linux 401 // at the moment. 402 403 // We need to store the CR in the low 4-bits of the saved value. First, 404 // issue a MFCR to save all of the CRBits. 405 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ? 406 PPC::R2 : PPC::R0; 407 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCRpseud), ScratchReg) 408 .addReg(SrcReg, getKillRegState(isKill))); 409 410 // If the saved register wasn't CR0, shift the bits left so that they are 411 // in CR0's slot. 412 if (SrcReg != PPC::CR0) { 413 unsigned ShiftBits = getPPCRegisterNumbering(SrcReg)*4; 414 // rlwinm scratch, scratch, ShiftBits, 0, 31. 415 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) 416 .addReg(ScratchReg).addImm(ShiftBits) 417 .addImm(0).addImm(31)); 418 } 419 420 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 421 .addReg(ScratchReg, 422 getKillRegState(isKill)), 423 FrameIdx)); 424 } 425 } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) { 426 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the 427 // backend currently only uses CR1EQ as an individual bit, this should 428 // not cause any bug. If we need other uses of CR bits, the following 429 // code may be invalid. 430 unsigned Reg = 0; 431 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || 432 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) 433 Reg = PPC::CR0; 434 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || 435 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) 436 Reg = PPC::CR1; 437 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || 438 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) 439 Reg = PPC::CR2; 440 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || 441 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) 442 Reg = PPC::CR3; 443 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || 444 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) 445 Reg = PPC::CR4; 446 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT || 447 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) 448 Reg = PPC::CR5; 449 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT || 450 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) 451 Reg = PPC::CR6; 452 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT || 453 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN) 454 Reg = PPC::CR7; 455 456 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx, 457 PPC::CRRCRegisterClass, NewMIs); 458 459 } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) { 460 // We don't have indexed addressing for vector loads. Emit: 461 // R0 = ADDI FI# 462 // STVX VAL, 0, R0 463 // 464 // FIXME: We use R0 here, because it isn't available for RA. 465 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), 466 FrameIdx, 0, 0)); 467 NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX)) 468 .addReg(SrcReg, getKillRegState(isKill)) 469 .addReg(PPC::R0) 470 .addReg(PPC::R0)); 471 } else { 472 llvm_unreachable("Unknown regclass!"); 473 } 474 475 return false; 476 } 477 478 void 479 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 480 MachineBasicBlock::iterator MI, 481 unsigned SrcReg, bool isKill, int FrameIdx, 482 const TargetRegisterClass *RC, 483 const TargetRegisterInfo *TRI) const { 484 MachineFunction &MF = *MBB.getParent(); 485 SmallVector<MachineInstr*, 4> NewMIs; 486 487 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) { 488 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 489 FuncInfo->setSpillsCR(); 490 } 491 492 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 493 MBB.insert(MI, NewMIs[i]); 494 495 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 496 MachineMemOperand *MMO = 497 MF.getMachineMemOperand( 498 MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)), 499 MachineMemOperand::MOStore, 500 MFI.getObjectSize(FrameIdx), 501 MFI.getObjectAlignment(FrameIdx)); 502 NewMIs.back()->addMemOperand(MF, MMO); 503 } 504 505 void 506 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, 507 unsigned DestReg, int FrameIdx, 508 const TargetRegisterClass *RC, 509 SmallVectorImpl<MachineInstr*> &NewMIs)const{ 510 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) { 511 if (DestReg != PPC::LR) { 512 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 513 DestReg), FrameIdx)); 514 } else { 515 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 516 PPC::R11), FrameIdx)); 517 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11)); 518 } 519 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) { 520 if (DestReg != PPC::LR8) { 521 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg), 522 FrameIdx)); 523 } else { 524 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), 525 PPC::R11), FrameIdx)); 526 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11)); 527 } 528 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) { 529 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg), 530 FrameIdx)); 531 } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) { 532 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg), 533 FrameIdx)); 534 } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) { 535 // FIXME: We need a scatch reg here. The trouble with using R0 is that 536 // it's possible for the stack frame to be so big the save location is 537 // out of range of immediate offsets, necessitating another register. 538 // We hack this on Darwin by reserving R2. It's probably broken on Linux 539 // at the moment. 540 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ? 541 PPC::R2 : PPC::R0; 542 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 543 ScratchReg), FrameIdx)); 544 545 // If the reloaded register isn't CR0, shift the bits right so that they are 546 // in the right CR's slot. 547 if (DestReg != PPC::CR0) { 548 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; 549 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 550 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) 551 .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0) 552 .addImm(31)); 553 } 554 555 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg) 556 .addReg(ScratchReg)); 557 } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) { 558 559 unsigned Reg = 0; 560 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT || 561 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN) 562 Reg = PPC::CR0; 563 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT || 564 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN) 565 Reg = PPC::CR1; 566 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT || 567 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN) 568 Reg = PPC::CR2; 569 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT || 570 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN) 571 Reg = PPC::CR3; 572 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT || 573 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN) 574 Reg = PPC::CR4; 575 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT || 576 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN) 577 Reg = PPC::CR5; 578 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT || 579 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN) 580 Reg = PPC::CR6; 581 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT || 582 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN) 583 Reg = PPC::CR7; 584 585 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx, 586 PPC::CRRCRegisterClass, NewMIs); 587 588 } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) { 589 // We don't have indexed addressing for vector loads. Emit: 590 // R0 = ADDI FI# 591 // Dest = LVX 0, R0 592 // 593 // FIXME: We use R0 here, because it isn't available for RA. 594 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), 595 FrameIdx, 0, 0)); 596 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0) 597 .addReg(PPC::R0)); 598 } else { 599 llvm_unreachable("Unknown regclass!"); 600 } 601 } 602 603 void 604 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 605 MachineBasicBlock::iterator MI, 606 unsigned DestReg, int FrameIdx, 607 const TargetRegisterClass *RC, 608 const TargetRegisterInfo *TRI) const { 609 MachineFunction &MF = *MBB.getParent(); 610 SmallVector<MachineInstr*, 4> NewMIs; 611 DebugLoc DL; 612 if (MI != MBB.end()) DL = MI->getDebugLoc(); 613 LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs); 614 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 615 MBB.insert(MI, NewMIs[i]); 616 617 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 618 MachineMemOperand *MMO = 619 MF.getMachineMemOperand( 620 MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)), 621 MachineMemOperand::MOLoad, 622 MFI.getObjectSize(FrameIdx), 623 MFI.getObjectAlignment(FrameIdx)); 624 NewMIs.back()->addMemOperand(MF, MMO); 625 } 626 627 MachineInstr* 628 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 629 int FrameIx, uint64_t Offset, 630 const MDNode *MDPtr, 631 DebugLoc DL) const { 632 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE)); 633 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr); 634 return &*MIB; 635 } 636 637 bool PPCInstrInfo:: 638 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 639 assert(Cond.size() == 2 && "Invalid PPC branch opcode!"); 640 // Leave the CR# the same, but invert the condition. 641 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); 642 return false; 643 } 644 645 /// GetInstSize - Return the number of bytes of code the specified 646 /// instruction may be. This returns the maximum number of bytes. 647 /// 648 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 649 switch (MI->getOpcode()) { 650 case PPC::INLINEASM: { // Inline Asm: Variable size. 651 const MachineFunction *MF = MI->getParent()->getParent(); 652 const char *AsmStr = MI->getOperand(0).getSymbolName(); 653 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); 654 } 655 case PPC::PROLOG_LABEL: 656 case PPC::EH_LABEL: 657 case PPC::GC_LABEL: 658 case PPC::DBG_VALUE: 659 return 0; 660 default: 661 return 4; // PowerPC instructions are all 4 bytes 662 } 663 } 664