1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCInstrInfo.h" 15 #include "PPCInstrBuilder.h" 16 #include "PPCMachineFunctionInfo.h" 17 #include "PPCPredicates.h" 18 #include "PPCGenInstrInfo.inc" 19 #include "PPCTargetMachine.h" 20 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/CodeGen/MachineFrameInfo.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineMemOperand.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/CodeGen/PseudoSourceValue.h" 26 #include "llvm/Support/CommandLine.h" 27 #include "llvm/Support/ErrorHandling.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include "llvm/MC/MCAsmInfo.h" 30 31 namespace llvm { 32 extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. 33 extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. 34 } 35 36 using namespace llvm; 37 38 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) 39 : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm), 40 RI(*TM.getSubtargetImpl(), *this) {} 41 42 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 43 int &FrameIndex) const { 44 switch (MI->getOpcode()) { 45 default: break; 46 case PPC::LD: 47 case PPC::LWZ: 48 case PPC::LFS: 49 case PPC::LFD: 50 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 51 MI->getOperand(2).isFI()) { 52 FrameIndex = MI->getOperand(2).getIndex(); 53 return MI->getOperand(0).getReg(); 54 } 55 break; 56 } 57 return 0; 58 } 59 60 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 61 int &FrameIndex) const { 62 switch (MI->getOpcode()) { 63 default: break; 64 case PPC::STD: 65 case PPC::STW: 66 case PPC::STFS: 67 case PPC::STFD: 68 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 69 MI->getOperand(2).isFI()) { 70 FrameIndex = MI->getOperand(2).getIndex(); 71 return MI->getOperand(0).getReg(); 72 } 73 break; 74 } 75 return 0; 76 } 77 78 // commuteInstruction - We can commute rlwimi instructions, but only if the 79 // rotate amt is zero. We also have to munge the immediates a bit. 80 MachineInstr * 81 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 82 MachineFunction &MF = *MI->getParent()->getParent(); 83 84 // Normal instructions can be commuted the obvious way. 85 if (MI->getOpcode() != PPC::RLWIMI) 86 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 87 88 // Cannot commute if it has a non-zero rotate count. 89 if (MI->getOperand(3).getImm() != 0) 90 return 0; 91 92 // If we have a zero rotate count, we have: 93 // M = mask(MB,ME) 94 // Op0 = (Op1 & ~M) | (Op2 & M) 95 // Change this to: 96 // M = mask((ME+1)&31, (MB-1)&31) 97 // Op0 = (Op2 & ~M) | (Op1 & M) 98 99 // Swap op1/op2 100 unsigned Reg0 = MI->getOperand(0).getReg(); 101 unsigned Reg1 = MI->getOperand(1).getReg(); 102 unsigned Reg2 = MI->getOperand(2).getReg(); 103 bool Reg1IsKill = MI->getOperand(1).isKill(); 104 bool Reg2IsKill = MI->getOperand(2).isKill(); 105 bool ChangeReg0 = false; 106 // If machine instrs are no longer in two-address forms, update 107 // destination register as well. 108 if (Reg0 == Reg1) { 109 // Must be two address instruction! 110 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) && 111 "Expecting a two-address instruction!"); 112 Reg2IsKill = false; 113 ChangeReg0 = true; 114 } 115 116 // Masks. 117 unsigned MB = MI->getOperand(4).getImm(); 118 unsigned ME = MI->getOperand(5).getImm(); 119 120 if (NewMI) { 121 // Create a new instruction. 122 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); 123 bool Reg0IsDead = MI->getOperand(0).isDead(); 124 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 125 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) 126 .addReg(Reg2, getKillRegState(Reg2IsKill)) 127 .addReg(Reg1, getKillRegState(Reg1IsKill)) 128 .addImm((ME+1) & 31) 129 .addImm((MB-1) & 31); 130 } 131 132 if (ChangeReg0) 133 MI->getOperand(0).setReg(Reg2); 134 MI->getOperand(2).setReg(Reg1); 135 MI->getOperand(1).setReg(Reg2); 136 MI->getOperand(2).setIsKill(Reg1IsKill); 137 MI->getOperand(1).setIsKill(Reg2IsKill); 138 139 // Swap the mask around. 140 MI->getOperand(4).setImm((ME+1) & 31); 141 MI->getOperand(5).setImm((MB-1) & 31); 142 return MI; 143 } 144 145 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, 146 MachineBasicBlock::iterator MI) const { 147 DebugLoc DL; 148 BuildMI(MBB, MI, DL, get(PPC::NOP)); 149 } 150 151 152 // Branch analysis. 153 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 154 MachineBasicBlock *&FBB, 155 SmallVectorImpl<MachineOperand> &Cond, 156 bool AllowModify) const { 157 // If the block has no terminators, it just falls into the block after it. 158 MachineBasicBlock::iterator I = MBB.end(); 159 if (I == MBB.begin()) 160 return false; 161 --I; 162 while (I->isDebugValue()) { 163 if (I == MBB.begin()) 164 return false; 165 --I; 166 } 167 if (!isUnpredicatedTerminator(I)) 168 return false; 169 170 // Get the last instruction in the block. 171 MachineInstr *LastInst = I; 172 173 // If there is only one terminator instruction, process it. 174 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 175 if (LastInst->getOpcode() == PPC::B) { 176 if (!LastInst->getOperand(0).isMBB()) 177 return true; 178 TBB = LastInst->getOperand(0).getMBB(); 179 return false; 180 } else if (LastInst->getOpcode() == PPC::BCC) { 181 if (!LastInst->getOperand(2).isMBB()) 182 return true; 183 // Block ends with fall-through condbranch. 184 TBB = LastInst->getOperand(2).getMBB(); 185 Cond.push_back(LastInst->getOperand(0)); 186 Cond.push_back(LastInst->getOperand(1)); 187 return false; 188 } 189 // Otherwise, don't know what this is. 190 return true; 191 } 192 193 // Get the instruction before it if it's a terminator. 194 MachineInstr *SecondLastInst = I; 195 196 // If there are three terminators, we don't know what sort of block this is. 197 if (SecondLastInst && I != MBB.begin() && 198 isUnpredicatedTerminator(--I)) 199 return true; 200 201 // If the block ends with PPC::B and PPC:BCC, handle it. 202 if (SecondLastInst->getOpcode() == PPC::BCC && 203 LastInst->getOpcode() == PPC::B) { 204 if (!SecondLastInst->getOperand(2).isMBB() || 205 !LastInst->getOperand(0).isMBB()) 206 return true; 207 TBB = SecondLastInst->getOperand(2).getMBB(); 208 Cond.push_back(SecondLastInst->getOperand(0)); 209 Cond.push_back(SecondLastInst->getOperand(1)); 210 FBB = LastInst->getOperand(0).getMBB(); 211 return false; 212 } 213 214 // If the block ends with two PPC:Bs, handle it. The second one is not 215 // executed, so remove it. 216 if (SecondLastInst->getOpcode() == PPC::B && 217 LastInst->getOpcode() == PPC::B) { 218 if (!SecondLastInst->getOperand(0).isMBB()) 219 return true; 220 TBB = SecondLastInst->getOperand(0).getMBB(); 221 I = LastInst; 222 if (AllowModify) 223 I->eraseFromParent(); 224 return false; 225 } 226 227 // Otherwise, can't handle this. 228 return true; 229 } 230 231 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 232 MachineBasicBlock::iterator I = MBB.end(); 233 if (I == MBB.begin()) return 0; 234 --I; 235 while (I->isDebugValue()) { 236 if (I == MBB.begin()) 237 return 0; 238 --I; 239 } 240 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC) 241 return 0; 242 243 // Remove the branch. 244 I->eraseFromParent(); 245 246 I = MBB.end(); 247 248 if (I == MBB.begin()) return 1; 249 --I; 250 if (I->getOpcode() != PPC::BCC) 251 return 1; 252 253 // Remove the branch. 254 I->eraseFromParent(); 255 return 2; 256 } 257 258 unsigned 259 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 260 MachineBasicBlock *FBB, 261 const SmallVectorImpl<MachineOperand> &Cond, 262 DebugLoc DL) const { 263 // Shouldn't be a fall through. 264 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 265 assert((Cond.size() == 2 || Cond.size() == 0) && 266 "PPC branch conditions have two components!"); 267 268 // One-way branch. 269 if (FBB == 0) { 270 if (Cond.empty()) // Unconditional branch 271 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); 272 else // Conditional branch 273 BuildMI(&MBB, DL, get(PPC::BCC)) 274 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 275 return 1; 276 } 277 278 // Two-way Conditional Branch. 279 BuildMI(&MBB, DL, get(PPC::BCC)) 280 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 281 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); 282 return 2; 283 } 284 285 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 286 MachineBasicBlock::iterator I, DebugLoc DL, 287 unsigned DestReg, unsigned SrcReg, 288 bool KillSrc) const { 289 unsigned Opc; 290 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) 291 Opc = PPC::OR; 292 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) 293 Opc = PPC::OR8; 294 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) 295 Opc = PPC::FMR; 296 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) 297 Opc = PPC::MCRF; 298 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) 299 Opc = PPC::VOR; 300 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) 301 Opc = PPC::CROR; 302 else 303 llvm_unreachable("Impossible reg-to-reg copy"); 304 305 const TargetInstrDesc &TID = get(Opc); 306 if (TID.getNumOperands() == 3) 307 BuildMI(MBB, I, DL, TID, DestReg) 308 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); 309 else 310 BuildMI(MBB, I, DL, TID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); 311 } 312 313 bool 314 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, 315 unsigned SrcReg, bool isKill, 316 int FrameIdx, 317 const TargetRegisterClass *RC, 318 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 319 DebugLoc DL; 320 if (RC == PPC::GPRCRegisterClass) { 321 if (SrcReg != PPC::LR) { 322 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 323 .addReg(SrcReg, 324 getKillRegState(isKill)), 325 FrameIdx)); 326 } else { 327 // FIXME: this spills LR immediately to memory in one step. To do this, 328 // we use R11, which we know cannot be used in the prolog/epilog. This is 329 // a hack. 330 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11)); 331 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 332 .addReg(PPC::R11, 333 getKillRegState(isKill)), 334 FrameIdx)); 335 } 336 } else if (RC == PPC::G8RCRegisterClass) { 337 if (SrcReg != PPC::LR8) { 338 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 339 .addReg(SrcReg, 340 getKillRegState(isKill)), 341 FrameIdx)); 342 } else { 343 // FIXME: this spills LR immediately to memory in one step. To do this, 344 // we use R11, which we know cannot be used in the prolog/epilog. This is 345 // a hack. 346 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11)); 347 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 348 .addReg(PPC::X11, 349 getKillRegState(isKill)), 350 FrameIdx)); 351 } 352 } else if (RC == PPC::F8RCRegisterClass) { 353 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) 354 .addReg(SrcReg, 355 getKillRegState(isKill)), 356 FrameIdx)); 357 } else if (RC == PPC::F4RCRegisterClass) { 358 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) 359 .addReg(SrcReg, 360 getKillRegState(isKill)), 361 FrameIdx)); 362 } else if (RC == PPC::CRRCRegisterClass) { 363 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || 364 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { 365 // FIXME (64-bit): Enable 366 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) 367 .addReg(SrcReg, 368 getKillRegState(isKill)), 369 FrameIdx)); 370 return true; 371 } else { 372 // FIXME: We need a scatch reg here. The trouble with using R0 is that 373 // it's possible for the stack frame to be so big the save location is 374 // out of range of immediate offsets, necessitating another register. 375 // We hack this on Darwin by reserving R2. It's probably broken on Linux 376 // at the moment. 377 378 // We need to store the CR in the low 4-bits of the saved value. First, 379 // issue a MFCR to save all of the CRBits. 380 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ? 381 PPC::R2 : PPC::R0; 382 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCRpseud), ScratchReg) 383 .addReg(SrcReg, getKillRegState(isKill))); 384 385 // If the saved register wasn't CR0, shift the bits left so that they are 386 // in CR0's slot. 387 if (SrcReg != PPC::CR0) { 388 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; 389 // rlwinm scratch, scratch, ShiftBits, 0, 31. 390 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) 391 .addReg(ScratchReg).addImm(ShiftBits) 392 .addImm(0).addImm(31)); 393 } 394 395 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 396 .addReg(ScratchReg, 397 getKillRegState(isKill)), 398 FrameIdx)); 399 } 400 } else if (RC == PPC::CRBITRCRegisterClass) { 401 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the 402 // backend currently only uses CR1EQ as an individual bit, this should 403 // not cause any bug. If we need other uses of CR bits, the following 404 // code may be invalid. 405 unsigned Reg = 0; 406 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || 407 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) 408 Reg = PPC::CR0; 409 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || 410 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) 411 Reg = PPC::CR1; 412 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || 413 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) 414 Reg = PPC::CR2; 415 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || 416 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) 417 Reg = PPC::CR3; 418 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || 419 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) 420 Reg = PPC::CR4; 421 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT || 422 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) 423 Reg = PPC::CR5; 424 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT || 425 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) 426 Reg = PPC::CR6; 427 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT || 428 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN) 429 Reg = PPC::CR7; 430 431 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx, 432 PPC::CRRCRegisterClass, NewMIs); 433 434 } else if (RC == PPC::VRRCRegisterClass) { 435 // We don't have indexed addressing for vector loads. Emit: 436 // R0 = ADDI FI# 437 // STVX VAL, 0, R0 438 // 439 // FIXME: We use R0 here, because it isn't available for RA. 440 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), 441 FrameIdx, 0, 0)); 442 NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX)) 443 .addReg(SrcReg, getKillRegState(isKill)) 444 .addReg(PPC::R0) 445 .addReg(PPC::R0)); 446 } else { 447 llvm_unreachable("Unknown regclass!"); 448 } 449 450 return false; 451 } 452 453 void 454 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 455 MachineBasicBlock::iterator MI, 456 unsigned SrcReg, bool isKill, int FrameIdx, 457 const TargetRegisterClass *RC, 458 const TargetRegisterInfo *TRI) const { 459 MachineFunction &MF = *MBB.getParent(); 460 SmallVector<MachineInstr*, 4> NewMIs; 461 462 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) { 463 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 464 FuncInfo->setSpillsCR(); 465 } 466 467 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 468 MBB.insert(MI, NewMIs[i]); 469 470 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 471 MachineMemOperand *MMO = 472 MF.getMachineMemOperand( 473 MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)), 474 MachineMemOperand::MOStore, 475 MFI.getObjectSize(FrameIdx), 476 MFI.getObjectAlignment(FrameIdx)); 477 NewMIs.back()->addMemOperand(MF, MMO); 478 } 479 480 void 481 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, 482 unsigned DestReg, int FrameIdx, 483 const TargetRegisterClass *RC, 484 SmallVectorImpl<MachineInstr*> &NewMIs)const{ 485 if (RC == PPC::GPRCRegisterClass) { 486 if (DestReg != PPC::LR) { 487 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 488 DestReg), FrameIdx)); 489 } else { 490 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 491 PPC::R11), FrameIdx)); 492 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11)); 493 } 494 } else if (RC == PPC::G8RCRegisterClass) { 495 if (DestReg != PPC::LR8) { 496 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg), 497 FrameIdx)); 498 } else { 499 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), 500 PPC::R11), FrameIdx)); 501 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11)); 502 } 503 } else if (RC == PPC::F8RCRegisterClass) { 504 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg), 505 FrameIdx)); 506 } else if (RC == PPC::F4RCRegisterClass) { 507 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg), 508 FrameIdx)); 509 } else if (RC == PPC::CRRCRegisterClass) { 510 // FIXME: We need a scatch reg here. The trouble with using R0 is that 511 // it's possible for the stack frame to be so big the save location is 512 // out of range of immediate offsets, necessitating another register. 513 // We hack this on Darwin by reserving R2. It's probably broken on Linux 514 // at the moment. 515 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ? 516 PPC::R2 : PPC::R0; 517 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 518 ScratchReg), FrameIdx)); 519 520 // If the reloaded register isn't CR0, shift the bits right so that they are 521 // in the right CR's slot. 522 if (DestReg != PPC::CR0) { 523 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; 524 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 525 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) 526 .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0) 527 .addImm(31)); 528 } 529 530 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg) 531 .addReg(ScratchReg)); 532 } else if (RC == PPC::CRBITRCRegisterClass) { 533 534 unsigned Reg = 0; 535 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT || 536 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN) 537 Reg = PPC::CR0; 538 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT || 539 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN) 540 Reg = PPC::CR1; 541 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT || 542 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN) 543 Reg = PPC::CR2; 544 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT || 545 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN) 546 Reg = PPC::CR3; 547 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT || 548 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN) 549 Reg = PPC::CR4; 550 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT || 551 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN) 552 Reg = PPC::CR5; 553 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT || 554 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN) 555 Reg = PPC::CR6; 556 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT || 557 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN) 558 Reg = PPC::CR7; 559 560 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx, 561 PPC::CRRCRegisterClass, NewMIs); 562 563 } else if (RC == PPC::VRRCRegisterClass) { 564 // We don't have indexed addressing for vector loads. Emit: 565 // R0 = ADDI FI# 566 // Dest = LVX 0, R0 567 // 568 // FIXME: We use R0 here, because it isn't available for RA. 569 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), 570 FrameIdx, 0, 0)); 571 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0) 572 .addReg(PPC::R0)); 573 } else { 574 llvm_unreachable("Unknown regclass!"); 575 } 576 } 577 578 void 579 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 580 MachineBasicBlock::iterator MI, 581 unsigned DestReg, int FrameIdx, 582 const TargetRegisterClass *RC, 583 const TargetRegisterInfo *TRI) const { 584 MachineFunction &MF = *MBB.getParent(); 585 SmallVector<MachineInstr*, 4> NewMIs; 586 DebugLoc DL; 587 if (MI != MBB.end()) DL = MI->getDebugLoc(); 588 LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs); 589 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 590 MBB.insert(MI, NewMIs[i]); 591 592 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 593 MachineMemOperand *MMO = 594 MF.getMachineMemOperand( 595 MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)), 596 MachineMemOperand::MOLoad, 597 MFI.getObjectSize(FrameIdx), 598 MFI.getObjectAlignment(FrameIdx)); 599 NewMIs.back()->addMemOperand(MF, MMO); 600 } 601 602 MachineInstr* 603 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 604 int FrameIx, uint64_t Offset, 605 const MDNode *MDPtr, 606 DebugLoc DL) const { 607 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE)); 608 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr); 609 return &*MIB; 610 } 611 612 bool PPCInstrInfo:: 613 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 614 assert(Cond.size() == 2 && "Invalid PPC branch opcode!"); 615 // Leave the CR# the same, but invert the condition. 616 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); 617 return false; 618 } 619 620 /// GetInstSize - Return the number of bytes of code the specified 621 /// instruction may be. This returns the maximum number of bytes. 622 /// 623 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 624 switch (MI->getOpcode()) { 625 case PPC::INLINEASM: { // Inline Asm: Variable size. 626 const MachineFunction *MF = MI->getParent()->getParent(); 627 const char *AsmStr = MI->getOperand(0).getSymbolName(); 628 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); 629 } 630 case PPC::PROLOG_LABEL: 631 case PPC::EH_LABEL: 632 case PPC::GC_LABEL: 633 case PPC::DBG_VALUE: 634 return 0; 635 default: 636 return 4; // PowerPC instructions are all 4 bytes 637 } 638 } 639