1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCInstrInfo.h" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCMachineFunctionInfo.h" 18 #include "PPCTargetMachine.h" 19 #include "PPCHazardRecognizers.h" 20 #include "MCTargetDesc/PPCPredicates.h" 21 #include "llvm/CodeGen/MachineFrameInfo.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineMemOperand.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/CodeGen/PseudoSourceValue.h" 26 #include "llvm/MC/MCAsmInfo.h" 27 #include "llvm/Support/CommandLine.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include "llvm/Support/raw_ostream.h" 31 #include "llvm/ADT/STLExtras.h" 32 33 #define GET_INSTRINFO_CTOR 34 #include "PPCGenInstrInfo.inc" 35 36 namespace llvm { 37 extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. 38 extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. 39 } 40 41 using namespace llvm; 42 43 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) 44 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 45 TM(tm), RI(*TM.getSubtargetImpl(), *this) {} 46 47 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for 48 /// this target when scheduling the DAG. 49 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer( 50 const TargetMachine *TM, 51 const ScheduleDAG *DAG) const { 52 // Should use subtarget info to pick the right hazard recognizer. For 53 // now, always return a PPC970 recognizer. 54 const TargetInstrInfo *TII = TM->getInstrInfo(); 55 assert(TII && "No InstrInfo?"); 56 57 unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective(); 58 if (Directive == PPC::DIR_440) { 59 // Disable the hazard recognizer for now, as it doesn't support 60 // bottom-up scheduling. 61 //const InstrItineraryData *II = TM->getInstrItineraryData(); 62 //return new PPCHazardRecognizer440(II, DAG); 63 return new ScheduleHazardRecognizer(); 64 } 65 else { 66 // Disable the hazard recognizer for now, as it doesn't support 67 // bottom-up scheduling. 68 //return new PPCHazardRecognizer970(*TII); 69 return new ScheduleHazardRecognizer(); 70 } 71 } 72 73 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 74 int &FrameIndex) const { 75 switch (MI->getOpcode()) { 76 default: break; 77 case PPC::LD: 78 case PPC::LWZ: 79 case PPC::LFS: 80 case PPC::LFD: 81 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 82 MI->getOperand(2).isFI()) { 83 FrameIndex = MI->getOperand(2).getIndex(); 84 return MI->getOperand(0).getReg(); 85 } 86 break; 87 } 88 return 0; 89 } 90 91 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 92 int &FrameIndex) const { 93 switch (MI->getOpcode()) { 94 default: break; 95 case PPC::STD: 96 case PPC::STW: 97 case PPC::STFS: 98 case PPC::STFD: 99 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 100 MI->getOperand(2).isFI()) { 101 FrameIndex = MI->getOperand(2).getIndex(); 102 return MI->getOperand(0).getReg(); 103 } 104 break; 105 } 106 return 0; 107 } 108 109 // commuteInstruction - We can commute rlwimi instructions, but only if the 110 // rotate amt is zero. We also have to munge the immediates a bit. 111 MachineInstr * 112 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 113 MachineFunction &MF = *MI->getParent()->getParent(); 114 115 // Normal instructions can be commuted the obvious way. 116 if (MI->getOpcode() != PPC::RLWIMI) 117 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 118 119 // Cannot commute if it has a non-zero rotate count. 120 if (MI->getOperand(3).getImm() != 0) 121 return 0; 122 123 // If we have a zero rotate count, we have: 124 // M = mask(MB,ME) 125 // Op0 = (Op1 & ~M) | (Op2 & M) 126 // Change this to: 127 // M = mask((ME+1)&31, (MB-1)&31) 128 // Op0 = (Op2 & ~M) | (Op1 & M) 129 130 // Swap op1/op2 131 unsigned Reg0 = MI->getOperand(0).getReg(); 132 unsigned Reg1 = MI->getOperand(1).getReg(); 133 unsigned Reg2 = MI->getOperand(2).getReg(); 134 bool Reg1IsKill = MI->getOperand(1).isKill(); 135 bool Reg2IsKill = MI->getOperand(2).isKill(); 136 bool ChangeReg0 = false; 137 // If machine instrs are no longer in two-address forms, update 138 // destination register as well. 139 if (Reg0 == Reg1) { 140 // Must be two address instruction! 141 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) && 142 "Expecting a two-address instruction!"); 143 Reg2IsKill = false; 144 ChangeReg0 = true; 145 } 146 147 // Masks. 148 unsigned MB = MI->getOperand(4).getImm(); 149 unsigned ME = MI->getOperand(5).getImm(); 150 151 if (NewMI) { 152 // Create a new instruction. 153 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); 154 bool Reg0IsDead = MI->getOperand(0).isDead(); 155 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 156 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) 157 .addReg(Reg2, getKillRegState(Reg2IsKill)) 158 .addReg(Reg1, getKillRegState(Reg1IsKill)) 159 .addImm((ME+1) & 31) 160 .addImm((MB-1) & 31); 161 } 162 163 if (ChangeReg0) 164 MI->getOperand(0).setReg(Reg2); 165 MI->getOperand(2).setReg(Reg1); 166 MI->getOperand(1).setReg(Reg2); 167 MI->getOperand(2).setIsKill(Reg1IsKill); 168 MI->getOperand(1).setIsKill(Reg2IsKill); 169 170 // Swap the mask around. 171 MI->getOperand(4).setImm((ME+1) & 31); 172 MI->getOperand(5).setImm((MB-1) & 31); 173 return MI; 174 } 175 176 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, 177 MachineBasicBlock::iterator MI) const { 178 DebugLoc DL; 179 BuildMI(MBB, MI, DL, get(PPC::NOP)); 180 } 181 182 183 // Branch analysis. 184 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 185 MachineBasicBlock *&FBB, 186 SmallVectorImpl<MachineOperand> &Cond, 187 bool AllowModify) const { 188 // If the block has no terminators, it just falls into the block after it. 189 MachineBasicBlock::iterator I = MBB.end(); 190 if (I == MBB.begin()) 191 return false; 192 --I; 193 while (I->isDebugValue()) { 194 if (I == MBB.begin()) 195 return false; 196 --I; 197 } 198 if (!isUnpredicatedTerminator(I)) 199 return false; 200 201 // Get the last instruction in the block. 202 MachineInstr *LastInst = I; 203 204 // If there is only one terminator instruction, process it. 205 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 206 if (LastInst->getOpcode() == PPC::B) { 207 if (!LastInst->getOperand(0).isMBB()) 208 return true; 209 TBB = LastInst->getOperand(0).getMBB(); 210 return false; 211 } else if (LastInst->getOpcode() == PPC::BCC) { 212 if (!LastInst->getOperand(2).isMBB()) 213 return true; 214 // Block ends with fall-through condbranch. 215 TBB = LastInst->getOperand(2).getMBB(); 216 Cond.push_back(LastInst->getOperand(0)); 217 Cond.push_back(LastInst->getOperand(1)); 218 return false; 219 } 220 // Otherwise, don't know what this is. 221 return true; 222 } 223 224 // Get the instruction before it if it's a terminator. 225 MachineInstr *SecondLastInst = I; 226 227 // If there are three terminators, we don't know what sort of block this is. 228 if (SecondLastInst && I != MBB.begin() && 229 isUnpredicatedTerminator(--I)) 230 return true; 231 232 // If the block ends with PPC::B and PPC:BCC, handle it. 233 if (SecondLastInst->getOpcode() == PPC::BCC && 234 LastInst->getOpcode() == PPC::B) { 235 if (!SecondLastInst->getOperand(2).isMBB() || 236 !LastInst->getOperand(0).isMBB()) 237 return true; 238 TBB = SecondLastInst->getOperand(2).getMBB(); 239 Cond.push_back(SecondLastInst->getOperand(0)); 240 Cond.push_back(SecondLastInst->getOperand(1)); 241 FBB = LastInst->getOperand(0).getMBB(); 242 return false; 243 } 244 245 // If the block ends with two PPC:Bs, handle it. The second one is not 246 // executed, so remove it. 247 if (SecondLastInst->getOpcode() == PPC::B && 248 LastInst->getOpcode() == PPC::B) { 249 if (!SecondLastInst->getOperand(0).isMBB()) 250 return true; 251 TBB = SecondLastInst->getOperand(0).getMBB(); 252 I = LastInst; 253 if (AllowModify) 254 I->eraseFromParent(); 255 return false; 256 } 257 258 // Otherwise, can't handle this. 259 return true; 260 } 261 262 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 263 MachineBasicBlock::iterator I = MBB.end(); 264 if (I == MBB.begin()) return 0; 265 --I; 266 while (I->isDebugValue()) { 267 if (I == MBB.begin()) 268 return 0; 269 --I; 270 } 271 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC) 272 return 0; 273 274 // Remove the branch. 275 I->eraseFromParent(); 276 277 I = MBB.end(); 278 279 if (I == MBB.begin()) return 1; 280 --I; 281 if (I->getOpcode() != PPC::BCC) 282 return 1; 283 284 // Remove the branch. 285 I->eraseFromParent(); 286 return 2; 287 } 288 289 unsigned 290 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 291 MachineBasicBlock *FBB, 292 const SmallVectorImpl<MachineOperand> &Cond, 293 DebugLoc DL) const { 294 // Shouldn't be a fall through. 295 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 296 assert((Cond.size() == 2 || Cond.size() == 0) && 297 "PPC branch conditions have two components!"); 298 299 // One-way branch. 300 if (FBB == 0) { 301 if (Cond.empty()) // Unconditional branch 302 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); 303 else // Conditional branch 304 BuildMI(&MBB, DL, get(PPC::BCC)) 305 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 306 return 1; 307 } 308 309 // Two-way Conditional Branch. 310 BuildMI(&MBB, DL, get(PPC::BCC)) 311 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 312 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); 313 return 2; 314 } 315 316 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 317 MachineBasicBlock::iterator I, DebugLoc DL, 318 unsigned DestReg, unsigned SrcReg, 319 bool KillSrc) const { 320 unsigned Opc; 321 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) 322 Opc = PPC::OR; 323 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) 324 Opc = PPC::OR8; 325 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) 326 Opc = PPC::FMR; 327 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) 328 Opc = PPC::MCRF; 329 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) 330 Opc = PPC::VOR; 331 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) 332 Opc = PPC::CROR; 333 else 334 llvm_unreachable("Impossible reg-to-reg copy"); 335 336 const MCInstrDesc &MCID = get(Opc); 337 if (MCID.getNumOperands() == 3) 338 BuildMI(MBB, I, DL, MCID, DestReg) 339 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); 340 else 341 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); 342 } 343 344 bool 345 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, 346 unsigned SrcReg, bool isKill, 347 int FrameIdx, 348 const TargetRegisterClass *RC, 349 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 350 DebugLoc DL; 351 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) { 352 if (SrcReg != PPC::LR) { 353 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 354 .addReg(SrcReg, 355 getKillRegState(isKill)), 356 FrameIdx)); 357 } else { 358 // FIXME: this spills LR immediately to memory in one step. To do this, 359 // we use R11, which we know cannot be used in the prolog/epilog. This is 360 // a hack. 361 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11)); 362 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 363 .addReg(PPC::R11, 364 getKillRegState(isKill)), 365 FrameIdx)); 366 } 367 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) { 368 if (SrcReg != PPC::LR8) { 369 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 370 .addReg(SrcReg, 371 getKillRegState(isKill)), 372 FrameIdx)); 373 } else { 374 // FIXME: this spills LR immediately to memory in one step. To do this, 375 // we use R11, which we know cannot be used in the prolog/epilog. This is 376 // a hack. 377 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11)); 378 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 379 .addReg(PPC::X11, 380 getKillRegState(isKill)), 381 FrameIdx)); 382 } 383 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) { 384 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) 385 .addReg(SrcReg, 386 getKillRegState(isKill)), 387 FrameIdx)); 388 } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) { 389 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) 390 .addReg(SrcReg, 391 getKillRegState(isKill)), 392 FrameIdx)); 393 } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) { 394 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || 395 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { 396 // FIXME (64-bit): Enable 397 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) 398 .addReg(SrcReg, 399 getKillRegState(isKill)), 400 FrameIdx)); 401 return true; 402 } else { 403 // FIXME: We need a scatch reg here. The trouble with using R0 is that 404 // it's possible for the stack frame to be so big the save location is 405 // out of range of immediate offsets, necessitating another register. 406 // We hack this on Darwin by reserving R2. It's probably broken on Linux 407 // at the moment. 408 409 // We need to store the CR in the low 4-bits of the saved value. First, 410 // issue a MFCR to save all of the CRBits. 411 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ? 412 PPC::R2 : PPC::R0; 413 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCRpseud), ScratchReg) 414 .addReg(SrcReg, getKillRegState(isKill))); 415 416 // If the saved register wasn't CR0, shift the bits left so that they are 417 // in CR0's slot. 418 if (SrcReg != PPC::CR0) { 419 unsigned ShiftBits = getPPCRegisterNumbering(SrcReg)*4; 420 // rlwinm scratch, scratch, ShiftBits, 0, 31. 421 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) 422 .addReg(ScratchReg).addImm(ShiftBits) 423 .addImm(0).addImm(31)); 424 } 425 426 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 427 .addReg(ScratchReg, 428 getKillRegState(isKill)), 429 FrameIdx)); 430 } 431 } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) { 432 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the 433 // backend currently only uses CR1EQ as an individual bit, this should 434 // not cause any bug. If we need other uses of CR bits, the following 435 // code may be invalid. 436 unsigned Reg = 0; 437 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || 438 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) 439 Reg = PPC::CR0; 440 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || 441 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) 442 Reg = PPC::CR1; 443 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || 444 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) 445 Reg = PPC::CR2; 446 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || 447 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) 448 Reg = PPC::CR3; 449 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || 450 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) 451 Reg = PPC::CR4; 452 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT || 453 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) 454 Reg = PPC::CR5; 455 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT || 456 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) 457 Reg = PPC::CR6; 458 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT || 459 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN) 460 Reg = PPC::CR7; 461 462 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx, 463 PPC::CRRCRegisterClass, NewMIs); 464 465 } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) { 466 // We don't have indexed addressing for vector loads. Emit: 467 // R0 = ADDI FI# 468 // STVX VAL, 0, R0 469 // 470 // FIXME: We use R0 here, because it isn't available for RA. 471 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), 472 FrameIdx, 0, 0)); 473 NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX)) 474 .addReg(SrcReg, getKillRegState(isKill)) 475 .addReg(PPC::R0) 476 .addReg(PPC::R0)); 477 } else { 478 llvm_unreachable("Unknown regclass!"); 479 } 480 481 return false; 482 } 483 484 void 485 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 486 MachineBasicBlock::iterator MI, 487 unsigned SrcReg, bool isKill, int FrameIdx, 488 const TargetRegisterClass *RC, 489 const TargetRegisterInfo *TRI) const { 490 MachineFunction &MF = *MBB.getParent(); 491 SmallVector<MachineInstr*, 4> NewMIs; 492 493 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) { 494 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 495 FuncInfo->setSpillsCR(); 496 } 497 498 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 499 MBB.insert(MI, NewMIs[i]); 500 501 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 502 MachineMemOperand *MMO = 503 MF.getMachineMemOperand( 504 MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)), 505 MachineMemOperand::MOStore, 506 MFI.getObjectSize(FrameIdx), 507 MFI.getObjectAlignment(FrameIdx)); 508 NewMIs.back()->addMemOperand(MF, MMO); 509 } 510 511 void 512 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, 513 unsigned DestReg, int FrameIdx, 514 const TargetRegisterClass *RC, 515 SmallVectorImpl<MachineInstr*> &NewMIs)const{ 516 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) { 517 if (DestReg != PPC::LR) { 518 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 519 DestReg), FrameIdx)); 520 } else { 521 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 522 PPC::R11), FrameIdx)); 523 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11)); 524 } 525 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) { 526 if (DestReg != PPC::LR8) { 527 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg), 528 FrameIdx)); 529 } else { 530 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), 531 PPC::R11), FrameIdx)); 532 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11)); 533 } 534 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) { 535 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg), 536 FrameIdx)); 537 } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) { 538 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg), 539 FrameIdx)); 540 } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) { 541 // FIXME: We need a scatch reg here. The trouble with using R0 is that 542 // it's possible for the stack frame to be so big the save location is 543 // out of range of immediate offsets, necessitating another register. 544 // We hack this on Darwin by reserving R2. It's probably broken on Linux 545 // at the moment. 546 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ? 547 PPC::R2 : PPC::R0; 548 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 549 ScratchReg), FrameIdx)); 550 551 // If the reloaded register isn't CR0, shift the bits right so that they are 552 // in the right CR's slot. 553 if (DestReg != PPC::CR0) { 554 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; 555 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 556 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) 557 .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0) 558 .addImm(31)); 559 } 560 561 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg) 562 .addReg(ScratchReg)); 563 } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) { 564 565 unsigned Reg = 0; 566 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT || 567 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN) 568 Reg = PPC::CR0; 569 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT || 570 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN) 571 Reg = PPC::CR1; 572 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT || 573 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN) 574 Reg = PPC::CR2; 575 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT || 576 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN) 577 Reg = PPC::CR3; 578 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT || 579 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN) 580 Reg = PPC::CR4; 581 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT || 582 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN) 583 Reg = PPC::CR5; 584 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT || 585 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN) 586 Reg = PPC::CR6; 587 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT || 588 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN) 589 Reg = PPC::CR7; 590 591 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx, 592 PPC::CRRCRegisterClass, NewMIs); 593 594 } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) { 595 // We don't have indexed addressing for vector loads. Emit: 596 // R0 = ADDI FI# 597 // Dest = LVX 0, R0 598 // 599 // FIXME: We use R0 here, because it isn't available for RA. 600 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), 601 FrameIdx, 0, 0)); 602 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0) 603 .addReg(PPC::R0)); 604 } else { 605 llvm_unreachable("Unknown regclass!"); 606 } 607 } 608 609 void 610 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 611 MachineBasicBlock::iterator MI, 612 unsigned DestReg, int FrameIdx, 613 const TargetRegisterClass *RC, 614 const TargetRegisterInfo *TRI) const { 615 MachineFunction &MF = *MBB.getParent(); 616 SmallVector<MachineInstr*, 4> NewMIs; 617 DebugLoc DL; 618 if (MI != MBB.end()) DL = MI->getDebugLoc(); 619 LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs); 620 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 621 MBB.insert(MI, NewMIs[i]); 622 623 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 624 MachineMemOperand *MMO = 625 MF.getMachineMemOperand( 626 MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)), 627 MachineMemOperand::MOLoad, 628 MFI.getObjectSize(FrameIdx), 629 MFI.getObjectAlignment(FrameIdx)); 630 NewMIs.back()->addMemOperand(MF, MMO); 631 } 632 633 MachineInstr* 634 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 635 int FrameIx, uint64_t Offset, 636 const MDNode *MDPtr, 637 DebugLoc DL) const { 638 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE)); 639 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr); 640 return &*MIB; 641 } 642 643 bool PPCInstrInfo:: 644 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 645 assert(Cond.size() == 2 && "Invalid PPC branch opcode!"); 646 // Leave the CR# the same, but invert the condition. 647 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); 648 return false; 649 } 650 651 /// GetInstSize - Return the number of bytes of code the specified 652 /// instruction may be. This returns the maximum number of bytes. 653 /// 654 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 655 switch (MI->getOpcode()) { 656 case PPC::INLINEASM: { // Inline Asm: Variable size. 657 const MachineFunction *MF = MI->getParent()->getParent(); 658 const char *AsmStr = MI->getOperand(0).getSymbolName(); 659 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); 660 } 661 case PPC::PROLOG_LABEL: 662 case PPC::EH_LABEL: 663 case PPC::GC_LABEL: 664 case PPC::DBG_VALUE: 665 return 0; 666 default: 667 return 4; // PowerPC instructions are all 4 bytes 668 } 669 } 670