1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCInstrInfo.h" 15 #include "PPCInstrBuilder.h" 16 #include "PPCMachineFunctionInfo.h" 17 #include "PPCPredicates.h" 18 #include "PPCGenInstrInfo.inc" 19 #include "PPCTargetMachine.h" 20 #include "PPCHazardRecognizers.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/CodeGen/MachineFrameInfo.h" 23 #include "llvm/CodeGen/MachineInstrBuilder.h" 24 #include "llvm/CodeGen/MachineMemOperand.h" 25 #include "llvm/CodeGen/MachineRegisterInfo.h" 26 #include "llvm/CodeGen/PseudoSourceValue.h" 27 #include "llvm/Support/CommandLine.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/raw_ostream.h" 30 #include "llvm/MC/MCAsmInfo.h" 31 32 namespace llvm { 33 extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. 34 extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. 35 } 36 37 using namespace llvm; 38 39 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) 40 : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm), 41 RI(*TM.getSubtargetImpl(), *this) {} 42 43 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for 44 /// this target when scheduling the DAG. 45 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer( 46 const TargetMachine *TM, 47 const ScheduleDAG *DAG) const { 48 // Should use subtarget info to pick the right hazard recognizer. For 49 // now, always return a PPC970 recognizer. 50 const TargetInstrInfo *TII = TM->getInstrInfo(); 51 assert(TII && "No InstrInfo?"); 52 return new PPCHazardRecognizer970(*TII); 53 } 54 55 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 56 int &FrameIndex) const { 57 switch (MI->getOpcode()) { 58 default: break; 59 case PPC::LD: 60 case PPC::LWZ: 61 case PPC::LFS: 62 case PPC::LFD: 63 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 64 MI->getOperand(2).isFI()) { 65 FrameIndex = MI->getOperand(2).getIndex(); 66 return MI->getOperand(0).getReg(); 67 } 68 break; 69 } 70 return 0; 71 } 72 73 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 74 int &FrameIndex) const { 75 switch (MI->getOpcode()) { 76 default: break; 77 case PPC::STD: 78 case PPC::STW: 79 case PPC::STFS: 80 case PPC::STFD: 81 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 82 MI->getOperand(2).isFI()) { 83 FrameIndex = MI->getOperand(2).getIndex(); 84 return MI->getOperand(0).getReg(); 85 } 86 break; 87 } 88 return 0; 89 } 90 91 // commuteInstruction - We can commute rlwimi instructions, but only if the 92 // rotate amt is zero. We also have to munge the immediates a bit. 93 MachineInstr * 94 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 95 MachineFunction &MF = *MI->getParent()->getParent(); 96 97 // Normal instructions can be commuted the obvious way. 98 if (MI->getOpcode() != PPC::RLWIMI) 99 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 100 101 // Cannot commute if it has a non-zero rotate count. 102 if (MI->getOperand(3).getImm() != 0) 103 return 0; 104 105 // If we have a zero rotate count, we have: 106 // M = mask(MB,ME) 107 // Op0 = (Op1 & ~M) | (Op2 & M) 108 // Change this to: 109 // M = mask((ME+1)&31, (MB-1)&31) 110 // Op0 = (Op2 & ~M) | (Op1 & M) 111 112 // Swap op1/op2 113 unsigned Reg0 = MI->getOperand(0).getReg(); 114 unsigned Reg1 = MI->getOperand(1).getReg(); 115 unsigned Reg2 = MI->getOperand(2).getReg(); 116 bool Reg1IsKill = MI->getOperand(1).isKill(); 117 bool Reg2IsKill = MI->getOperand(2).isKill(); 118 bool ChangeReg0 = false; 119 // If machine instrs are no longer in two-address forms, update 120 // destination register as well. 121 if (Reg0 == Reg1) { 122 // Must be two address instruction! 123 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) && 124 "Expecting a two-address instruction!"); 125 Reg2IsKill = false; 126 ChangeReg0 = true; 127 } 128 129 // Masks. 130 unsigned MB = MI->getOperand(4).getImm(); 131 unsigned ME = MI->getOperand(5).getImm(); 132 133 if (NewMI) { 134 // Create a new instruction. 135 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); 136 bool Reg0IsDead = MI->getOperand(0).isDead(); 137 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 138 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) 139 .addReg(Reg2, getKillRegState(Reg2IsKill)) 140 .addReg(Reg1, getKillRegState(Reg1IsKill)) 141 .addImm((ME+1) & 31) 142 .addImm((MB-1) & 31); 143 } 144 145 if (ChangeReg0) 146 MI->getOperand(0).setReg(Reg2); 147 MI->getOperand(2).setReg(Reg1); 148 MI->getOperand(1).setReg(Reg2); 149 MI->getOperand(2).setIsKill(Reg1IsKill); 150 MI->getOperand(1).setIsKill(Reg2IsKill); 151 152 // Swap the mask around. 153 MI->getOperand(4).setImm((ME+1) & 31); 154 MI->getOperand(5).setImm((MB-1) & 31); 155 return MI; 156 } 157 158 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, 159 MachineBasicBlock::iterator MI) const { 160 DebugLoc DL; 161 BuildMI(MBB, MI, DL, get(PPC::NOP)); 162 } 163 164 165 // Branch analysis. 166 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 167 MachineBasicBlock *&FBB, 168 SmallVectorImpl<MachineOperand> &Cond, 169 bool AllowModify) const { 170 // If the block has no terminators, it just falls into the block after it. 171 MachineBasicBlock::iterator I = MBB.end(); 172 if (I == MBB.begin()) 173 return false; 174 --I; 175 while (I->isDebugValue()) { 176 if (I == MBB.begin()) 177 return false; 178 --I; 179 } 180 if (!isUnpredicatedTerminator(I)) 181 return false; 182 183 // Get the last instruction in the block. 184 MachineInstr *LastInst = I; 185 186 // If there is only one terminator instruction, process it. 187 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 188 if (LastInst->getOpcode() == PPC::B) { 189 if (!LastInst->getOperand(0).isMBB()) 190 return true; 191 TBB = LastInst->getOperand(0).getMBB(); 192 return false; 193 } else if (LastInst->getOpcode() == PPC::BCC) { 194 if (!LastInst->getOperand(2).isMBB()) 195 return true; 196 // Block ends with fall-through condbranch. 197 TBB = LastInst->getOperand(2).getMBB(); 198 Cond.push_back(LastInst->getOperand(0)); 199 Cond.push_back(LastInst->getOperand(1)); 200 return false; 201 } 202 // Otherwise, don't know what this is. 203 return true; 204 } 205 206 // Get the instruction before it if it's a terminator. 207 MachineInstr *SecondLastInst = I; 208 209 // If there are three terminators, we don't know what sort of block this is. 210 if (SecondLastInst && I != MBB.begin() && 211 isUnpredicatedTerminator(--I)) 212 return true; 213 214 // If the block ends with PPC::B and PPC:BCC, handle it. 215 if (SecondLastInst->getOpcode() == PPC::BCC && 216 LastInst->getOpcode() == PPC::B) { 217 if (!SecondLastInst->getOperand(2).isMBB() || 218 !LastInst->getOperand(0).isMBB()) 219 return true; 220 TBB = SecondLastInst->getOperand(2).getMBB(); 221 Cond.push_back(SecondLastInst->getOperand(0)); 222 Cond.push_back(SecondLastInst->getOperand(1)); 223 FBB = LastInst->getOperand(0).getMBB(); 224 return false; 225 } 226 227 // If the block ends with two PPC:Bs, handle it. The second one is not 228 // executed, so remove it. 229 if (SecondLastInst->getOpcode() == PPC::B && 230 LastInst->getOpcode() == PPC::B) { 231 if (!SecondLastInst->getOperand(0).isMBB()) 232 return true; 233 TBB = SecondLastInst->getOperand(0).getMBB(); 234 I = LastInst; 235 if (AllowModify) 236 I->eraseFromParent(); 237 return false; 238 } 239 240 // Otherwise, can't handle this. 241 return true; 242 } 243 244 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 245 MachineBasicBlock::iterator I = MBB.end(); 246 if (I == MBB.begin()) return 0; 247 --I; 248 while (I->isDebugValue()) { 249 if (I == MBB.begin()) 250 return 0; 251 --I; 252 } 253 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC) 254 return 0; 255 256 // Remove the branch. 257 I->eraseFromParent(); 258 259 I = MBB.end(); 260 261 if (I == MBB.begin()) return 1; 262 --I; 263 if (I->getOpcode() != PPC::BCC) 264 return 1; 265 266 // Remove the branch. 267 I->eraseFromParent(); 268 return 2; 269 } 270 271 unsigned 272 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 273 MachineBasicBlock *FBB, 274 const SmallVectorImpl<MachineOperand> &Cond, 275 DebugLoc DL) const { 276 // Shouldn't be a fall through. 277 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 278 assert((Cond.size() == 2 || Cond.size() == 0) && 279 "PPC branch conditions have two components!"); 280 281 // One-way branch. 282 if (FBB == 0) { 283 if (Cond.empty()) // Unconditional branch 284 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); 285 else // Conditional branch 286 BuildMI(&MBB, DL, get(PPC::BCC)) 287 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 288 return 1; 289 } 290 291 // Two-way Conditional Branch. 292 BuildMI(&MBB, DL, get(PPC::BCC)) 293 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 294 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); 295 return 2; 296 } 297 298 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 299 MachineBasicBlock::iterator I, DebugLoc DL, 300 unsigned DestReg, unsigned SrcReg, 301 bool KillSrc) const { 302 unsigned Opc; 303 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) 304 Opc = PPC::OR; 305 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) 306 Opc = PPC::OR8; 307 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) 308 Opc = PPC::FMR; 309 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) 310 Opc = PPC::MCRF; 311 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) 312 Opc = PPC::VOR; 313 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) 314 Opc = PPC::CROR; 315 else 316 llvm_unreachable("Impossible reg-to-reg copy"); 317 318 const TargetInstrDesc &TID = get(Opc); 319 if (TID.getNumOperands() == 3) 320 BuildMI(MBB, I, DL, TID, DestReg) 321 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); 322 else 323 BuildMI(MBB, I, DL, TID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); 324 } 325 326 bool 327 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, 328 unsigned SrcReg, bool isKill, 329 int FrameIdx, 330 const TargetRegisterClass *RC, 331 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 332 DebugLoc DL; 333 if (RC == PPC::GPRCRegisterClass) { 334 if (SrcReg != PPC::LR) { 335 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 336 .addReg(SrcReg, 337 getKillRegState(isKill)), 338 FrameIdx)); 339 } else { 340 // FIXME: this spills LR immediately to memory in one step. To do this, 341 // we use R11, which we know cannot be used in the prolog/epilog. This is 342 // a hack. 343 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11)); 344 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 345 .addReg(PPC::R11, 346 getKillRegState(isKill)), 347 FrameIdx)); 348 } 349 } else if (RC == PPC::G8RCRegisterClass) { 350 if (SrcReg != PPC::LR8) { 351 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 352 .addReg(SrcReg, 353 getKillRegState(isKill)), 354 FrameIdx)); 355 } else { 356 // FIXME: this spills LR immediately to memory in one step. To do this, 357 // we use R11, which we know cannot be used in the prolog/epilog. This is 358 // a hack. 359 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11)); 360 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 361 .addReg(PPC::X11, 362 getKillRegState(isKill)), 363 FrameIdx)); 364 } 365 } else if (RC == PPC::F8RCRegisterClass) { 366 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) 367 .addReg(SrcReg, 368 getKillRegState(isKill)), 369 FrameIdx)); 370 } else if (RC == PPC::F4RCRegisterClass) { 371 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) 372 .addReg(SrcReg, 373 getKillRegState(isKill)), 374 FrameIdx)); 375 } else if (RC == PPC::CRRCRegisterClass) { 376 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || 377 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { 378 // FIXME (64-bit): Enable 379 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) 380 .addReg(SrcReg, 381 getKillRegState(isKill)), 382 FrameIdx)); 383 return true; 384 } else { 385 // FIXME: We need a scatch reg here. The trouble with using R0 is that 386 // it's possible for the stack frame to be so big the save location is 387 // out of range of immediate offsets, necessitating another register. 388 // We hack this on Darwin by reserving R2. It's probably broken on Linux 389 // at the moment. 390 391 // We need to store the CR in the low 4-bits of the saved value. First, 392 // issue a MFCR to save all of the CRBits. 393 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ? 394 PPC::R2 : PPC::R0; 395 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCRpseud), ScratchReg) 396 .addReg(SrcReg, getKillRegState(isKill))); 397 398 // If the saved register wasn't CR0, shift the bits left so that they are 399 // in CR0's slot. 400 if (SrcReg != PPC::CR0) { 401 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; 402 // rlwinm scratch, scratch, ShiftBits, 0, 31. 403 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) 404 .addReg(ScratchReg).addImm(ShiftBits) 405 .addImm(0).addImm(31)); 406 } 407 408 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 409 .addReg(ScratchReg, 410 getKillRegState(isKill)), 411 FrameIdx)); 412 } 413 } else if (RC == PPC::CRBITRCRegisterClass) { 414 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the 415 // backend currently only uses CR1EQ as an individual bit, this should 416 // not cause any bug. If we need other uses of CR bits, the following 417 // code may be invalid. 418 unsigned Reg = 0; 419 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || 420 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) 421 Reg = PPC::CR0; 422 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || 423 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) 424 Reg = PPC::CR1; 425 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || 426 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) 427 Reg = PPC::CR2; 428 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || 429 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) 430 Reg = PPC::CR3; 431 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || 432 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) 433 Reg = PPC::CR4; 434 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT || 435 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) 436 Reg = PPC::CR5; 437 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT || 438 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) 439 Reg = PPC::CR6; 440 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT || 441 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN) 442 Reg = PPC::CR7; 443 444 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx, 445 PPC::CRRCRegisterClass, NewMIs); 446 447 } else if (RC == PPC::VRRCRegisterClass) { 448 // We don't have indexed addressing for vector loads. Emit: 449 // R0 = ADDI FI# 450 // STVX VAL, 0, R0 451 // 452 // FIXME: We use R0 here, because it isn't available for RA. 453 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), 454 FrameIdx, 0, 0)); 455 NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX)) 456 .addReg(SrcReg, getKillRegState(isKill)) 457 .addReg(PPC::R0) 458 .addReg(PPC::R0)); 459 } else { 460 llvm_unreachable("Unknown regclass!"); 461 } 462 463 return false; 464 } 465 466 void 467 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 468 MachineBasicBlock::iterator MI, 469 unsigned SrcReg, bool isKill, int FrameIdx, 470 const TargetRegisterClass *RC, 471 const TargetRegisterInfo *TRI) const { 472 MachineFunction &MF = *MBB.getParent(); 473 SmallVector<MachineInstr*, 4> NewMIs; 474 475 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) { 476 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 477 FuncInfo->setSpillsCR(); 478 } 479 480 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 481 MBB.insert(MI, NewMIs[i]); 482 483 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 484 MachineMemOperand *MMO = 485 MF.getMachineMemOperand( 486 MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)), 487 MachineMemOperand::MOStore, 488 MFI.getObjectSize(FrameIdx), 489 MFI.getObjectAlignment(FrameIdx)); 490 NewMIs.back()->addMemOperand(MF, MMO); 491 } 492 493 void 494 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, 495 unsigned DestReg, int FrameIdx, 496 const TargetRegisterClass *RC, 497 SmallVectorImpl<MachineInstr*> &NewMIs)const{ 498 if (RC == PPC::GPRCRegisterClass) { 499 if (DestReg != PPC::LR) { 500 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 501 DestReg), FrameIdx)); 502 } else { 503 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 504 PPC::R11), FrameIdx)); 505 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11)); 506 } 507 } else if (RC == PPC::G8RCRegisterClass) { 508 if (DestReg != PPC::LR8) { 509 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg), 510 FrameIdx)); 511 } else { 512 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), 513 PPC::R11), FrameIdx)); 514 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11)); 515 } 516 } else if (RC == PPC::F8RCRegisterClass) { 517 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg), 518 FrameIdx)); 519 } else if (RC == PPC::F4RCRegisterClass) { 520 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg), 521 FrameIdx)); 522 } else if (RC == PPC::CRRCRegisterClass) { 523 // FIXME: We need a scatch reg here. The trouble with using R0 is that 524 // it's possible for the stack frame to be so big the save location is 525 // out of range of immediate offsets, necessitating another register. 526 // We hack this on Darwin by reserving R2. It's probably broken on Linux 527 // at the moment. 528 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ? 529 PPC::R2 : PPC::R0; 530 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 531 ScratchReg), FrameIdx)); 532 533 // If the reloaded register isn't CR0, shift the bits right so that they are 534 // in the right CR's slot. 535 if (DestReg != PPC::CR0) { 536 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; 537 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 538 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) 539 .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0) 540 .addImm(31)); 541 } 542 543 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg) 544 .addReg(ScratchReg)); 545 } else if (RC == PPC::CRBITRCRegisterClass) { 546 547 unsigned Reg = 0; 548 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT || 549 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN) 550 Reg = PPC::CR0; 551 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT || 552 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN) 553 Reg = PPC::CR1; 554 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT || 555 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN) 556 Reg = PPC::CR2; 557 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT || 558 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN) 559 Reg = PPC::CR3; 560 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT || 561 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN) 562 Reg = PPC::CR4; 563 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT || 564 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN) 565 Reg = PPC::CR5; 566 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT || 567 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN) 568 Reg = PPC::CR6; 569 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT || 570 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN) 571 Reg = PPC::CR7; 572 573 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx, 574 PPC::CRRCRegisterClass, NewMIs); 575 576 } else if (RC == PPC::VRRCRegisterClass) { 577 // We don't have indexed addressing for vector loads. Emit: 578 // R0 = ADDI FI# 579 // Dest = LVX 0, R0 580 // 581 // FIXME: We use R0 here, because it isn't available for RA. 582 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), 583 FrameIdx, 0, 0)); 584 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0) 585 .addReg(PPC::R0)); 586 } else { 587 llvm_unreachable("Unknown regclass!"); 588 } 589 } 590 591 void 592 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 593 MachineBasicBlock::iterator MI, 594 unsigned DestReg, int FrameIdx, 595 const TargetRegisterClass *RC, 596 const TargetRegisterInfo *TRI) const { 597 MachineFunction &MF = *MBB.getParent(); 598 SmallVector<MachineInstr*, 4> NewMIs; 599 DebugLoc DL; 600 if (MI != MBB.end()) DL = MI->getDebugLoc(); 601 LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs); 602 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 603 MBB.insert(MI, NewMIs[i]); 604 605 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 606 MachineMemOperand *MMO = 607 MF.getMachineMemOperand( 608 MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)), 609 MachineMemOperand::MOLoad, 610 MFI.getObjectSize(FrameIdx), 611 MFI.getObjectAlignment(FrameIdx)); 612 NewMIs.back()->addMemOperand(MF, MMO); 613 } 614 615 MachineInstr* 616 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 617 int FrameIx, uint64_t Offset, 618 const MDNode *MDPtr, 619 DebugLoc DL) const { 620 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE)); 621 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr); 622 return &*MIB; 623 } 624 625 bool PPCInstrInfo:: 626 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 627 assert(Cond.size() == 2 && "Invalid PPC branch opcode!"); 628 // Leave the CR# the same, but invert the condition. 629 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); 630 return false; 631 } 632 633 /// GetInstSize - Return the number of bytes of code the specified 634 /// instruction may be. This returns the maximum number of bytes. 635 /// 636 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 637 switch (MI->getOpcode()) { 638 case PPC::INLINEASM: { // Inline Asm: Variable size. 639 const MachineFunction *MF = MI->getParent()->getParent(); 640 const char *AsmStr = MI->getOperand(0).getSymbolName(); 641 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); 642 } 643 case PPC::PROLOG_LABEL: 644 case PPC::EH_LABEL: 645 case PPC::GC_LABEL: 646 case PPC::DBG_VALUE: 647 return 0; 648 default: 649 return 4; // PowerPC instructions are all 4 bytes 650 } 651 } 652