1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCInstrInfo.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPredicates.h"
18 #include "PPCGenInstrInfo.inc"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 
28 namespace llvm {
29 extern cl::opt<bool> EnablePPC32RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
30 extern cl::opt<bool> EnablePPC64RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
31 }
32 
33 using namespace llvm;
34 
35 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
36   : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
37     RI(*TM.getSubtargetImpl(), *this) {}
38 
39 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
40                                unsigned& sourceReg,
41                                unsigned& destReg,
42                                unsigned& sourceSubIdx,
43                                unsigned& destSubIdx) const {
44   sourceSubIdx = destSubIdx = 0; // No sub-registers.
45 
46   unsigned oc = MI.getOpcode();
47   if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
48       oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
49     assert(MI.getNumOperands() >= 3 &&
50            MI.getOperand(0).isReg() &&
51            MI.getOperand(1).isReg() &&
52            MI.getOperand(2).isReg() &&
53            "invalid PPC OR instruction!");
54     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
55       sourceReg = MI.getOperand(1).getReg();
56       destReg = MI.getOperand(0).getReg();
57       return true;
58     }
59   } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
60     assert(MI.getNumOperands() >= 3 &&
61            MI.getOperand(0).isReg() &&
62            MI.getOperand(2).isImm() &&
63            "invalid PPC ADDI instruction!");
64     if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
65       sourceReg = MI.getOperand(1).getReg();
66       destReg = MI.getOperand(0).getReg();
67       return true;
68     }
69   } else if (oc == PPC::ORI) {             // ori r1, r2, 0
70     assert(MI.getNumOperands() >= 3 &&
71            MI.getOperand(0).isReg() &&
72            MI.getOperand(1).isReg() &&
73            MI.getOperand(2).isImm() &&
74            "invalid PPC ORI instruction!");
75     if (MI.getOperand(2).getImm() == 0) {
76       sourceReg = MI.getOperand(1).getReg();
77       destReg = MI.getOperand(0).getReg();
78       return true;
79     }
80   } else if (oc == PPC::FMR || oc == PPC::FMRSD) { // fmr r1, r2
81     assert(MI.getNumOperands() >= 2 &&
82            MI.getOperand(0).isReg() &&
83            MI.getOperand(1).isReg() &&
84            "invalid PPC FMR instruction");
85     sourceReg = MI.getOperand(1).getReg();
86     destReg = MI.getOperand(0).getReg();
87     return true;
88   } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
89     assert(MI.getNumOperands() >= 2 &&
90            MI.getOperand(0).isReg() &&
91            MI.getOperand(1).isReg() &&
92            "invalid PPC MCRF instruction");
93     sourceReg = MI.getOperand(1).getReg();
94     destReg = MI.getOperand(0).getReg();
95     return true;
96   }
97   return false;
98 }
99 
100 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
101                                            int &FrameIndex) const {
102   switch (MI->getOpcode()) {
103   default: break;
104   case PPC::LD:
105   case PPC::LWZ:
106   case PPC::LFS:
107   case PPC::LFD:
108     if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
109         MI->getOperand(2).isFI()) {
110       FrameIndex = MI->getOperand(2).getIndex();
111       return MI->getOperand(0).getReg();
112     }
113     break;
114   }
115   return 0;
116 }
117 
118 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
119                                           int &FrameIndex) const {
120   switch (MI->getOpcode()) {
121   default: break;
122   case PPC::STD:
123   case PPC::STW:
124   case PPC::STFS:
125   case PPC::STFD:
126     if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
127         MI->getOperand(2).isFI()) {
128       FrameIndex = MI->getOperand(2).getIndex();
129       return MI->getOperand(0).getReg();
130     }
131     break;
132   }
133   return 0;
134 }
135 
136 // commuteInstruction - We can commute rlwimi instructions, but only if the
137 // rotate amt is zero.  We also have to munge the immediates a bit.
138 MachineInstr *
139 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
140   MachineFunction &MF = *MI->getParent()->getParent();
141 
142   // Normal instructions can be commuted the obvious way.
143   if (MI->getOpcode() != PPC::RLWIMI)
144     return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
145 
146   // Cannot commute if it has a non-zero rotate count.
147   if (MI->getOperand(3).getImm() != 0)
148     return 0;
149 
150   // If we have a zero rotate count, we have:
151   //   M = mask(MB,ME)
152   //   Op0 = (Op1 & ~M) | (Op2 & M)
153   // Change this to:
154   //   M = mask((ME+1)&31, (MB-1)&31)
155   //   Op0 = (Op2 & ~M) | (Op1 & M)
156 
157   // Swap op1/op2
158   unsigned Reg0 = MI->getOperand(0).getReg();
159   unsigned Reg1 = MI->getOperand(1).getReg();
160   unsigned Reg2 = MI->getOperand(2).getReg();
161   bool Reg1IsKill = MI->getOperand(1).isKill();
162   bool Reg2IsKill = MI->getOperand(2).isKill();
163   bool ChangeReg0 = false;
164   // If machine instrs are no longer in two-address forms, update
165   // destination register as well.
166   if (Reg0 == Reg1) {
167     // Must be two address instruction!
168     assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
169            "Expecting a two-address instruction!");
170     Reg2IsKill = false;
171     ChangeReg0 = true;
172   }
173 
174   // Masks.
175   unsigned MB = MI->getOperand(4).getImm();
176   unsigned ME = MI->getOperand(5).getImm();
177 
178   if (NewMI) {
179     // Create a new instruction.
180     unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
181     bool Reg0IsDead = MI->getOperand(0).isDead();
182     return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
183       .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
184       .addReg(Reg2, getKillRegState(Reg2IsKill))
185       .addReg(Reg1, getKillRegState(Reg1IsKill))
186       .addImm((ME+1) & 31)
187       .addImm((MB-1) & 31);
188   }
189 
190   if (ChangeReg0)
191     MI->getOperand(0).setReg(Reg2);
192   MI->getOperand(2).setReg(Reg1);
193   MI->getOperand(1).setReg(Reg2);
194   MI->getOperand(2).setIsKill(Reg1IsKill);
195   MI->getOperand(1).setIsKill(Reg2IsKill);
196 
197   // Swap the mask around.
198   MI->getOperand(4).setImm((ME+1) & 31);
199   MI->getOperand(5).setImm((MB-1) & 31);
200   return MI;
201 }
202 
203 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
204                               MachineBasicBlock::iterator MI) const {
205   DebugLoc DL;
206   BuildMI(MBB, MI, DL, get(PPC::NOP));
207 }
208 
209 
210 // Branch analysis.
211 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
212                                  MachineBasicBlock *&FBB,
213                                  SmallVectorImpl<MachineOperand> &Cond,
214                                  bool AllowModify) const {
215   // If the block has no terminators, it just falls into the block after it.
216   MachineBasicBlock::iterator I = MBB.end();
217   if (I == MBB.begin())
218     return false;
219   --I;
220   while (I->isDebugValue()) {
221     if (I == MBB.begin())
222       return false;
223     --I;
224   }
225   if (!isUnpredicatedTerminator(I))
226     return false;
227 
228   // Get the last instruction in the block.
229   MachineInstr *LastInst = I;
230 
231   // If there is only one terminator instruction, process it.
232   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
233     if (LastInst->getOpcode() == PPC::B) {
234       if (!LastInst->getOperand(0).isMBB())
235         return true;
236       TBB = LastInst->getOperand(0).getMBB();
237       return false;
238     } else if (LastInst->getOpcode() == PPC::BCC) {
239       if (!LastInst->getOperand(2).isMBB())
240         return true;
241       // Block ends with fall-through condbranch.
242       TBB = LastInst->getOperand(2).getMBB();
243       Cond.push_back(LastInst->getOperand(0));
244       Cond.push_back(LastInst->getOperand(1));
245       return false;
246     }
247     // Otherwise, don't know what this is.
248     return true;
249   }
250 
251   // Get the instruction before it if it's a terminator.
252   MachineInstr *SecondLastInst = I;
253 
254   // If there are three terminators, we don't know what sort of block this is.
255   if (SecondLastInst && I != MBB.begin() &&
256       isUnpredicatedTerminator(--I))
257     return true;
258 
259   // If the block ends with PPC::B and PPC:BCC, handle it.
260   if (SecondLastInst->getOpcode() == PPC::BCC &&
261       LastInst->getOpcode() == PPC::B) {
262     if (!SecondLastInst->getOperand(2).isMBB() ||
263         !LastInst->getOperand(0).isMBB())
264       return true;
265     TBB =  SecondLastInst->getOperand(2).getMBB();
266     Cond.push_back(SecondLastInst->getOperand(0));
267     Cond.push_back(SecondLastInst->getOperand(1));
268     FBB = LastInst->getOperand(0).getMBB();
269     return false;
270   }
271 
272   // If the block ends with two PPC:Bs, handle it.  The second one is not
273   // executed, so remove it.
274   if (SecondLastInst->getOpcode() == PPC::B &&
275       LastInst->getOpcode() == PPC::B) {
276     if (!SecondLastInst->getOperand(0).isMBB())
277       return true;
278     TBB = SecondLastInst->getOperand(0).getMBB();
279     I = LastInst;
280     if (AllowModify)
281       I->eraseFromParent();
282     return false;
283   }
284 
285   // Otherwise, can't handle this.
286   return true;
287 }
288 
289 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
290   MachineBasicBlock::iterator I = MBB.end();
291   if (I == MBB.begin()) return 0;
292   --I;
293   while (I->isDebugValue()) {
294     if (I == MBB.begin())
295       return 0;
296     --I;
297   }
298   if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
299     return 0;
300 
301   // Remove the branch.
302   I->eraseFromParent();
303 
304   I = MBB.end();
305 
306   if (I == MBB.begin()) return 1;
307   --I;
308   if (I->getOpcode() != PPC::BCC)
309     return 1;
310 
311   // Remove the branch.
312   I->eraseFromParent();
313   return 2;
314 }
315 
316 unsigned
317 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
318                            MachineBasicBlock *FBB,
319                            const SmallVectorImpl<MachineOperand> &Cond,
320                            DebugLoc DL) const {
321   // Shouldn't be a fall through.
322   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
323   assert((Cond.size() == 2 || Cond.size() == 0) &&
324          "PPC branch conditions have two components!");
325 
326   // One-way branch.
327   if (FBB == 0) {
328     if (Cond.empty())   // Unconditional branch
329       BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
330     else                // Conditional branch
331       BuildMI(&MBB, DL, get(PPC::BCC))
332         .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
333     return 1;
334   }
335 
336   // Two-way Conditional Branch.
337   BuildMI(&MBB, DL, get(PPC::BCC))
338     .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
339   BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
340   return 2;
341 }
342 
343 bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
344                                    MachineBasicBlock::iterator MI,
345                                    unsigned DestReg, unsigned SrcReg,
346                                    const TargetRegisterClass *DestRC,
347                                    const TargetRegisterClass *SrcRC,
348                                    DebugLoc DL) const {
349   if (DestRC != SrcRC) {
350     // Not yet supported!
351     return false;
352   }
353 
354   if (DestRC == PPC::GPRCRegisterClass) {
355     BuildMI(MBB, MI, DL, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
356   } else if (DestRC == PPC::G8RCRegisterClass) {
357     BuildMI(MBB, MI, DL, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
358   } else if (DestRC == PPC::F4RCRegisterClass ||
359              DestRC == PPC::F8RCRegisterClass) {
360     BuildMI(MBB, MI, DL, get(PPC::FMR), DestReg).addReg(SrcReg);
361   } else if (DestRC == PPC::CRRCRegisterClass) {
362     BuildMI(MBB, MI, DL, get(PPC::MCRF), DestReg).addReg(SrcReg);
363   } else if (DestRC == PPC::VRRCRegisterClass) {
364     BuildMI(MBB, MI, DL, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
365   } else if (DestRC == PPC::CRBITRCRegisterClass) {
366     BuildMI(MBB, MI, DL, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
367   } else {
368     // Attempt to copy register that is not GPR or FPR
369     return false;
370   }
371 
372   return true;
373 }
374 
375 bool
376 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
377                                   unsigned SrcReg, bool isKill,
378                                   int FrameIdx,
379                                   const TargetRegisterClass *RC,
380                                   SmallVectorImpl<MachineInstr*> &NewMIs) const{
381   DebugLoc DL;
382   if (RC == PPC::GPRCRegisterClass) {
383     if (SrcReg != PPC::LR) {
384       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
385                                          .addReg(SrcReg,
386                                                  getKillRegState(isKill)),
387                                          FrameIdx));
388     } else {
389       // FIXME: this spills LR immediately to memory in one step.  To do this,
390       // we use R11, which we know cannot be used in the prolog/epilog.  This is
391       // a hack.
392       NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
393       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
394                                          .addReg(PPC::R11,
395                                                  getKillRegState(isKill)),
396                                          FrameIdx));
397     }
398   } else if (RC == PPC::G8RCRegisterClass) {
399     if (SrcReg != PPC::LR8) {
400       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
401                                          .addReg(SrcReg,
402                                                  getKillRegState(isKill)),
403                                          FrameIdx));
404     } else {
405       // FIXME: this spills LR immediately to memory in one step.  To do this,
406       // we use R11, which we know cannot be used in the prolog/epilog.  This is
407       // a hack.
408       NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
409       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
410                                          .addReg(PPC::X11,
411                                                  getKillRegState(isKill)),
412                                          FrameIdx));
413     }
414   } else if (RC == PPC::F8RCRegisterClass) {
415     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
416                                        .addReg(SrcReg,
417                                                getKillRegState(isKill)),
418                                        FrameIdx));
419   } else if (RC == PPC::F4RCRegisterClass) {
420     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
421                                        .addReg(SrcReg,
422                                                getKillRegState(isKill)),
423                                        FrameIdx));
424   } else if (RC == PPC::CRRCRegisterClass) {
425     if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
426         (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
427       // FIXME (64-bit): Enable
428       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
429                                          .addReg(SrcReg,
430                                                  getKillRegState(isKill)),
431                                          FrameIdx));
432       return true;
433     } else {
434       // FIXME: We need a scatch reg here.  The trouble with using R0 is that
435       // it's possible for the stack frame to be so big the save location is
436       // out of range of immediate offsets, necessitating another register.
437       // We hack this on Darwin by reserving R2.  It's probably broken on Linux
438       // at the moment.
439 
440       // We need to store the CR in the low 4-bits of the saved value.  First,
441       // issue a MFCR to save all of the CRBits.
442       unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
443                                                            PPC::R2 : PPC::R0;
444       NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCRpseud), ScratchReg)
445                                .addReg(SrcReg, getKillRegState(isKill)));
446 
447       // If the saved register wasn't CR0, shift the bits left so that they are
448       // in CR0's slot.
449       if (SrcReg != PPC::CR0) {
450         unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
451         // rlwinm scratch, scratch, ShiftBits, 0, 31.
452         NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
453                        .addReg(ScratchReg).addImm(ShiftBits)
454                        .addImm(0).addImm(31));
455       }
456 
457       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
458                                          .addReg(ScratchReg,
459                                                  getKillRegState(isKill)),
460                                          FrameIdx));
461     }
462   } else if (RC == PPC::CRBITRCRegisterClass) {
463     // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
464     // backend currently only uses CR1EQ as an individual bit, this should
465     // not cause any bug. If we need other uses of CR bits, the following
466     // code may be invalid.
467     unsigned Reg = 0;
468     if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
469         SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
470       Reg = PPC::CR0;
471     else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
472              SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
473       Reg = PPC::CR1;
474     else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
475              SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
476       Reg = PPC::CR2;
477     else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
478              SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
479       Reg = PPC::CR3;
480     else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
481              SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
482       Reg = PPC::CR4;
483     else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
484              SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
485       Reg = PPC::CR5;
486     else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
487              SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
488       Reg = PPC::CR6;
489     else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
490              SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
491       Reg = PPC::CR7;
492 
493     return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
494                                PPC::CRRCRegisterClass, NewMIs);
495 
496   } else if (RC == PPC::VRRCRegisterClass) {
497     // We don't have indexed addressing for vector loads.  Emit:
498     // R0 = ADDI FI#
499     // STVX VAL, 0, R0
500     //
501     // FIXME: We use R0 here, because it isn't available for RA.
502     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
503                                        FrameIdx, 0, 0));
504     NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
505                      .addReg(SrcReg, getKillRegState(isKill))
506                      .addReg(PPC::R0)
507                      .addReg(PPC::R0));
508   } else {
509     llvm_unreachable("Unknown regclass!");
510   }
511 
512   return false;
513 }
514 
515 void
516 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
517                                   MachineBasicBlock::iterator MI,
518                                   unsigned SrcReg, bool isKill, int FrameIdx,
519                                   const TargetRegisterClass *RC,
520                                   const TargetRegisterInfo *TRI) const {
521   MachineFunction &MF = *MBB.getParent();
522   SmallVector<MachineInstr*, 4> NewMIs;
523 
524   if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
525     PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
526     FuncInfo->setSpillsCR();
527   }
528 
529   for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
530     MBB.insert(MI, NewMIs[i]);
531 }
532 
533 void
534 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
535                                    unsigned DestReg, int FrameIdx,
536                                    const TargetRegisterClass *RC,
537                                    SmallVectorImpl<MachineInstr*> &NewMIs)const{
538   if (RC == PPC::GPRCRegisterClass) {
539     if (DestReg != PPC::LR) {
540       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
541                                                  DestReg), FrameIdx));
542     } else {
543       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
544                                                  PPC::R11), FrameIdx));
545       NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
546     }
547   } else if (RC == PPC::G8RCRegisterClass) {
548     if (DestReg != PPC::LR8) {
549       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
550                                          FrameIdx));
551     } else {
552       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
553                                                  PPC::R11), FrameIdx));
554       NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
555     }
556   } else if (RC == PPC::F8RCRegisterClass) {
557     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
558                                        FrameIdx));
559   } else if (RC == PPC::F4RCRegisterClass) {
560     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
561                                        FrameIdx));
562   } else if (RC == PPC::CRRCRegisterClass) {
563     // FIXME: We need a scatch reg here.  The trouble with using R0 is that
564     // it's possible for the stack frame to be so big the save location is
565     // out of range of immediate offsets, necessitating another register.
566     // We hack this on Darwin by reserving R2.  It's probably broken on Linux
567     // at the moment.
568     unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
569                                                           PPC::R2 : PPC::R0;
570     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
571                                        ScratchReg), FrameIdx));
572 
573     // If the reloaded register isn't CR0, shift the bits right so that they are
574     // in the right CR's slot.
575     if (DestReg != PPC::CR0) {
576       unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
577       // rlwinm r11, r11, 32-ShiftBits, 0, 31.
578       NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
579                     .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
580                     .addImm(31));
581     }
582 
583     NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg)
584                      .addReg(ScratchReg));
585   } else if (RC == PPC::CRBITRCRegisterClass) {
586 
587     unsigned Reg = 0;
588     if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
589         DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
590       Reg = PPC::CR0;
591     else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
592              DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
593       Reg = PPC::CR1;
594     else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
595              DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
596       Reg = PPC::CR2;
597     else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
598              DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
599       Reg = PPC::CR3;
600     else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
601              DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
602       Reg = PPC::CR4;
603     else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
604              DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
605       Reg = PPC::CR5;
606     else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
607              DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
608       Reg = PPC::CR6;
609     else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
610              DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
611       Reg = PPC::CR7;
612 
613     return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
614                                 PPC::CRRCRegisterClass, NewMIs);
615 
616   } else if (RC == PPC::VRRCRegisterClass) {
617     // We don't have indexed addressing for vector loads.  Emit:
618     // R0 = ADDI FI#
619     // Dest = LVX 0, R0
620     //
621     // FIXME: We use R0 here, because it isn't available for RA.
622     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
623                                        FrameIdx, 0, 0));
624     NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
625                      .addReg(PPC::R0));
626   } else {
627     llvm_unreachable("Unknown regclass!");
628   }
629 }
630 
631 void
632 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
633                                    MachineBasicBlock::iterator MI,
634                                    unsigned DestReg, int FrameIdx,
635                                    const TargetRegisterClass *RC,
636                                    const TargetRegisterInfo *TRI) const {
637   MachineFunction &MF = *MBB.getParent();
638   SmallVector<MachineInstr*, 4> NewMIs;
639   DebugLoc DL;
640   if (MI != MBB.end()) DL = MI->getDebugLoc();
641   LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
642   for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
643     MBB.insert(MI, NewMIs[i]);
644 }
645 
646 MachineInstr*
647 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
648                                        int FrameIx, uint64_t Offset,
649                                        const MDNode *MDPtr,
650                                        DebugLoc DL) const {
651   MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
652   addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
653   return &*MIB;
654 }
655 
656 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
657 /// copy instructions, turning them into load/store instructions.
658 MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
659                                                   MachineInstr *MI,
660                                            const SmallVectorImpl<unsigned> &Ops,
661                                                   int FrameIndex) const {
662   if (Ops.size() != 1) return NULL;
663 
664   // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
665   // it takes more than one instruction to store it.
666   unsigned Opc = MI->getOpcode();
667   unsigned OpNum = Ops[0];
668 
669   MachineInstr *NewMI = NULL;
670   if ((Opc == PPC::OR &&
671        MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
672     if (OpNum == 0) {  // move -> store
673       unsigned InReg = MI->getOperand(1).getReg();
674       bool isKill = MI->getOperand(1).isKill();
675       bool isUndef = MI->getOperand(1).isUndef();
676       NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW))
677                                 .addReg(InReg,
678                                         getKillRegState(isKill) |
679                                         getUndefRegState(isUndef)),
680                                 FrameIndex);
681     } else {           // move -> load
682       unsigned OutReg = MI->getOperand(0).getReg();
683       bool isDead = MI->getOperand(0).isDead();
684       bool isUndef = MI->getOperand(0).isUndef();
685       NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ))
686                                 .addReg(OutReg,
687                                         RegState::Define |
688                                         getDeadRegState(isDead) |
689                                         getUndefRegState(isUndef)),
690                                 FrameIndex);
691     }
692   } else if ((Opc == PPC::OR8 &&
693               MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
694     if (OpNum == 0) {  // move -> store
695       unsigned InReg = MI->getOperand(1).getReg();
696       bool isKill = MI->getOperand(1).isKill();
697       bool isUndef = MI->getOperand(1).isUndef();
698       NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD))
699                                 .addReg(InReg,
700                                         getKillRegState(isKill) |
701                                         getUndefRegState(isUndef)),
702                                 FrameIndex);
703     } else {           // move -> load
704       unsigned OutReg = MI->getOperand(0).getReg();
705       bool isDead = MI->getOperand(0).isDead();
706       bool isUndef = MI->getOperand(0).isUndef();
707       NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD))
708                                 .addReg(OutReg,
709                                         RegState::Define |
710                                         getDeadRegState(isDead) |
711                                         getUndefRegState(isUndef)),
712                                 FrameIndex);
713     }
714   } else if (Opc == PPC::FMR || Opc == PPC::FMRSD) {
715     // The register may be F4RC or F8RC, and that determines the memory op.
716     unsigned OrigReg = MI->getOperand(OpNum).getReg();
717     // We cannot tell the register class from a physreg alone.
718     if (TargetRegisterInfo::isPhysicalRegister(OrigReg))
719       return NULL;
720     const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(OrigReg);
721     const bool is64 = RC == PPC::F8RCRegisterClass;
722 
723     if (OpNum == 0) {  // move -> store
724       unsigned InReg = MI->getOperand(1).getReg();
725       bool isKill = MI->getOperand(1).isKill();
726       bool isUndef = MI->getOperand(1).isUndef();
727       NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(),
728                                         get(is64 ? PPC::STFD : PPC::STFS))
729                                 .addReg(InReg,
730                                         getKillRegState(isKill) |
731                                         getUndefRegState(isUndef)),
732                                 FrameIndex);
733     } else {           // move -> load
734       unsigned OutReg = MI->getOperand(0).getReg();
735       bool isDead = MI->getOperand(0).isDead();
736       bool isUndef = MI->getOperand(0).isUndef();
737       NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(),
738                                         get(is64 ? PPC::LFD : PPC::LFS))
739                                 .addReg(OutReg,
740                                         RegState::Define |
741                                         getDeadRegState(isDead) |
742                                         getUndefRegState(isUndef)),
743                                 FrameIndex);
744     }
745   }
746 
747   return NewMI;
748 }
749 
750 bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
751                                   const SmallVectorImpl<unsigned> &Ops) const {
752   if (Ops.size() != 1) return false;
753 
754   // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
755   // it takes more than one instruction to store it.
756   unsigned Opc = MI->getOpcode();
757 
758   if ((Opc == PPC::OR &&
759        MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
760     return true;
761   else if ((Opc == PPC::OR8 &&
762               MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
763     return true;
764   else if (Opc == PPC::FMR || Opc == PPC::FMRSD)
765     return true;
766 
767   return false;
768 }
769 
770 
771 bool PPCInstrInfo::
772 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
773   assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
774   // Leave the CR# the same, but invert the condition.
775   Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
776   return false;
777 }
778 
779 /// GetInstSize - Return the number of bytes of code the specified
780 /// instruction may be.  This returns the maximum number of bytes.
781 ///
782 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
783   switch (MI->getOpcode()) {
784   case PPC::INLINEASM: {       // Inline Asm: Variable size.
785     const MachineFunction *MF = MI->getParent()->getParent();
786     const char *AsmStr = MI->getOperand(0).getSymbolName();
787     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
788   }
789   case PPC::DBG_LABEL:
790   case PPC::EH_LABEL:
791   case PPC::GC_LABEL:
792   case PPC::DBG_VALUE:
793     return 0;
794   default:
795     return 4; // PowerPC instructions are all 4 bytes
796   }
797 }
798