1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCInstrInfo.h"
15 #include "PPC.h"
16 #include "PPCInstrBuilder.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPredicates.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCHazardRecognizers.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/Target/TargetRegistry.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/ADT/STLExtras.h"
32 
33 #define GET_INSTRINFO_CTOR
34 #define GET_INSTRINFO_MC_DESC
35 #include "PPCGenInstrInfo.inc"
36 
37 namespace llvm {
38 extern cl::opt<bool> EnablePPC32RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
39 extern cl::opt<bool> EnablePPC64RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
40 }
41 
42 using namespace llvm;
43 
44 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
45   : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
46     TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
47 
48 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
49 /// this target when scheduling the DAG.
50 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
51   const TargetMachine *TM,
52   const ScheduleDAG *DAG) const {
53   // Should use subtarget info to pick the right hazard recognizer.  For
54   // now, always return a PPC970 recognizer.
55   const TargetInstrInfo *TII = TM->getInstrInfo();
56   assert(TII && "No InstrInfo?");
57   return new PPCHazardRecognizer970(*TII);
58 }
59 
60 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
61                                            int &FrameIndex) const {
62   switch (MI->getOpcode()) {
63   default: break;
64   case PPC::LD:
65   case PPC::LWZ:
66   case PPC::LFS:
67   case PPC::LFD:
68     if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
69         MI->getOperand(2).isFI()) {
70       FrameIndex = MI->getOperand(2).getIndex();
71       return MI->getOperand(0).getReg();
72     }
73     break;
74   }
75   return 0;
76 }
77 
78 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
79                                           int &FrameIndex) const {
80   switch (MI->getOpcode()) {
81   default: break;
82   case PPC::STD:
83   case PPC::STW:
84   case PPC::STFS:
85   case PPC::STFD:
86     if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
87         MI->getOperand(2).isFI()) {
88       FrameIndex = MI->getOperand(2).getIndex();
89       return MI->getOperand(0).getReg();
90     }
91     break;
92   }
93   return 0;
94 }
95 
96 // commuteInstruction - We can commute rlwimi instructions, but only if the
97 // rotate amt is zero.  We also have to munge the immediates a bit.
98 MachineInstr *
99 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
100   MachineFunction &MF = *MI->getParent()->getParent();
101 
102   // Normal instructions can be commuted the obvious way.
103   if (MI->getOpcode() != PPC::RLWIMI)
104     return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
105 
106   // Cannot commute if it has a non-zero rotate count.
107   if (MI->getOperand(3).getImm() != 0)
108     return 0;
109 
110   // If we have a zero rotate count, we have:
111   //   M = mask(MB,ME)
112   //   Op0 = (Op1 & ~M) | (Op2 & M)
113   // Change this to:
114   //   M = mask((ME+1)&31, (MB-1)&31)
115   //   Op0 = (Op2 & ~M) | (Op1 & M)
116 
117   // Swap op1/op2
118   unsigned Reg0 = MI->getOperand(0).getReg();
119   unsigned Reg1 = MI->getOperand(1).getReg();
120   unsigned Reg2 = MI->getOperand(2).getReg();
121   bool Reg1IsKill = MI->getOperand(1).isKill();
122   bool Reg2IsKill = MI->getOperand(2).isKill();
123   bool ChangeReg0 = false;
124   // If machine instrs are no longer in two-address forms, update
125   // destination register as well.
126   if (Reg0 == Reg1) {
127     // Must be two address instruction!
128     assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
129            "Expecting a two-address instruction!");
130     Reg2IsKill = false;
131     ChangeReg0 = true;
132   }
133 
134   // Masks.
135   unsigned MB = MI->getOperand(4).getImm();
136   unsigned ME = MI->getOperand(5).getImm();
137 
138   if (NewMI) {
139     // Create a new instruction.
140     unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
141     bool Reg0IsDead = MI->getOperand(0).isDead();
142     return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
143       .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
144       .addReg(Reg2, getKillRegState(Reg2IsKill))
145       .addReg(Reg1, getKillRegState(Reg1IsKill))
146       .addImm((ME+1) & 31)
147       .addImm((MB-1) & 31);
148   }
149 
150   if (ChangeReg0)
151     MI->getOperand(0).setReg(Reg2);
152   MI->getOperand(2).setReg(Reg1);
153   MI->getOperand(1).setReg(Reg2);
154   MI->getOperand(2).setIsKill(Reg1IsKill);
155   MI->getOperand(1).setIsKill(Reg2IsKill);
156 
157   // Swap the mask around.
158   MI->getOperand(4).setImm((ME+1) & 31);
159   MI->getOperand(5).setImm((MB-1) & 31);
160   return MI;
161 }
162 
163 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
164                               MachineBasicBlock::iterator MI) const {
165   DebugLoc DL;
166   BuildMI(MBB, MI, DL, get(PPC::NOP));
167 }
168 
169 
170 // Branch analysis.
171 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
172                                  MachineBasicBlock *&FBB,
173                                  SmallVectorImpl<MachineOperand> &Cond,
174                                  bool AllowModify) const {
175   // If the block has no terminators, it just falls into the block after it.
176   MachineBasicBlock::iterator I = MBB.end();
177   if (I == MBB.begin())
178     return false;
179   --I;
180   while (I->isDebugValue()) {
181     if (I == MBB.begin())
182       return false;
183     --I;
184   }
185   if (!isUnpredicatedTerminator(I))
186     return false;
187 
188   // Get the last instruction in the block.
189   MachineInstr *LastInst = I;
190 
191   // If there is only one terminator instruction, process it.
192   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
193     if (LastInst->getOpcode() == PPC::B) {
194       if (!LastInst->getOperand(0).isMBB())
195         return true;
196       TBB = LastInst->getOperand(0).getMBB();
197       return false;
198     } else if (LastInst->getOpcode() == PPC::BCC) {
199       if (!LastInst->getOperand(2).isMBB())
200         return true;
201       // Block ends with fall-through condbranch.
202       TBB = LastInst->getOperand(2).getMBB();
203       Cond.push_back(LastInst->getOperand(0));
204       Cond.push_back(LastInst->getOperand(1));
205       return false;
206     }
207     // Otherwise, don't know what this is.
208     return true;
209   }
210 
211   // Get the instruction before it if it's a terminator.
212   MachineInstr *SecondLastInst = I;
213 
214   // If there are three terminators, we don't know what sort of block this is.
215   if (SecondLastInst && I != MBB.begin() &&
216       isUnpredicatedTerminator(--I))
217     return true;
218 
219   // If the block ends with PPC::B and PPC:BCC, handle it.
220   if (SecondLastInst->getOpcode() == PPC::BCC &&
221       LastInst->getOpcode() == PPC::B) {
222     if (!SecondLastInst->getOperand(2).isMBB() ||
223         !LastInst->getOperand(0).isMBB())
224       return true;
225     TBB =  SecondLastInst->getOperand(2).getMBB();
226     Cond.push_back(SecondLastInst->getOperand(0));
227     Cond.push_back(SecondLastInst->getOperand(1));
228     FBB = LastInst->getOperand(0).getMBB();
229     return false;
230   }
231 
232   // If the block ends with two PPC:Bs, handle it.  The second one is not
233   // executed, so remove it.
234   if (SecondLastInst->getOpcode() == PPC::B &&
235       LastInst->getOpcode() == PPC::B) {
236     if (!SecondLastInst->getOperand(0).isMBB())
237       return true;
238     TBB = SecondLastInst->getOperand(0).getMBB();
239     I = LastInst;
240     if (AllowModify)
241       I->eraseFromParent();
242     return false;
243   }
244 
245   // Otherwise, can't handle this.
246   return true;
247 }
248 
249 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
250   MachineBasicBlock::iterator I = MBB.end();
251   if (I == MBB.begin()) return 0;
252   --I;
253   while (I->isDebugValue()) {
254     if (I == MBB.begin())
255       return 0;
256     --I;
257   }
258   if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
259     return 0;
260 
261   // Remove the branch.
262   I->eraseFromParent();
263 
264   I = MBB.end();
265 
266   if (I == MBB.begin()) return 1;
267   --I;
268   if (I->getOpcode() != PPC::BCC)
269     return 1;
270 
271   // Remove the branch.
272   I->eraseFromParent();
273   return 2;
274 }
275 
276 unsigned
277 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
278                            MachineBasicBlock *FBB,
279                            const SmallVectorImpl<MachineOperand> &Cond,
280                            DebugLoc DL) const {
281   // Shouldn't be a fall through.
282   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
283   assert((Cond.size() == 2 || Cond.size() == 0) &&
284          "PPC branch conditions have two components!");
285 
286   // One-way branch.
287   if (FBB == 0) {
288     if (Cond.empty())   // Unconditional branch
289       BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
290     else                // Conditional branch
291       BuildMI(&MBB, DL, get(PPC::BCC))
292         .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
293     return 1;
294   }
295 
296   // Two-way Conditional Branch.
297   BuildMI(&MBB, DL, get(PPC::BCC))
298     .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
299   BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
300   return 2;
301 }
302 
303 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
304                                MachineBasicBlock::iterator I, DebugLoc DL,
305                                unsigned DestReg, unsigned SrcReg,
306                                bool KillSrc) const {
307   unsigned Opc;
308   if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
309     Opc = PPC::OR;
310   else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
311     Opc = PPC::OR8;
312   else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
313     Opc = PPC::FMR;
314   else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
315     Opc = PPC::MCRF;
316   else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
317     Opc = PPC::VOR;
318   else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
319     Opc = PPC::CROR;
320   else
321     llvm_unreachable("Impossible reg-to-reg copy");
322 
323   const MCInstrDesc &MCID = get(Opc);
324   if (MCID.getNumOperands() == 3)
325     BuildMI(MBB, I, DL, MCID, DestReg)
326       .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
327   else
328     BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
329 }
330 
331 bool
332 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
333                                   unsigned SrcReg, bool isKill,
334                                   int FrameIdx,
335                                   const TargetRegisterClass *RC,
336                                   SmallVectorImpl<MachineInstr*> &NewMIs) const{
337   DebugLoc DL;
338   if (RC == PPC::GPRCRegisterClass) {
339     if (SrcReg != PPC::LR) {
340       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
341                                          .addReg(SrcReg,
342                                                  getKillRegState(isKill)),
343                                          FrameIdx));
344     } else {
345       // FIXME: this spills LR immediately to memory in one step.  To do this,
346       // we use R11, which we know cannot be used in the prolog/epilog.  This is
347       // a hack.
348       NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
349       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
350                                          .addReg(PPC::R11,
351                                                  getKillRegState(isKill)),
352                                          FrameIdx));
353     }
354   } else if (RC == PPC::G8RCRegisterClass) {
355     if (SrcReg != PPC::LR8) {
356       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
357                                          .addReg(SrcReg,
358                                                  getKillRegState(isKill)),
359                                          FrameIdx));
360     } else {
361       // FIXME: this spills LR immediately to memory in one step.  To do this,
362       // we use R11, which we know cannot be used in the prolog/epilog.  This is
363       // a hack.
364       NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
365       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
366                                          .addReg(PPC::X11,
367                                                  getKillRegState(isKill)),
368                                          FrameIdx));
369     }
370   } else if (RC == PPC::F8RCRegisterClass) {
371     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
372                                        .addReg(SrcReg,
373                                                getKillRegState(isKill)),
374                                        FrameIdx));
375   } else if (RC == PPC::F4RCRegisterClass) {
376     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
377                                        .addReg(SrcReg,
378                                                getKillRegState(isKill)),
379                                        FrameIdx));
380   } else if (RC == PPC::CRRCRegisterClass) {
381     if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
382         (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
383       // FIXME (64-bit): Enable
384       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
385                                          .addReg(SrcReg,
386                                                  getKillRegState(isKill)),
387                                          FrameIdx));
388       return true;
389     } else {
390       // FIXME: We need a scatch reg here.  The trouble with using R0 is that
391       // it's possible for the stack frame to be so big the save location is
392       // out of range of immediate offsets, necessitating another register.
393       // We hack this on Darwin by reserving R2.  It's probably broken on Linux
394       // at the moment.
395 
396       // We need to store the CR in the low 4-bits of the saved value.  First,
397       // issue a MFCR to save all of the CRBits.
398       unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
399                                                            PPC::R2 : PPC::R0;
400       NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCRpseud), ScratchReg)
401                                .addReg(SrcReg, getKillRegState(isKill)));
402 
403       // If the saved register wasn't CR0, shift the bits left so that they are
404       // in CR0's slot.
405       if (SrcReg != PPC::CR0) {
406         unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
407         // rlwinm scratch, scratch, ShiftBits, 0, 31.
408         NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
409                        .addReg(ScratchReg).addImm(ShiftBits)
410                        .addImm(0).addImm(31));
411       }
412 
413       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
414                                          .addReg(ScratchReg,
415                                                  getKillRegState(isKill)),
416                                          FrameIdx));
417     }
418   } else if (RC == PPC::CRBITRCRegisterClass) {
419     // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
420     // backend currently only uses CR1EQ as an individual bit, this should
421     // not cause any bug. If we need other uses of CR bits, the following
422     // code may be invalid.
423     unsigned Reg = 0;
424     if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
425         SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
426       Reg = PPC::CR0;
427     else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
428              SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
429       Reg = PPC::CR1;
430     else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
431              SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
432       Reg = PPC::CR2;
433     else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
434              SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
435       Reg = PPC::CR3;
436     else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
437              SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
438       Reg = PPC::CR4;
439     else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
440              SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
441       Reg = PPC::CR5;
442     else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
443              SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
444       Reg = PPC::CR6;
445     else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
446              SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
447       Reg = PPC::CR7;
448 
449     return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
450                                PPC::CRRCRegisterClass, NewMIs);
451 
452   } else if (RC == PPC::VRRCRegisterClass) {
453     // We don't have indexed addressing for vector loads.  Emit:
454     // R0 = ADDI FI#
455     // STVX VAL, 0, R0
456     //
457     // FIXME: We use R0 here, because it isn't available for RA.
458     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
459                                        FrameIdx, 0, 0));
460     NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
461                      .addReg(SrcReg, getKillRegState(isKill))
462                      .addReg(PPC::R0)
463                      .addReg(PPC::R0));
464   } else {
465     llvm_unreachable("Unknown regclass!");
466   }
467 
468   return false;
469 }
470 
471 void
472 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
473                                   MachineBasicBlock::iterator MI,
474                                   unsigned SrcReg, bool isKill, int FrameIdx,
475                                   const TargetRegisterClass *RC,
476                                   const TargetRegisterInfo *TRI) const {
477   MachineFunction &MF = *MBB.getParent();
478   SmallVector<MachineInstr*, 4> NewMIs;
479 
480   if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
481     PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
482     FuncInfo->setSpillsCR();
483   }
484 
485   for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
486     MBB.insert(MI, NewMIs[i]);
487 
488   const MachineFrameInfo &MFI = *MF.getFrameInfo();
489   MachineMemOperand *MMO =
490     MF.getMachineMemOperand(
491                 MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
492                             MachineMemOperand::MOStore,
493                             MFI.getObjectSize(FrameIdx),
494                             MFI.getObjectAlignment(FrameIdx));
495   NewMIs.back()->addMemOperand(MF, MMO);
496 }
497 
498 void
499 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
500                                    unsigned DestReg, int FrameIdx,
501                                    const TargetRegisterClass *RC,
502                                    SmallVectorImpl<MachineInstr*> &NewMIs)const{
503   if (RC == PPC::GPRCRegisterClass) {
504     if (DestReg != PPC::LR) {
505       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
506                                                  DestReg), FrameIdx));
507     } else {
508       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
509                                                  PPC::R11), FrameIdx));
510       NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
511     }
512   } else if (RC == PPC::G8RCRegisterClass) {
513     if (DestReg != PPC::LR8) {
514       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
515                                          FrameIdx));
516     } else {
517       NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
518                                                  PPC::R11), FrameIdx));
519       NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
520     }
521   } else if (RC == PPC::F8RCRegisterClass) {
522     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
523                                        FrameIdx));
524   } else if (RC == PPC::F4RCRegisterClass) {
525     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
526                                        FrameIdx));
527   } else if (RC == PPC::CRRCRegisterClass) {
528     // FIXME: We need a scatch reg here.  The trouble with using R0 is that
529     // it's possible for the stack frame to be so big the save location is
530     // out of range of immediate offsets, necessitating another register.
531     // We hack this on Darwin by reserving R2.  It's probably broken on Linux
532     // at the moment.
533     unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
534                                                           PPC::R2 : PPC::R0;
535     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
536                                        ScratchReg), FrameIdx));
537 
538     // If the reloaded register isn't CR0, shift the bits right so that they are
539     // in the right CR's slot.
540     if (DestReg != PPC::CR0) {
541       unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
542       // rlwinm r11, r11, 32-ShiftBits, 0, 31.
543       NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
544                     .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
545                     .addImm(31));
546     }
547 
548     NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg)
549                      .addReg(ScratchReg));
550   } else if (RC == PPC::CRBITRCRegisterClass) {
551 
552     unsigned Reg = 0;
553     if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
554         DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
555       Reg = PPC::CR0;
556     else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
557              DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
558       Reg = PPC::CR1;
559     else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
560              DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
561       Reg = PPC::CR2;
562     else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
563              DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
564       Reg = PPC::CR3;
565     else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
566              DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
567       Reg = PPC::CR4;
568     else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
569              DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
570       Reg = PPC::CR5;
571     else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
572              DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
573       Reg = PPC::CR6;
574     else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
575              DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
576       Reg = PPC::CR7;
577 
578     return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
579                                 PPC::CRRCRegisterClass, NewMIs);
580 
581   } else if (RC == PPC::VRRCRegisterClass) {
582     // We don't have indexed addressing for vector loads.  Emit:
583     // R0 = ADDI FI#
584     // Dest = LVX 0, R0
585     //
586     // FIXME: We use R0 here, because it isn't available for RA.
587     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
588                                        FrameIdx, 0, 0));
589     NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
590                      .addReg(PPC::R0));
591   } else {
592     llvm_unreachable("Unknown regclass!");
593   }
594 }
595 
596 void
597 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
598                                    MachineBasicBlock::iterator MI,
599                                    unsigned DestReg, int FrameIdx,
600                                    const TargetRegisterClass *RC,
601                                    const TargetRegisterInfo *TRI) const {
602   MachineFunction &MF = *MBB.getParent();
603   SmallVector<MachineInstr*, 4> NewMIs;
604   DebugLoc DL;
605   if (MI != MBB.end()) DL = MI->getDebugLoc();
606   LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
607   for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
608     MBB.insert(MI, NewMIs[i]);
609 
610   const MachineFrameInfo &MFI = *MF.getFrameInfo();
611   MachineMemOperand *MMO =
612     MF.getMachineMemOperand(
613                 MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
614                             MachineMemOperand::MOLoad,
615                             MFI.getObjectSize(FrameIdx),
616                             MFI.getObjectAlignment(FrameIdx));
617   NewMIs.back()->addMemOperand(MF, MMO);
618 }
619 
620 MachineInstr*
621 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
622                                        int FrameIx, uint64_t Offset,
623                                        const MDNode *MDPtr,
624                                        DebugLoc DL) const {
625   MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
626   addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
627   return &*MIB;
628 }
629 
630 bool PPCInstrInfo::
631 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
632   assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
633   // Leave the CR# the same, but invert the condition.
634   Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
635   return false;
636 }
637 
638 /// GetInstSize - Return the number of bytes of code the specified
639 /// instruction may be.  This returns the maximum number of bytes.
640 ///
641 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
642   switch (MI->getOpcode()) {
643   case PPC::INLINEASM: {       // Inline Asm: Variable size.
644     const MachineFunction *MF = MI->getParent()->getParent();
645     const char *AsmStr = MI->getOperand(0).getSymbolName();
646     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
647   }
648   case PPC::PROLOG_LABEL:
649   case PPC::EH_LABEL:
650   case PPC::GC_LABEL:
651   case PPC::DBG_VALUE:
652     return 0;
653   default:
654     return 4; // PowerPC instructions are all 4 bytes
655   }
656 }
657 
658 MCInstrInfo *createPPCMCInstrInfo() {
659   MCInstrInfo *X = new MCInstrInfo();
660   InitPPCMCInstrInfo(X);
661   return X;
662 }
663 
664 extern "C" void LLVMInitializePowerPCMCInstrInfo() {
665   TargetRegistry::RegisterMCInstrInfo(ThePPC32Target, createPPCMCInstrInfo);
666   TargetRegistry::RegisterMCInstrInfo(ThePPC64Target, createPPCMCInstrInfo);
667 }
668