1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCInstrInfo.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPC.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/MC/MCAsmInfo.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_ostream.h"
32 
33 #define GET_INSTRINFO_CTOR
34 #include "PPCGenInstrInfo.inc"
35 
36 using namespace llvm;
37 
38 static cl::
39 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
40             cl::desc("Disable analysis for CTR loops"));
41 
42 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
43   : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
44     TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
45 
46 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
47 /// this target when scheduling the DAG.
48 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
49   const TargetMachine *TM,
50   const ScheduleDAG *DAG) const {
51   unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
52   if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
53       Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
54     const InstrItineraryData *II = TM->getInstrItineraryData();
55     return new PPCScoreboardHazardRecognizer(II, DAG);
56   }
57 
58   return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG);
59 }
60 
61 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
62 /// to use for this target when scheduling the DAG.
63 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
64   const InstrItineraryData *II,
65   const ScheduleDAG *DAG) const {
66   unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
67 
68   // Most subtargets use a PPC970 recognizer.
69   if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
70       Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
71     const TargetInstrInfo *TII = TM.getInstrInfo();
72     assert(TII && "No InstrInfo?");
73 
74     return new PPCHazardRecognizer970(*TII);
75   }
76 
77   return new PPCScoreboardHazardRecognizer(II, DAG);
78 }
79 
80 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
81 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
82                                          unsigned &SrcReg, unsigned &DstReg,
83                                          unsigned &SubIdx) const {
84   switch (MI.getOpcode()) {
85   default: return false;
86   case PPC::EXTSW:
87   case PPC::EXTSW_32_64:
88     SrcReg = MI.getOperand(1).getReg();
89     DstReg = MI.getOperand(0).getReg();
90     SubIdx = PPC::sub_32;
91     return true;
92   }
93 }
94 
95 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
96                                            int &FrameIndex) const {
97   // Note: This list must be kept consistent with LoadRegFromStackSlot.
98   switch (MI->getOpcode()) {
99   default: break;
100   case PPC::LD:
101   case PPC::LWZ:
102   case PPC::LFS:
103   case PPC::LFD:
104   case PPC::RESTORE_CR:
105   case PPC::LVX:
106   case PPC::RESTORE_VRSAVE:
107     // Check for the operands added by addFrameReference (the immediate is the
108     // offset which defaults to 0).
109     if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
110         MI->getOperand(2).isFI()) {
111       FrameIndex = MI->getOperand(2).getIndex();
112       return MI->getOperand(0).getReg();
113     }
114     break;
115   }
116   return 0;
117 }
118 
119 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
120                                           int &FrameIndex) const {
121   // Note: This list must be kept consistent with StoreRegToStackSlot.
122   switch (MI->getOpcode()) {
123   default: break;
124   case PPC::STD:
125   case PPC::STW:
126   case PPC::STFS:
127   case PPC::STFD:
128   case PPC::SPILL_CR:
129   case PPC::STVX:
130   case PPC::SPILL_VRSAVE:
131     // Check for the operands added by addFrameReference (the immediate is the
132     // offset which defaults to 0).
133     if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
134         MI->getOperand(2).isFI()) {
135       FrameIndex = MI->getOperand(2).getIndex();
136       return MI->getOperand(0).getReg();
137     }
138     break;
139   }
140   return 0;
141 }
142 
143 // commuteInstruction - We can commute rlwimi instructions, but only if the
144 // rotate amt is zero.  We also have to munge the immediates a bit.
145 MachineInstr *
146 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
147   MachineFunction &MF = *MI->getParent()->getParent();
148 
149   // Normal instructions can be commuted the obvious way.
150   if (MI->getOpcode() != PPC::RLWIMI)
151     return TargetInstrInfo::commuteInstruction(MI, NewMI);
152 
153   // Cannot commute if it has a non-zero rotate count.
154   if (MI->getOperand(3).getImm() != 0)
155     return 0;
156 
157   // If we have a zero rotate count, we have:
158   //   M = mask(MB,ME)
159   //   Op0 = (Op1 & ~M) | (Op2 & M)
160   // Change this to:
161   //   M = mask((ME+1)&31, (MB-1)&31)
162   //   Op0 = (Op2 & ~M) | (Op1 & M)
163 
164   // Swap op1/op2
165   unsigned Reg0 = MI->getOperand(0).getReg();
166   unsigned Reg1 = MI->getOperand(1).getReg();
167   unsigned Reg2 = MI->getOperand(2).getReg();
168   bool Reg1IsKill = MI->getOperand(1).isKill();
169   bool Reg2IsKill = MI->getOperand(2).isKill();
170   bool ChangeReg0 = false;
171   // If machine instrs are no longer in two-address forms, update
172   // destination register as well.
173   if (Reg0 == Reg1) {
174     // Must be two address instruction!
175     assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
176            "Expecting a two-address instruction!");
177     Reg2IsKill = false;
178     ChangeReg0 = true;
179   }
180 
181   // Masks.
182   unsigned MB = MI->getOperand(4).getImm();
183   unsigned ME = MI->getOperand(5).getImm();
184 
185   if (NewMI) {
186     // Create a new instruction.
187     unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
188     bool Reg0IsDead = MI->getOperand(0).isDead();
189     return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
190       .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
191       .addReg(Reg2, getKillRegState(Reg2IsKill))
192       .addReg(Reg1, getKillRegState(Reg1IsKill))
193       .addImm((ME+1) & 31)
194       .addImm((MB-1) & 31);
195   }
196 
197   if (ChangeReg0)
198     MI->getOperand(0).setReg(Reg2);
199   MI->getOperand(2).setReg(Reg1);
200   MI->getOperand(1).setReg(Reg2);
201   MI->getOperand(2).setIsKill(Reg1IsKill);
202   MI->getOperand(1).setIsKill(Reg2IsKill);
203 
204   // Swap the mask around.
205   MI->getOperand(4).setImm((ME+1) & 31);
206   MI->getOperand(5).setImm((MB-1) & 31);
207   return MI;
208 }
209 
210 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
211                               MachineBasicBlock::iterator MI) const {
212   DebugLoc DL;
213   BuildMI(MBB, MI, DL, get(PPC::NOP));
214 }
215 
216 
217 // Branch analysis.
218 // Note: If the condition register is set to CTR or CTR8 then this is a
219 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
220 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
221                                  MachineBasicBlock *&FBB,
222                                  SmallVectorImpl<MachineOperand> &Cond,
223                                  bool AllowModify) const {
224   bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
225 
226   // If the block has no terminators, it just falls into the block after it.
227   MachineBasicBlock::iterator I = MBB.end();
228   if (I == MBB.begin())
229     return false;
230   --I;
231   while (I->isDebugValue()) {
232     if (I == MBB.begin())
233       return false;
234     --I;
235   }
236   if (!isUnpredicatedTerminator(I))
237     return false;
238 
239   // Get the last instruction in the block.
240   MachineInstr *LastInst = I;
241 
242   // If there is only one terminator instruction, process it.
243   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
244     if (LastInst->getOpcode() == PPC::B) {
245       if (!LastInst->getOperand(0).isMBB())
246         return true;
247       TBB = LastInst->getOperand(0).getMBB();
248       return false;
249     } else if (LastInst->getOpcode() == PPC::BCC) {
250       if (!LastInst->getOperand(2).isMBB())
251         return true;
252       // Block ends with fall-through condbranch.
253       TBB = LastInst->getOperand(2).getMBB();
254       Cond.push_back(LastInst->getOperand(0));
255       Cond.push_back(LastInst->getOperand(1));
256       return false;
257     } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
258                LastInst->getOpcode() == PPC::BDNZ) {
259       if (!LastInst->getOperand(0).isMBB())
260         return true;
261       if (DisableCTRLoopAnal)
262         return true;
263       TBB = LastInst->getOperand(0).getMBB();
264       Cond.push_back(MachineOperand::CreateImm(1));
265       Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
266                                                true));
267       return false;
268     } else if (LastInst->getOpcode() == PPC::BDZ8 ||
269                LastInst->getOpcode() == PPC::BDZ) {
270       if (!LastInst->getOperand(0).isMBB())
271         return true;
272       if (DisableCTRLoopAnal)
273         return true;
274       TBB = LastInst->getOperand(0).getMBB();
275       Cond.push_back(MachineOperand::CreateImm(0));
276       Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
277                                                true));
278       return false;
279     }
280 
281     // Otherwise, don't know what this is.
282     return true;
283   }
284 
285   // Get the instruction before it if it's a terminator.
286   MachineInstr *SecondLastInst = I;
287 
288   // If there are three terminators, we don't know what sort of block this is.
289   if (SecondLastInst && I != MBB.begin() &&
290       isUnpredicatedTerminator(--I))
291     return true;
292 
293   // If the block ends with PPC::B and PPC:BCC, handle it.
294   if (SecondLastInst->getOpcode() == PPC::BCC &&
295       LastInst->getOpcode() == PPC::B) {
296     if (!SecondLastInst->getOperand(2).isMBB() ||
297         !LastInst->getOperand(0).isMBB())
298       return true;
299     TBB =  SecondLastInst->getOperand(2).getMBB();
300     Cond.push_back(SecondLastInst->getOperand(0));
301     Cond.push_back(SecondLastInst->getOperand(1));
302     FBB = LastInst->getOperand(0).getMBB();
303     return false;
304   } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
305               SecondLastInst->getOpcode() == PPC::BDNZ) &&
306       LastInst->getOpcode() == PPC::B) {
307     if (!SecondLastInst->getOperand(0).isMBB() ||
308         !LastInst->getOperand(0).isMBB())
309       return true;
310     if (DisableCTRLoopAnal)
311       return true;
312     TBB = SecondLastInst->getOperand(0).getMBB();
313     Cond.push_back(MachineOperand::CreateImm(1));
314     Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
315                                              true));
316     FBB = LastInst->getOperand(0).getMBB();
317     return false;
318   } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
319               SecondLastInst->getOpcode() == PPC::BDZ) &&
320       LastInst->getOpcode() == PPC::B) {
321     if (!SecondLastInst->getOperand(0).isMBB() ||
322         !LastInst->getOperand(0).isMBB())
323       return true;
324     if (DisableCTRLoopAnal)
325       return true;
326     TBB = SecondLastInst->getOperand(0).getMBB();
327     Cond.push_back(MachineOperand::CreateImm(0));
328     Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
329                                              true));
330     FBB = LastInst->getOperand(0).getMBB();
331     return false;
332   }
333 
334   // If the block ends with two PPC:Bs, handle it.  The second one is not
335   // executed, so remove it.
336   if (SecondLastInst->getOpcode() == PPC::B &&
337       LastInst->getOpcode() == PPC::B) {
338     if (!SecondLastInst->getOperand(0).isMBB())
339       return true;
340     TBB = SecondLastInst->getOperand(0).getMBB();
341     I = LastInst;
342     if (AllowModify)
343       I->eraseFromParent();
344     return false;
345   }
346 
347   // Otherwise, can't handle this.
348   return true;
349 }
350 
351 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
352   MachineBasicBlock::iterator I = MBB.end();
353   if (I == MBB.begin()) return 0;
354   --I;
355   while (I->isDebugValue()) {
356     if (I == MBB.begin())
357       return 0;
358     --I;
359   }
360   if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
361       I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
362       I->getOpcode() != PPC::BDZ8  && I->getOpcode() != PPC::BDZ)
363     return 0;
364 
365   // Remove the branch.
366   I->eraseFromParent();
367 
368   I = MBB.end();
369 
370   if (I == MBB.begin()) return 1;
371   --I;
372   if (I->getOpcode() != PPC::BCC &&
373       I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
374       I->getOpcode() != PPC::BDZ8  && I->getOpcode() != PPC::BDZ)
375     return 1;
376 
377   // Remove the branch.
378   I->eraseFromParent();
379   return 2;
380 }
381 
382 unsigned
383 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
384                            MachineBasicBlock *FBB,
385                            const SmallVectorImpl<MachineOperand> &Cond,
386                            DebugLoc DL) const {
387   // Shouldn't be a fall through.
388   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
389   assert((Cond.size() == 2 || Cond.size() == 0) &&
390          "PPC branch conditions have two components!");
391 
392   bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
393 
394   // One-way branch.
395   if (FBB == 0) {
396     if (Cond.empty())   // Unconditional branch
397       BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
398     else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
399       BuildMI(&MBB, DL, get(Cond[0].getImm() ?
400                               (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
401                               (isPPC64 ? PPC::BDZ8  : PPC::BDZ))).addMBB(TBB);
402     else                // Conditional branch
403       BuildMI(&MBB, DL, get(PPC::BCC))
404         .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
405     return 1;
406   }
407 
408   // Two-way Conditional Branch.
409   if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
410     BuildMI(&MBB, DL, get(Cond[0].getImm() ?
411                             (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
412                             (isPPC64 ? PPC::BDZ8  : PPC::BDZ))).addMBB(TBB);
413   else
414     BuildMI(&MBB, DL, get(PPC::BCC))
415       .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
416   BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
417   return 2;
418 }
419 
420 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
421                                MachineBasicBlock::iterator I, DebugLoc DL,
422                                unsigned DestReg, unsigned SrcReg,
423                                bool KillSrc) const {
424   unsigned Opc;
425   if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
426     Opc = PPC::OR;
427   else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
428     Opc = PPC::OR8;
429   else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
430     Opc = PPC::FMR;
431   else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
432     Opc = PPC::MCRF;
433   else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
434     Opc = PPC::VOR;
435   else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
436     Opc = PPC::CROR;
437   else
438     llvm_unreachable("Impossible reg-to-reg copy");
439 
440   const MCInstrDesc &MCID = get(Opc);
441   if (MCID.getNumOperands() == 3)
442     BuildMI(MBB, I, DL, MCID, DestReg)
443       .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
444   else
445     BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
446 }
447 
448 // This function returns true if a CR spill is necessary and false otherwise.
449 bool
450 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
451                                   unsigned SrcReg, bool isKill,
452                                   int FrameIdx,
453                                   const TargetRegisterClass *RC,
454                                   SmallVectorImpl<MachineInstr*> &NewMIs,
455                                   bool &NonRI, bool &SpillsVRS) const{
456   // Note: If additional store instructions are added here,
457   // update isStoreToStackSlot.
458 
459   DebugLoc DL;
460   if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
461     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
462                                        .addReg(SrcReg,
463                                                getKillRegState(isKill)),
464                                        FrameIdx));
465   } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
466     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
467                                        .addReg(SrcReg,
468                                                getKillRegState(isKill)),
469                                        FrameIdx));
470   } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
471     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
472                                        .addReg(SrcReg,
473                                                getKillRegState(isKill)),
474                                        FrameIdx));
475   } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
476     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
477                                        .addReg(SrcReg,
478                                                getKillRegState(isKill)),
479                                        FrameIdx));
480   } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
481     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
482                                        .addReg(SrcReg,
483                                                getKillRegState(isKill)),
484                                        FrameIdx));
485     return true;
486   } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
487     // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
488     // backend currently only uses CR1EQ as an individual bit, this should
489     // not cause any bug. If we need other uses of CR bits, the following
490     // code may be invalid.
491     unsigned Reg = 0;
492     if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
493         SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
494       Reg = PPC::CR0;
495     else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
496              SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
497       Reg = PPC::CR1;
498     else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
499              SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
500       Reg = PPC::CR2;
501     else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
502              SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
503       Reg = PPC::CR3;
504     else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
505              SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
506       Reg = PPC::CR4;
507     else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
508              SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
509       Reg = PPC::CR5;
510     else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
511              SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
512       Reg = PPC::CR6;
513     else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
514              SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
515       Reg = PPC::CR7;
516 
517     return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
518                                &PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS);
519 
520   } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
521     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
522                                        .addReg(SrcReg,
523                                                getKillRegState(isKill)),
524                                        FrameIdx));
525     NonRI = true;
526   } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
527     assert(TM.getSubtargetImpl()->isDarwin() &&
528            "VRSAVE only needs spill/restore on Darwin");
529     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
530                                        .addReg(SrcReg,
531                                                getKillRegState(isKill)),
532                                        FrameIdx));
533     SpillsVRS = true;
534   } else {
535     llvm_unreachable("Unknown regclass!");
536   }
537 
538   return false;
539 }
540 
541 void
542 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
543                                   MachineBasicBlock::iterator MI,
544                                   unsigned SrcReg, bool isKill, int FrameIdx,
545                                   const TargetRegisterClass *RC,
546                                   const TargetRegisterInfo *TRI) const {
547   MachineFunction &MF = *MBB.getParent();
548   SmallVector<MachineInstr*, 4> NewMIs;
549 
550   PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
551   FuncInfo->setHasSpills();
552 
553   bool NonRI = false, SpillsVRS = false;
554   if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
555                           NonRI, SpillsVRS))
556     FuncInfo->setSpillsCR();
557 
558   if (SpillsVRS)
559     FuncInfo->setSpillsVRSAVE();
560 
561   if (NonRI)
562     FuncInfo->setHasNonRISpills();
563 
564   for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
565     MBB.insert(MI, NewMIs[i]);
566 
567   const MachineFrameInfo &MFI = *MF.getFrameInfo();
568   MachineMemOperand *MMO =
569     MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
570                             MachineMemOperand::MOStore,
571                             MFI.getObjectSize(FrameIdx),
572                             MFI.getObjectAlignment(FrameIdx));
573   NewMIs.back()->addMemOperand(MF, MMO);
574 }
575 
576 bool
577 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
578                                    unsigned DestReg, int FrameIdx,
579                                    const TargetRegisterClass *RC,
580                                    SmallVectorImpl<MachineInstr*> &NewMIs,
581                                    bool &NonRI, bool &SpillsVRS) const{
582   // Note: If additional load instructions are added here,
583   // update isLoadFromStackSlot.
584 
585   if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
586     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
587                                                DestReg), FrameIdx));
588   } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
589     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
590                                        FrameIdx));
591   } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
592     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
593                                        FrameIdx));
594   } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
595     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
596                                        FrameIdx));
597   } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
598     NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
599                                                get(PPC::RESTORE_CR), DestReg),
600                                        FrameIdx));
601     return true;
602   } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
603 
604     unsigned Reg = 0;
605     if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
606         DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
607       Reg = PPC::CR0;
608     else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
609              DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
610       Reg = PPC::CR1;
611     else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
612              DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
613       Reg = PPC::CR2;
614     else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
615              DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
616       Reg = PPC::CR3;
617     else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
618              DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
619       Reg = PPC::CR4;
620     else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
621              DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
622       Reg = PPC::CR5;
623     else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
624              DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
625       Reg = PPC::CR6;
626     else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
627              DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
628       Reg = PPC::CR7;
629 
630     return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
631                                 &PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS);
632 
633   } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
634     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
635                                        FrameIdx));
636     NonRI = true;
637   } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
638     assert(TM.getSubtargetImpl()->isDarwin() &&
639            "VRSAVE only needs spill/restore on Darwin");
640     NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
641                                                get(PPC::RESTORE_VRSAVE),
642                                                DestReg),
643                                        FrameIdx));
644     SpillsVRS = true;
645   } else {
646     llvm_unreachable("Unknown regclass!");
647   }
648 
649   return false;
650 }
651 
652 void
653 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
654                                    MachineBasicBlock::iterator MI,
655                                    unsigned DestReg, int FrameIdx,
656                                    const TargetRegisterClass *RC,
657                                    const TargetRegisterInfo *TRI) const {
658   MachineFunction &MF = *MBB.getParent();
659   SmallVector<MachineInstr*, 4> NewMIs;
660   DebugLoc DL;
661   if (MI != MBB.end()) DL = MI->getDebugLoc();
662 
663   PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
664   FuncInfo->setHasSpills();
665 
666   bool NonRI = false, SpillsVRS = false;
667   if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
668                            NonRI, SpillsVRS))
669     FuncInfo->setSpillsCR();
670 
671   if (SpillsVRS)
672     FuncInfo->setSpillsVRSAVE();
673 
674   if (NonRI)
675     FuncInfo->setHasNonRISpills();
676 
677   for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
678     MBB.insert(MI, NewMIs[i]);
679 
680   const MachineFrameInfo &MFI = *MF.getFrameInfo();
681   MachineMemOperand *MMO =
682     MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
683                             MachineMemOperand::MOLoad,
684                             MFI.getObjectSize(FrameIdx),
685                             MFI.getObjectAlignment(FrameIdx));
686   NewMIs.back()->addMemOperand(MF, MMO);
687 }
688 
689 MachineInstr*
690 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
691                                        int FrameIx, uint64_t Offset,
692                                        const MDNode *MDPtr,
693                                        DebugLoc DL) const {
694   MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
695   addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
696   return &*MIB;
697 }
698 
699 bool PPCInstrInfo::
700 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
701   assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
702   if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
703     Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
704   else
705     // Leave the CR# the same, but invert the condition.
706     Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
707   return false;
708 }
709 
710 /// GetInstSize - Return the number of bytes of code the specified
711 /// instruction may be.  This returns the maximum number of bytes.
712 ///
713 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
714   switch (MI->getOpcode()) {
715   case PPC::INLINEASM: {       // Inline Asm: Variable size.
716     const MachineFunction *MF = MI->getParent()->getParent();
717     const char *AsmStr = MI->getOperand(0).getSymbolName();
718     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
719   }
720   case PPC::PROLOG_LABEL:
721   case PPC::EH_LABEL:
722   case PPC::GC_LABEL:
723   case PPC::DBG_VALUE:
724     return 0;
725   case PPC::BL8_NOP:
726   case PPC::BLA8_NOP:
727     return 8;
728   default:
729     return 4; // PowerPC instructions are all 4 bytes
730   }
731 }
732