1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCInstrInfo.h" 15 #include "MCTargetDesc/PPCPredicates.h" 16 #include "PPC.h" 17 #include "PPCHazardRecognizers.h" 18 #include "PPCInstrBuilder.h" 19 #include "PPCMachineFunctionInfo.h" 20 #include "PPCTargetMachine.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/CodeGen/MachineFrameInfo.h" 23 #include "llvm/CodeGen/MachineInstrBuilder.h" 24 #include "llvm/CodeGen/MachineMemOperand.h" 25 #include "llvm/CodeGen/MachineRegisterInfo.h" 26 #include "llvm/CodeGen/PseudoSourceValue.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/Support/CommandLine.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/TargetRegistry.h" 31 #include "llvm/Support/raw_ostream.h" 32 33 #define GET_INSTRINFO_CTOR 34 #include "PPCGenInstrInfo.inc" 35 36 using namespace llvm; 37 38 static cl:: 39 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, 40 cl::desc("Disable analysis for CTR loops")); 41 42 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) 43 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 44 TM(tm), RI(*TM.getSubtargetImpl(), *this) {} 45 46 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for 47 /// this target when scheduling the DAG. 48 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer( 49 const TargetMachine *TM, 50 const ScheduleDAG *DAG) const { 51 unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective(); 52 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 || 53 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) { 54 const InstrItineraryData *II = TM->getInstrItineraryData(); 55 return new PPCScoreboardHazardRecognizer(II, DAG); 56 } 57 58 return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG); 59 } 60 61 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer 62 /// to use for this target when scheduling the DAG. 63 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer( 64 const InstrItineraryData *II, 65 const ScheduleDAG *DAG) const { 66 unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective(); 67 68 // Most subtargets use a PPC970 recognizer. 69 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 && 70 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) { 71 const TargetInstrInfo *TII = TM.getInstrInfo(); 72 assert(TII && "No InstrInfo?"); 73 74 return new PPCHazardRecognizer970(*TII); 75 } 76 77 return new PPCScoreboardHazardRecognizer(II, DAG); 78 } 79 80 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register. 81 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 82 unsigned &SrcReg, unsigned &DstReg, 83 unsigned &SubIdx) const { 84 switch (MI.getOpcode()) { 85 default: return false; 86 case PPC::EXTSW: 87 case PPC::EXTSW_32_64: 88 SrcReg = MI.getOperand(1).getReg(); 89 DstReg = MI.getOperand(0).getReg(); 90 SubIdx = PPC::sub_32; 91 return true; 92 } 93 } 94 95 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 96 int &FrameIndex) const { 97 switch (MI->getOpcode()) { 98 default: break; 99 case PPC::LD: 100 case PPC::LWZ: 101 case PPC::LFS: 102 case PPC::LFD: 103 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 104 MI->getOperand(2).isFI()) { 105 FrameIndex = MI->getOperand(2).getIndex(); 106 return MI->getOperand(0).getReg(); 107 } 108 break; 109 } 110 return 0; 111 } 112 113 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 114 int &FrameIndex) const { 115 switch (MI->getOpcode()) { 116 default: break; 117 case PPC::STD: 118 case PPC::STW: 119 case PPC::STFS: 120 case PPC::STFD: 121 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && 122 MI->getOperand(2).isFI()) { 123 FrameIndex = MI->getOperand(2).getIndex(); 124 return MI->getOperand(0).getReg(); 125 } 126 break; 127 } 128 return 0; 129 } 130 131 // commuteInstruction - We can commute rlwimi instructions, but only if the 132 // rotate amt is zero. We also have to munge the immediates a bit. 133 MachineInstr * 134 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 135 MachineFunction &MF = *MI->getParent()->getParent(); 136 137 // Normal instructions can be commuted the obvious way. 138 if (MI->getOpcode() != PPC::RLWIMI) 139 return TargetInstrInfo::commuteInstruction(MI, NewMI); 140 141 // Cannot commute if it has a non-zero rotate count. 142 if (MI->getOperand(3).getImm() != 0) 143 return 0; 144 145 // If we have a zero rotate count, we have: 146 // M = mask(MB,ME) 147 // Op0 = (Op1 & ~M) | (Op2 & M) 148 // Change this to: 149 // M = mask((ME+1)&31, (MB-1)&31) 150 // Op0 = (Op2 & ~M) | (Op1 & M) 151 152 // Swap op1/op2 153 unsigned Reg0 = MI->getOperand(0).getReg(); 154 unsigned Reg1 = MI->getOperand(1).getReg(); 155 unsigned Reg2 = MI->getOperand(2).getReg(); 156 bool Reg1IsKill = MI->getOperand(1).isKill(); 157 bool Reg2IsKill = MI->getOperand(2).isKill(); 158 bool ChangeReg0 = false; 159 // If machine instrs are no longer in two-address forms, update 160 // destination register as well. 161 if (Reg0 == Reg1) { 162 // Must be two address instruction! 163 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) && 164 "Expecting a two-address instruction!"); 165 Reg2IsKill = false; 166 ChangeReg0 = true; 167 } 168 169 // Masks. 170 unsigned MB = MI->getOperand(4).getImm(); 171 unsigned ME = MI->getOperand(5).getImm(); 172 173 if (NewMI) { 174 // Create a new instruction. 175 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); 176 bool Reg0IsDead = MI->getOperand(0).isDead(); 177 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) 178 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) 179 .addReg(Reg2, getKillRegState(Reg2IsKill)) 180 .addReg(Reg1, getKillRegState(Reg1IsKill)) 181 .addImm((ME+1) & 31) 182 .addImm((MB-1) & 31); 183 } 184 185 if (ChangeReg0) 186 MI->getOperand(0).setReg(Reg2); 187 MI->getOperand(2).setReg(Reg1); 188 MI->getOperand(1).setReg(Reg2); 189 MI->getOperand(2).setIsKill(Reg1IsKill); 190 MI->getOperand(1).setIsKill(Reg2IsKill); 191 192 // Swap the mask around. 193 MI->getOperand(4).setImm((ME+1) & 31); 194 MI->getOperand(5).setImm((MB-1) & 31); 195 return MI; 196 } 197 198 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB, 199 MachineBasicBlock::iterator MI) const { 200 DebugLoc DL; 201 BuildMI(MBB, MI, DL, get(PPC::NOP)); 202 } 203 204 205 // Branch analysis. 206 // Note: If the condition register is set to CTR or CTR8 then this is a 207 // BDNZ (imm == 1) or BDZ (imm == 0) branch. 208 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 209 MachineBasicBlock *&FBB, 210 SmallVectorImpl<MachineOperand> &Cond, 211 bool AllowModify) const { 212 bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); 213 214 // If the block has no terminators, it just falls into the block after it. 215 MachineBasicBlock::iterator I = MBB.end(); 216 if (I == MBB.begin()) 217 return false; 218 --I; 219 while (I->isDebugValue()) { 220 if (I == MBB.begin()) 221 return false; 222 --I; 223 } 224 if (!isUnpredicatedTerminator(I)) 225 return false; 226 227 // Get the last instruction in the block. 228 MachineInstr *LastInst = I; 229 230 // If there is only one terminator instruction, process it. 231 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 232 if (LastInst->getOpcode() == PPC::B) { 233 if (!LastInst->getOperand(0).isMBB()) 234 return true; 235 TBB = LastInst->getOperand(0).getMBB(); 236 return false; 237 } else if (LastInst->getOpcode() == PPC::BCC) { 238 if (!LastInst->getOperand(2).isMBB()) 239 return true; 240 // Block ends with fall-through condbranch. 241 TBB = LastInst->getOperand(2).getMBB(); 242 Cond.push_back(LastInst->getOperand(0)); 243 Cond.push_back(LastInst->getOperand(1)); 244 return false; 245 } else if (LastInst->getOpcode() == PPC::BDNZ8 || 246 LastInst->getOpcode() == PPC::BDNZ) { 247 if (!LastInst->getOperand(0).isMBB()) 248 return true; 249 if (DisableCTRLoopAnal) 250 return true; 251 TBB = LastInst->getOperand(0).getMBB(); 252 Cond.push_back(MachineOperand::CreateImm(1)); 253 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 254 true)); 255 return false; 256 } else if (LastInst->getOpcode() == PPC::BDZ8 || 257 LastInst->getOpcode() == PPC::BDZ) { 258 if (!LastInst->getOperand(0).isMBB()) 259 return true; 260 if (DisableCTRLoopAnal) 261 return true; 262 TBB = LastInst->getOperand(0).getMBB(); 263 Cond.push_back(MachineOperand::CreateImm(0)); 264 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 265 true)); 266 return false; 267 } 268 269 // Otherwise, don't know what this is. 270 return true; 271 } 272 273 // Get the instruction before it if it's a terminator. 274 MachineInstr *SecondLastInst = I; 275 276 // If there are three terminators, we don't know what sort of block this is. 277 if (SecondLastInst && I != MBB.begin() && 278 isUnpredicatedTerminator(--I)) 279 return true; 280 281 // If the block ends with PPC::B and PPC:BCC, handle it. 282 if (SecondLastInst->getOpcode() == PPC::BCC && 283 LastInst->getOpcode() == PPC::B) { 284 if (!SecondLastInst->getOperand(2).isMBB() || 285 !LastInst->getOperand(0).isMBB()) 286 return true; 287 TBB = SecondLastInst->getOperand(2).getMBB(); 288 Cond.push_back(SecondLastInst->getOperand(0)); 289 Cond.push_back(SecondLastInst->getOperand(1)); 290 FBB = LastInst->getOperand(0).getMBB(); 291 return false; 292 } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 || 293 SecondLastInst->getOpcode() == PPC::BDNZ) && 294 LastInst->getOpcode() == PPC::B) { 295 if (!SecondLastInst->getOperand(0).isMBB() || 296 !LastInst->getOperand(0).isMBB()) 297 return true; 298 if (DisableCTRLoopAnal) 299 return true; 300 TBB = SecondLastInst->getOperand(0).getMBB(); 301 Cond.push_back(MachineOperand::CreateImm(1)); 302 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 303 true)); 304 FBB = LastInst->getOperand(0).getMBB(); 305 return false; 306 } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 || 307 SecondLastInst->getOpcode() == PPC::BDZ) && 308 LastInst->getOpcode() == PPC::B) { 309 if (!SecondLastInst->getOperand(0).isMBB() || 310 !LastInst->getOperand(0).isMBB()) 311 return true; 312 if (DisableCTRLoopAnal) 313 return true; 314 TBB = SecondLastInst->getOperand(0).getMBB(); 315 Cond.push_back(MachineOperand::CreateImm(0)); 316 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 317 true)); 318 FBB = LastInst->getOperand(0).getMBB(); 319 return false; 320 } 321 322 // If the block ends with two PPC:Bs, handle it. The second one is not 323 // executed, so remove it. 324 if (SecondLastInst->getOpcode() == PPC::B && 325 LastInst->getOpcode() == PPC::B) { 326 if (!SecondLastInst->getOperand(0).isMBB()) 327 return true; 328 TBB = SecondLastInst->getOperand(0).getMBB(); 329 I = LastInst; 330 if (AllowModify) 331 I->eraseFromParent(); 332 return false; 333 } 334 335 // Otherwise, can't handle this. 336 return true; 337 } 338 339 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 340 MachineBasicBlock::iterator I = MBB.end(); 341 if (I == MBB.begin()) return 0; 342 --I; 343 while (I->isDebugValue()) { 344 if (I == MBB.begin()) 345 return 0; 346 --I; 347 } 348 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC && 349 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ && 350 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ) 351 return 0; 352 353 // Remove the branch. 354 I->eraseFromParent(); 355 356 I = MBB.end(); 357 358 if (I == MBB.begin()) return 1; 359 --I; 360 if (I->getOpcode() != PPC::BCC && 361 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ && 362 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ) 363 return 1; 364 365 // Remove the branch. 366 I->eraseFromParent(); 367 return 2; 368 } 369 370 unsigned 371 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 372 MachineBasicBlock *FBB, 373 const SmallVectorImpl<MachineOperand> &Cond, 374 DebugLoc DL) const { 375 // Shouldn't be a fall through. 376 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 377 assert((Cond.size() == 2 || Cond.size() == 0) && 378 "PPC branch conditions have two components!"); 379 380 bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); 381 382 // One-way branch. 383 if (FBB == 0) { 384 if (Cond.empty()) // Unconditional branch 385 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); 386 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) 387 BuildMI(&MBB, DL, get(Cond[0].getImm() ? 388 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : 389 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); 390 else // Conditional branch 391 BuildMI(&MBB, DL, get(PPC::BCC)) 392 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 393 return 1; 394 } 395 396 // Two-way Conditional Branch. 397 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) 398 BuildMI(&MBB, DL, get(Cond[0].getImm() ? 399 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : 400 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); 401 else 402 BuildMI(&MBB, DL, get(PPC::BCC)) 403 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 404 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); 405 return 2; 406 } 407 408 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 409 MachineBasicBlock::iterator I, DebugLoc DL, 410 unsigned DestReg, unsigned SrcReg, 411 bool KillSrc) const { 412 unsigned Opc; 413 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) 414 Opc = PPC::OR; 415 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) 416 Opc = PPC::OR8; 417 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) 418 Opc = PPC::FMR; 419 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) 420 Opc = PPC::MCRF; 421 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) 422 Opc = PPC::VOR; 423 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) 424 Opc = PPC::CROR; 425 426 // Asymmetric copies: 427 428 else if (PPC::GPRCRegClass.contains(DestReg) && 429 PPC::G8RCRegClass.contains(SrcReg)) 430 Opc = PPC::OR_64; 431 else if (PPC::G8RCRegClass.contains(DestReg) && 432 PPC::GPRCRegClass.contains(SrcReg)) 433 Opc = PPC::OR8_32; 434 else 435 llvm_unreachable("Impossible reg-to-reg copy"); 436 437 const MCInstrDesc &MCID = get(Opc); 438 if (MCID.getNumOperands() == 3) 439 BuildMI(MBB, I, DL, MCID, DestReg) 440 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); 441 else 442 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); 443 } 444 445 // This function returns true if a CR spill is necessary and false otherwise. 446 bool 447 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, 448 unsigned SrcReg, bool isKill, 449 int FrameIdx, 450 const TargetRegisterClass *RC, 451 SmallVectorImpl<MachineInstr*> &NewMIs, 452 bool &NonRI) const{ 453 DebugLoc DL; 454 if (PPC::GPRCRegClass.hasSubClassEq(RC)) { 455 if (SrcReg != PPC::LR) { 456 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 457 .addReg(SrcReg, 458 getKillRegState(isKill)), 459 FrameIdx)); 460 } else { 461 // FIXME: this spills LR immediately to memory in one step. To do this, 462 // we use R11, which we know cannot be used in the prolog/epilog. This is 463 // a hack. 464 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11)); 465 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 466 .addReg(PPC::R11, 467 getKillRegState(isKill)), 468 FrameIdx)); 469 } 470 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) { 471 if (SrcReg != PPC::LR8) { 472 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 473 .addReg(SrcReg, 474 getKillRegState(isKill)), 475 FrameIdx)); 476 } else { 477 // FIXME: this spills LR immediately to memory in one step. To do this, 478 // we use X11, which we know cannot be used in the prolog/epilog. This is 479 // a hack. 480 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11)); 481 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 482 .addReg(PPC::X11, 483 getKillRegState(isKill)), 484 FrameIdx)); 485 } 486 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { 487 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) 488 .addReg(SrcReg, 489 getKillRegState(isKill)), 490 FrameIdx)); 491 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { 492 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) 493 .addReg(SrcReg, 494 getKillRegState(isKill)), 495 FrameIdx)); 496 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { 497 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) 498 .addReg(SrcReg, 499 getKillRegState(isKill)), 500 FrameIdx)); 501 return true; 502 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { 503 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the 504 // backend currently only uses CR1EQ as an individual bit, this should 505 // not cause any bug. If we need other uses of CR bits, the following 506 // code may be invalid. 507 unsigned Reg = 0; 508 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || 509 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) 510 Reg = PPC::CR0; 511 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || 512 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) 513 Reg = PPC::CR1; 514 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || 515 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) 516 Reg = PPC::CR2; 517 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || 518 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) 519 Reg = PPC::CR3; 520 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || 521 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) 522 Reg = PPC::CR4; 523 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT || 524 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) 525 Reg = PPC::CR5; 526 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT || 527 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) 528 Reg = PPC::CR6; 529 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT || 530 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN) 531 Reg = PPC::CR7; 532 533 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx, 534 &PPC::CRRCRegClass, NewMIs, NonRI); 535 536 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { 537 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX)) 538 .addReg(SrcReg, 539 getKillRegState(isKill)), 540 FrameIdx)); 541 NonRI = true; 542 } else { 543 llvm_unreachable("Unknown regclass!"); 544 } 545 546 return false; 547 } 548 549 void 550 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 551 MachineBasicBlock::iterator MI, 552 unsigned SrcReg, bool isKill, int FrameIdx, 553 const TargetRegisterClass *RC, 554 const TargetRegisterInfo *TRI) const { 555 MachineFunction &MF = *MBB.getParent(); 556 SmallVector<MachineInstr*, 4> NewMIs; 557 558 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 559 FuncInfo->setHasSpills(); 560 561 bool NonRI = false; 562 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs, NonRI)) 563 FuncInfo->setSpillsCR(); 564 565 if (NonRI) 566 FuncInfo->setHasNonRISpills(); 567 568 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 569 MBB.insert(MI, NewMIs[i]); 570 571 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 572 MachineMemOperand *MMO = 573 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 574 MachineMemOperand::MOStore, 575 MFI.getObjectSize(FrameIdx), 576 MFI.getObjectAlignment(FrameIdx)); 577 NewMIs.back()->addMemOperand(MF, MMO); 578 } 579 580 bool 581 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, 582 unsigned DestReg, int FrameIdx, 583 const TargetRegisterClass *RC, 584 SmallVectorImpl<MachineInstr*> &NewMIs, 585 bool &NonRI) const{ 586 if (PPC::GPRCRegClass.hasSubClassEq(RC)) { 587 if (DestReg != PPC::LR) { 588 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 589 DestReg), FrameIdx)); 590 } else { 591 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), 592 PPC::R11), FrameIdx)); 593 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11)); 594 } 595 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) { 596 if (DestReg != PPC::LR8) { 597 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg), 598 FrameIdx)); 599 } else { 600 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), 601 PPC::X11), FrameIdx)); 602 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::X11)); 603 } 604 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { 605 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg), 606 FrameIdx)); 607 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { 608 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg), 609 FrameIdx)); 610 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { 611 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, 612 get(PPC::RESTORE_CR), DestReg), 613 FrameIdx)); 614 return true; 615 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { 616 617 unsigned Reg = 0; 618 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT || 619 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN) 620 Reg = PPC::CR0; 621 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT || 622 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN) 623 Reg = PPC::CR1; 624 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT || 625 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN) 626 Reg = PPC::CR2; 627 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT || 628 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN) 629 Reg = PPC::CR3; 630 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT || 631 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN) 632 Reg = PPC::CR4; 633 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT || 634 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN) 635 Reg = PPC::CR5; 636 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT || 637 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN) 638 Reg = PPC::CR6; 639 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT || 640 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN) 641 Reg = PPC::CR7; 642 643 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx, 644 &PPC::CRRCRegClass, NewMIs, NonRI); 645 646 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { 647 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg), 648 FrameIdx)); 649 NonRI = true; 650 } else { 651 llvm_unreachable("Unknown regclass!"); 652 } 653 654 return false; 655 } 656 657 void 658 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 659 MachineBasicBlock::iterator MI, 660 unsigned DestReg, int FrameIdx, 661 const TargetRegisterClass *RC, 662 const TargetRegisterInfo *TRI) const { 663 MachineFunction &MF = *MBB.getParent(); 664 SmallVector<MachineInstr*, 4> NewMIs; 665 DebugLoc DL; 666 if (MI != MBB.end()) DL = MI->getDebugLoc(); 667 668 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 669 FuncInfo->setHasSpills(); 670 671 bool NonRI = false; 672 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs, NonRI)) 673 FuncInfo->setSpillsCR(); 674 675 if (NonRI) 676 FuncInfo->setHasNonRISpills(); 677 678 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 679 MBB.insert(MI, NewMIs[i]); 680 681 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 682 MachineMemOperand *MMO = 683 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 684 MachineMemOperand::MOLoad, 685 MFI.getObjectSize(FrameIdx), 686 MFI.getObjectAlignment(FrameIdx)); 687 NewMIs.back()->addMemOperand(MF, MMO); 688 } 689 690 MachineInstr* 691 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 692 int FrameIx, uint64_t Offset, 693 const MDNode *MDPtr, 694 DebugLoc DL) const { 695 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE)); 696 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr); 697 return &*MIB; 698 } 699 700 bool PPCInstrInfo:: 701 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 702 assert(Cond.size() == 2 && "Invalid PPC branch opcode!"); 703 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR) 704 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0); 705 else 706 // Leave the CR# the same, but invert the condition. 707 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); 708 return false; 709 } 710 711 /// GetInstSize - Return the number of bytes of code the specified 712 /// instruction may be. This returns the maximum number of bytes. 713 /// 714 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 715 switch (MI->getOpcode()) { 716 case PPC::INLINEASM: { // Inline Asm: Variable size. 717 const MachineFunction *MF = MI->getParent()->getParent(); 718 const char *AsmStr = MI->getOperand(0).getSymbolName(); 719 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); 720 } 721 case PPC::PROLOG_LABEL: 722 case PPC::EH_LABEL: 723 case PPC::GC_LABEL: 724 case PPC::DBG_VALUE: 725 return 0; 726 case PPC::BL8_NOP_ELF: 727 case PPC::BLA8_NOP_ELF: 728 return 8; 729 default: 730 return 4; // PowerPC instructions are all 4 bytes 731 } 732 } 733