1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// PowerPC instruction formats 13 14class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 15 : Instruction { 16 field bits<32> Inst; 17 field bits<32> SoftFail = 0; 18 let Size = 4; 19 20 bit PPC64 = 0; // Default value, override with isPPC64 21 22 let Namespace = "PPC"; 23 let Inst{0-5} = opcode; 24 let OutOperandList = OOL; 25 let InOperandList = IOL; 26 let AsmString = asmstr; 27 let Itinerary = itin; 28 29 bits<1> PPC970_First = 0; 30 bits<1> PPC970_Single = 0; 31 bits<1> PPC970_Cracked = 0; 32 bits<3> PPC970_Unit = 0; 33 34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 35 /// these must be reflected there! See comments there for what these are. 36 let TSFlags{0} = PPC970_First; 37 let TSFlags{1} = PPC970_Single; 38 let TSFlags{2} = PPC970_Cracked; 39 let TSFlags{5-3} = PPC970_Unit; 40 41 // Fields used for relation models. 42 string BaseName = ""; 43 44 // For cases where multiple instruction definitions really represent the 45 // same underlying instruction but with one definition for 64-bit arguments 46 // and one for 32-bit arguments, this bit breaks the degeneracy between 47 // the two forms and allows TableGen to generate mapping tables. 48 bit Interpretation64Bit = 0; 49} 50 51class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 52class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 53class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 54class PPC970_MicroCode; 55 56class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 57class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 58class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 59class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 60class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 61class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 62class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 63class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 64 65// Two joined instructions; used to emit two adjacent instructions as one. 66// The itinerary from the first instruction is used for scheduling and 67// classification. 68class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 69 InstrItinClass itin> 70 : Instruction { 71 field bits<64> Inst; 72 field bits<64> SoftFail = 0; 73 let Size = 8; 74 75 bit PPC64 = 0; // Default value, override with isPPC64 76 77 let Namespace = "PPC"; 78 let Inst{0-5} = opcode1; 79 let Inst{32-37} = opcode2; 80 let OutOperandList = OOL; 81 let InOperandList = IOL; 82 let AsmString = asmstr; 83 let Itinerary = itin; 84 85 bits<1> PPC970_First = 0; 86 bits<1> PPC970_Single = 0; 87 bits<1> PPC970_Cracked = 0; 88 bits<3> PPC970_Unit = 0; 89 90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 91 /// these must be reflected there! See comments there for what these are. 92 let TSFlags{0} = PPC970_First; 93 let TSFlags{1} = PPC970_Single; 94 let TSFlags{2} = PPC970_Cracked; 95 let TSFlags{5-3} = PPC970_Unit; 96 97 // Fields used for relation models. 98 string BaseName = ""; 99 bit Interpretation64Bit = 0; 100} 101 102// 1.7.1 I-Form 103class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 104 InstrItinClass itin, list<dag> pattern> 105 : I<opcode, OOL, IOL, asmstr, itin> { 106 let Pattern = pattern; 107 bits<24> LI; 108 109 let Inst{6-29} = LI; 110 let Inst{30} = aa; 111 let Inst{31} = lk; 112} 113 114// 1.7.2 B-Form 115class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 118 bits<3> CR; 119 bits<14> BD; 120 121 bits<5> BI; 122 let BI{0-1} = BIBO{5-6}; 123 let BI{2-4} = CR{0-2}; 124 125 let Inst{6-10} = BIBO{4-0}; 126 let Inst{11-15} = BI; 127 let Inst{16-29} = BD; 128 let Inst{30} = aa; 129 let Inst{31} = lk; 130} 131 132class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 133 string asmstr> 134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 135 let BIBO{4-0} = bo; 136 let BIBO{6-5} = 0; 137 let CR = 0; 138} 139 140class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 141 dag OOL, dag IOL, string asmstr> 142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 143 bits<14> BD; 144 145 let Inst{6-10} = bo; 146 let Inst{11-15} = bi; 147 let Inst{16-29} = BD; 148 let Inst{30} = aa; 149 let Inst{31} = lk; 150} 151 152class BForm_3<bits<6> opcode, bit aa, bit lk, 153 dag OOL, dag IOL, string asmstr> 154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 155 bits<5> BO; 156 bits<5> BI; 157 bits<14> BD; 158 159 let Inst{6-10} = BO; 160 let Inst{11-15} = BI; 161 let Inst{16-29} = BD; 162 let Inst{30} = aa; 163 let Inst{31} = lk; 164} 165 166class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, 167 dag OOL, dag IOL, string asmstr> 168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 169 bits<5> BI; 170 bits<14> BD; 171 172 let Inst{6-10} = bo; 173 let Inst{11-15} = BI; 174 let Inst{16-29} = BD; 175 let Inst{30} = aa; 176 let Inst{31} = lk; 177} 178 179// 1.7.3 SC-Form 180class SCForm<bits<6> opcode, bits<1> xo, 181 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 182 list<dag> pattern> 183 : I<opcode, OOL, IOL, asmstr, itin> { 184 bits<7> LEV; 185 186 let Pattern = pattern; 187 188 let Inst{20-26} = LEV; 189 let Inst{30} = xo; 190} 191 192// 1.7.4 D-Form 193class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 194 InstrItinClass itin, list<dag> pattern> 195 : I<opcode, OOL, IOL, asmstr, itin> { 196 bits<5> A; 197 bits<5> B; 198 bits<16> C; 199 200 let Pattern = pattern; 201 202 let Inst{6-10} = A; 203 let Inst{11-15} = B; 204 let Inst{16-31} = C; 205} 206 207class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 208 InstrItinClass itin, list<dag> pattern> 209 : I<opcode, OOL, IOL, asmstr, itin> { 210 bits<5> A; 211 bits<21> Addr; 212 213 let Pattern = pattern; 214 215 let Inst{6-10} = A; 216 let Inst{11-15} = Addr{20-16}; // Base Reg 217 let Inst{16-31} = Addr{15-0}; // Displacement 218} 219 220class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 221 InstrItinClass itin, list<dag> pattern> 222 : I<opcode, OOL, IOL, asmstr, itin> { 223 bits<5> A; 224 bits<16> C; 225 bits<5> B; 226 227 let Pattern = pattern; 228 229 let Inst{6-10} = A; 230 let Inst{11-15} = B; 231 let Inst{16-31} = C; 232} 233 234 235class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 236 InstrItinClass itin, list<dag> pattern> 237 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 238 239 // Even though ADDICo does not really have an RC bit, provide 240 // the declaration of one here so that isDOT has something to set. 241 bit RC = 0; 242} 243 244class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 245 InstrItinClass itin, list<dag> pattern> 246 : I<opcode, OOL, IOL, asmstr, itin> { 247 bits<5> A; 248 bits<16> B; 249 250 let Pattern = pattern; 251 252 let Inst{6-10} = A; 253 let Inst{11-15} = 0; 254 let Inst{16-31} = B; 255} 256 257class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 258 InstrItinClass itin, list<dag> pattern> 259 : I<opcode, OOL, IOL, asmstr, itin> { 260 bits<5> B; 261 bits<5> A; 262 bits<16> C; 263 264 let Pattern = pattern; 265 266 let Inst{6-10} = A; 267 let Inst{11-15} = B; 268 let Inst{16-31} = C; 269} 270 271class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 272 InstrItinClass itin, list<dag> pattern> 273 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 274 let A = 0; 275 let Addr = 0; 276} 277 278class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 279 string asmstr, InstrItinClass itin, 280 list<dag> pattern> 281 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 282 let A = R; 283 let B = R; 284 let C = 0; 285} 286 287class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 288 dag OOL, dag IOL, string asmstr, 289 InstrItinClass itin, list<dag> pattern> 290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 291 bits<5> A; 292 bits<21> Addr; 293 294 let Pattern = pattern; 295 bits<24> LI; 296 297 let Inst{6-29} = LI; 298 let Inst{30} = aa; 299 let Inst{31} = lk; 300 301 let Inst{38-42} = A; 302 let Inst{43-47} = Addr{20-16}; // Base Reg 303 let Inst{48-63} = Addr{15-0}; // Displacement 304} 305 306// This is used to emit BL8+NOP. 307class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 308 dag OOL, dag IOL, string asmstr, 309 InstrItinClass itin, list<dag> pattern> 310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 311 OOL, IOL, asmstr, itin, pattern> { 312 let A = 0; 313 let Addr = 0; 314} 315 316class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 317 InstrItinClass itin> 318 : I<opcode, OOL, IOL, asmstr, itin> { 319 bits<3> BF; 320 bits<1> L; 321 bits<5> RA; 322 bits<16> I; 323 324 let Inst{6-8} = BF; 325 let Inst{9} = 0; 326 let Inst{10} = L; 327 let Inst{11-15} = RA; 328 let Inst{16-31} = I; 329} 330 331class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 332 InstrItinClass itin> 333 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 334 let L = PPC64; 335} 336 337class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 338 InstrItinClass itin> 339 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 340 341class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 342 InstrItinClass itin> 343 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 344 let L = PPC64; 345} 346 347 348// 1.7.5 DS-Form 349class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 350 InstrItinClass itin, list<dag> pattern> 351 : I<opcode, OOL, IOL, asmstr, itin> { 352 bits<5> RST; 353 bits<19> DS_RA; 354 355 let Pattern = pattern; 356 357 let Inst{6-10} = RST; 358 let Inst{11-15} = DS_RA{18-14}; // Register # 359 let Inst{16-29} = DS_RA{13-0}; // Displacement. 360 let Inst{30-31} = xo; 361} 362 363// DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO] 364class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 365 string asmstr, InstrItinClass itin, list<dag> pattern> 366 : I<opcode, OOL, IOL, asmstr, itin> { 367 bits<6> XT; 368 bits<17> DS_RA; 369 370 let Pattern = pattern; 371 372 let Inst{6-10} = XT{4-0}; 373 let Inst{11-15} = DS_RA{16-12}; // Register # 374 let Inst{16-27} = DS_RA{11-0}; // Displacement. 375 let Inst{28} = XT{5}; 376 let Inst{29-31} = xo; 377} 378 379// 1.7.6 X-Form 380class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 381 InstrItinClass itin, list<dag> pattern> 382 : I<opcode, OOL, IOL, asmstr, itin> { 383 bits<5> RST; 384 bits<5> A; 385 bits<5> B; 386 387 let Pattern = pattern; 388 389 bit RC = 0; // set by isDOT 390 391 let Inst{6-10} = RST; 392 let Inst{11-15} = A; 393 let Inst{16-20} = B; 394 let Inst{21-30} = xo; 395 let Inst{31} = RC; 396} 397 398class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr, 399 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 400 let RST = 0; 401} 402 403class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 404 InstrItinClass itin> 405 : I<opcode, OOL, IOL, asmstr, itin> { 406 let Inst{21-30} = xo; 407} 408 409// This is the same as XForm_base_r3xo, but the first two operands are swapped 410// when code is emitted. 411class XForm_base_r3xo_swapped 412 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 413 InstrItinClass itin> 414 : I<opcode, OOL, IOL, asmstr, itin> { 415 bits<5> A; 416 bits<5> RST; 417 bits<5> B; 418 419 bit RC = 0; // set by isDOT 420 421 let Inst{6-10} = RST; 422 let Inst{11-15} = A; 423 let Inst{16-20} = B; 424 let Inst{21-30} = xo; 425 let Inst{31} = RC; 426} 427 428 429class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 430 InstrItinClass itin, list<dag> pattern> 431 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 432 433class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 434 InstrItinClass itin, list<dag> pattern> 435 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 436 let RST = 0; 437} 438 439class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 440 InstrItinClass itin, list<dag> pattern> 441 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 442 let A = 0; 443 let B = 0; 444} 445 446class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 447 InstrItinClass itin, list<dag> pattern> 448 : I<opcode, OOL, IOL, asmstr, itin> { 449 bits<5> RST; 450 bits<5> A; 451 bits<1> WS; 452 453 let Pattern = pattern; 454 455 let Inst{6-10} = RST; 456 let Inst{11-15} = A; 457 let Inst{20} = WS; 458 let Inst{21-30} = xo; 459 let Inst{31} = 0; 460} 461 462class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 463 InstrItinClass itin, list<dag> pattern> 464 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 465 let Pattern = pattern; 466} 467 468class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 469 InstrItinClass itin, list<dag> pattern> 470 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 471 472class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 473 InstrItinClass itin, list<dag> pattern> 474 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 475 let Pattern = pattern; 476} 477 478class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 479 InstrItinClass itin, list<dag> pattern> 480 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 481 let B = 0; 482 let Pattern = pattern; 483} 484 485class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 486 InstrItinClass itin> 487 : I<opcode, OOL, IOL, asmstr, itin> { 488 bits<3> BF; 489 bits<1> L; 490 bits<5> RA; 491 bits<5> RB; 492 493 let Inst{6-8} = BF; 494 let Inst{9} = 0; 495 let Inst{10} = L; 496 let Inst{11-15} = RA; 497 let Inst{16-20} = RB; 498 let Inst{21-30} = xo; 499 let Inst{31} = 0; 500} 501 502class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 503 InstrItinClass itin> 504 : I<opcode, OOL, IOL, asmstr, itin> { 505 bits<4> CT; 506 bits<5> RA; 507 bits<5> RB; 508 509 let Inst{6} = 0; 510 let Inst{7-10} = CT; 511 let Inst{11-15} = RA; 512 let Inst{16-20} = RB; 513 let Inst{21-30} = xo; 514 let Inst{31} = 0; 515} 516 517class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 518 InstrItinClass itin> 519 : I<opcode, OOL, IOL, asmstr, itin> { 520 bits<5> RS; 521 bits<4> SR; 522 523 let Inst{6-10} = RS; 524 let Inst{12-15} = SR; 525 let Inst{21-30} = xo; 526} 527 528class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 529 InstrItinClass itin> 530 : I<opcode, OOL, IOL, asmstr, itin> { 531 bits<5> MO; 532 533 let Inst{6-10} = MO; 534 let Inst{21-30} = xo; 535} 536 537class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 538 InstrItinClass itin> 539 : I<opcode, OOL, IOL, asmstr, itin> { 540 bits<5> RS; 541 bits<5> RB; 542 543 let Inst{6-10} = RS; 544 let Inst{16-20} = RB; 545 let Inst{21-30} = xo; 546} 547 548class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 549 InstrItinClass itin> 550 : I<opcode, OOL, IOL, asmstr, itin> { 551 bits<5> RS; 552 bits<1> L; 553 554 let Inst{6-10} = RS; 555 let Inst{15} = L; 556 let Inst{21-30} = xo; 557} 558 559class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 560 InstrItinClass itin> 561 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 562 let L = PPC64; 563} 564 565class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 566 InstrItinClass itin> 567 : I<opcode, OOL, IOL, asmstr, itin> { 568 bits<3> BF; 569 bits<5> FRA; 570 bits<5> FRB; 571 572 let Inst{6-8} = BF; 573 let Inst{9-10} = 0; 574 let Inst{11-15} = FRA; 575 let Inst{16-20} = FRB; 576 let Inst{21-30} = xo; 577 let Inst{31} = 0; 578} 579 580// Used for QPX 581class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 582 InstrItinClass itin, list<dag> pattern> 583 : I<opcode, OOL, IOL, asmstr, itin> { 584 bits<5> FRT; 585 bits<5> FRA; 586 bits<5> FRB; 587 588 let Pattern = pattern; 589 590 let Inst{6-10} = FRT; 591 let Inst{11-15} = FRA; 592 let Inst{16-20} = FRB; 593 let Inst{21-30} = xo; 594 let Inst{31} = 0; 595} 596 597class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 598 InstrItinClass itin, list<dag> pattern> 599 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 600 let FRA = 0; 601} 602 603class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr, 604 InstrItinClass itin, list<dag> pattern> 605 : I<opcode, OOL, IOL, asmstr, itin> { 606 bits<5> FRT; 607 bits<5> FRA; 608 bits<5> FRB; 609 bits<4> tttt; 610 611 let Pattern = pattern; 612 613 let Inst{6-10} = FRT; 614 let Inst{11-15} = FRA; 615 let Inst{16-20} = FRB; 616 let Inst{21-24} = tttt; 617 let Inst{25-30} = xo; 618 let Inst{31} = 0; 619} 620 621class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 622 InstrItinClass itin, list<dag> pattern> 623 : I<opcode, OOL, IOL, asmstr, itin> { 624 let Pattern = pattern; 625 let Inst{6-10} = 31; 626 let Inst{11-15} = 0; 627 let Inst{16-20} = 0; 628 let Inst{21-30} = xo; 629 let Inst{31} = 0; 630} 631 632class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 633 string asmstr, InstrItinClass itin, list<dag> pattern> 634 : I<opcode, OOL, IOL, asmstr, itin> { 635 bits<2> L; 636 637 let Pattern = pattern; 638 let Inst{6-8} = 0; 639 let Inst{9-10} = L; 640 let Inst{11-15} = 0; 641 let Inst{16-20} = 0; 642 let Inst{21-30} = xo; 643 let Inst{31} = 0; 644} 645 646class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 647 string asmstr, InstrItinClass itin, list<dag> pattern> 648 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 649 let L = 0; 650} 651 652class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 653 InstrItinClass itin, list<dag> pattern> 654 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 655} 656 657class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 658 InstrItinClass itin, list<dag> pattern> 659 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 660 let A = 0; 661} 662 663class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 664 InstrItinClass itin, list<dag> pattern> 665 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 666} 667 668// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 669// numbers presumably relates to some document, but I haven't found it. 670class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 671 InstrItinClass itin, list<dag> pattern> 672 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 673 let Pattern = pattern; 674 675 bit RC = 0; // set by isDOT 676 677 let Inst{6-10} = RST; 678 let Inst{11-20} = 0; 679 let Inst{21-30} = xo; 680 let Inst{31} = RC; 681} 682class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 683 InstrItinClass itin, list<dag> pattern> 684 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 685 let Pattern = pattern; 686 bits<5> FM; 687 688 bit RC = 0; // set by isDOT 689 690 let Inst{6-10} = FM; 691 let Inst{11-20} = 0; 692 let Inst{21-30} = xo; 693 let Inst{31} = RC; 694} 695 696class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 697 InstrItinClass itin, list<dag> pattern> 698 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 699 let RST = 0; 700 let A = 0; 701 let B = 0; 702} 703 704class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 705 InstrItinClass itin, list<dag> pattern> 706 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 707 let RST = 0; 708 let A = 0; 709} 710 711class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 712 string asmstr, InstrItinClass itin, list<dag> pattern> 713 : I<opcode, OOL, IOL, asmstr, itin> { 714 bit R; 715 716 bit RC = 1; 717 718 let Inst{6-9} = 0; 719 let Inst{10} = R; 720 let Inst{11-20} = 0; 721 let Inst{21-30} = xo; 722 let Inst{31} = RC; 723} 724 725class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 726 string asmstr, InstrItinClass itin, list<dag> pattern> 727 : I<opcode, OOL, IOL, asmstr, itin> { 728 bit A; 729 730 bit RC = 1; 731 732 let Inst{6} = A; 733 let Inst{7-20} = 0; 734 let Inst{21-30} = xo; 735 let Inst{31} = RC; 736} 737 738class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 739 InstrItinClass itin, list<dag> pattern> 740 : I<opcode, OOL, IOL, asmstr, itin> { 741 bit L; 742 743 bit RC = 0; // set by isDOT 744 745 let Inst{7-9} = 0; 746 let Inst{10} = L; 747 let Inst{11-20} = 0; 748 let Inst{21-30} = xo; 749 let Inst{31} = RC; 750} 751 752class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 753 InstrItinClass itin, list<dag> pattern> 754 : I<opcode, OOL, IOL, asmstr, itin> { 755 bits<3> BF; 756 757 bit RC = 0; 758 759 let Inst{6-8} = BF; 760 let Inst{9-20} = 0; 761 let Inst{21-30} = xo; 762 let Inst{31} = RC; 763} 764 765// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO] 766class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, 767 string asmstr, InstrItinClass itin, list<dag> pattern> 768 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 769 let A = xo2; 770} 771 772class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 773 string asmstr, InstrItinClass itin, list<dag> pattern> 774 : I<opcode, OOL, IOL, asmstr, itin> { 775 bits<3> BF; 776 bits<7> DCMX; 777 bits<5> VB; 778 779 let Pattern = pattern; 780 781 let Inst{6-8} = BF; 782 let Inst{9-15} = DCMX; 783 let Inst{16-20} = VB; 784 let Inst{21-30} = xo; 785 let Inst{31} = 0; 786} 787 788class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 789 string asmstr, InstrItinClass itin, list<dag> pattern> 790 : I<opcode, OOL, IOL, asmstr, itin> { 791 bits<6> XT; 792 bits<8> IMM8; 793 794 let Pattern = pattern; 795 796 let Inst{6-10} = XT{4-0}; 797 let Inst{11-12} = 0; 798 let Inst{13-20} = IMM8; 799 let Inst{21-30} = xo; 800 let Inst{31} = XT{5}; 801} 802 803// XX*-Form (VSX) 804class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 805 InstrItinClass itin, list<dag> pattern> 806 : I<opcode, OOL, IOL, asmstr, itin> { 807 bits<6> XT; 808 bits<5> A; 809 bits<5> B; 810 811 let Pattern = pattern; 812 813 let Inst{6-10} = XT{4-0}; 814 let Inst{11-15} = A; 815 let Inst{16-20} = B; 816 let Inst{21-30} = xo; 817 let Inst{31} = XT{5}; 818} 819 820class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 821 string asmstr, InstrItinClass itin, list<dag> pattern> 822 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 823 let B = 0; 824} 825 826class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 827 InstrItinClass itin, list<dag> pattern> 828 : I<opcode, OOL, IOL, asmstr, itin> { 829 bits<6> XT; 830 bits<6> XB; 831 832 let Pattern = pattern; 833 834 let Inst{6-10} = XT{4-0}; 835 let Inst{11-15} = 0; 836 let Inst{16-20} = XB{4-0}; 837 let Inst{21-29} = xo; 838 let Inst{30} = XB{5}; 839 let Inst{31} = XT{5}; 840} 841 842class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 843 InstrItinClass itin, list<dag> pattern> 844 : I<opcode, OOL, IOL, asmstr, itin> { 845 bits<3> CR; 846 bits<6> XB; 847 848 let Pattern = pattern; 849 850 let Inst{6-8} = CR; 851 let Inst{9-15} = 0; 852 let Inst{16-20} = XB{4-0}; 853 let Inst{21-29} = xo; 854 let Inst{30} = XB{5}; 855 let Inst{31} = 0; 856} 857 858class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 859 InstrItinClass itin, list<dag> pattern> 860 : I<opcode, OOL, IOL, asmstr, itin> { 861 bits<6> XT; 862 bits<6> XB; 863 bits<2> D; 864 865 let Pattern = pattern; 866 867 let Inst{6-10} = XT{4-0}; 868 let Inst{11-13} = 0; 869 let Inst{14-15} = D; 870 let Inst{16-20} = XB{4-0}; 871 let Inst{21-29} = xo; 872 let Inst{30} = XB{5}; 873 let Inst{31} = XT{5}; 874} 875 876class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 877 string asmstr, InstrItinClass itin, list<dag> pattern> 878 : I<opcode, OOL, IOL, asmstr, itin> { 879 bits<6> XT; 880 bits<6> XB; 881 bits<5> UIM5; 882 883 let Pattern = pattern; 884 885 let Inst{6-10} = XT{4-0}; 886 let Inst{11-15} = UIM5; 887 let Inst{16-20} = XB{4-0}; 888 let Inst{21-29} = xo; 889 let Inst{30} = XB{5}; 890 let Inst{31} = XT{5}; 891} 892 893// [PO T XO B XO BX /] 894class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 895 string asmstr, InstrItinClass itin, list<dag> pattern> 896 : I<opcode, OOL, IOL, asmstr, itin> { 897 bits<5> RT; 898 bits<6> XB; 899 900 let Pattern = pattern; 901 902 let Inst{6-10} = RT; 903 let Inst{11-15} = xo2; 904 let Inst{16-20} = XB{4-0}; 905 let Inst{21-29} = xo; 906 let Inst{30} = XB{5}; 907 let Inst{31} = 0; 908} 909 910// [PO T XO B XO BX TX] 911class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 912 string asmstr, InstrItinClass itin, list<dag> pattern> 913 : I<opcode, OOL, IOL, asmstr, itin> { 914 bits<6> XT; 915 bits<6> XB; 916 917 let Pattern = pattern; 918 919 let Inst{6-10} = XT{4-0}; 920 let Inst{11-15} = xo2; 921 let Inst{16-20} = XB{4-0}; 922 let Inst{21-29} = xo; 923 let Inst{30} = XB{5}; 924 let Inst{31} = XT{5}; 925} 926 927class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 928 string asmstr, InstrItinClass itin, list<dag> pattern> 929 : I<opcode, OOL, IOL, asmstr, itin> { 930 bits<3> BF; 931 bits<7> DCMX; 932 bits<6> XB; 933 934 let Pattern = pattern; 935 936 let Inst{6-8} = BF; 937 let Inst{9-15} = DCMX; 938 let Inst{16-20} = XB{4-0}; 939 let Inst{21-29} = xo; 940 let Inst{30} = XB{5}; 941 let Inst{31} = 0; 942} 943 944class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2, 945 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 946 list<dag> pattern> 947 : I<opcode, OOL, IOL, asmstr, itin> { 948 bits<6> XT; 949 bits<7> DCMX; 950 bits<6> XB; 951 952 let Pattern = pattern; 953 954 let Inst{6-10} = XT{4-0}; 955 let Inst{11-15} = DCMX{4-0}; 956 let Inst{16-20} = XB{4-0}; 957 let Inst{21-24} = xo1; 958 let Inst{25} = DCMX{5}; 959 let Inst{26-28} = xo2; 960 let Inst{29} = DCMX{6}; 961 let Inst{30} = XB{5}; 962 let Inst{31} = XT{5}; 963} 964 965class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 966 InstrItinClass itin, list<dag> pattern> 967 : I<opcode, OOL, IOL, asmstr, itin> { 968 bits<6> XT; 969 bits<6> XA; 970 bits<6> XB; 971 972 let Pattern = pattern; 973 974 let Inst{6-10} = XT{4-0}; 975 let Inst{11-15} = XA{4-0}; 976 let Inst{16-20} = XB{4-0}; 977 let Inst{21-28} = xo; 978 let Inst{29} = XA{5}; 979 let Inst{30} = XB{5}; 980 let Inst{31} = XT{5}; 981} 982 983class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 984 InstrItinClass itin, list<dag> pattern> 985 : I<opcode, OOL, IOL, asmstr, itin> { 986 bits<3> CR; 987 bits<6> XA; 988 bits<6> XB; 989 990 let Pattern = pattern; 991 992 let Inst{6-8} = CR; 993 let Inst{9-10} = 0; 994 let Inst{11-15} = XA{4-0}; 995 let Inst{16-20} = XB{4-0}; 996 let Inst{21-28} = xo; 997 let Inst{29} = XA{5}; 998 let Inst{30} = XB{5}; 999 let Inst{31} = 0; 1000} 1001 1002class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1003 InstrItinClass itin, list<dag> pattern> 1004 : I<opcode, OOL, IOL, asmstr, itin> { 1005 bits<6> XT; 1006 bits<6> XA; 1007 bits<6> XB; 1008 bits<2> D; 1009 1010 let Pattern = pattern; 1011 1012 let Inst{6-10} = XT{4-0}; 1013 let Inst{11-15} = XA{4-0}; 1014 let Inst{16-20} = XB{4-0}; 1015 let Inst{21} = 0; 1016 let Inst{22-23} = D; 1017 let Inst{24-28} = xo; 1018 let Inst{29} = XA{5}; 1019 let Inst{30} = XB{5}; 1020 let Inst{31} = XT{5}; 1021} 1022 1023class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr, 1024 InstrItinClass itin, list<dag> pattern> 1025 : I<opcode, OOL, IOL, asmstr, itin> { 1026 bits<6> XT; 1027 bits<6> XA; 1028 bits<6> XB; 1029 1030 let Pattern = pattern; 1031 1032 bit RC = 0; // set by isDOT 1033 1034 let Inst{6-10} = XT{4-0}; 1035 let Inst{11-15} = XA{4-0}; 1036 let Inst{16-20} = XB{4-0}; 1037 let Inst{21} = RC; 1038 let Inst{22-28} = xo; 1039 let Inst{29} = XA{5}; 1040 let Inst{30} = XB{5}; 1041 let Inst{31} = XT{5}; 1042} 1043 1044class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 1045 InstrItinClass itin, list<dag> pattern> 1046 : I<opcode, OOL, IOL, asmstr, itin> { 1047 bits<6> XT; 1048 bits<6> XA; 1049 bits<6> XB; 1050 bits<6> XC; 1051 1052 let Pattern = pattern; 1053 1054 let Inst{6-10} = XT{4-0}; 1055 let Inst{11-15} = XA{4-0}; 1056 let Inst{16-20} = XB{4-0}; 1057 let Inst{21-25} = XC{4-0}; 1058 let Inst{26-27} = xo; 1059 let Inst{28} = XC{5}; 1060 let Inst{29} = XA{5}; 1061 let Inst{30} = XB{5}; 1062 let Inst{31} = XT{5}; 1063} 1064 1065// DCB_Form - Form X instruction, used for dcb* instructions. 1066class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 1067 InstrItinClass itin, list<dag> pattern> 1068 : I<31, OOL, IOL, asmstr, itin> { 1069 bits<5> A; 1070 bits<5> B; 1071 1072 let Pattern = pattern; 1073 1074 let Inst{6-10} = immfield; 1075 let Inst{11-15} = A; 1076 let Inst{16-20} = B; 1077 let Inst{21-30} = xo; 1078 let Inst{31} = 0; 1079} 1080 1081class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr, 1082 InstrItinClass itin, list<dag> pattern> 1083 : I<31, OOL, IOL, asmstr, itin> { 1084 bits<5> TH; 1085 bits<5> A; 1086 bits<5> B; 1087 1088 let Pattern = pattern; 1089 1090 let Inst{6-10} = TH; 1091 let Inst{11-15} = A; 1092 let Inst{16-20} = B; 1093 let Inst{21-30} = xo; 1094 let Inst{31} = 0; 1095} 1096 1097// DSS_Form - Form X instruction, used for altivec dss* instructions. 1098class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr, 1099 InstrItinClass itin, list<dag> pattern> 1100 : I<31, OOL, IOL, asmstr, itin> { 1101 bits<2> STRM; 1102 bits<5> A; 1103 bits<5> B; 1104 1105 let Pattern = pattern; 1106 1107 let Inst{6} = T; 1108 let Inst{7-8} = 0; 1109 let Inst{9-10} = STRM; 1110 let Inst{11-15} = A; 1111 let Inst{16-20} = B; 1112 let Inst{21-30} = xo; 1113 let Inst{31} = 0; 1114} 1115 1116// 1.7.7 XL-Form 1117class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1118 InstrItinClass itin, list<dag> pattern> 1119 : I<opcode, OOL, IOL, asmstr, itin> { 1120 bits<5> CRD; 1121 bits<5> CRA; 1122 bits<5> CRB; 1123 1124 let Pattern = pattern; 1125 1126 let Inst{6-10} = CRD; 1127 let Inst{11-15} = CRA; 1128 let Inst{16-20} = CRB; 1129 let Inst{21-30} = xo; 1130 let Inst{31} = 0; 1131} 1132 1133class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1134 InstrItinClass itin, list<dag> pattern> 1135 : I<opcode, OOL, IOL, asmstr, itin> { 1136 bits<5> CRD; 1137 1138 let Pattern = pattern; 1139 1140 let Inst{6-10} = CRD; 1141 let Inst{11-15} = CRD; 1142 let Inst{16-20} = CRD; 1143 let Inst{21-30} = xo; 1144 let Inst{31} = 0; 1145} 1146 1147class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 1148 InstrItinClass itin, list<dag> pattern> 1149 : I<opcode, OOL, IOL, asmstr, itin> { 1150 bits<5> BO; 1151 bits<5> BI; 1152 bits<2> BH; 1153 1154 let Pattern = pattern; 1155 1156 let Inst{6-10} = BO; 1157 let Inst{11-15} = BI; 1158 let Inst{16-18} = 0; 1159 let Inst{19-20} = BH; 1160 let Inst{21-30} = xo; 1161 let Inst{31} = lk; 1162} 1163 1164class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 1165 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1166 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1167 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 1168 bits<3> CR; 1169 1170 let BO = BIBO{4-0}; 1171 let BI{0-1} = BIBO{5-6}; 1172 let BI{2-4} = CR{0-2}; 1173 let BH = 0; 1174} 1175 1176class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk, 1177 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1178 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1179 let BO = bo; 1180 let BH = 0; 1181} 1182 1183class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 1184 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1185 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1186 let BO = bo; 1187 let BI = bi; 1188 let BH = 0; 1189} 1190 1191class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1192 InstrItinClass itin> 1193 : I<opcode, OOL, IOL, asmstr, itin> { 1194 bits<3> BF; 1195 bits<3> BFA; 1196 1197 let Inst{6-8} = BF; 1198 let Inst{9-10} = 0; 1199 let Inst{11-13} = BFA; 1200 let Inst{14-15} = 0; 1201 let Inst{16-20} = 0; 1202 let Inst{21-30} = xo; 1203 let Inst{31} = 0; 1204} 1205 1206class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1207 InstrItinClass itin> 1208 : I<opcode, OOL, IOL, asmstr, itin> { 1209 bits<3> BF; 1210 bit W; 1211 bits<4> U; 1212 1213 bit RC = 0; 1214 1215 let Inst{6-8} = BF; 1216 let Inst{9-10} = 0; 1217 let Inst{11-14} = 0; 1218 let Inst{15} = W; 1219 let Inst{16-19} = U; 1220 let Inst{20} = 0; 1221 let Inst{21-30} = xo; 1222 let Inst{31} = RC; 1223} 1224 1225class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1226 InstrItinClass itin, list<dag> pattern> 1227 : I<opcode, OOL, IOL, asmstr, itin> { 1228 bits<1> S; 1229 1230 let Pattern = pattern; 1231 1232 let Inst{6-19} = 0; 1233 let Inst{20} = S; 1234 let Inst{21-30} = xo; 1235 let Inst{31} = 0; 1236} 1237 1238class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk, 1239 bits<6> opcode2, bits<2> xo2, 1240 dag OOL, dag IOL, string asmstr, 1241 InstrItinClass itin, list<dag> pattern> 1242 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1243 bits<5> BO; 1244 bits<5> BI; 1245 bits<2> BH; 1246 1247 bits<5> RST; 1248 bits<19> DS_RA; 1249 1250 let Pattern = pattern; 1251 1252 let Inst{6-10} = BO; 1253 let Inst{11-15} = BI; 1254 let Inst{16-18} = 0; 1255 let Inst{19-20} = BH; 1256 let Inst{21-30} = xo1; 1257 let Inst{31} = lk; 1258 1259 let Inst{38-42} = RST; 1260 let Inst{43-47} = DS_RA{18-14}; // Register # 1261 let Inst{48-61} = DS_RA{13-0}; // Displacement. 1262 let Inst{62-63} = xo2; 1263} 1264 1265class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1, 1266 bits<5> bo, bits<5> bi, bit lk, 1267 bits<6> opcode2, bits<2> xo2, 1268 dag OOL, dag IOL, string asmstr, 1269 InstrItinClass itin, list<dag> pattern> 1270 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2, 1271 OOL, IOL, asmstr, itin, pattern> { 1272 let BO = bo; 1273 let BI = bi; 1274 let BH = 0; 1275} 1276 1277// 1.7.8 XFX-Form 1278class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1279 InstrItinClass itin> 1280 : I<opcode, OOL, IOL, asmstr, itin> { 1281 bits<5> RT; 1282 bits<10> SPR; 1283 1284 let Inst{6-10} = RT; 1285 let Inst{11} = SPR{4}; 1286 let Inst{12} = SPR{3}; 1287 let Inst{13} = SPR{2}; 1288 let Inst{14} = SPR{1}; 1289 let Inst{15} = SPR{0}; 1290 let Inst{16} = SPR{9}; 1291 let Inst{17} = SPR{8}; 1292 let Inst{18} = SPR{7}; 1293 let Inst{19} = SPR{6}; 1294 let Inst{20} = SPR{5}; 1295 let Inst{21-30} = xo; 1296 let Inst{31} = 0; 1297} 1298 1299class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1300 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1301 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 1302 let SPR = spr; 1303} 1304 1305class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1306 InstrItinClass itin> 1307 : I<opcode, OOL, IOL, asmstr, itin> { 1308 bits<5> RT; 1309 1310 let Inst{6-10} = RT; 1311 let Inst{11-20} = 0; 1312 let Inst{21-30} = xo; 1313 let Inst{31} = 0; 1314} 1315 1316class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1317 InstrItinClass itin, list<dag> pattern> 1318 : I<opcode, OOL, IOL, asmstr, itin> { 1319 bits<5> RT; 1320 bits<10> Entry; 1321 let Pattern = pattern; 1322 1323 let Inst{6-10} = RT; 1324 let Inst{11-20} = Entry; 1325 let Inst{21-30} = xo; 1326 let Inst{31} = 0; 1327} 1328 1329class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1330 InstrItinClass itin> 1331 : I<opcode, OOL, IOL, asmstr, itin> { 1332 bits<8> FXM; 1333 bits<5> rS; 1334 1335 let Inst{6-10} = rS; 1336 let Inst{11} = 0; 1337 let Inst{12-19} = FXM; 1338 let Inst{20} = 0; 1339 let Inst{21-30} = xo; 1340 let Inst{31} = 0; 1341} 1342 1343class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1344 InstrItinClass itin> 1345 : I<opcode, OOL, IOL, asmstr, itin> { 1346 bits<5> ST; 1347 bits<8> FXM; 1348 1349 let Inst{6-10} = ST; 1350 let Inst{11} = 1; 1351 let Inst{12-19} = FXM; 1352 let Inst{20} = 0; 1353 let Inst{21-30} = xo; 1354 let Inst{31} = 0; 1355} 1356 1357class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1358 InstrItinClass itin> 1359 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 1360 1361class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1362 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1363 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 1364 let SPR = spr; 1365} 1366 1367// XFL-Form - MTFSF 1368// This is probably 1.7.9, but I don't have the reference that uses this 1369// numbering scheme... 1370class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1371 InstrItinClass itin, list<dag>pattern> 1372 : I<opcode, OOL, IOL, asmstr, itin> { 1373 bits<8> FM; 1374 bits<5> rT; 1375 1376 bit RC = 0; // set by isDOT 1377 let Pattern = pattern; 1378 1379 let Inst{6} = 0; 1380 let Inst{7-14} = FM; 1381 let Inst{15} = 0; 1382 let Inst{16-20} = rT; 1383 let Inst{21-30} = xo; 1384 let Inst{31} = RC; 1385} 1386 1387class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1388 InstrItinClass itin, list<dag>pattern> 1389 : I<opcode, OOL, IOL, asmstr, itin> { 1390 bit L; 1391 bits<8> FLM; 1392 bit W; 1393 bits<5> FRB; 1394 1395 bit RC = 0; // set by isDOT 1396 let Pattern = pattern; 1397 1398 let Inst{6} = L; 1399 let Inst{7-14} = FLM; 1400 let Inst{15} = W; 1401 let Inst{16-20} = FRB; 1402 let Inst{21-30} = xo; 1403 let Inst{31} = RC; 1404} 1405 1406// 1.7.10 XS-Form - SRADI. 1407class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1408 InstrItinClass itin, list<dag> pattern> 1409 : I<opcode, OOL, IOL, asmstr, itin> { 1410 bits<5> A; 1411 bits<5> RS; 1412 bits<6> SH; 1413 1414 bit RC = 0; // set by isDOT 1415 let Pattern = pattern; 1416 1417 let Inst{6-10} = RS; 1418 let Inst{11-15} = A; 1419 let Inst{16-20} = SH{4,3,2,1,0}; 1420 let Inst{21-29} = xo; 1421 let Inst{30} = SH{5}; 1422 let Inst{31} = RC; 1423} 1424 1425// 1.7.11 XO-Form 1426class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 1427 InstrItinClass itin, list<dag> pattern> 1428 : I<opcode, OOL, IOL, asmstr, itin> { 1429 bits<5> RT; 1430 bits<5> RA; 1431 bits<5> RB; 1432 1433 let Pattern = pattern; 1434 1435 bit RC = 0; // set by isDOT 1436 1437 let Inst{6-10} = RT; 1438 let Inst{11-15} = RA; 1439 let Inst{16-20} = RB; 1440 let Inst{21} = oe; 1441 let Inst{22-30} = xo; 1442 let Inst{31} = RC; 1443} 1444 1445class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 1446 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1447 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 1448 let RB = 0; 1449} 1450 1451// 1.7.12 A-Form 1452class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1453 InstrItinClass itin, list<dag> pattern> 1454 : I<opcode, OOL, IOL, asmstr, itin> { 1455 bits<5> FRT; 1456 bits<5> FRA; 1457 bits<5> FRC; 1458 bits<5> FRB; 1459 1460 let Pattern = pattern; 1461 1462 bit RC = 0; // set by isDOT 1463 1464 let Inst{6-10} = FRT; 1465 let Inst{11-15} = FRA; 1466 let Inst{16-20} = FRB; 1467 let Inst{21-25} = FRC; 1468 let Inst{26-30} = xo; 1469 let Inst{31} = RC; 1470} 1471 1472class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1473 InstrItinClass itin, list<dag> pattern> 1474 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1475 let FRC = 0; 1476} 1477 1478class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1479 InstrItinClass itin, list<dag> pattern> 1480 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1481 let FRB = 0; 1482} 1483 1484class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1485 InstrItinClass itin, list<dag> pattern> 1486 : I<opcode, OOL, IOL, asmstr, itin> { 1487 bits<5> RT; 1488 bits<5> RA; 1489 bits<5> RB; 1490 bits<5> COND; 1491 1492 let Pattern = pattern; 1493 1494 let Inst{6-10} = RT; 1495 let Inst{11-15} = RA; 1496 let Inst{16-20} = RB; 1497 let Inst{21-25} = COND; 1498 let Inst{26-30} = xo; 1499 let Inst{31} = 0; 1500} 1501 1502// Used for QPX 1503class AForm_4a<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1504 InstrItinClass itin, list<dag> pattern> 1505 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1506 let FRA = 0; 1507 let FRC = 0; 1508} 1509 1510// 1.7.13 M-Form 1511class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1512 InstrItinClass itin, list<dag> pattern> 1513 : I<opcode, OOL, IOL, asmstr, itin> { 1514 bits<5> RA; 1515 bits<5> RS; 1516 bits<5> RB; 1517 bits<5> MB; 1518 bits<5> ME; 1519 1520 let Pattern = pattern; 1521 1522 bit RC = 0; // set by isDOT 1523 1524 let Inst{6-10} = RS; 1525 let Inst{11-15} = RA; 1526 let Inst{16-20} = RB; 1527 let Inst{21-25} = MB; 1528 let Inst{26-30} = ME; 1529 let Inst{31} = RC; 1530} 1531 1532class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1533 InstrItinClass itin, list<dag> pattern> 1534 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 1535} 1536 1537// 1.7.14 MD-Form 1538class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 1539 InstrItinClass itin, list<dag> pattern> 1540 : I<opcode, OOL, IOL, asmstr, itin> { 1541 bits<5> RA; 1542 bits<5> RS; 1543 bits<6> SH; 1544 bits<6> MBE; 1545 1546 let Pattern = pattern; 1547 1548 bit RC = 0; // set by isDOT 1549 1550 let Inst{6-10} = RS; 1551 let Inst{11-15} = RA; 1552 let Inst{16-20} = SH{4,3,2,1,0}; 1553 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1554 let Inst{27-29} = xo; 1555 let Inst{30} = SH{5}; 1556 let Inst{31} = RC; 1557} 1558 1559class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 1560 InstrItinClass itin, list<dag> pattern> 1561 : I<opcode, OOL, IOL, asmstr, itin> { 1562 bits<5> RA; 1563 bits<5> RS; 1564 bits<5> RB; 1565 bits<6> MBE; 1566 1567 let Pattern = pattern; 1568 1569 bit RC = 0; // set by isDOT 1570 1571 let Inst{6-10} = RS; 1572 let Inst{11-15} = RA; 1573 let Inst{16-20} = RB; 1574 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1575 let Inst{27-30} = xo; 1576 let Inst{31} = RC; 1577} 1578 1579 1580// E-1 VA-Form 1581 1582// VAForm_1 - DACB ordering. 1583class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 1584 InstrItinClass itin, list<dag> pattern> 1585 : I<4, OOL, IOL, asmstr, itin> { 1586 bits<5> VD; 1587 bits<5> VA; 1588 bits<5> VC; 1589 bits<5> VB; 1590 1591 let Pattern = pattern; 1592 1593 let Inst{6-10} = VD; 1594 let Inst{11-15} = VA; 1595 let Inst{16-20} = VB; 1596 let Inst{21-25} = VC; 1597 let Inst{26-31} = xo; 1598} 1599 1600// VAForm_1a - DABC ordering. 1601class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 1602 InstrItinClass itin, list<dag> pattern> 1603 : I<4, OOL, IOL, asmstr, itin> { 1604 bits<5> VD; 1605 bits<5> VA; 1606 bits<5> VB; 1607 bits<5> VC; 1608 1609 let Pattern = pattern; 1610 1611 let Inst{6-10} = VD; 1612 let Inst{11-15} = VA; 1613 let Inst{16-20} = VB; 1614 let Inst{21-25} = VC; 1615 let Inst{26-31} = xo; 1616} 1617 1618class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 1619 InstrItinClass itin, list<dag> pattern> 1620 : I<4, OOL, IOL, asmstr, itin> { 1621 bits<5> VD; 1622 bits<5> VA; 1623 bits<5> VB; 1624 bits<4> SH; 1625 1626 let Pattern = pattern; 1627 1628 let Inst{6-10} = VD; 1629 let Inst{11-15} = VA; 1630 let Inst{16-20} = VB; 1631 let Inst{21} = 0; 1632 let Inst{22-25} = SH; 1633 let Inst{26-31} = xo; 1634} 1635 1636// E-2 VX-Form 1637class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 1638 InstrItinClass itin, list<dag> pattern> 1639 : I<4, OOL, IOL, asmstr, itin> { 1640 bits<5> VD; 1641 bits<5> VA; 1642 bits<5> VB; 1643 1644 let Pattern = pattern; 1645 1646 let Inst{6-10} = VD; 1647 let Inst{11-15} = VA; 1648 let Inst{16-20} = VB; 1649 let Inst{21-31} = xo; 1650} 1651 1652class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 1653 InstrItinClass itin, list<dag> pattern> 1654 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 1655 let VA = VD; 1656 let VB = VD; 1657} 1658 1659 1660class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 1661 InstrItinClass itin, list<dag> pattern> 1662 : I<4, OOL, IOL, asmstr, itin> { 1663 bits<5> VD; 1664 bits<5> VB; 1665 1666 let Pattern = pattern; 1667 1668 let Inst{6-10} = VD; 1669 let Inst{11-15} = 0; 1670 let Inst{16-20} = VB; 1671 let Inst{21-31} = xo; 1672} 1673 1674class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 1675 InstrItinClass itin, list<dag> pattern> 1676 : I<4, OOL, IOL, asmstr, itin> { 1677 bits<5> VD; 1678 bits<5> IMM; 1679 1680 let Pattern = pattern; 1681 1682 let Inst{6-10} = VD; 1683 let Inst{11-15} = IMM; 1684 let Inst{16-20} = 0; 1685 let Inst{21-31} = xo; 1686} 1687 1688/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 1689class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 1690 InstrItinClass itin, list<dag> pattern> 1691 : I<4, OOL, IOL, asmstr, itin> { 1692 bits<5> VD; 1693 1694 let Pattern = pattern; 1695 1696 let Inst{6-10} = VD; 1697 let Inst{11-15} = 0; 1698 let Inst{16-20} = 0; 1699 let Inst{21-31} = xo; 1700} 1701 1702/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 1703class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 1704 InstrItinClass itin, list<dag> pattern> 1705 : I<4, OOL, IOL, asmstr, itin> { 1706 bits<5> VB; 1707 1708 let Pattern = pattern; 1709 1710 let Inst{6-10} = 0; 1711 let Inst{11-15} = 0; 1712 let Inst{16-20} = VB; 1713 let Inst{21-31} = xo; 1714} 1715 1716// e.g. [PO VRT EO VRB XO] 1717class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL, 1718 string asmstr, InstrItinClass itin, list<dag> pattern> 1719 : I<4, OOL, IOL, asmstr, itin> { 1720 bits<5> RD; 1721 bits<5> VB; 1722 1723 let Pattern = pattern; 1724 1725 let Inst{6-10} = RD; 1726 let Inst{11-15} = eo; 1727 let Inst{16-20} = VB; 1728 let Inst{21-31} = xo; 1729} 1730 1731/// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX" 1732class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr, 1733 InstrItinClass itin, list<dag> pattern> 1734 : I<4, OOL, IOL, asmstr, itin> { 1735 bits<5> VD; 1736 bits<5> VA; 1737 bits<1> ST; 1738 bits<4> SIX; 1739 1740 let Pattern = pattern; 1741 1742 let Inst{6-10} = VD; 1743 let Inst{11-15} = VA; 1744 let Inst{16} = ST; 1745 let Inst{17-20} = SIX; 1746 let Inst{21-31} = xo; 1747} 1748 1749/// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox" 1750class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr, 1751 InstrItinClass itin, list<dag> pattern> 1752 : I<4, OOL, IOL, asmstr, itin> { 1753 bits<5> VD; 1754 bits<5> VA; 1755 1756 let Pattern = pattern; 1757 1758 let Inst{6-10} = VD; 1759 let Inst{11-15} = VA; 1760 let Inst{16-20} = 0; 1761 let Inst{21-31} = xo; 1762} 1763 1764// E-4 VXR-Form 1765class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 1766 InstrItinClass itin, list<dag> pattern> 1767 : I<4, OOL, IOL, asmstr, itin> { 1768 bits<5> VD; 1769 bits<5> VA; 1770 bits<5> VB; 1771 bit RC = 0; 1772 1773 let Pattern = pattern; 1774 1775 let Inst{6-10} = VD; 1776 let Inst{11-15} = VA; 1777 let Inst{16-20} = VB; 1778 let Inst{21} = RC; 1779 let Inst{22-31} = xo; 1780} 1781 1782// VX-Form: [PO VRT EO VRB 1 PS XO] 1783class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo, 1784 dag OOL, dag IOL, string asmstr, 1785 InstrItinClass itin, list<dag> pattern> 1786 : I<4, OOL, IOL, asmstr, itin> { 1787 bits<5> VD; 1788 bits<5> VB; 1789 bit PS; 1790 1791 let Pattern = pattern; 1792 1793 let Inst{6-10} = VD; 1794 let Inst{11-15} = eo; 1795 let Inst{16-20} = VB; 1796 let Inst{21} = 1; 1797 let Inst{22} = PS; 1798 let Inst{23-31} = xo; 1799} 1800 1801// VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO] 1802class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr, 1803 InstrItinClass itin, list<dag> pattern> 1804 : I<4, OOL, IOL, asmstr, itin> { 1805 bits<5> VD; 1806 bits<5> VA; 1807 bits<5> VB; 1808 bit PS; 1809 1810 let Pattern = pattern; 1811 1812 let Inst{6-10} = VD; 1813 let Inst{11-15} = VA; 1814 let Inst{16-20} = VB; 1815 let Inst{21} = 1; 1816 let Inst{22} = PS; 1817 let Inst{23-31} = xo; 1818} 1819 1820// Z23-Form (used by QPX) 1821class Z23Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1822 InstrItinClass itin, list<dag> pattern> 1823 : I<opcode, OOL, IOL, asmstr, itin> { 1824 bits<5> FRT; 1825 bits<5> FRA; 1826 bits<5> FRB; 1827 bits<2> idx; 1828 1829 let Pattern = pattern; 1830 1831 bit RC = 0; // set by isDOT 1832 1833 let Inst{6-10} = FRT; 1834 let Inst{11-15} = FRA; 1835 let Inst{16-20} = FRB; 1836 let Inst{21-22} = idx; 1837 let Inst{23-30} = xo; 1838 let Inst{31} = RC; 1839} 1840 1841class Z23Form_2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1842 InstrItinClass itin, list<dag> pattern> 1843 : Z23Form_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1844 let FRB = 0; 1845} 1846 1847class Z23Form_3<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1848 InstrItinClass itin, list<dag> pattern> 1849 : I<opcode, OOL, IOL, asmstr, itin> { 1850 bits<5> FRT; 1851 bits<12> idx; 1852 1853 let Pattern = pattern; 1854 1855 bit RC = 0; // set by isDOT 1856 1857 let Inst{6-10} = FRT; 1858 let Inst{11-22} = idx; 1859 let Inst{23-30} = xo; 1860 let Inst{31} = RC; 1861} 1862 1863//===----------------------------------------------------------------------===// 1864class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 1865 : I<0, OOL, IOL, asmstr, NoItinerary> { 1866 let isCodeGenOnly = 1; 1867 let PPC64 = 0; 1868 let Pattern = pattern; 1869 let Inst{31-0} = 0; 1870} 1871