1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// PowerPC instruction formats 13 14class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 15 : Instruction { 16 field bits<32> Inst; 17 field bits<32> SoftFail = 0; 18 let Size = 4; 19 20 bit PPC64 = 0; // Default value, override with isPPC64 21 22 let Namespace = "PPC"; 23 let Inst{0-5} = opcode; 24 let OutOperandList = OOL; 25 let InOperandList = IOL; 26 let AsmString = asmstr; 27 let Itinerary = itin; 28 29 bits<1> PPC970_First = 0; 30 bits<1> PPC970_Single = 0; 31 bits<1> PPC970_Cracked = 0; 32 bits<3> PPC970_Unit = 0; 33 34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 35 /// these must be reflected there! See comments there for what these are. 36 let TSFlags{0} = PPC970_First; 37 let TSFlags{1} = PPC970_Single; 38 let TSFlags{2} = PPC970_Cracked; 39 let TSFlags{5-3} = PPC970_Unit; 40 41 // Fields used for relation models. 42 string BaseName = ""; 43 44 // For cases where multiple instruction definitions really represent the 45 // same underlying instruction but with one definition for 64-bit arguments 46 // and one for 32-bit arguments, this bit breaks the degeneracy between 47 // the two forms and allows TableGen to generate mapping tables. 48 bit Interpretation64Bit = 0; 49} 50 51class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 52class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 53class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 54class PPC970_MicroCode; 55 56class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 57class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 58class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 59class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 60class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 61class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 62class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 63class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 64 65// Two joined instructions; used to emit two adjacent instructions as one. 66// The itinerary from the first instruction is used for scheduling and 67// classification. 68class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 69 InstrItinClass itin> 70 : Instruction { 71 field bits<64> Inst; 72 field bits<64> SoftFail = 0; 73 let Size = 8; 74 75 bit PPC64 = 0; // Default value, override with isPPC64 76 77 let Namespace = "PPC"; 78 let Inst{0-5} = opcode1; 79 let Inst{32-37} = opcode2; 80 let OutOperandList = OOL; 81 let InOperandList = IOL; 82 let AsmString = asmstr; 83 let Itinerary = itin; 84 85 bits<1> PPC970_First = 0; 86 bits<1> PPC970_Single = 0; 87 bits<1> PPC970_Cracked = 0; 88 bits<3> PPC970_Unit = 0; 89 90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 91 /// these must be reflected there! See comments there for what these are. 92 let TSFlags{0} = PPC970_First; 93 let TSFlags{1} = PPC970_Single; 94 let TSFlags{2} = PPC970_Cracked; 95 let TSFlags{5-3} = PPC970_Unit; 96 97 // Fields used for relation models. 98 string BaseName = ""; 99 bit Interpretation64Bit = 0; 100} 101 102// 1.7.1 I-Form 103class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 104 InstrItinClass itin, list<dag> pattern> 105 : I<opcode, OOL, IOL, asmstr, itin> { 106 let Pattern = pattern; 107 bits<24> LI; 108 109 let Inst{6-29} = LI; 110 let Inst{30} = aa; 111 let Inst{31} = lk; 112} 113 114// 1.7.2 B-Form 115class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 118 bits<3> CR; 119 bits<14> BD; 120 121 bits<5> BI; 122 let BI{0-1} = BIBO{5-6}; 123 let BI{2-4} = CR{0-2}; 124 125 let Inst{6-10} = BIBO{4-0}; 126 let Inst{11-15} = BI; 127 let Inst{16-29} = BD; 128 let Inst{30} = aa; 129 let Inst{31} = lk; 130} 131 132class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 133 string asmstr> 134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 135 let BIBO{4-0} = bo; 136 let BIBO{6-5} = 0; 137 let CR = 0; 138} 139 140class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 141 dag OOL, dag IOL, string asmstr> 142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 143 bits<14> BD; 144 145 let Inst{6-10} = bo; 146 let Inst{11-15} = bi; 147 let Inst{16-29} = BD; 148 let Inst{30} = aa; 149 let Inst{31} = lk; 150} 151 152class BForm_3<bits<6> opcode, bit aa, bit lk, 153 dag OOL, dag IOL, string asmstr> 154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 155 bits<5> BO; 156 bits<5> BI; 157 bits<14> BD; 158 159 let Inst{6-10} = BO; 160 let Inst{11-15} = BI; 161 let Inst{16-29} = BD; 162 let Inst{30} = aa; 163 let Inst{31} = lk; 164} 165 166class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, 167 dag OOL, dag IOL, string asmstr> 168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 169 bits<5> BI; 170 bits<14> BD; 171 172 let Inst{6-10} = bo; 173 let Inst{11-15} = BI; 174 let Inst{16-29} = BD; 175 let Inst{30} = aa; 176 let Inst{31} = lk; 177} 178 179// 1.7.3 SC-Form 180class SCForm<bits<6> opcode, bits<1> xo, 181 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 182 list<dag> pattern> 183 : I<opcode, OOL, IOL, asmstr, itin> { 184 bits<7> LEV; 185 186 let Pattern = pattern; 187 188 let Inst{20-26} = LEV; 189 let Inst{30} = xo; 190} 191 192// 1.7.4 D-Form 193class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 194 InstrItinClass itin, list<dag> pattern> 195 : I<opcode, OOL, IOL, asmstr, itin> { 196 bits<5> A; 197 bits<5> B; 198 bits<16> C; 199 200 let Pattern = pattern; 201 202 let Inst{6-10} = A; 203 let Inst{11-15} = B; 204 let Inst{16-31} = C; 205} 206 207class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 208 InstrItinClass itin, list<dag> pattern> 209 : I<opcode, OOL, IOL, asmstr, itin> { 210 bits<5> A; 211 bits<21> Addr; 212 213 let Pattern = pattern; 214 215 let Inst{6-10} = A; 216 let Inst{11-15} = Addr{20-16}; // Base Reg 217 let Inst{16-31} = Addr{15-0}; // Displacement 218} 219 220class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 221 InstrItinClass itin, list<dag> pattern> 222 : I<opcode, OOL, IOL, asmstr, itin> { 223 bits<5> A; 224 bits<16> C; 225 bits<5> B; 226 227 let Pattern = pattern; 228 229 let Inst{6-10} = A; 230 let Inst{11-15} = B; 231 let Inst{16-31} = C; 232} 233 234 235class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 236 InstrItinClass itin, list<dag> pattern> 237 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 238 239 // Even though ADDICo does not really have an RC bit, provide 240 // the declaration of one here so that isDOT has something to set. 241 bit RC = 0; 242} 243 244class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 245 InstrItinClass itin, list<dag> pattern> 246 : I<opcode, OOL, IOL, asmstr, itin> { 247 bits<5> A; 248 bits<16> B; 249 250 let Pattern = pattern; 251 252 let Inst{6-10} = A; 253 let Inst{11-15} = 0; 254 let Inst{16-31} = B; 255} 256 257class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 258 InstrItinClass itin, list<dag> pattern> 259 : I<opcode, OOL, IOL, asmstr, itin> { 260 bits<5> B; 261 bits<5> A; 262 bits<16> C; 263 264 let Pattern = pattern; 265 266 let Inst{6-10} = A; 267 let Inst{11-15} = B; 268 let Inst{16-31} = C; 269} 270 271class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 272 InstrItinClass itin, list<dag> pattern> 273 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 274 let A = 0; 275 let Addr = 0; 276} 277 278class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 279 string asmstr, InstrItinClass itin, 280 list<dag> pattern> 281 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 282 let A = R; 283 let B = R; 284 let C = 0; 285} 286 287class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 288 dag OOL, dag IOL, string asmstr, 289 InstrItinClass itin, list<dag> pattern> 290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 291 bits<5> A; 292 bits<21> Addr; 293 294 let Pattern = pattern; 295 bits<24> LI; 296 297 let Inst{6-29} = LI; 298 let Inst{30} = aa; 299 let Inst{31} = lk; 300 301 let Inst{38-42} = A; 302 let Inst{43-47} = Addr{20-16}; // Base Reg 303 let Inst{48-63} = Addr{15-0}; // Displacement 304} 305 306// This is used to emit BL8+NOP. 307class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 308 dag OOL, dag IOL, string asmstr, 309 InstrItinClass itin, list<dag> pattern> 310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 311 OOL, IOL, asmstr, itin, pattern> { 312 let A = 0; 313 let Addr = 0; 314} 315 316class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 317 InstrItinClass itin> 318 : I<opcode, OOL, IOL, asmstr, itin> { 319 bits<3> BF; 320 bits<1> L; 321 bits<5> RA; 322 bits<16> I; 323 324 let Inst{6-8} = BF; 325 let Inst{9} = 0; 326 let Inst{10} = L; 327 let Inst{11-15} = RA; 328 let Inst{16-31} = I; 329} 330 331class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 332 InstrItinClass itin> 333 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 334 let L = PPC64; 335} 336 337class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 338 InstrItinClass itin> 339 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 340 341class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 342 InstrItinClass itin> 343 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 344 let L = PPC64; 345} 346 347 348// 1.7.5 DS-Form 349class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 350 InstrItinClass itin, list<dag> pattern> 351 : I<opcode, OOL, IOL, asmstr, itin> { 352 bits<5> RST; 353 bits<19> DS_RA; 354 355 let Pattern = pattern; 356 357 let Inst{6-10} = RST; 358 let Inst{11-15} = DS_RA{18-14}; // Register # 359 let Inst{16-29} = DS_RA{13-0}; // Displacement. 360 let Inst{30-31} = xo; 361} 362 363 364// 1.7.6 X-Form 365class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 366 InstrItinClass itin, list<dag> pattern> 367 : I<opcode, OOL, IOL, asmstr, itin> { 368 bits<5> RST; 369 bits<5> A; 370 bits<5> B; 371 372 let Pattern = pattern; 373 374 bit RC = 0; // set by isDOT 375 376 let Inst{6-10} = RST; 377 let Inst{11-15} = A; 378 let Inst{16-20} = B; 379 let Inst{21-30} = xo; 380 let Inst{31} = RC; 381} 382 383class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr, 384 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 385 let RST = 0; 386} 387 388// This is the same as XForm_base_r3xo, but the first two operands are swapped 389// when code is emitted. 390class XForm_base_r3xo_swapped 391 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 392 InstrItinClass itin> 393 : I<opcode, OOL, IOL, asmstr, itin> { 394 bits<5> A; 395 bits<5> RST; 396 bits<5> B; 397 398 bit RC = 0; // set by isDOT 399 400 let Inst{6-10} = RST; 401 let Inst{11-15} = A; 402 let Inst{16-20} = B; 403 let Inst{21-30} = xo; 404 let Inst{31} = RC; 405} 406 407 408class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 409 InstrItinClass itin, list<dag> pattern> 410 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 411 412class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 413 InstrItinClass itin, list<dag> pattern> 414 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 415 let RST = 0; 416} 417 418class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 419 InstrItinClass itin, list<dag> pattern> 420 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 421 let A = 0; 422 let B = 0; 423} 424 425class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 426 InstrItinClass itin, list<dag> pattern> 427 : I<opcode, OOL, IOL, asmstr, itin> { 428 bits<5> RST; 429 bits<5> A; 430 bits<1> WS; 431 432 let Pattern = pattern; 433 434 let Inst{6-10} = RST; 435 let Inst{11-15} = A; 436 let Inst{20} = WS; 437 let Inst{21-30} = xo; 438 let Inst{31} = 0; 439} 440 441class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 442 InstrItinClass itin, list<dag> pattern> 443 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 444 let Pattern = pattern; 445} 446 447class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 448 InstrItinClass itin, list<dag> pattern> 449 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 450 451class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 452 InstrItinClass itin, list<dag> pattern> 453 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 454 let Pattern = pattern; 455} 456 457class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 458 InstrItinClass itin, list<dag> pattern> 459 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 460 let B = 0; 461 let Pattern = pattern; 462} 463 464class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 465 InstrItinClass itin> 466 : I<opcode, OOL, IOL, asmstr, itin> { 467 bits<3> BF; 468 bits<1> L; 469 bits<5> RA; 470 bits<5> RB; 471 472 let Inst{6-8} = BF; 473 let Inst{9} = 0; 474 let Inst{10} = L; 475 let Inst{11-15} = RA; 476 let Inst{16-20} = RB; 477 let Inst{21-30} = xo; 478 let Inst{31} = 0; 479} 480 481class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 482 InstrItinClass itin> 483 : I<opcode, OOL, IOL, asmstr, itin> { 484 bits<5> RS; 485 bits<4> SR; 486 487 let Inst{6-10} = RS; 488 let Inst{12-15} = SR; 489 let Inst{21-30} = xo; 490} 491 492class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 493 InstrItinClass itin> 494 : I<opcode, OOL, IOL, asmstr, itin> { 495 bits<5> MO; 496 497 let Inst{6-10} = MO; 498 let Inst{21-30} = xo; 499} 500 501class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 502 InstrItinClass itin> 503 : I<opcode, OOL, IOL, asmstr, itin> { 504 bits<5> RS; 505 bits<5> RB; 506 507 let Inst{6-10} = RS; 508 let Inst{16-20} = RB; 509 let Inst{21-30} = xo; 510} 511 512class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 513 InstrItinClass itin> 514 : I<opcode, OOL, IOL, asmstr, itin> { 515 bits<5> RS; 516 bits<1> L; 517 518 let Inst{6-10} = RS; 519 let Inst{15} = L; 520 let Inst{21-30} = xo; 521} 522 523class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 524 InstrItinClass itin> 525 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 526 let L = PPC64; 527} 528 529class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 530 InstrItinClass itin> 531 : I<opcode, OOL, IOL, asmstr, itin> { 532 bits<3> BF; 533 bits<5> FRA; 534 bits<5> FRB; 535 536 let Inst{6-8} = BF; 537 let Inst{9-10} = 0; 538 let Inst{11-15} = FRA; 539 let Inst{16-20} = FRB; 540 let Inst{21-30} = xo; 541 let Inst{31} = 0; 542} 543 544class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 545 InstrItinClass itin, list<dag> pattern> 546 : I<opcode, OOL, IOL, asmstr, itin> { 547 let Pattern = pattern; 548 let Inst{6-10} = 31; 549 let Inst{11-15} = 0; 550 let Inst{16-20} = 0; 551 let Inst{21-30} = xo; 552 let Inst{31} = 0; 553} 554 555class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 556 string asmstr, InstrItinClass itin, list<dag> pattern> 557 : I<opcode, OOL, IOL, asmstr, itin> { 558 bits<2> L; 559 560 let Pattern = pattern; 561 let Inst{6-8} = 0; 562 let Inst{9-10} = L; 563 let Inst{11-15} = 0; 564 let Inst{16-20} = 0; 565 let Inst{21-30} = xo; 566 let Inst{31} = 0; 567} 568 569class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 570 string asmstr, InstrItinClass itin, list<dag> pattern> 571 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 572 let L = 0; 573} 574 575class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 576 InstrItinClass itin, list<dag> pattern> 577 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 578} 579 580class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 581 InstrItinClass itin, list<dag> pattern> 582 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 583 let A = 0; 584} 585 586class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 587 InstrItinClass itin, list<dag> pattern> 588 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 589} 590 591// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 592// numbers presumably relates to some document, but I haven't found it. 593class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 594 InstrItinClass itin, list<dag> pattern> 595 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 596 let Pattern = pattern; 597 598 bit RC = 0; // set by isDOT 599 600 let Inst{6-10} = RST; 601 let Inst{11-20} = 0; 602 let Inst{21-30} = xo; 603 let Inst{31} = RC; 604} 605class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 606 InstrItinClass itin, list<dag> pattern> 607 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 608 let Pattern = pattern; 609 bits<5> FM; 610 611 bit RC = 0; // set by isDOT 612 613 let Inst{6-10} = FM; 614 let Inst{11-20} = 0; 615 let Inst{21-30} = xo; 616 let Inst{31} = RC; 617} 618 619class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 620 InstrItinClass itin, list<dag> pattern> 621 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 622 let RST = 0; 623 let A = 0; 624 let B = 0; 625} 626 627class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 628 InstrItinClass itin, list<dag> pattern> 629 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 630 let RST = 0; 631 let A = 0; 632} 633 634// XX*-Form (VSX) 635class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 636 InstrItinClass itin, list<dag> pattern> 637 : I<opcode, OOL, IOL, asmstr, itin> { 638 bits<6> XT; 639 bits<5> A; 640 bits<5> B; 641 642 let Pattern = pattern; 643 644 let Inst{6-10} = XT{4-0}; 645 let Inst{11-15} = A; 646 let Inst{16-20} = B; 647 let Inst{21-30} = xo; 648 let Inst{31} = XT{5}; 649} 650 651class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 652 InstrItinClass itin, list<dag> pattern> 653 : I<opcode, OOL, IOL, asmstr, itin> { 654 bits<6> XT; 655 bits<6> XB; 656 657 let Pattern = pattern; 658 659 let Inst{6-10} = XT{4-0}; 660 let Inst{11-15} = 0; 661 let Inst{16-20} = XB{4-0}; 662 let Inst{21-29} = xo; 663 let Inst{30} = XB{5}; 664 let Inst{31} = XT{5}; 665} 666 667class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 668 InstrItinClass itin, list<dag> pattern> 669 : I<opcode, OOL, IOL, asmstr, itin> { 670 bits<3> CR; 671 bits<6> XB; 672 673 let Pattern = pattern; 674 675 let Inst{6-8} = CR; 676 let Inst{9-15} = 0; 677 let Inst{16-20} = XB{4-0}; 678 let Inst{21-29} = xo; 679 let Inst{30} = XB{5}; 680 let Inst{31} = 0; 681} 682 683class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 684 InstrItinClass itin, list<dag> pattern> 685 : I<opcode, OOL, IOL, asmstr, itin> { 686 bits<6> XT; 687 bits<6> XB; 688 bits<2> D; 689 690 let Pattern = pattern; 691 692 let Inst{6-10} = XT{4-0}; 693 let Inst{11-13} = 0; 694 let Inst{14-15} = D; 695 let Inst{16-20} = XB{4-0}; 696 let Inst{21-29} = xo; 697 let Inst{30} = XB{5}; 698 let Inst{31} = XT{5}; 699} 700 701class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 702 InstrItinClass itin, list<dag> pattern> 703 : I<opcode, OOL, IOL, asmstr, itin> { 704 bits<6> XT; 705 bits<6> XA; 706 bits<6> XB; 707 708 let Pattern = pattern; 709 710 let Inst{6-10} = XT{4-0}; 711 let Inst{11-15} = XA{4-0}; 712 let Inst{16-20} = XB{4-0}; 713 let Inst{21-28} = xo; 714 let Inst{29} = XA{5}; 715 let Inst{30} = XB{5}; 716 let Inst{31} = XT{5}; 717} 718 719class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 720 InstrItinClass itin, list<dag> pattern> 721 : I<opcode, OOL, IOL, asmstr, itin> { 722 bits<3> CR; 723 bits<6> XA; 724 bits<6> XB; 725 726 let Pattern = pattern; 727 728 let Inst{6-8} = CR; 729 let Inst{9-10} = 0; 730 let Inst{11-15} = XA{4-0}; 731 let Inst{16-20} = XB{4-0}; 732 let Inst{21-28} = xo; 733 let Inst{29} = XA{5}; 734 let Inst{30} = XB{5}; 735 let Inst{31} = 0; 736} 737 738class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 739 InstrItinClass itin, list<dag> pattern> 740 : I<opcode, OOL, IOL, asmstr, itin> { 741 bits<6> XT; 742 bits<6> XA; 743 bits<6> XB; 744 bits<2> D; 745 746 let Pattern = pattern; 747 748 let Inst{6-10} = XT{4-0}; 749 let Inst{11-15} = XA{4-0}; 750 let Inst{16-20} = XB{4-0}; 751 let Inst{21} = 0; 752 let Inst{22-23} = D; 753 let Inst{24-28} = xo; 754 let Inst{29} = XA{5}; 755 let Inst{30} = XB{5}; 756 let Inst{31} = XT{5}; 757} 758 759class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr, 760 InstrItinClass itin, list<dag> pattern> 761 : I<opcode, OOL, IOL, asmstr, itin> { 762 bits<6> XT; 763 bits<6> XA; 764 bits<6> XB; 765 766 let Pattern = pattern; 767 768 bit RC = 0; // set by isDOT 769 770 let Inst{6-10} = XT{4-0}; 771 let Inst{11-15} = XA{4-0}; 772 let Inst{16-20} = XB{4-0}; 773 let Inst{21} = RC; 774 let Inst{22-28} = xo; 775 let Inst{29} = XA{5}; 776 let Inst{30} = XB{5}; 777 let Inst{31} = XT{5}; 778} 779 780class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 781 InstrItinClass itin, list<dag> pattern> 782 : I<opcode, OOL, IOL, asmstr, itin> { 783 bits<6> XT; 784 bits<6> XA; 785 bits<6> XB; 786 bits<6> XC; 787 788 let Pattern = pattern; 789 790 let Inst{6-10} = XT{4-0}; 791 let Inst{11-15} = XA{4-0}; 792 let Inst{16-20} = XB{4-0}; 793 let Inst{21-25} = XC{4-0}; 794 let Inst{26-27} = xo; 795 let Inst{28} = XC{5}; 796 let Inst{29} = XA{5}; 797 let Inst{30} = XB{5}; 798 let Inst{31} = XT{5}; 799} 800 801// DCB_Form - Form X instruction, used for dcb* instructions. 802class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 803 InstrItinClass itin, list<dag> pattern> 804 : I<31, OOL, IOL, asmstr, itin> { 805 bits<5> A; 806 bits<5> B; 807 808 let Pattern = pattern; 809 810 let Inst{6-10} = immfield; 811 let Inst{11-15} = A; 812 let Inst{16-20} = B; 813 let Inst{21-30} = xo; 814 let Inst{31} = 0; 815} 816 817 818// DSS_Form - Form X instruction, used for altivec dss* instructions. 819class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr, 820 InstrItinClass itin, list<dag> pattern> 821 : I<31, OOL, IOL, asmstr, itin> { 822 bits<2> STRM; 823 bits<5> A; 824 bits<5> B; 825 826 let Pattern = pattern; 827 828 let Inst{6} = T; 829 let Inst{7-8} = 0; 830 let Inst{9-10} = STRM; 831 let Inst{11-15} = A; 832 let Inst{16-20} = B; 833 let Inst{21-30} = xo; 834 let Inst{31} = 0; 835} 836 837// 1.7.7 XL-Form 838class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 839 InstrItinClass itin, list<dag> pattern> 840 : I<opcode, OOL, IOL, asmstr, itin> { 841 bits<5> CRD; 842 bits<5> CRA; 843 bits<5> CRB; 844 845 let Pattern = pattern; 846 847 let Inst{6-10} = CRD; 848 let Inst{11-15} = CRA; 849 let Inst{16-20} = CRB; 850 let Inst{21-30} = xo; 851 let Inst{31} = 0; 852} 853 854class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 855 InstrItinClass itin, list<dag> pattern> 856 : I<opcode, OOL, IOL, asmstr, itin> { 857 bits<5> CRD; 858 859 let Pattern = pattern; 860 861 let Inst{6-10} = CRD; 862 let Inst{11-15} = CRD; 863 let Inst{16-20} = CRD; 864 let Inst{21-30} = xo; 865 let Inst{31} = 0; 866} 867 868class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 869 InstrItinClass itin, list<dag> pattern> 870 : I<opcode, OOL, IOL, asmstr, itin> { 871 bits<5> BO; 872 bits<5> BI; 873 bits<2> BH; 874 875 let Pattern = pattern; 876 877 let Inst{6-10} = BO; 878 let Inst{11-15} = BI; 879 let Inst{16-18} = 0; 880 let Inst{19-20} = BH; 881 let Inst{21-30} = xo; 882 let Inst{31} = lk; 883} 884 885class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 886 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 887 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 888 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 889 bits<3> CR; 890 891 let BO = BIBO{4-0}; 892 let BI{0-1} = BIBO{5-6}; 893 let BI{2-4} = CR{0-2}; 894 let BH = 0; 895} 896 897class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk, 898 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 899 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 900 let BO = bo; 901 let BH = 0; 902} 903 904class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 905 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 906 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 907 let BO = bo; 908 let BI = bi; 909 let BH = 0; 910} 911 912class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 913 InstrItinClass itin> 914 : I<opcode, OOL, IOL, asmstr, itin> { 915 bits<3> BF; 916 bits<3> BFA; 917 918 let Inst{6-8} = BF; 919 let Inst{9-10} = 0; 920 let Inst{11-13} = BFA; 921 let Inst{14-15} = 0; 922 let Inst{16-20} = 0; 923 let Inst{21-30} = xo; 924 let Inst{31} = 0; 925} 926 927// 1.7.8 XFX-Form 928class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 929 InstrItinClass itin> 930 : I<opcode, OOL, IOL, asmstr, itin> { 931 bits<5> RT; 932 bits<10> SPR; 933 934 let Inst{6-10} = RT; 935 let Inst{11} = SPR{4}; 936 let Inst{12} = SPR{3}; 937 let Inst{13} = SPR{2}; 938 let Inst{14} = SPR{1}; 939 let Inst{15} = SPR{0}; 940 let Inst{16} = SPR{9}; 941 let Inst{17} = SPR{8}; 942 let Inst{18} = SPR{7}; 943 let Inst{19} = SPR{6}; 944 let Inst{20} = SPR{5}; 945 let Inst{21-30} = xo; 946 let Inst{31} = 0; 947} 948 949class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 950 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 951 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 952 let SPR = spr; 953} 954 955class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 956 InstrItinClass itin> 957 : I<opcode, OOL, IOL, asmstr, itin> { 958 bits<5> RT; 959 960 let Inst{6-10} = RT; 961 let Inst{11-20} = 0; 962 let Inst{21-30} = xo; 963 let Inst{31} = 0; 964} 965 966class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 967 InstrItinClass itin> 968 : I<opcode, OOL, IOL, asmstr, itin> { 969 bits<8> FXM; 970 bits<5> rS; 971 972 let Inst{6-10} = rS; 973 let Inst{11} = 0; 974 let Inst{12-19} = FXM; 975 let Inst{20} = 0; 976 let Inst{21-30} = xo; 977 let Inst{31} = 0; 978} 979 980class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 981 InstrItinClass itin> 982 : I<opcode, OOL, IOL, asmstr, itin> { 983 bits<5> ST; 984 bits<8> FXM; 985 986 let Inst{6-10} = ST; 987 let Inst{11} = 1; 988 let Inst{12-19} = FXM; 989 let Inst{20} = 0; 990 let Inst{21-30} = xo; 991 let Inst{31} = 0; 992} 993 994class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 995 InstrItinClass itin> 996 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 997 998class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 999 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1000 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 1001 let SPR = spr; 1002} 1003 1004// XFL-Form - MTFSF 1005// This is probably 1.7.9, but I don't have the reference that uses this 1006// numbering scheme... 1007class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1008 InstrItinClass itin, list<dag>pattern> 1009 : I<opcode, OOL, IOL, asmstr, itin> { 1010 bits<8> FM; 1011 bits<5> rT; 1012 1013 bit RC = 0; // set by isDOT 1014 let Pattern = pattern; 1015 1016 let Inst{6} = 0; 1017 let Inst{7-14} = FM; 1018 let Inst{15} = 0; 1019 let Inst{16-20} = rT; 1020 let Inst{21-30} = xo; 1021 let Inst{31} = RC; 1022} 1023 1024// 1.7.10 XS-Form - SRADI. 1025class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1026 InstrItinClass itin, list<dag> pattern> 1027 : I<opcode, OOL, IOL, asmstr, itin> { 1028 bits<5> A; 1029 bits<5> RS; 1030 bits<6> SH; 1031 1032 bit RC = 0; // set by isDOT 1033 let Pattern = pattern; 1034 1035 let Inst{6-10} = RS; 1036 let Inst{11-15} = A; 1037 let Inst{16-20} = SH{4,3,2,1,0}; 1038 let Inst{21-29} = xo; 1039 let Inst{30} = SH{5}; 1040 let Inst{31} = RC; 1041} 1042 1043// 1.7.11 XO-Form 1044class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 1045 InstrItinClass itin, list<dag> pattern> 1046 : I<opcode, OOL, IOL, asmstr, itin> { 1047 bits<5> RT; 1048 bits<5> RA; 1049 bits<5> RB; 1050 1051 let Pattern = pattern; 1052 1053 bit RC = 0; // set by isDOT 1054 1055 let Inst{6-10} = RT; 1056 let Inst{11-15} = RA; 1057 let Inst{16-20} = RB; 1058 let Inst{21} = oe; 1059 let Inst{22-30} = xo; 1060 let Inst{31} = RC; 1061} 1062 1063class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 1064 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1065 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 1066 let RB = 0; 1067} 1068 1069// 1.7.12 A-Form 1070class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1071 InstrItinClass itin, list<dag> pattern> 1072 : I<opcode, OOL, IOL, asmstr, itin> { 1073 bits<5> FRT; 1074 bits<5> FRA; 1075 bits<5> FRC; 1076 bits<5> FRB; 1077 1078 let Pattern = pattern; 1079 1080 bit RC = 0; // set by isDOT 1081 1082 let Inst{6-10} = FRT; 1083 let Inst{11-15} = FRA; 1084 let Inst{16-20} = FRB; 1085 let Inst{21-25} = FRC; 1086 let Inst{26-30} = xo; 1087 let Inst{31} = RC; 1088} 1089 1090class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1091 InstrItinClass itin, list<dag> pattern> 1092 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1093 let FRC = 0; 1094} 1095 1096class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1097 InstrItinClass itin, list<dag> pattern> 1098 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1099 let FRB = 0; 1100} 1101 1102class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1103 InstrItinClass itin, list<dag> pattern> 1104 : I<opcode, OOL, IOL, asmstr, itin> { 1105 bits<5> RT; 1106 bits<5> RA; 1107 bits<5> RB; 1108 bits<5> COND; 1109 1110 let Pattern = pattern; 1111 1112 let Inst{6-10} = RT; 1113 let Inst{11-15} = RA; 1114 let Inst{16-20} = RB; 1115 let Inst{21-25} = COND; 1116 let Inst{26-30} = xo; 1117 let Inst{31} = 0; 1118} 1119 1120// 1.7.13 M-Form 1121class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1122 InstrItinClass itin, list<dag> pattern> 1123 : I<opcode, OOL, IOL, asmstr, itin> { 1124 bits<5> RA; 1125 bits<5> RS; 1126 bits<5> RB; 1127 bits<5> MB; 1128 bits<5> ME; 1129 1130 let Pattern = pattern; 1131 1132 bit RC = 0; // set by isDOT 1133 1134 let Inst{6-10} = RS; 1135 let Inst{11-15} = RA; 1136 let Inst{16-20} = RB; 1137 let Inst{21-25} = MB; 1138 let Inst{26-30} = ME; 1139 let Inst{31} = RC; 1140} 1141 1142class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1143 InstrItinClass itin, list<dag> pattern> 1144 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 1145} 1146 1147// 1.7.14 MD-Form 1148class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 1149 InstrItinClass itin, list<dag> pattern> 1150 : I<opcode, OOL, IOL, asmstr, itin> { 1151 bits<5> RA; 1152 bits<5> RS; 1153 bits<6> SH; 1154 bits<6> MBE; 1155 1156 let Pattern = pattern; 1157 1158 bit RC = 0; // set by isDOT 1159 1160 let Inst{6-10} = RS; 1161 let Inst{11-15} = RA; 1162 let Inst{16-20} = SH{4,3,2,1,0}; 1163 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1164 let Inst{27-29} = xo; 1165 let Inst{30} = SH{5}; 1166 let Inst{31} = RC; 1167} 1168 1169class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 1170 InstrItinClass itin, list<dag> pattern> 1171 : I<opcode, OOL, IOL, asmstr, itin> { 1172 bits<5> RA; 1173 bits<5> RS; 1174 bits<5> RB; 1175 bits<6> MBE; 1176 1177 let Pattern = pattern; 1178 1179 bit RC = 0; // set by isDOT 1180 1181 let Inst{6-10} = RS; 1182 let Inst{11-15} = RA; 1183 let Inst{16-20} = RB; 1184 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1185 let Inst{27-30} = xo; 1186 let Inst{31} = RC; 1187} 1188 1189 1190// E-1 VA-Form 1191 1192// VAForm_1 - DACB ordering. 1193class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 1194 InstrItinClass itin, list<dag> pattern> 1195 : I<4, OOL, IOL, asmstr, itin> { 1196 bits<5> VD; 1197 bits<5> VA; 1198 bits<5> VC; 1199 bits<5> VB; 1200 1201 let Pattern = pattern; 1202 1203 let Inst{6-10} = VD; 1204 let Inst{11-15} = VA; 1205 let Inst{16-20} = VB; 1206 let Inst{21-25} = VC; 1207 let Inst{26-31} = xo; 1208} 1209 1210// VAForm_1a - DABC ordering. 1211class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 1212 InstrItinClass itin, list<dag> pattern> 1213 : I<4, OOL, IOL, asmstr, itin> { 1214 bits<5> VD; 1215 bits<5> VA; 1216 bits<5> VB; 1217 bits<5> VC; 1218 1219 let Pattern = pattern; 1220 1221 let Inst{6-10} = VD; 1222 let Inst{11-15} = VA; 1223 let Inst{16-20} = VB; 1224 let Inst{21-25} = VC; 1225 let Inst{26-31} = xo; 1226} 1227 1228class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 1229 InstrItinClass itin, list<dag> pattern> 1230 : I<4, OOL, IOL, asmstr, itin> { 1231 bits<5> VD; 1232 bits<5> VA; 1233 bits<5> VB; 1234 bits<4> SH; 1235 1236 let Pattern = pattern; 1237 1238 let Inst{6-10} = VD; 1239 let Inst{11-15} = VA; 1240 let Inst{16-20} = VB; 1241 let Inst{21} = 0; 1242 let Inst{22-25} = SH; 1243 let Inst{26-31} = xo; 1244} 1245 1246// E-2 VX-Form 1247class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 1248 InstrItinClass itin, list<dag> pattern> 1249 : I<4, OOL, IOL, asmstr, itin> { 1250 bits<5> VD; 1251 bits<5> VA; 1252 bits<5> VB; 1253 1254 let Pattern = pattern; 1255 1256 let Inst{6-10} = VD; 1257 let Inst{11-15} = VA; 1258 let Inst{16-20} = VB; 1259 let Inst{21-31} = xo; 1260} 1261 1262class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 1263 InstrItinClass itin, list<dag> pattern> 1264 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 1265 let VA = VD; 1266 let VB = VD; 1267} 1268 1269 1270class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 1271 InstrItinClass itin, list<dag> pattern> 1272 : I<4, OOL, IOL, asmstr, itin> { 1273 bits<5> VD; 1274 bits<5> VB; 1275 1276 let Pattern = pattern; 1277 1278 let Inst{6-10} = VD; 1279 let Inst{11-15} = 0; 1280 let Inst{16-20} = VB; 1281 let Inst{21-31} = xo; 1282} 1283 1284class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 1285 InstrItinClass itin, list<dag> pattern> 1286 : I<4, OOL, IOL, asmstr, itin> { 1287 bits<5> VD; 1288 bits<5> IMM; 1289 1290 let Pattern = pattern; 1291 1292 let Inst{6-10} = VD; 1293 let Inst{11-15} = IMM; 1294 let Inst{16-20} = 0; 1295 let Inst{21-31} = xo; 1296} 1297 1298/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 1299class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 1300 InstrItinClass itin, list<dag> pattern> 1301 : I<4, OOL, IOL, asmstr, itin> { 1302 bits<5> VD; 1303 1304 let Pattern = pattern; 1305 1306 let Inst{6-10} = VD; 1307 let Inst{11-15} = 0; 1308 let Inst{16-20} = 0; 1309 let Inst{21-31} = xo; 1310} 1311 1312/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 1313class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 1314 InstrItinClass itin, list<dag> pattern> 1315 : I<4, OOL, IOL, asmstr, itin> { 1316 bits<5> VB; 1317 1318 let Pattern = pattern; 1319 1320 let Inst{6-10} = 0; 1321 let Inst{11-15} = 0; 1322 let Inst{16-20} = VB; 1323 let Inst{21-31} = xo; 1324} 1325 1326// E-4 VXR-Form 1327class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 1328 InstrItinClass itin, list<dag> pattern> 1329 : I<4, OOL, IOL, asmstr, itin> { 1330 bits<5> VD; 1331 bits<5> VA; 1332 bits<5> VB; 1333 bit RC = 0; 1334 1335 let Pattern = pattern; 1336 1337 let Inst{6-10} = VD; 1338 let Inst{11-15} = VA; 1339 let Inst{16-20} = VB; 1340 let Inst{21} = RC; 1341 let Inst{22-31} = xo; 1342} 1343 1344//===----------------------------------------------------------------------===// 1345class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 1346 : I<0, OOL, IOL, asmstr, NoItinerary> { 1347 let isCodeGenOnly = 1; 1348 let PPC64 = 0; 1349 let Pattern = pattern; 1350 let Inst{31-0} = 0; 1351} 1352