1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// 11// PowerPC instruction formats 12 13class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 14 : Instruction { 15 field bits<32> Inst; 16 field bits<32> SoftFail = 0; 17 let Size = 4; 18 19 bit PPC64 = 0; // Default value, override with isPPC64 20 21 let Namespace = "PPC"; 22 let Inst{0-5} = opcode; 23 let OutOperandList = OOL; 24 let InOperandList = IOL; 25 let AsmString = asmstr; 26 let Itinerary = itin; 27 28 bits<1> PPC970_First = 0; 29 bits<1> PPC970_Single = 0; 30 bits<1> PPC970_Cracked = 0; 31 bits<3> PPC970_Unit = 0; 32 33 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 34 /// these must be reflected there! See comments there for what these are. 35 let TSFlags{0} = PPC970_First; 36 let TSFlags{1} = PPC970_Single; 37 let TSFlags{2} = PPC970_Cracked; 38 let TSFlags{5-3} = PPC970_Unit; 39 40 // Indicate that this instruction is of type X-Form Load or Store 41 bits<1> XFormMemOp = 0; 42 let TSFlags{6} = XFormMemOp; 43 44 // Indicate that this instruction is prefixed. 45 bits<1> Prefixed = 0; 46 let TSFlags{7} = Prefixed; 47 48 // Fields used for relation models. 49 string BaseName = ""; 50 51 // For cases where multiple instruction definitions really represent the 52 // same underlying instruction but with one definition for 64-bit arguments 53 // and one for 32-bit arguments, this bit breaks the degeneracy between 54 // the two forms and allows TableGen to generate mapping tables. 55 bit Interpretation64Bit = 0; 56} 57 58class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 59class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 60class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 61class PPC970_MicroCode; 62 63class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 64class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 65class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 66class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 67class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 68class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 69class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 70class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 71 72class XFormMemOp { bits<1> XFormMemOp = 1; } 73 74// Two joined instructions; used to emit two adjacent instructions as one. 75// The itinerary from the first instruction is used for scheduling and 76// classification. 77class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 78 InstrItinClass itin> 79 : Instruction { 80 field bits<64> Inst; 81 field bits<64> SoftFail = 0; 82 let Size = 8; 83 84 bit PPC64 = 0; // Default value, override with isPPC64 85 86 let Namespace = "PPC"; 87 let Inst{0-5} = opcode1; 88 let Inst{32-37} = opcode2; 89 let OutOperandList = OOL; 90 let InOperandList = IOL; 91 let AsmString = asmstr; 92 let Itinerary = itin; 93 94 bits<1> PPC970_First = 0; 95 bits<1> PPC970_Single = 0; 96 bits<1> PPC970_Cracked = 0; 97 bits<3> PPC970_Unit = 0; 98 99 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 100 /// these must be reflected there! See comments there for what these are. 101 let TSFlags{0} = PPC970_First; 102 let TSFlags{1} = PPC970_Single; 103 let TSFlags{2} = PPC970_Cracked; 104 let TSFlags{5-3} = PPC970_Unit; 105 106 // Fields used for relation models. 107 string BaseName = ""; 108 bit Interpretation64Bit = 0; 109} 110 111// Base class for all X-Form memory instructions 112class IXFormMemOp<bits<6> opcode, dag OOL, dag IOL, string asmstr, 113 InstrItinClass itin> 114 :I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp; 115 116// 1.7.1 I-Form 117class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 118 InstrItinClass itin, list<dag> pattern> 119 : I<opcode, OOL, IOL, asmstr, itin> { 120 let Pattern = pattern; 121 bits<24> LI; 122 123 let Inst{6-29} = LI; 124 let Inst{30} = aa; 125 let Inst{31} = lk; 126} 127 128// 1.7.2 B-Form 129class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 130 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 131 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 132 bits<3> CR; 133 bits<14> BD; 134 135 bits<5> BI; 136 let BI{0-1} = BIBO{5-6}; 137 let BI{2-4} = CR{0-2}; 138 139 let Inst{6-10} = BIBO{4-0}; 140 let Inst{11-15} = BI; 141 let Inst{16-29} = BD; 142 let Inst{30} = aa; 143 let Inst{31} = lk; 144} 145 146class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 147 string asmstr> 148 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 149 let BIBO{4-0} = bo; 150 let BIBO{6-5} = 0; 151 let CR = 0; 152} 153 154class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 155 dag OOL, dag IOL, string asmstr> 156 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 157 bits<14> BD; 158 159 let Inst{6-10} = bo; 160 let Inst{11-15} = bi; 161 let Inst{16-29} = BD; 162 let Inst{30} = aa; 163 let Inst{31} = lk; 164} 165 166class BForm_3<bits<6> opcode, bit aa, bit lk, 167 dag OOL, dag IOL, string asmstr> 168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 169 bits<5> BO; 170 bits<5> BI; 171 bits<14> BD; 172 173 let Inst{6-10} = BO; 174 let Inst{11-15} = BI; 175 let Inst{16-29} = BD; 176 let Inst{30} = aa; 177 let Inst{31} = lk; 178} 179 180class BForm_3_at<bits<6> opcode, bit aa, bit lk, 181 dag OOL, dag IOL, string asmstr> 182 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 183 bits<5> BO; 184 bits<2> at; 185 bits<5> BI; 186 bits<14> BD; 187 188 let Inst{6-8} = BO{4-2}; 189 let Inst{9-10} = at; 190 let Inst{11-15} = BI; 191 let Inst{16-29} = BD; 192 let Inst{30} = aa; 193 let Inst{31} = lk; 194} 195 196class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, 197 dag OOL, dag IOL, string asmstr> 198 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 199 bits<5> BI; 200 bits<14> BD; 201 202 let Inst{6-10} = bo; 203 let Inst{11-15} = BI; 204 let Inst{16-29} = BD; 205 let Inst{30} = aa; 206 let Inst{31} = lk; 207} 208 209// 1.7.3 SC-Form 210class SCForm<bits<6> opcode, bits<1> xo, 211 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 212 list<dag> pattern> 213 : I<opcode, OOL, IOL, asmstr, itin> { 214 bits<7> LEV; 215 216 let Pattern = pattern; 217 218 let Inst{20-26} = LEV; 219 let Inst{30} = xo; 220} 221 222// 1.7.4 D-Form 223class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 224 InstrItinClass itin, list<dag> pattern> 225 : I<opcode, OOL, IOL, asmstr, itin> { 226 bits<5> A; 227 bits<5> B; 228 bits<16> C; 229 230 let Pattern = pattern; 231 232 let Inst{6-10} = A; 233 let Inst{11-15} = B; 234 let Inst{16-31} = C; 235} 236 237class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 238 InstrItinClass itin, list<dag> pattern> 239 : I<opcode, OOL, IOL, asmstr, itin> { 240 bits<5> A; 241 bits<21> Addr; 242 243 let Pattern = pattern; 244 245 let Inst{6-10} = A; 246 let Inst{11-15} = Addr{20-16}; // Base Reg 247 let Inst{16-31} = Addr{15-0}; // Displacement 248} 249 250class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 251 InstrItinClass itin, list<dag> pattern> 252 : I<opcode, OOL, IOL, asmstr, itin> { 253 bits<5> A; 254 bits<16> C; 255 bits<5> B; 256 257 let Pattern = pattern; 258 259 let Inst{6-10} = A; 260 let Inst{11-15} = B; 261 let Inst{16-31} = C; 262} 263 264 265class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 266 InstrItinClass itin, list<dag> pattern> 267 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 268 269 // Even though ADDIC_rec does not really have an RC bit, provide 270 // the declaration of one here so that isRecordForm has something to set. 271 bit RC = 0; 272} 273 274class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 275 InstrItinClass itin, list<dag> pattern> 276 : I<opcode, OOL, IOL, asmstr, itin> { 277 bits<5> A; 278 bits<16> B; 279 280 let Pattern = pattern; 281 282 let Inst{6-10} = A; 283 let Inst{11-15} = 0; 284 let Inst{16-31} = B; 285} 286 287class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 288 InstrItinClass itin, list<dag> pattern> 289 : I<opcode, OOL, IOL, asmstr, itin> { 290 bits<5> B; 291 bits<5> A; 292 bits<16> C; 293 294 let Pattern = pattern; 295 296 let Inst{6-10} = A; 297 let Inst{11-15} = B; 298 let Inst{16-31} = C; 299} 300 301class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 302 InstrItinClass itin, list<dag> pattern> 303 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 304 let A = 0; 305 let Addr = 0; 306} 307 308class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 309 string asmstr, InstrItinClass itin, 310 list<dag> pattern> 311 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 312 let A = R; 313 let B = R; 314 let C = 0; 315} 316 317class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 318 dag OOL, dag IOL, string asmstr, 319 InstrItinClass itin, list<dag> pattern> 320 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 321 bits<5> A; 322 bits<21> Addr; 323 324 let Pattern = pattern; 325 bits<24> LI; 326 327 let Inst{6-29} = LI; 328 let Inst{30} = aa; 329 let Inst{31} = lk; 330 331 let Inst{38-42} = A; 332 let Inst{43-47} = Addr{20-16}; // Base Reg 333 let Inst{48-63} = Addr{15-0}; // Displacement 334} 335 336// This is used to emit BL8+NOP. 337class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 338 dag OOL, dag IOL, string asmstr, 339 InstrItinClass itin, list<dag> pattern> 340 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 341 OOL, IOL, asmstr, itin, pattern> { 342 let A = 0; 343 let Addr = 0; 344} 345 346class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 347 InstrItinClass itin> 348 : I<opcode, OOL, IOL, asmstr, itin> { 349 bits<3> BF; 350 bits<1> L; 351 bits<5> RA; 352 bits<16> I; 353 354 let Inst{6-8} = BF; 355 let Inst{9} = 0; 356 let Inst{10} = L; 357 let Inst{11-15} = RA; 358 let Inst{16-31} = I; 359} 360 361class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 362 InstrItinClass itin> 363 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 364 let L = PPC64; 365} 366 367class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 368 InstrItinClass itin> 369 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 370 371class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 372 InstrItinClass itin> 373 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 374 let L = PPC64; 375} 376 377 378// 1.7.5 DS-Form 379class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 380 InstrItinClass itin, list<dag> pattern> 381 : I<opcode, OOL, IOL, asmstr, itin> { 382 bits<5> RST; 383 bits<19> DS_RA; 384 385 let Pattern = pattern; 386 387 let Inst{6-10} = RST; 388 let Inst{11-15} = DS_RA{18-14}; // Register # 389 let Inst{16-29} = DS_RA{13-0}; // Displacement. 390 let Inst{30-31} = xo; 391} 392 393// ISA V3.0B 1.6.6 DX-Form 394class DXForm<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 395 InstrItinClass itin, list<dag> pattern> 396 : I<opcode, OOL, IOL, asmstr, itin> { 397 bits<5> RT; 398 bits<16> D; 399 400 let Pattern = pattern; 401 402 let Inst{6-10} = RT; 403 let Inst{11-15} = D{5-1}; // d1 404 let Inst{16-25} = D{15-6}; // d0 405 let Inst{26-30} = xo; 406 let Inst{31} = D{0}; // d2 407} 408 409// DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO] 410class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 411 string asmstr, InstrItinClass itin, list<dag> pattern> 412 : I<opcode, OOL, IOL, asmstr, itin> { 413 bits<6> XT; 414 bits<17> DS_RA; 415 416 let Pattern = pattern; 417 418 let Inst{6-10} = XT{4-0}; 419 let Inst{11-15} = DS_RA{16-12}; // Register # 420 let Inst{16-27} = DS_RA{11-0}; // Displacement. 421 let Inst{28} = XT{5}; 422 let Inst{29-31} = xo; 423} 424 425// 1.7.6 X-Form 426class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 427 InstrItinClass itin, list<dag> pattern> 428 : I<opcode, OOL, IOL, asmstr, itin> { 429 bits<5> RST; 430 bits<5> A; 431 bits<5> B; 432 433 let Pattern = pattern; 434 435 bit RC = 0; // set by isRecordForm 436 437 let Inst{6-10} = RST; 438 let Inst{11-15} = A; 439 let Inst{16-20} = B; 440 let Inst{21-30} = xo; 441 let Inst{31} = RC; 442} 443 444class XForm_base_r3xo_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 445 string asmstr, InstrItinClass itin, 446 list<dag> pattern> 447 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; 448 449class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr, 450 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 451 let RST = 0; 452} 453 454class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 455 InstrItinClass itin> 456 : I<opcode, OOL, IOL, asmstr, itin> { 457 let Inst{21-30} = xo; 458} 459 460// This is the same as XForm_base_r3xo, but the first two operands are swapped 461// when code is emitted. 462class XForm_base_r3xo_swapped 463 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 464 InstrItinClass itin> 465 : I<opcode, OOL, IOL, asmstr, itin> { 466 bits<5> A; 467 bits<5> RST; 468 bits<5> B; 469 470 bit RC = 0; // set by isRecordForm 471 472 let Inst{6-10} = RST; 473 let Inst{11-15} = A; 474 let Inst{16-20} = B; 475 let Inst{21-30} = xo; 476 let Inst{31} = RC; 477} 478 479 480class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 481 InstrItinClass itin, list<dag> pattern> 482 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 483 484class XForm_1_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 485 InstrItinClass itin, list<dag> pattern> 486 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 487 488class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 489 InstrItinClass itin, list<dag> pattern> 490 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 491 let RST = 0; 492} 493 494class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 495 InstrItinClass itin, list<dag> pattern> 496 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 497 let A = 0; 498 let B = 0; 499} 500 501class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 502 InstrItinClass itin, list<dag> pattern> 503 : I<opcode, OOL, IOL, asmstr, itin> { 504 bits<5> RST; 505 bits<5> A; 506 bits<1> WS; 507 508 let Pattern = pattern; 509 510 let Inst{6-10} = RST; 511 let Inst{11-15} = A; 512 let Inst{20} = WS; 513 let Inst{21-30} = xo; 514 let Inst{31} = 0; 515} 516 517class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 518 InstrItinClass itin, list<dag> pattern> 519 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 520 let Pattern = pattern; 521} 522 523class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 524 InstrItinClass itin, list<dag> pattern> 525 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 526 527class XForm_8_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 528 InstrItinClass itin, list<dag> pattern> 529 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 530 531class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 532 InstrItinClass itin, list<dag> pattern> 533 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 534 let Pattern = pattern; 535} 536 537class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 538 InstrItinClass itin, list<dag> pattern> 539 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 540 let B = 0; 541 let Pattern = pattern; 542} 543 544class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 545 InstrItinClass itin> 546 : I<opcode, OOL, IOL, asmstr, itin> { 547 bits<3> BF; 548 bits<1> L; 549 bits<5> RA; 550 bits<5> RB; 551 552 let Inst{6-8} = BF; 553 let Inst{9} = 0; 554 let Inst{10} = L; 555 let Inst{11-15} = RA; 556 let Inst{16-20} = RB; 557 let Inst{21-30} = xo; 558 let Inst{31} = 0; 559} 560 561class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 562 InstrItinClass itin> 563 : I<opcode, OOL, IOL, asmstr, itin> { 564 bits<4> CT; 565 bits<5> RA; 566 bits<5> RB; 567 568 let Inst{6} = 0; 569 let Inst{7-10} = CT; 570 let Inst{11-15} = RA; 571 let Inst{16-20} = RB; 572 let Inst{21-30} = xo; 573 let Inst{31} = 0; 574} 575 576class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 577 InstrItinClass itin> 578 : I<opcode, OOL, IOL, asmstr, itin> { 579 bits<5> RS; 580 bits<4> SR; 581 582 let Inst{6-10} = RS; 583 let Inst{12-15} = SR; 584 let Inst{21-30} = xo; 585} 586 587class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 588 InstrItinClass itin> 589 : I<opcode, OOL, IOL, asmstr, itin> { 590 bits<5> MO; 591 592 let Inst{6-10} = MO; 593 let Inst{21-30} = xo; 594} 595 596class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 597 InstrItinClass itin> 598 : I<opcode, OOL, IOL, asmstr, itin> { 599 bits<5> RS; 600 bits<5> RB; 601 602 let Inst{6-10} = RS; 603 let Inst{16-20} = RB; 604 let Inst{21-30} = xo; 605} 606 607class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 608 InstrItinClass itin> 609 : I<opcode, OOL, IOL, asmstr, itin> { 610 bits<5> RS; 611 bits<1> L; 612 613 let Inst{6-10} = RS; 614 let Inst{15} = L; 615 let Inst{21-30} = xo; 616} 617 618class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 619 InstrItinClass itin> 620 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 621 let L = PPC64; 622} 623 624class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 625 InstrItinClass itin> 626 : I<opcode, OOL, IOL, asmstr, itin> { 627 bits<3> BF; 628 bits<5> FRA; 629 bits<5> FRB; 630 631 let Inst{6-8} = BF; 632 let Inst{9-10} = 0; 633 let Inst{11-15} = FRA; 634 let Inst{16-20} = FRB; 635 let Inst{21-30} = xo; 636 let Inst{31} = 0; 637} 638 639class XForm_17a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 640 InstrItinClass itin> 641 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin > { 642 let FRA = 0; 643} 644 645class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 646 InstrItinClass itin, list<dag> pattern> 647 : I<opcode, OOL, IOL, asmstr, itin> { 648 bits<5> FRT; 649 bits<5> FRA; 650 bits<5> FRB; 651 652 let Pattern = pattern; 653 654 let Inst{6-10} = FRT; 655 let Inst{11-15} = FRA; 656 let Inst{16-20} = FRB; 657 let Inst{21-30} = xo; 658 let Inst{31} = 0; 659} 660 661class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 662 InstrItinClass itin, list<dag> pattern> 663 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 664 let FRA = 0; 665} 666 667class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr, 668 InstrItinClass itin, list<dag> pattern> 669 : I<opcode, OOL, IOL, asmstr, itin> { 670 bits<5> FRT; 671 bits<5> FRA; 672 bits<5> FRB; 673 bits<4> tttt; 674 675 let Pattern = pattern; 676 677 let Inst{6-10} = FRT; 678 let Inst{11-15} = FRA; 679 let Inst{16-20} = FRB; 680 let Inst{21-24} = tttt; 681 let Inst{25-30} = xo; 682 let Inst{31} = 0; 683} 684 685class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 686 InstrItinClass itin, list<dag> pattern> 687 : I<opcode, OOL, IOL, asmstr, itin> { 688 let Pattern = pattern; 689 let Inst{6-10} = 31; 690 let Inst{11-15} = 0; 691 let Inst{16-20} = 0; 692 let Inst{21-30} = xo; 693 let Inst{31} = 0; 694} 695 696class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 697 string asmstr, InstrItinClass itin, list<dag> pattern> 698 : I<opcode, OOL, IOL, asmstr, itin> { 699 bits<2> L; 700 701 let Pattern = pattern; 702 let Inst{6-8} = 0; 703 let Inst{9-10} = L; 704 let Inst{11-15} = 0; 705 let Inst{16-20} = 0; 706 let Inst{21-30} = xo; 707 let Inst{31} = 0; 708} 709 710class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 711 string asmstr, InstrItinClass itin, list<dag> pattern> 712 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 713 let L = 0; 714} 715 716class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 717 InstrItinClass itin, list<dag> pattern> 718 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 719} 720 721class XForm_25_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 722 string asmstr, InstrItinClass itin, list<dag> pattern> 723 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 724} 725 726// [PO RT /// RB XO RC] 727class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 728 InstrItinClass itin, list<dag> pattern> 729 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 730 let A = 0; 731} 732 733class XForm_28_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 734 string asmstr, InstrItinClass itin, list<dag> pattern> 735 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 736} 737 738class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 739 InstrItinClass itin, list<dag> pattern> 740 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 741} 742 743// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 744// numbers presumably relates to some document, but I haven't found it. 745class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 746 InstrItinClass itin, list<dag> pattern> 747 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 748 let Pattern = pattern; 749 750 bit RC = 0; // set by isRecordForm 751 752 let Inst{6-10} = RST; 753 let Inst{11-20} = 0; 754 let Inst{21-30} = xo; 755 let Inst{31} = RC; 756} 757class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 758 InstrItinClass itin, list<dag> pattern> 759 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 760 let Pattern = pattern; 761 bits<5> FM; 762 763 bit RC = 0; // set by isRecordForm 764 765 let Inst{6-10} = FM; 766 let Inst{11-20} = 0; 767 let Inst{21-30} = xo; 768 let Inst{31} = RC; 769} 770 771class XForm_44<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 772 InstrItinClass itin> 773 : I<opcode, OOL, IOL, asmstr, itin> { 774 bits<5> RT; 775 bits<3> BFA; 776 777 let Inst{6-10} = RT; 778 let Inst{11-13} = BFA; 779 let Inst{14-15} = 0; 780 let Inst{16-20} = 0; 781 let Inst{21-30} = xo; 782 let Inst{31} = 0; 783} 784 785class XForm_45<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 786 InstrItinClass itin> 787 : I<opcode, OOL, IOL, asmstr, itin> { 788 bits<5> RT; 789 bits<2> L; 790 791 let Inst{6-10} = RT; 792 let Inst{11-13} = 0; 793 let Inst{14-15} = L; 794 let Inst{16-20} = 0; 795 let Inst{21-30} = xo; 796 let Inst{31} = 0; 797} 798 799class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo, 800 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 801 list<dag> pattern> 802 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 803 let Pattern = pattern; 804 805 let Inst{6-10} = RST; 806 let Inst{11-12} = xo1; 807 let Inst{13-15} = xo2; 808 let Inst{16-20} = 0; 809 let Inst{21-30} = xo; 810 let Inst{31} = 0; 811} 812 813class X_FRT5_XO2_XO3_FRB5_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 814 bits<10> xo, dag OOL, dag IOL, string asmstr, 815 InstrItinClass itin, list<dag> pattern> 816 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 817 let Pattern = pattern; 818 bits<5> FRB; 819 820 let Inst{6-10} = RST; 821 let Inst{11-12} = xo1; 822 let Inst{13-15} = xo2; 823 let Inst{16-20} = FRB; 824 let Inst{21-30} = xo; 825 let Inst{31} = 0; 826} 827 828class X_FRT5_XO2_XO3_DRM3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 829 bits<10> xo, dag OOL, dag IOL, string asmstr, 830 InstrItinClass itin, list<dag> pattern> 831 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 832 let Pattern = pattern; 833 bits<3> DRM; 834 835 let Inst{6-10} = RST; 836 let Inst{11-12} = xo1; 837 let Inst{13-15} = xo2; 838 let Inst{16-17} = 0; 839 let Inst{18-20} = DRM; 840 let Inst{21-30} = xo; 841 let Inst{31} = 0; 842} 843 844class X_FRT5_XO2_XO3_RM2_X10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 845 bits<10> xo, dag OOL, dag IOL, string asmstr, 846 InstrItinClass itin, list<dag> pattern> 847 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 848 let Pattern = pattern; 849 bits<2> RM; 850 851 let Inst{6-10} = RST; 852 let Inst{11-12} = xo1; 853 let Inst{13-15} = xo2; 854 let Inst{16-18} = 0; 855 let Inst{19-20} = RM; 856 let Inst{21-30} = xo; 857 let Inst{31} = 0; 858} 859 860 861class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 862 InstrItinClass itin, list<dag> pattern> 863 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 864 let RST = 0; 865 let A = 0; 866 let B = 0; 867} 868 869class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 870 InstrItinClass itin, list<dag> pattern> 871 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 872 let RST = 0; 873 let A = 0; 874} 875 876class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 877 string asmstr, InstrItinClass itin, list<dag> pattern> 878 : I<opcode, OOL, IOL, asmstr, itin> { 879 bit R; 880 881 bit RC = 1; 882 883 let Inst{6-9} = 0; 884 let Inst{10} = R; 885 let Inst{11-20} = 0; 886 let Inst{21-30} = xo; 887 let Inst{31} = RC; 888} 889 890class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 891 string asmstr, InstrItinClass itin, list<dag> pattern> 892 : I<opcode, OOL, IOL, asmstr, itin> { 893 bit A; 894 895 bit RC = 1; 896 897 let Inst{6} = A; 898 let Inst{7-20} = 0; 899 let Inst{21-30} = xo; 900 let Inst{31} = RC; 901} 902 903class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 904 InstrItinClass itin, list<dag> pattern> 905 : I<opcode, OOL, IOL, asmstr, itin> { 906 bit L; 907 908 bit RC = 0; // set by isRecordForm 909 910 let Inst{7-9} = 0; 911 let Inst{10} = L; 912 let Inst{11-20} = 0; 913 let Inst{21-30} = xo; 914 let Inst{31} = RC; 915} 916 917class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 918 InstrItinClass itin, list<dag> pattern> 919 : I<opcode, OOL, IOL, asmstr, itin> { 920 bits<3> BF; 921 922 bit RC = 0; 923 924 let Inst{6-8} = BF; 925 let Inst{9-20} = 0; 926 let Inst{21-30} = xo; 927 let Inst{31} = RC; 928} 929 930// [PO RT RA RB XO /] 931class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 932 string asmstr, InstrItinClass itin, list<dag> pattern> 933 : I<opcode, OOL, IOL, asmstr, itin> { 934 bits<3> BF; 935 bits<1> L; 936 bits<5> RA; 937 bits<5> RB; 938 939 let Pattern = pattern; 940 941 let Inst{6-8} = BF; 942 let Inst{9} = 0; 943 let Inst{10} = L; 944 let Inst{11-15} = RA; 945 let Inst{16-20} = RB; 946 let Inst{21-30} = xo; 947 let Inst{31} = 0; 948} 949 950// Same as XForm_17 but with GPR's and new naming convention 951class X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 952 string asmstr, InstrItinClass itin, list<dag> pattern> 953 : I<opcode, OOL, IOL, asmstr, itin> { 954 bits<3> BF; 955 bits<5> RA; 956 bits<5> RB; 957 958 let Pattern = pattern; 959 960 let Inst{6-8} = BF; 961 let Inst{9-10} = 0; 962 let Inst{11-15} = RA; 963 let Inst{16-20} = RB; 964 let Inst{21-30} = xo; 965 let Inst{31} = 0; 966} 967 968// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO] 969class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, 970 string asmstr, InstrItinClass itin, list<dag> pattern> 971 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 972 let A = xo2; 973} 974 975class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 976 string asmstr, InstrItinClass itin, list<dag> pattern> 977 : I<opcode, OOL, IOL, asmstr, itin> { 978 bits<3> BF; 979 bits<7> DCMX; 980 bits<5> VB; 981 982 let Pattern = pattern; 983 984 let Inst{6-8} = BF; 985 let Inst{9-15} = DCMX; 986 let Inst{16-20} = VB; 987 let Inst{21-30} = xo; 988 let Inst{31} = 0; 989} 990 991class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 992 string asmstr, InstrItinClass itin, list<dag> pattern> 993 : I<opcode, OOL, IOL, asmstr, itin> { 994 bits<6> XT; 995 bits<8> IMM8; 996 997 let Pattern = pattern; 998 999 let Inst{6-10} = XT{4-0}; 1000 let Inst{11-12} = 0; 1001 let Inst{13-20} = IMM8; 1002 let Inst{21-30} = xo; 1003 let Inst{31} = XT{5}; 1004} 1005 1006// XForm_base_r3xo for instructions such as P9 atomics where we don't want 1007// to specify an SDAG pattern for matching. 1008class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1009 string asmstr, InstrItinClass itin> 1010 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, []> { 1011} 1012 1013class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1014 InstrItinClass itin> 1015 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> { 1016 let FRA = 0; 1017 let FRB = 0; 1018} 1019 1020// [PO /// L RA RB XO /] 1021class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1022 string asmstr, InstrItinClass itin, list<dag> pattern> 1023 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 1024 let BF = 0; 1025 let Pattern = pattern; 1026 1027 bit RC = 0; 1028 let Inst{31} = RC; 1029} 1030 1031// XX*-Form (VSX) 1032class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1033 InstrItinClass itin, list<dag> pattern> 1034 : I<opcode, OOL, IOL, asmstr, itin> { 1035 bits<6> XT; 1036 bits<5> A; 1037 bits<5> B; 1038 1039 let Pattern = pattern; 1040 1041 let Inst{6-10} = XT{4-0}; 1042 let Inst{11-15} = A; 1043 let Inst{16-20} = B; 1044 let Inst{21-30} = xo; 1045 let Inst{31} = XT{5}; 1046} 1047 1048class XX1Form_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1049 string asmstr, InstrItinClass itin, list<dag> pattern> 1050 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; 1051 1052class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1053 string asmstr, InstrItinClass itin, list<dag> pattern> 1054 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1055 let B = 0; 1056} 1057 1058class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1059 InstrItinClass itin, list<dag> pattern> 1060 : I<opcode, OOL, IOL, asmstr, itin> { 1061 bits<6> XT; 1062 bits<6> XB; 1063 1064 let Pattern = pattern; 1065 1066 let Inst{6-10} = XT{4-0}; 1067 let Inst{11-15} = 0; 1068 let Inst{16-20} = XB{4-0}; 1069 let Inst{21-29} = xo; 1070 let Inst{30} = XB{5}; 1071 let Inst{31} = XT{5}; 1072} 1073 1074class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1075 InstrItinClass itin, list<dag> pattern> 1076 : I<opcode, OOL, IOL, asmstr, itin> { 1077 bits<3> CR; 1078 bits<6> XB; 1079 1080 let Pattern = pattern; 1081 1082 let Inst{6-8} = CR; 1083 let Inst{9-15} = 0; 1084 let Inst{16-20} = XB{4-0}; 1085 let Inst{21-29} = xo; 1086 let Inst{30} = XB{5}; 1087 let Inst{31} = 0; 1088} 1089 1090class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1091 InstrItinClass itin, list<dag> pattern> 1092 : I<opcode, OOL, IOL, asmstr, itin> { 1093 bits<6> XT; 1094 bits<6> XB; 1095 bits<2> D; 1096 1097 let Pattern = pattern; 1098 1099 let Inst{6-10} = XT{4-0}; 1100 let Inst{11-13} = 0; 1101 let Inst{14-15} = D; 1102 let Inst{16-20} = XB{4-0}; 1103 let Inst{21-29} = xo; 1104 let Inst{30} = XB{5}; 1105 let Inst{31} = XT{5}; 1106} 1107 1108class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1109 string asmstr, InstrItinClass itin, list<dag> pattern> 1110 : I<opcode, OOL, IOL, asmstr, itin> { 1111 bits<6> XT; 1112 bits<6> XB; 1113 bits<5> UIM5; 1114 1115 let Pattern = pattern; 1116 1117 let Inst{6-10} = XT{4-0}; 1118 let Inst{11-15} = UIM5; 1119 let Inst{16-20} = XB{4-0}; 1120 let Inst{21-29} = xo; 1121 let Inst{30} = XB{5}; 1122 let Inst{31} = XT{5}; 1123} 1124 1125// [PO T XO B XO BX /] 1126class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1127 string asmstr, InstrItinClass itin, list<dag> pattern> 1128 : I<opcode, OOL, IOL, asmstr, itin> { 1129 bits<5> RT; 1130 bits<6> XB; 1131 1132 let Pattern = pattern; 1133 1134 let Inst{6-10} = RT; 1135 let Inst{11-15} = xo2; 1136 let Inst{16-20} = XB{4-0}; 1137 let Inst{21-29} = xo; 1138 let Inst{30} = XB{5}; 1139 let Inst{31} = 0; 1140} 1141 1142// [PO T XO B XO BX TX] 1143class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1144 string asmstr, InstrItinClass itin, list<dag> pattern> 1145 : I<opcode, OOL, IOL, asmstr, itin> { 1146 bits<6> XT; 1147 bits<6> XB; 1148 1149 let Pattern = pattern; 1150 1151 let Inst{6-10} = XT{4-0}; 1152 let Inst{11-15} = xo2; 1153 let Inst{16-20} = XB{4-0}; 1154 let Inst{21-29} = xo; 1155 let Inst{30} = XB{5}; 1156 let Inst{31} = XT{5}; 1157} 1158 1159class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1160 string asmstr, InstrItinClass itin, list<dag> pattern> 1161 : I<opcode, OOL, IOL, asmstr, itin> { 1162 bits<3> BF; 1163 bits<7> DCMX; 1164 bits<6> XB; 1165 1166 let Pattern = pattern; 1167 1168 let Inst{6-8} = BF; 1169 let Inst{9-15} = DCMX; 1170 let Inst{16-20} = XB{4-0}; 1171 let Inst{21-29} = xo; 1172 let Inst{30} = XB{5}; 1173 let Inst{31} = 0; 1174} 1175 1176class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2, 1177 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 1178 list<dag> pattern> 1179 : I<opcode, OOL, IOL, asmstr, itin> { 1180 bits<6> XT; 1181 bits<7> DCMX; 1182 bits<6> XB; 1183 1184 let Pattern = pattern; 1185 1186 let Inst{6-10} = XT{4-0}; 1187 let Inst{11-15} = DCMX{4-0}; 1188 let Inst{16-20} = XB{4-0}; 1189 let Inst{21-24} = xo1; 1190 let Inst{25} = DCMX{6}; 1191 let Inst{26-28} = xo2; 1192 let Inst{29} = DCMX{5}; 1193 let Inst{30} = XB{5}; 1194 let Inst{31} = XT{5}; 1195} 1196 1197class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1198 InstrItinClass itin, list<dag> pattern> 1199 : I<opcode, OOL, IOL, asmstr, itin> { 1200 bits<6> XT; 1201 bits<6> XA; 1202 bits<6> XB; 1203 1204 let Pattern = pattern; 1205 1206 let Inst{6-10} = XT{4-0}; 1207 let Inst{11-15} = XA{4-0}; 1208 let Inst{16-20} = XB{4-0}; 1209 let Inst{21-28} = xo; 1210 let Inst{29} = XA{5}; 1211 let Inst{30} = XB{5}; 1212 let Inst{31} = XT{5}; 1213} 1214 1215class XX3Form_SameOp<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1216 InstrItinClass itin, list<dag> pattern> 1217 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1218 let XA = XT; 1219 let XB = XT; 1220} 1221 1222class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1223 InstrItinClass itin, list<dag> pattern> 1224 : I<opcode, OOL, IOL, asmstr, itin> { 1225 bits<3> CR; 1226 bits<6> XA; 1227 bits<6> XB; 1228 1229 let Pattern = pattern; 1230 1231 let Inst{6-8} = CR; 1232 let Inst{9-10} = 0; 1233 let Inst{11-15} = XA{4-0}; 1234 let Inst{16-20} = XB{4-0}; 1235 let Inst{21-28} = xo; 1236 let Inst{29} = XA{5}; 1237 let Inst{30} = XB{5}; 1238 let Inst{31} = 0; 1239} 1240 1241class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1242 InstrItinClass itin, list<dag> pattern> 1243 : I<opcode, OOL, IOL, asmstr, itin> { 1244 bits<6> XT; 1245 bits<6> XA; 1246 bits<6> XB; 1247 bits<2> D; 1248 1249 let Pattern = pattern; 1250 1251 let Inst{6-10} = XT{4-0}; 1252 let Inst{11-15} = XA{4-0}; 1253 let Inst{16-20} = XB{4-0}; 1254 let Inst{21} = 0; 1255 let Inst{22-23} = D; 1256 let Inst{24-28} = xo; 1257 let Inst{29} = XA{5}; 1258 let Inst{30} = XB{5}; 1259 let Inst{31} = XT{5}; 1260} 1261 1262class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr, 1263 InstrItinClass itin, list<dag> pattern> 1264 : I<opcode, OOL, IOL, asmstr, itin> { 1265 bits<6> XT; 1266 bits<6> XA; 1267 bits<6> XB; 1268 1269 let Pattern = pattern; 1270 1271 bit RC = 0; // set by isRecordForm 1272 1273 let Inst{6-10} = XT{4-0}; 1274 let Inst{11-15} = XA{4-0}; 1275 let Inst{16-20} = XB{4-0}; 1276 let Inst{21} = RC; 1277 let Inst{22-28} = xo; 1278 let Inst{29} = XA{5}; 1279 let Inst{30} = XB{5}; 1280 let Inst{31} = XT{5}; 1281} 1282 1283class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 1284 InstrItinClass itin, list<dag> pattern> 1285 : I<opcode, OOL, IOL, asmstr, itin> { 1286 bits<6> XT; 1287 bits<6> XA; 1288 bits<6> XB; 1289 bits<6> XC; 1290 1291 let Pattern = pattern; 1292 1293 let Inst{6-10} = XT{4-0}; 1294 let Inst{11-15} = XA{4-0}; 1295 let Inst{16-20} = XB{4-0}; 1296 let Inst{21-25} = XC{4-0}; 1297 let Inst{26-27} = xo; 1298 let Inst{28} = XC{5}; 1299 let Inst{29} = XA{5}; 1300 let Inst{30} = XB{5}; 1301 let Inst{31} = XT{5}; 1302} 1303 1304// DCB_Form - Form X instruction, used for dcb* instructions. 1305class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 1306 InstrItinClass itin, list<dag> pattern> 1307 : I<31, OOL, IOL, asmstr, itin> { 1308 bits<5> A; 1309 bits<5> B; 1310 1311 let Pattern = pattern; 1312 1313 let Inst{6-10} = immfield; 1314 let Inst{11-15} = A; 1315 let Inst{16-20} = B; 1316 let Inst{21-30} = xo; 1317 let Inst{31} = 0; 1318} 1319 1320class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr, 1321 InstrItinClass itin, list<dag> pattern> 1322 : I<31, OOL, IOL, asmstr, itin> { 1323 bits<5> TH; 1324 bits<5> A; 1325 bits<5> B; 1326 1327 let Pattern = pattern; 1328 1329 let Inst{6-10} = TH; 1330 let Inst{11-15} = A; 1331 let Inst{16-20} = B; 1332 let Inst{21-30} = xo; 1333 let Inst{31} = 0; 1334} 1335 1336// DSS_Form - Form X instruction, used for altivec dss* instructions. 1337class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr, 1338 InstrItinClass itin, list<dag> pattern> 1339 : I<31, OOL, IOL, asmstr, itin> { 1340 bits<2> STRM; 1341 bits<5> A; 1342 bits<5> B; 1343 1344 let Pattern = pattern; 1345 1346 let Inst{6} = T; 1347 let Inst{7-8} = 0; 1348 let Inst{9-10} = STRM; 1349 let Inst{11-15} = A; 1350 let Inst{16-20} = B; 1351 let Inst{21-30} = xo; 1352 let Inst{31} = 0; 1353} 1354 1355// 1.7.7 XL-Form 1356class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1357 InstrItinClass itin, list<dag> pattern> 1358 : I<opcode, OOL, IOL, asmstr, itin> { 1359 bits<5> CRD; 1360 bits<5> CRA; 1361 bits<5> CRB; 1362 1363 let Pattern = pattern; 1364 1365 let Inst{6-10} = CRD; 1366 let Inst{11-15} = CRA; 1367 let Inst{16-20} = CRB; 1368 let Inst{21-30} = xo; 1369 let Inst{31} = 0; 1370} 1371 1372class XLForm_1_np<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1373 InstrItinClass itin, list<dag> pattern> 1374 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1375 let CRD = 0; 1376 let CRA = 0; 1377 let CRB = 0; 1378} 1379 1380class XLForm_1_gen<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1381 InstrItinClass itin, list<dag> pattern> 1382 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1383 bits<5> RT; 1384 bits<5> RB; 1385 1386 let CRD = RT; 1387 let CRA = 0; 1388 let CRB = RB; 1389} 1390 1391class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1392 InstrItinClass itin, list<dag> pattern> 1393 : I<opcode, OOL, IOL, asmstr, itin> { 1394 bits<5> CRD; 1395 1396 let Pattern = pattern; 1397 1398 let Inst{6-10} = CRD; 1399 let Inst{11-15} = CRD; 1400 let Inst{16-20} = CRD; 1401 let Inst{21-30} = xo; 1402 let Inst{31} = 0; 1403} 1404 1405class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 1406 InstrItinClass itin, list<dag> pattern> 1407 : I<opcode, OOL, IOL, asmstr, itin> { 1408 bits<5> BO; 1409 bits<5> BI; 1410 bits<2> BH; 1411 1412 let Pattern = pattern; 1413 1414 let Inst{6-10} = BO; 1415 let Inst{11-15} = BI; 1416 let Inst{16-18} = 0; 1417 let Inst{19-20} = BH; 1418 let Inst{21-30} = xo; 1419 let Inst{31} = lk; 1420} 1421 1422class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 1423 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1424 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1425 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 1426 bits<3> CR; 1427 1428 let BO = BIBO{4-0}; 1429 let BI{0-1} = BIBO{5-6}; 1430 let BI{2-4} = CR{0-2}; 1431 let BH = 0; 1432} 1433 1434class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk, 1435 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1436 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1437 let BO = bo; 1438 let BH = 0; 1439} 1440 1441class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 1442 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1443 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1444 let BO = bo; 1445 let BI = bi; 1446 let BH = 0; 1447} 1448 1449class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1450 InstrItinClass itin> 1451 : I<opcode, OOL, IOL, asmstr, itin> { 1452 bits<3> BF; 1453 bits<3> BFA; 1454 1455 let Inst{6-8} = BF; 1456 let Inst{9-10} = 0; 1457 let Inst{11-13} = BFA; 1458 let Inst{14-15} = 0; 1459 let Inst{16-20} = 0; 1460 let Inst{21-30} = xo; 1461 let Inst{31} = 0; 1462} 1463 1464class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1465 InstrItinClass itin> 1466 : I<opcode, OOL, IOL, asmstr, itin> { 1467 bits<3> BF; 1468 bit W; 1469 bits<4> U; 1470 1471 bit RC = 0; 1472 1473 let Inst{6-8} = BF; 1474 let Inst{9-10} = 0; 1475 let Inst{11-14} = 0; 1476 let Inst{15} = W; 1477 let Inst{16-19} = U; 1478 let Inst{20} = 0; 1479 let Inst{21-30} = xo; 1480 let Inst{31} = RC; 1481} 1482 1483class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1484 InstrItinClass itin, list<dag> pattern> 1485 : I<opcode, OOL, IOL, asmstr, itin> { 1486 bits<1> S; 1487 1488 let Pattern = pattern; 1489 1490 let Inst{6-19} = 0; 1491 let Inst{20} = S; 1492 let Inst{21-30} = xo; 1493 let Inst{31} = 0; 1494} 1495 1496class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk, 1497 bits<6> opcode2, bits<2> xo2, 1498 dag OOL, dag IOL, string asmstr, 1499 InstrItinClass itin, list<dag> pattern> 1500 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1501 bits<5> BO; 1502 bits<5> BI; 1503 bits<2> BH; 1504 1505 bits<5> RST; 1506 bits<19> DS_RA; 1507 1508 let Pattern = pattern; 1509 1510 let Inst{6-10} = BO; 1511 let Inst{11-15} = BI; 1512 let Inst{16-18} = 0; 1513 let Inst{19-20} = BH; 1514 let Inst{21-30} = xo1; 1515 let Inst{31} = lk; 1516 1517 let Inst{38-42} = RST; 1518 let Inst{43-47} = DS_RA{18-14}; // Register # 1519 let Inst{48-61} = DS_RA{13-0}; // Displacement. 1520 let Inst{62-63} = xo2; 1521} 1522 1523class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1, 1524 bits<5> bo, bits<5> bi, bit lk, 1525 bits<6> opcode2, bits<2> xo2, 1526 dag OOL, dag IOL, string asmstr, 1527 InstrItinClass itin, list<dag> pattern> 1528 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2, 1529 OOL, IOL, asmstr, itin, pattern> { 1530 let BO = bo; 1531 let BI = bi; 1532 let BH = 0; 1533} 1534 1535class XLForm_2_ext_and_DForm_1<bits<6> opcode1, bits<10> xo1, bits<5> bo, 1536 bits<5> bi, bit lk, bits<6> opcode2, dag OOL, 1537 dag IOL, string asmstr, InstrItinClass itin, 1538 list<dag> pattern> 1539 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1540 1541 bits<5> RST; 1542 bits<21> D_RA; 1543 1544 let Pattern = pattern; 1545 1546 let Inst{6-10} = bo; 1547 let Inst{11-15} = bi; 1548 let Inst{16-18} = 0; 1549 let Inst{19-20} = 0; // Unused (BH) 1550 let Inst{21-30} = xo1; 1551 let Inst{31} = lk; 1552 1553 let Inst{38-42} = RST; 1554 let Inst{43-47} = D_RA{20-16}; // Base Register 1555 let Inst{48-63} = D_RA{15-0}; // Displacement 1556} 1557 1558// 1.7.8 XFX-Form 1559class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1560 InstrItinClass itin> 1561 : I<opcode, OOL, IOL, asmstr, itin> { 1562 bits<5> RT; 1563 bits<10> SPR; 1564 1565 let Inst{6-10} = RT; 1566 let Inst{11} = SPR{4}; 1567 let Inst{12} = SPR{3}; 1568 let Inst{13} = SPR{2}; 1569 let Inst{14} = SPR{1}; 1570 let Inst{15} = SPR{0}; 1571 let Inst{16} = SPR{9}; 1572 let Inst{17} = SPR{8}; 1573 let Inst{18} = SPR{7}; 1574 let Inst{19} = SPR{6}; 1575 let Inst{20} = SPR{5}; 1576 let Inst{21-30} = xo; 1577 let Inst{31} = 0; 1578} 1579 1580class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1581 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1582 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 1583 let SPR = spr; 1584} 1585 1586class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1587 InstrItinClass itin> 1588 : I<opcode, OOL, IOL, asmstr, itin> { 1589 bits<5> RT; 1590 1591 let Inst{6-10} = RT; 1592 let Inst{11-20} = 0; 1593 let Inst{21-30} = xo; 1594 let Inst{31} = 0; 1595} 1596 1597class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1598 InstrItinClass itin, list<dag> pattern> 1599 : I<opcode, OOL, IOL, asmstr, itin> { 1600 bits<5> RT; 1601 bits<10> Entry; 1602 let Pattern = pattern; 1603 1604 let Inst{6-10} = RT; 1605 let Inst{11-20} = Entry; 1606 let Inst{21-30} = xo; 1607 let Inst{31} = 0; 1608} 1609 1610class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1611 InstrItinClass itin> 1612 : I<opcode, OOL, IOL, asmstr, itin> { 1613 bits<8> FXM; 1614 bits<5> rS; 1615 1616 let Inst{6-10} = rS; 1617 let Inst{11} = 0; 1618 let Inst{12-19} = FXM; 1619 let Inst{20} = 0; 1620 let Inst{21-30} = xo; 1621 let Inst{31} = 0; 1622} 1623 1624class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1625 InstrItinClass itin> 1626 : I<opcode, OOL, IOL, asmstr, itin> { 1627 bits<5> ST; 1628 bits<8> FXM; 1629 1630 let Inst{6-10} = ST; 1631 let Inst{11} = 1; 1632 let Inst{12-19} = FXM; 1633 let Inst{20} = 0; 1634 let Inst{21-30} = xo; 1635 let Inst{31} = 0; 1636} 1637 1638class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1639 InstrItinClass itin> 1640 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 1641 1642class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1643 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1644 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 1645 let SPR = spr; 1646} 1647 1648// XFL-Form - MTFSF 1649// This is probably 1.7.9, but I don't have the reference that uses this 1650// numbering scheme... 1651class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1652 InstrItinClass itin, list<dag>pattern> 1653 : I<opcode, OOL, IOL, asmstr, itin> { 1654 bits<8> FM; 1655 bits<5> rT; 1656 1657 bit RC = 0; // set by isRecordForm 1658 let Pattern = pattern; 1659 1660 let Inst{6} = 0; 1661 let Inst{7-14} = FM; 1662 let Inst{15} = 0; 1663 let Inst{16-20} = rT; 1664 let Inst{21-30} = xo; 1665 let Inst{31} = RC; 1666} 1667 1668class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1669 InstrItinClass itin, list<dag>pattern> 1670 : I<opcode, OOL, IOL, asmstr, itin> { 1671 bit L; 1672 bits<8> FLM; 1673 bit W; 1674 bits<5> FRB; 1675 1676 bit RC = 0; // set by isRecordForm 1677 let Pattern = pattern; 1678 1679 let Inst{6} = L; 1680 let Inst{7-14} = FLM; 1681 let Inst{15} = W; 1682 let Inst{16-20} = FRB; 1683 let Inst{21-30} = xo; 1684 let Inst{31} = RC; 1685} 1686 1687// 1.7.10 XS-Form - SRADI. 1688class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1689 InstrItinClass itin, list<dag> pattern> 1690 : I<opcode, OOL, IOL, asmstr, itin> { 1691 bits<5> A; 1692 bits<5> RS; 1693 bits<6> SH; 1694 1695 bit RC = 0; // set by isRecordForm 1696 let Pattern = pattern; 1697 1698 let Inst{6-10} = RS; 1699 let Inst{11-15} = A; 1700 let Inst{16-20} = SH{4,3,2,1,0}; 1701 let Inst{21-29} = xo; 1702 let Inst{30} = SH{5}; 1703 let Inst{31} = RC; 1704} 1705 1706// 1.7.11 XO-Form 1707class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 1708 InstrItinClass itin, list<dag> pattern> 1709 : I<opcode, OOL, IOL, asmstr, itin> { 1710 bits<5> RT; 1711 bits<5> RA; 1712 bits<5> RB; 1713 1714 let Pattern = pattern; 1715 1716 bit RC = 0; // set by isRecordForm 1717 1718 let Inst{6-10} = RT; 1719 let Inst{11-15} = RA; 1720 let Inst{16-20} = RB; 1721 let Inst{21} = oe; 1722 let Inst{22-30} = xo; 1723 let Inst{31} = RC; 1724} 1725 1726class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 1727 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1728 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 1729 let RB = 0; 1730} 1731 1732// 1.7.12 A-Form 1733class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1734 InstrItinClass itin, list<dag> pattern> 1735 : I<opcode, OOL, IOL, asmstr, itin> { 1736 bits<5> FRT; 1737 bits<5> FRA; 1738 bits<5> FRC; 1739 bits<5> FRB; 1740 1741 let Pattern = pattern; 1742 1743 bit RC = 0; // set by isRecordForm 1744 1745 let Inst{6-10} = FRT; 1746 let Inst{11-15} = FRA; 1747 let Inst{16-20} = FRB; 1748 let Inst{21-25} = FRC; 1749 let Inst{26-30} = xo; 1750 let Inst{31} = RC; 1751} 1752 1753class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1754 InstrItinClass itin, list<dag> pattern> 1755 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1756 let FRC = 0; 1757} 1758 1759class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1760 InstrItinClass itin, list<dag> pattern> 1761 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1762 let FRB = 0; 1763} 1764 1765class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1766 InstrItinClass itin, list<dag> pattern> 1767 : I<opcode, OOL, IOL, asmstr, itin> { 1768 bits<5> RT; 1769 bits<5> RA; 1770 bits<5> RB; 1771 bits<5> COND; 1772 1773 let Pattern = pattern; 1774 1775 let Inst{6-10} = RT; 1776 let Inst{11-15} = RA; 1777 let Inst{16-20} = RB; 1778 let Inst{21-25} = COND; 1779 let Inst{26-30} = xo; 1780 let Inst{31} = 0; 1781} 1782 1783// 1.7.13 M-Form 1784class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1785 InstrItinClass itin, list<dag> pattern> 1786 : I<opcode, OOL, IOL, asmstr, itin> { 1787 bits<5> RA; 1788 bits<5> RS; 1789 bits<5> RB; 1790 bits<5> MB; 1791 bits<5> ME; 1792 1793 let Pattern = pattern; 1794 1795 bit RC = 0; // set by isRecordForm 1796 1797 let Inst{6-10} = RS; 1798 let Inst{11-15} = RA; 1799 let Inst{16-20} = RB; 1800 let Inst{21-25} = MB; 1801 let Inst{26-30} = ME; 1802 let Inst{31} = RC; 1803} 1804 1805class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1806 InstrItinClass itin, list<dag> pattern> 1807 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 1808} 1809 1810// 1.7.14 MD-Form 1811class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 1812 InstrItinClass itin, list<dag> pattern> 1813 : I<opcode, OOL, IOL, asmstr, itin> { 1814 bits<5> RA; 1815 bits<5> RS; 1816 bits<6> SH; 1817 bits<6> MBE; 1818 1819 let Pattern = pattern; 1820 1821 bit RC = 0; // set by isRecordForm 1822 1823 let Inst{6-10} = RS; 1824 let Inst{11-15} = RA; 1825 let Inst{16-20} = SH{4,3,2,1,0}; 1826 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1827 let Inst{27-29} = xo; 1828 let Inst{30} = SH{5}; 1829 let Inst{31} = RC; 1830} 1831 1832class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 1833 InstrItinClass itin, list<dag> pattern> 1834 : I<opcode, OOL, IOL, asmstr, itin> { 1835 bits<5> RA; 1836 bits<5> RS; 1837 bits<5> RB; 1838 bits<6> MBE; 1839 1840 let Pattern = pattern; 1841 1842 bit RC = 0; // set by isRecordForm 1843 1844 let Inst{6-10} = RS; 1845 let Inst{11-15} = RA; 1846 let Inst{16-20} = RB; 1847 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1848 let Inst{27-30} = xo; 1849 let Inst{31} = RC; 1850} 1851 1852 1853// E-1 VA-Form 1854 1855// VAForm_1 - DACB ordering. 1856class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 1857 InstrItinClass itin, list<dag> pattern> 1858 : I<4, OOL, IOL, asmstr, itin> { 1859 bits<5> VD; 1860 bits<5> VA; 1861 bits<5> VC; 1862 bits<5> VB; 1863 1864 let Pattern = pattern; 1865 1866 let Inst{6-10} = VD; 1867 let Inst{11-15} = VA; 1868 let Inst{16-20} = VB; 1869 let Inst{21-25} = VC; 1870 let Inst{26-31} = xo; 1871} 1872 1873// VAForm_1a - DABC ordering. 1874class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 1875 InstrItinClass itin, list<dag> pattern> 1876 : I<4, OOL, IOL, asmstr, itin> { 1877 bits<5> VD; 1878 bits<5> VA; 1879 bits<5> VB; 1880 bits<5> VC; 1881 1882 let Pattern = pattern; 1883 1884 let Inst{6-10} = VD; 1885 let Inst{11-15} = VA; 1886 let Inst{16-20} = VB; 1887 let Inst{21-25} = VC; 1888 let Inst{26-31} = xo; 1889} 1890 1891class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 1892 InstrItinClass itin, list<dag> pattern> 1893 : I<4, OOL, IOL, asmstr, itin> { 1894 bits<5> VD; 1895 bits<5> VA; 1896 bits<5> VB; 1897 bits<4> SH; 1898 1899 let Pattern = pattern; 1900 1901 let Inst{6-10} = VD; 1902 let Inst{11-15} = VA; 1903 let Inst{16-20} = VB; 1904 let Inst{21} = 0; 1905 let Inst{22-25} = SH; 1906 let Inst{26-31} = xo; 1907} 1908 1909// E-2 VX-Form 1910class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 1911 InstrItinClass itin, list<dag> pattern> 1912 : I<4, OOL, IOL, asmstr, itin> { 1913 bits<5> VD; 1914 bits<5> VA; 1915 bits<5> VB; 1916 1917 let Pattern = pattern; 1918 1919 let Inst{6-10} = VD; 1920 let Inst{11-15} = VA; 1921 let Inst{16-20} = VB; 1922 let Inst{21-31} = xo; 1923} 1924 1925class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 1926 InstrItinClass itin, list<dag> pattern> 1927 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 1928 let VA = VD; 1929 let VB = VD; 1930} 1931 1932 1933class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 1934 InstrItinClass itin, list<dag> pattern> 1935 : I<4, OOL, IOL, asmstr, itin> { 1936 bits<5> VD; 1937 bits<5> VB; 1938 1939 let Pattern = pattern; 1940 1941 let Inst{6-10} = VD; 1942 let Inst{11-15} = 0; 1943 let Inst{16-20} = VB; 1944 let Inst{21-31} = xo; 1945} 1946 1947class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 1948 InstrItinClass itin, list<dag> pattern> 1949 : I<4, OOL, IOL, asmstr, itin> { 1950 bits<5> VD; 1951 bits<5> IMM; 1952 1953 let Pattern = pattern; 1954 1955 let Inst{6-10} = VD; 1956 let Inst{11-15} = IMM; 1957 let Inst{16-20} = 0; 1958 let Inst{21-31} = xo; 1959} 1960 1961/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 1962class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 1963 InstrItinClass itin, list<dag> pattern> 1964 : I<4, OOL, IOL, asmstr, itin> { 1965 bits<5> VD; 1966 1967 let Pattern = pattern; 1968 1969 let Inst{6-10} = VD; 1970 let Inst{11-15} = 0; 1971 let Inst{16-20} = 0; 1972 let Inst{21-31} = xo; 1973} 1974 1975/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 1976class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 1977 InstrItinClass itin, list<dag> pattern> 1978 : I<4, OOL, IOL, asmstr, itin> { 1979 bits<5> VB; 1980 1981 let Pattern = pattern; 1982 1983 let Inst{6-10} = 0; 1984 let Inst{11-15} = 0; 1985 let Inst{16-20} = VB; 1986 let Inst{21-31} = xo; 1987} 1988 1989// e.g. [PO VRT EO VRB XO] 1990class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL, 1991 string asmstr, InstrItinClass itin, list<dag> pattern> 1992 : I<4, OOL, IOL, asmstr, itin> { 1993 bits<5> RD; 1994 bits<5> VB; 1995 1996 let Pattern = pattern; 1997 1998 let Inst{6-10} = RD; 1999 let Inst{11-15} = eo; 2000 let Inst{16-20} = VB; 2001 let Inst{21-31} = xo; 2002} 2003 2004/// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX" 2005class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr, 2006 InstrItinClass itin, list<dag> pattern> 2007 : I<4, OOL, IOL, asmstr, itin> { 2008 bits<5> VD; 2009 bits<5> VA; 2010 bits<1> ST; 2011 bits<4> SIX; 2012 2013 let Pattern = pattern; 2014 2015 let Inst{6-10} = VD; 2016 let Inst{11-15} = VA; 2017 let Inst{16} = ST; 2018 let Inst{17-20} = SIX; 2019 let Inst{21-31} = xo; 2020} 2021 2022/// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox" 2023class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr, 2024 InstrItinClass itin, list<dag> pattern> 2025 : I<4, OOL, IOL, asmstr, itin> { 2026 bits<5> VD; 2027 bits<5> VA; 2028 2029 let Pattern = pattern; 2030 2031 let Inst{6-10} = VD; 2032 let Inst{11-15} = VA; 2033 let Inst{16-20} = 0; 2034 let Inst{21-31} = xo; 2035} 2036 2037// E-4 VXR-Form 2038class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 2039 InstrItinClass itin, list<dag> pattern> 2040 : I<4, OOL, IOL, asmstr, itin> { 2041 bits<5> VD; 2042 bits<5> VA; 2043 bits<5> VB; 2044 bit RC = 0; 2045 2046 let Pattern = pattern; 2047 2048 let Inst{6-10} = VD; 2049 let Inst{11-15} = VA; 2050 let Inst{16-20} = VB; 2051 let Inst{21} = RC; 2052 let Inst{22-31} = xo; 2053} 2054 2055// VX-Form: [PO VRT EO VRB 1 PS XO] 2056class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo, 2057 dag OOL, dag IOL, string asmstr, 2058 InstrItinClass itin, list<dag> pattern> 2059 : I<4, OOL, IOL, asmstr, itin> { 2060 bits<5> VD; 2061 bits<5> VB; 2062 bit PS; 2063 2064 let Pattern = pattern; 2065 2066 let Inst{6-10} = VD; 2067 let Inst{11-15} = eo; 2068 let Inst{16-20} = VB; 2069 let Inst{21} = 1; 2070 let Inst{22} = PS; 2071 let Inst{23-31} = xo; 2072} 2073 2074// VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO] 2075class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr, 2076 InstrItinClass itin, list<dag> pattern> 2077 : I<4, OOL, IOL, asmstr, itin> { 2078 bits<5> VD; 2079 bits<5> VA; 2080 bits<5> VB; 2081 bit PS; 2082 2083 let Pattern = pattern; 2084 2085 let Inst{6-10} = VD; 2086 let Inst{11-15} = VA; 2087 let Inst{16-20} = VB; 2088 let Inst{21} = 1; 2089 let Inst{22} = PS; 2090 let Inst{23-31} = xo; 2091} 2092 2093class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2094 InstrItinClass itin, list<dag> pattern> 2095 : I<opcode, OOL, IOL, asmstr, itin> { 2096 bits<5> VRT; 2097 bit R; 2098 bits<5> VRB; 2099 bits<2> idx; 2100 2101 let Pattern = pattern; 2102 2103 bit RC = 0; // set by isRecordForm 2104 2105 let Inst{6-10} = VRT; 2106 let Inst{11-14} = 0; 2107 let Inst{15} = R; 2108 let Inst{16-20} = VRB; 2109 let Inst{21-22} = idx; 2110 let Inst{23-30} = xo; 2111 let Inst{31} = RC; 2112} 2113 2114//===----------------------------------------------------------------------===// 2115// EmitTimePseudo won't have encoding information for the [MC]CodeEmitter 2116// stuff 2117class PPCEmitTimePseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2118 : I<0, OOL, IOL, asmstr, NoItinerary> { 2119 let isCodeGenOnly = 1; 2120 let PPC64 = 0; 2121 let Pattern = pattern; 2122 let Inst{31-0} = 0; 2123 let hasNoSchedulingInfo = 1; 2124} 2125 2126// Instruction that require custom insertion support 2127// a.k.a. ISelPseudos, however, these won't have isPseudo set 2128class PPCCustomInserterPseudo<dag OOL, dag IOL, string asmstr, 2129 list<dag> pattern> 2130 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> { 2131 let usesCustomInserter = 1; 2132} 2133 2134// PostRAPseudo will be expanded in expandPostRAPseudo, isPseudo flag in td 2135// files is set only for PostRAPseudo 2136class PPCPostRAExpPseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2137 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> { 2138 let isPseudo = 1; 2139} 2140 2141class PseudoXFormMemOp<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2142 : PPCPostRAExpPseudo<OOL, IOL, asmstr, pattern>, XFormMemOp; 2143 2144