1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// PowerPC instruction formats 13 14class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 15 : Instruction { 16 field bits<32> Inst; 17 field bits<32> SoftFail = 0; 18 let Size = 4; 19 20 bit PPC64 = 0; // Default value, override with isPPC64 21 22 let Namespace = "PPC"; 23 let Inst{0-5} = opcode; 24 let OutOperandList = OOL; 25 let InOperandList = IOL; 26 let AsmString = asmstr; 27 let Itinerary = itin; 28 29 bits<1> PPC970_First = 0; 30 bits<1> PPC970_Single = 0; 31 bits<1> PPC970_Cracked = 0; 32 bits<3> PPC970_Unit = 0; 33 34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 35 /// these must be reflected there! See comments there for what these are. 36 let TSFlags{0} = PPC970_First; 37 let TSFlags{1} = PPC970_Single; 38 let TSFlags{2} = PPC970_Cracked; 39 let TSFlags{5-3} = PPC970_Unit; 40 41 // Fields used for relation models. 42 string BaseName = ""; 43 44 // For cases where multiple instruction definitions really represent the 45 // same underlying instruction but with one definition for 64-bit arguments 46 // and one for 32-bit arguments, this bit breaks the degeneracy between 47 // the two forms and allows TableGen to generate mapping tables. 48 bit Interpretation64Bit = 0; 49} 50 51class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 52class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 53class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 54class PPC970_MicroCode; 55 56class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 57class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 58class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 59class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 60class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 61class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 62class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 63class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 64 65// Two joined instructions; used to emit two adjacent instructions as one. 66// The itinerary from the first instruction is used for scheduling and 67// classification. 68class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 69 InstrItinClass itin> 70 : Instruction { 71 field bits<64> Inst; 72 field bits<64> SoftFail = 0; 73 let Size = 8; 74 75 bit PPC64 = 0; // Default value, override with isPPC64 76 77 let Namespace = "PPC"; 78 let Inst{0-5} = opcode1; 79 let Inst{32-37} = opcode2; 80 let OutOperandList = OOL; 81 let InOperandList = IOL; 82 let AsmString = asmstr; 83 let Itinerary = itin; 84 85 bits<1> PPC970_First = 0; 86 bits<1> PPC970_Single = 0; 87 bits<1> PPC970_Cracked = 0; 88 bits<3> PPC970_Unit = 0; 89 90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 91 /// these must be reflected there! See comments there for what these are. 92 let TSFlags{0} = PPC970_First; 93 let TSFlags{1} = PPC970_Single; 94 let TSFlags{2} = PPC970_Cracked; 95 let TSFlags{5-3} = PPC970_Unit; 96 97 // Fields used for relation models. 98 string BaseName = ""; 99 bit Interpretation64Bit = 0; 100} 101 102// 1.7.1 I-Form 103class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 104 InstrItinClass itin, list<dag> pattern> 105 : I<opcode, OOL, IOL, asmstr, itin> { 106 let Pattern = pattern; 107 bits<24> LI; 108 109 let Inst{6-29} = LI; 110 let Inst{30} = aa; 111 let Inst{31} = lk; 112} 113 114// 1.7.2 B-Form 115class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 118 bits<3> CR; 119 bits<14> BD; 120 121 bits<5> BI; 122 let BI{0-1} = BIBO{5-6}; 123 let BI{2-4} = CR{0-2}; 124 125 let Inst{6-10} = BIBO{4-0}; 126 let Inst{11-15} = BI; 127 let Inst{16-29} = BD; 128 let Inst{30} = aa; 129 let Inst{31} = lk; 130} 131 132class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 133 string asmstr> 134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 135 let BIBO{4-0} = bo; 136 let BIBO{6-5} = 0; 137 let CR = 0; 138} 139 140class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 141 dag OOL, dag IOL, string asmstr> 142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 143 bits<14> BD; 144 145 let Inst{6-10} = bo; 146 let Inst{11-15} = bi; 147 let Inst{16-29} = BD; 148 let Inst{30} = aa; 149 let Inst{31} = lk; 150} 151 152class BForm_3<bits<6> opcode, bit aa, bit lk, 153 dag OOL, dag IOL, string asmstr> 154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 155 bits<5> BO; 156 bits<5> BI; 157 bits<14> BD; 158 159 let Inst{6-10} = BO; 160 let Inst{11-15} = BI; 161 let Inst{16-29} = BD; 162 let Inst{30} = aa; 163 let Inst{31} = lk; 164} 165 166class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, 167 dag OOL, dag IOL, string asmstr> 168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 169 bits<5> BI; 170 bits<14> BD; 171 172 let Inst{6-10} = bo; 173 let Inst{11-15} = BI; 174 let Inst{16-29} = BD; 175 let Inst{30} = aa; 176 let Inst{31} = lk; 177} 178 179// 1.7.3 SC-Form 180class SCForm<bits<6> opcode, bits<1> xo, 181 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 182 list<dag> pattern> 183 : I<opcode, OOL, IOL, asmstr, itin> { 184 bits<7> LEV; 185 186 let Pattern = pattern; 187 188 let Inst{20-26} = LEV; 189 let Inst{30} = xo; 190} 191 192// 1.7.4 D-Form 193class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 194 InstrItinClass itin, list<dag> pattern> 195 : I<opcode, OOL, IOL, asmstr, itin> { 196 bits<5> A; 197 bits<5> B; 198 bits<16> C; 199 200 let Pattern = pattern; 201 202 let Inst{6-10} = A; 203 let Inst{11-15} = B; 204 let Inst{16-31} = C; 205} 206 207class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 208 InstrItinClass itin, list<dag> pattern> 209 : I<opcode, OOL, IOL, asmstr, itin> { 210 bits<5> A; 211 bits<21> Addr; 212 213 let Pattern = pattern; 214 215 let Inst{6-10} = A; 216 let Inst{11-15} = Addr{20-16}; // Base Reg 217 let Inst{16-31} = Addr{15-0}; // Displacement 218} 219 220class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 221 InstrItinClass itin, list<dag> pattern> 222 : I<opcode, OOL, IOL, asmstr, itin> { 223 bits<5> A; 224 bits<16> C; 225 bits<5> B; 226 227 let Pattern = pattern; 228 229 let Inst{6-10} = A; 230 let Inst{11-15} = B; 231 let Inst{16-31} = C; 232} 233 234 235class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 236 InstrItinClass itin, list<dag> pattern> 237 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 238 239 // Even though ADDICo does not really have an RC bit, provide 240 // the declaration of one here so that isDOT has something to set. 241 bit RC = 0; 242} 243 244class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 245 InstrItinClass itin, list<dag> pattern> 246 : I<opcode, OOL, IOL, asmstr, itin> { 247 bits<5> A; 248 bits<16> B; 249 250 let Pattern = pattern; 251 252 let Inst{6-10} = A; 253 let Inst{11-15} = 0; 254 let Inst{16-31} = B; 255} 256 257class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 258 InstrItinClass itin, list<dag> pattern> 259 : I<opcode, OOL, IOL, asmstr, itin> { 260 bits<5> B; 261 bits<5> A; 262 bits<16> C; 263 264 let Pattern = pattern; 265 266 let Inst{6-10} = A; 267 let Inst{11-15} = B; 268 let Inst{16-31} = C; 269} 270 271class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 272 InstrItinClass itin, list<dag> pattern> 273 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 274 let A = 0; 275 let Addr = 0; 276} 277 278class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 279 string asmstr, InstrItinClass itin, 280 list<dag> pattern> 281 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 282 let A = R; 283 let B = R; 284 let C = 0; 285} 286 287class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 288 dag OOL, dag IOL, string asmstr, 289 InstrItinClass itin, list<dag> pattern> 290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 291 bits<5> A; 292 bits<21> Addr; 293 294 let Pattern = pattern; 295 bits<24> LI; 296 297 let Inst{6-29} = LI; 298 let Inst{30} = aa; 299 let Inst{31} = lk; 300 301 let Inst{38-42} = A; 302 let Inst{43-47} = Addr{20-16}; // Base Reg 303 let Inst{48-63} = Addr{15-0}; // Displacement 304} 305 306// This is used to emit BL8+NOP. 307class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 308 dag OOL, dag IOL, string asmstr, 309 InstrItinClass itin, list<dag> pattern> 310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 311 OOL, IOL, asmstr, itin, pattern> { 312 let A = 0; 313 let Addr = 0; 314} 315 316class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 317 InstrItinClass itin> 318 : I<opcode, OOL, IOL, asmstr, itin> { 319 bits<3> BF; 320 bits<1> L; 321 bits<5> RA; 322 bits<16> I; 323 324 let Inst{6-8} = BF; 325 let Inst{9} = 0; 326 let Inst{10} = L; 327 let Inst{11-15} = RA; 328 let Inst{16-31} = I; 329} 330 331class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 332 InstrItinClass itin> 333 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 334 let L = PPC64; 335} 336 337class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 338 InstrItinClass itin> 339 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 340 341class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 342 InstrItinClass itin> 343 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 344 let L = PPC64; 345} 346 347 348// 1.7.5 DS-Form 349class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 350 InstrItinClass itin, list<dag> pattern> 351 : I<opcode, OOL, IOL, asmstr, itin> { 352 bits<5> RST; 353 bits<19> DS_RA; 354 355 let Pattern = pattern; 356 357 let Inst{6-10} = RST; 358 let Inst{11-15} = DS_RA{18-14}; // Register # 359 let Inst{16-29} = DS_RA{13-0}; // Displacement. 360 let Inst{30-31} = xo; 361} 362 363 364// 1.7.6 X-Form 365class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 366 InstrItinClass itin, list<dag> pattern> 367 : I<opcode, OOL, IOL, asmstr, itin> { 368 bits<5> RST; 369 bits<5> A; 370 bits<5> B; 371 372 let Pattern = pattern; 373 374 bit RC = 0; // set by isDOT 375 376 let Inst{6-10} = RST; 377 let Inst{11-15} = A; 378 let Inst{16-20} = B; 379 let Inst{21-30} = xo; 380 let Inst{31} = RC; 381} 382 383class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr, 384 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 385 let RST = 0; 386} 387 388// This is the same as XForm_base_r3xo, but the first two operands are swapped 389// when code is emitted. 390class XForm_base_r3xo_swapped 391 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 392 InstrItinClass itin> 393 : I<opcode, OOL, IOL, asmstr, itin> { 394 bits<5> A; 395 bits<5> RST; 396 bits<5> B; 397 398 bit RC = 0; // set by isDOT 399 400 let Inst{6-10} = RST; 401 let Inst{11-15} = A; 402 let Inst{16-20} = B; 403 let Inst{21-30} = xo; 404 let Inst{31} = RC; 405} 406 407 408class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 409 InstrItinClass itin, list<dag> pattern> 410 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 411 412class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 413 InstrItinClass itin, list<dag> pattern> 414 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 415 let RST = 0; 416} 417 418class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 419 InstrItinClass itin, list<dag> pattern> 420 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 421 let A = 0; 422 let B = 0; 423} 424 425class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 426 InstrItinClass itin, list<dag> pattern> 427 : I<opcode, OOL, IOL, asmstr, itin> { 428 bits<5> RST; 429 bits<5> A; 430 bits<1> WS; 431 432 let Pattern = pattern; 433 434 let Inst{6-10} = RST; 435 let Inst{11-15} = A; 436 let Inst{20} = WS; 437 let Inst{21-30} = xo; 438 let Inst{31} = 0; 439} 440 441class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 442 InstrItinClass itin, list<dag> pattern> 443 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 444 let Pattern = pattern; 445} 446 447class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 448 InstrItinClass itin, list<dag> pattern> 449 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 450 451class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 452 InstrItinClass itin, list<dag> pattern> 453 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 454 let Pattern = pattern; 455} 456 457class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 458 InstrItinClass itin, list<dag> pattern> 459 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 460 let B = 0; 461 let Pattern = pattern; 462} 463 464class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 465 InstrItinClass itin> 466 : I<opcode, OOL, IOL, asmstr, itin> { 467 bits<3> BF; 468 bits<1> L; 469 bits<5> RA; 470 bits<5> RB; 471 472 let Inst{6-8} = BF; 473 let Inst{9} = 0; 474 let Inst{10} = L; 475 let Inst{11-15} = RA; 476 let Inst{16-20} = RB; 477 let Inst{21-30} = xo; 478 let Inst{31} = 0; 479} 480 481class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 482 InstrItinClass itin> 483 : I<opcode, OOL, IOL, asmstr, itin> { 484 bits<4> CT; 485 bits<5> RA; 486 bits<5> RB; 487 488 let Inst{6} = 0; 489 let Inst{7-10} = CT; 490 let Inst{11-15} = RA; 491 let Inst{16-20} = RB; 492 let Inst{21-30} = xo; 493 let Inst{31} = 0; 494} 495 496class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 497 InstrItinClass itin> 498 : I<opcode, OOL, IOL, asmstr, itin> { 499 bits<5> RS; 500 bits<4> SR; 501 502 let Inst{6-10} = RS; 503 let Inst{12-15} = SR; 504 let Inst{21-30} = xo; 505} 506 507class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 508 InstrItinClass itin> 509 : I<opcode, OOL, IOL, asmstr, itin> { 510 bits<5> MO; 511 512 let Inst{6-10} = MO; 513 let Inst{21-30} = xo; 514} 515 516class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 517 InstrItinClass itin> 518 : I<opcode, OOL, IOL, asmstr, itin> { 519 bits<5> RS; 520 bits<5> RB; 521 522 let Inst{6-10} = RS; 523 let Inst{16-20} = RB; 524 let Inst{21-30} = xo; 525} 526 527class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 528 InstrItinClass itin> 529 : I<opcode, OOL, IOL, asmstr, itin> { 530 bits<5> RS; 531 bits<1> L; 532 533 let Inst{6-10} = RS; 534 let Inst{15} = L; 535 let Inst{21-30} = xo; 536} 537 538class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 539 InstrItinClass itin> 540 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 541 let L = PPC64; 542} 543 544class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 545 InstrItinClass itin> 546 : I<opcode, OOL, IOL, asmstr, itin> { 547 bits<3> BF; 548 bits<5> FRA; 549 bits<5> FRB; 550 551 let Inst{6-8} = BF; 552 let Inst{9-10} = 0; 553 let Inst{11-15} = FRA; 554 let Inst{16-20} = FRB; 555 let Inst{21-30} = xo; 556 let Inst{31} = 0; 557} 558 559class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 560 InstrItinClass itin, list<dag> pattern> 561 : I<opcode, OOL, IOL, asmstr, itin> { 562 let Pattern = pattern; 563 let Inst{6-10} = 31; 564 let Inst{11-15} = 0; 565 let Inst{16-20} = 0; 566 let Inst{21-30} = xo; 567 let Inst{31} = 0; 568} 569 570class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 571 string asmstr, InstrItinClass itin, list<dag> pattern> 572 : I<opcode, OOL, IOL, asmstr, itin> { 573 bits<2> L; 574 575 let Pattern = pattern; 576 let Inst{6-8} = 0; 577 let Inst{9-10} = L; 578 let Inst{11-15} = 0; 579 let Inst{16-20} = 0; 580 let Inst{21-30} = xo; 581 let Inst{31} = 0; 582} 583 584class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 585 string asmstr, InstrItinClass itin, list<dag> pattern> 586 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 587 let L = 0; 588} 589 590class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 591 InstrItinClass itin, list<dag> pattern> 592 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 593} 594 595class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 596 InstrItinClass itin, list<dag> pattern> 597 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 598 let A = 0; 599} 600 601class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 602 InstrItinClass itin, list<dag> pattern> 603 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 604} 605 606// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 607// numbers presumably relates to some document, but I haven't found it. 608class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 609 InstrItinClass itin, list<dag> pattern> 610 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 611 let Pattern = pattern; 612 613 bit RC = 0; // set by isDOT 614 615 let Inst{6-10} = RST; 616 let Inst{11-20} = 0; 617 let Inst{21-30} = xo; 618 let Inst{31} = RC; 619} 620class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 621 InstrItinClass itin, list<dag> pattern> 622 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 623 let Pattern = pattern; 624 bits<5> FM; 625 626 bit RC = 0; // set by isDOT 627 628 let Inst{6-10} = FM; 629 let Inst{11-20} = 0; 630 let Inst{21-30} = xo; 631 let Inst{31} = RC; 632} 633 634class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 635 InstrItinClass itin, list<dag> pattern> 636 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 637 let RST = 0; 638 let A = 0; 639 let B = 0; 640} 641 642class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 643 InstrItinClass itin, list<dag> pattern> 644 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 645 let RST = 0; 646 let A = 0; 647} 648 649// XX*-Form (VSX) 650class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 651 InstrItinClass itin, list<dag> pattern> 652 : I<opcode, OOL, IOL, asmstr, itin> { 653 bits<6> XT; 654 bits<5> A; 655 bits<5> B; 656 657 let Pattern = pattern; 658 659 let Inst{6-10} = XT{4-0}; 660 let Inst{11-15} = A; 661 let Inst{16-20} = B; 662 let Inst{21-30} = xo; 663 let Inst{31} = XT{5}; 664} 665 666class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 667 InstrItinClass itin, list<dag> pattern> 668 : I<opcode, OOL, IOL, asmstr, itin> { 669 bits<6> XT; 670 bits<6> XB; 671 672 let Pattern = pattern; 673 674 let Inst{6-10} = XT{4-0}; 675 let Inst{11-15} = 0; 676 let Inst{16-20} = XB{4-0}; 677 let Inst{21-29} = xo; 678 let Inst{30} = XB{5}; 679 let Inst{31} = XT{5}; 680} 681 682class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 683 InstrItinClass itin, list<dag> pattern> 684 : I<opcode, OOL, IOL, asmstr, itin> { 685 bits<3> CR; 686 bits<6> XB; 687 688 let Pattern = pattern; 689 690 let Inst{6-8} = CR; 691 let Inst{9-15} = 0; 692 let Inst{16-20} = XB{4-0}; 693 let Inst{21-29} = xo; 694 let Inst{30} = XB{5}; 695 let Inst{31} = 0; 696} 697 698class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 699 InstrItinClass itin, list<dag> pattern> 700 : I<opcode, OOL, IOL, asmstr, itin> { 701 bits<6> XT; 702 bits<6> XB; 703 bits<2> D; 704 705 let Pattern = pattern; 706 707 let Inst{6-10} = XT{4-0}; 708 let Inst{11-13} = 0; 709 let Inst{14-15} = D; 710 let Inst{16-20} = XB{4-0}; 711 let Inst{21-29} = xo; 712 let Inst{30} = XB{5}; 713 let Inst{31} = XT{5}; 714} 715 716class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 717 InstrItinClass itin, list<dag> pattern> 718 : I<opcode, OOL, IOL, asmstr, itin> { 719 bits<6> XT; 720 bits<6> XA; 721 bits<6> XB; 722 723 let Pattern = pattern; 724 725 let Inst{6-10} = XT{4-0}; 726 let Inst{11-15} = XA{4-0}; 727 let Inst{16-20} = XB{4-0}; 728 let Inst{21-28} = xo; 729 let Inst{29} = XA{5}; 730 let Inst{30} = XB{5}; 731 let Inst{31} = XT{5}; 732} 733 734class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 735 InstrItinClass itin, list<dag> pattern> 736 : I<opcode, OOL, IOL, asmstr, itin> { 737 bits<3> CR; 738 bits<6> XA; 739 bits<6> XB; 740 741 let Pattern = pattern; 742 743 let Inst{6-8} = CR; 744 let Inst{9-10} = 0; 745 let Inst{11-15} = XA{4-0}; 746 let Inst{16-20} = XB{4-0}; 747 let Inst{21-28} = xo; 748 let Inst{29} = XA{5}; 749 let Inst{30} = XB{5}; 750 let Inst{31} = 0; 751} 752 753class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 754 InstrItinClass itin, list<dag> pattern> 755 : I<opcode, OOL, IOL, asmstr, itin> { 756 bits<6> XT; 757 bits<6> XA; 758 bits<6> XB; 759 bits<2> D; 760 761 let Pattern = pattern; 762 763 let Inst{6-10} = XT{4-0}; 764 let Inst{11-15} = XA{4-0}; 765 let Inst{16-20} = XB{4-0}; 766 let Inst{21} = 0; 767 let Inst{22-23} = D; 768 let Inst{24-28} = xo; 769 let Inst{29} = XA{5}; 770 let Inst{30} = XB{5}; 771 let Inst{31} = XT{5}; 772} 773 774class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr, 775 InstrItinClass itin, list<dag> pattern> 776 : I<opcode, OOL, IOL, asmstr, itin> { 777 bits<6> XT; 778 bits<6> XA; 779 bits<6> XB; 780 781 let Pattern = pattern; 782 783 bit RC = 0; // set by isDOT 784 785 let Inst{6-10} = XT{4-0}; 786 let Inst{11-15} = XA{4-0}; 787 let Inst{16-20} = XB{4-0}; 788 let Inst{21} = RC; 789 let Inst{22-28} = xo; 790 let Inst{29} = XA{5}; 791 let Inst{30} = XB{5}; 792 let Inst{31} = XT{5}; 793} 794 795class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 796 InstrItinClass itin, list<dag> pattern> 797 : I<opcode, OOL, IOL, asmstr, itin> { 798 bits<6> XT; 799 bits<6> XA; 800 bits<6> XB; 801 bits<6> XC; 802 803 let Pattern = pattern; 804 805 let Inst{6-10} = XT{4-0}; 806 let Inst{11-15} = XA{4-0}; 807 let Inst{16-20} = XB{4-0}; 808 let Inst{21-25} = XC{4-0}; 809 let Inst{26-27} = xo; 810 let Inst{28} = XC{5}; 811 let Inst{29} = XA{5}; 812 let Inst{30} = XB{5}; 813 let Inst{31} = XT{5}; 814} 815 816// DCB_Form - Form X instruction, used for dcb* instructions. 817class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 818 InstrItinClass itin, list<dag> pattern> 819 : I<31, OOL, IOL, asmstr, itin> { 820 bits<5> A; 821 bits<5> B; 822 823 let Pattern = pattern; 824 825 let Inst{6-10} = immfield; 826 let Inst{11-15} = A; 827 let Inst{16-20} = B; 828 let Inst{21-30} = xo; 829 let Inst{31} = 0; 830} 831 832 833// DSS_Form - Form X instruction, used for altivec dss* instructions. 834class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr, 835 InstrItinClass itin, list<dag> pattern> 836 : I<31, OOL, IOL, asmstr, itin> { 837 bits<2> STRM; 838 bits<5> A; 839 bits<5> B; 840 841 let Pattern = pattern; 842 843 let Inst{6} = T; 844 let Inst{7-8} = 0; 845 let Inst{9-10} = STRM; 846 let Inst{11-15} = A; 847 let Inst{16-20} = B; 848 let Inst{21-30} = xo; 849 let Inst{31} = 0; 850} 851 852// 1.7.7 XL-Form 853class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 854 InstrItinClass itin, list<dag> pattern> 855 : I<opcode, OOL, IOL, asmstr, itin> { 856 bits<5> CRD; 857 bits<5> CRA; 858 bits<5> CRB; 859 860 let Pattern = pattern; 861 862 let Inst{6-10} = CRD; 863 let Inst{11-15} = CRA; 864 let Inst{16-20} = CRB; 865 let Inst{21-30} = xo; 866 let Inst{31} = 0; 867} 868 869class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 870 InstrItinClass itin, list<dag> pattern> 871 : I<opcode, OOL, IOL, asmstr, itin> { 872 bits<5> CRD; 873 874 let Pattern = pattern; 875 876 let Inst{6-10} = CRD; 877 let Inst{11-15} = CRD; 878 let Inst{16-20} = CRD; 879 let Inst{21-30} = xo; 880 let Inst{31} = 0; 881} 882 883class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 884 InstrItinClass itin, list<dag> pattern> 885 : I<opcode, OOL, IOL, asmstr, itin> { 886 bits<5> BO; 887 bits<5> BI; 888 bits<2> BH; 889 890 let Pattern = pattern; 891 892 let Inst{6-10} = BO; 893 let Inst{11-15} = BI; 894 let Inst{16-18} = 0; 895 let Inst{19-20} = BH; 896 let Inst{21-30} = xo; 897 let Inst{31} = lk; 898} 899 900class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 901 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 902 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 903 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 904 bits<3> CR; 905 906 let BO = BIBO{4-0}; 907 let BI{0-1} = BIBO{5-6}; 908 let BI{2-4} = CR{0-2}; 909 let BH = 0; 910} 911 912class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk, 913 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 914 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 915 let BO = bo; 916 let BH = 0; 917} 918 919class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 920 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 921 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 922 let BO = bo; 923 let BI = bi; 924 let BH = 0; 925} 926 927class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 928 InstrItinClass itin> 929 : I<opcode, OOL, IOL, asmstr, itin> { 930 bits<3> BF; 931 bits<3> BFA; 932 933 let Inst{6-8} = BF; 934 let Inst{9-10} = 0; 935 let Inst{11-13} = BFA; 936 let Inst{14-15} = 0; 937 let Inst{16-20} = 0; 938 let Inst{21-30} = xo; 939 let Inst{31} = 0; 940} 941 942// 1.7.8 XFX-Form 943class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 944 InstrItinClass itin> 945 : I<opcode, OOL, IOL, asmstr, itin> { 946 bits<5> RT; 947 bits<10> SPR; 948 949 let Inst{6-10} = RT; 950 let Inst{11} = SPR{4}; 951 let Inst{12} = SPR{3}; 952 let Inst{13} = SPR{2}; 953 let Inst{14} = SPR{1}; 954 let Inst{15} = SPR{0}; 955 let Inst{16} = SPR{9}; 956 let Inst{17} = SPR{8}; 957 let Inst{18} = SPR{7}; 958 let Inst{19} = SPR{6}; 959 let Inst{20} = SPR{5}; 960 let Inst{21-30} = xo; 961 let Inst{31} = 0; 962} 963 964class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 965 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 966 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 967 let SPR = spr; 968} 969 970class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 971 InstrItinClass itin> 972 : I<opcode, OOL, IOL, asmstr, itin> { 973 bits<5> RT; 974 975 let Inst{6-10} = RT; 976 let Inst{11-20} = 0; 977 let Inst{21-30} = xo; 978 let Inst{31} = 0; 979} 980 981class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 982 InstrItinClass itin> 983 : I<opcode, OOL, IOL, asmstr, itin> { 984 bits<8> FXM; 985 bits<5> rS; 986 987 let Inst{6-10} = rS; 988 let Inst{11} = 0; 989 let Inst{12-19} = FXM; 990 let Inst{20} = 0; 991 let Inst{21-30} = xo; 992 let Inst{31} = 0; 993} 994 995class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 996 InstrItinClass itin> 997 : I<opcode, OOL, IOL, asmstr, itin> { 998 bits<5> ST; 999 bits<8> FXM; 1000 1001 let Inst{6-10} = ST; 1002 let Inst{11} = 1; 1003 let Inst{12-19} = FXM; 1004 let Inst{20} = 0; 1005 let Inst{21-30} = xo; 1006 let Inst{31} = 0; 1007} 1008 1009class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1010 InstrItinClass itin> 1011 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 1012 1013class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1014 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1015 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 1016 let SPR = spr; 1017} 1018 1019// XFL-Form - MTFSF 1020// This is probably 1.7.9, but I don't have the reference that uses this 1021// numbering scheme... 1022class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1023 InstrItinClass itin, list<dag>pattern> 1024 : I<opcode, OOL, IOL, asmstr, itin> { 1025 bits<8> FM; 1026 bits<5> rT; 1027 1028 bit RC = 0; // set by isDOT 1029 let Pattern = pattern; 1030 1031 let Inst{6} = 0; 1032 let Inst{7-14} = FM; 1033 let Inst{15} = 0; 1034 let Inst{16-20} = rT; 1035 let Inst{21-30} = xo; 1036 let Inst{31} = RC; 1037} 1038 1039// 1.7.10 XS-Form - SRADI. 1040class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1041 InstrItinClass itin, list<dag> pattern> 1042 : I<opcode, OOL, IOL, asmstr, itin> { 1043 bits<5> A; 1044 bits<5> RS; 1045 bits<6> SH; 1046 1047 bit RC = 0; // set by isDOT 1048 let Pattern = pattern; 1049 1050 let Inst{6-10} = RS; 1051 let Inst{11-15} = A; 1052 let Inst{16-20} = SH{4,3,2,1,0}; 1053 let Inst{21-29} = xo; 1054 let Inst{30} = SH{5}; 1055 let Inst{31} = RC; 1056} 1057 1058// 1.7.11 XO-Form 1059class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 1060 InstrItinClass itin, list<dag> pattern> 1061 : I<opcode, OOL, IOL, asmstr, itin> { 1062 bits<5> RT; 1063 bits<5> RA; 1064 bits<5> RB; 1065 1066 let Pattern = pattern; 1067 1068 bit RC = 0; // set by isDOT 1069 1070 let Inst{6-10} = RT; 1071 let Inst{11-15} = RA; 1072 let Inst{16-20} = RB; 1073 let Inst{21} = oe; 1074 let Inst{22-30} = xo; 1075 let Inst{31} = RC; 1076} 1077 1078class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 1079 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1080 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 1081 let RB = 0; 1082} 1083 1084// 1.7.12 A-Form 1085class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1086 InstrItinClass itin, list<dag> pattern> 1087 : I<opcode, OOL, IOL, asmstr, itin> { 1088 bits<5> FRT; 1089 bits<5> FRA; 1090 bits<5> FRC; 1091 bits<5> FRB; 1092 1093 let Pattern = pattern; 1094 1095 bit RC = 0; // set by isDOT 1096 1097 let Inst{6-10} = FRT; 1098 let Inst{11-15} = FRA; 1099 let Inst{16-20} = FRB; 1100 let Inst{21-25} = FRC; 1101 let Inst{26-30} = xo; 1102 let Inst{31} = RC; 1103} 1104 1105class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1106 InstrItinClass itin, list<dag> pattern> 1107 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1108 let FRC = 0; 1109} 1110 1111class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1112 InstrItinClass itin, list<dag> pattern> 1113 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1114 let FRB = 0; 1115} 1116 1117class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1118 InstrItinClass itin, list<dag> pattern> 1119 : I<opcode, OOL, IOL, asmstr, itin> { 1120 bits<5> RT; 1121 bits<5> RA; 1122 bits<5> RB; 1123 bits<5> COND; 1124 1125 let Pattern = pattern; 1126 1127 let Inst{6-10} = RT; 1128 let Inst{11-15} = RA; 1129 let Inst{16-20} = RB; 1130 let Inst{21-25} = COND; 1131 let Inst{26-30} = xo; 1132 let Inst{31} = 0; 1133} 1134 1135// 1.7.13 M-Form 1136class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1137 InstrItinClass itin, list<dag> pattern> 1138 : I<opcode, OOL, IOL, asmstr, itin> { 1139 bits<5> RA; 1140 bits<5> RS; 1141 bits<5> RB; 1142 bits<5> MB; 1143 bits<5> ME; 1144 1145 let Pattern = pattern; 1146 1147 bit RC = 0; // set by isDOT 1148 1149 let Inst{6-10} = RS; 1150 let Inst{11-15} = RA; 1151 let Inst{16-20} = RB; 1152 let Inst{21-25} = MB; 1153 let Inst{26-30} = ME; 1154 let Inst{31} = RC; 1155} 1156 1157class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1158 InstrItinClass itin, list<dag> pattern> 1159 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 1160} 1161 1162// 1.7.14 MD-Form 1163class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 1164 InstrItinClass itin, list<dag> pattern> 1165 : I<opcode, OOL, IOL, asmstr, itin> { 1166 bits<5> RA; 1167 bits<5> RS; 1168 bits<6> SH; 1169 bits<6> MBE; 1170 1171 let Pattern = pattern; 1172 1173 bit RC = 0; // set by isDOT 1174 1175 let Inst{6-10} = RS; 1176 let Inst{11-15} = RA; 1177 let Inst{16-20} = SH{4,3,2,1,0}; 1178 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1179 let Inst{27-29} = xo; 1180 let Inst{30} = SH{5}; 1181 let Inst{31} = RC; 1182} 1183 1184class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 1185 InstrItinClass itin, list<dag> pattern> 1186 : I<opcode, OOL, IOL, asmstr, itin> { 1187 bits<5> RA; 1188 bits<5> RS; 1189 bits<5> RB; 1190 bits<6> MBE; 1191 1192 let Pattern = pattern; 1193 1194 bit RC = 0; // set by isDOT 1195 1196 let Inst{6-10} = RS; 1197 let Inst{11-15} = RA; 1198 let Inst{16-20} = RB; 1199 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1200 let Inst{27-30} = xo; 1201 let Inst{31} = RC; 1202} 1203 1204 1205// E-1 VA-Form 1206 1207// VAForm_1 - DACB ordering. 1208class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 1209 InstrItinClass itin, list<dag> pattern> 1210 : I<4, OOL, IOL, asmstr, itin> { 1211 bits<5> VD; 1212 bits<5> VA; 1213 bits<5> VC; 1214 bits<5> VB; 1215 1216 let Pattern = pattern; 1217 1218 let Inst{6-10} = VD; 1219 let Inst{11-15} = VA; 1220 let Inst{16-20} = VB; 1221 let Inst{21-25} = VC; 1222 let Inst{26-31} = xo; 1223} 1224 1225// VAForm_1a - DABC ordering. 1226class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 1227 InstrItinClass itin, list<dag> pattern> 1228 : I<4, OOL, IOL, asmstr, itin> { 1229 bits<5> VD; 1230 bits<5> VA; 1231 bits<5> VB; 1232 bits<5> VC; 1233 1234 let Pattern = pattern; 1235 1236 let Inst{6-10} = VD; 1237 let Inst{11-15} = VA; 1238 let Inst{16-20} = VB; 1239 let Inst{21-25} = VC; 1240 let Inst{26-31} = xo; 1241} 1242 1243class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 1244 InstrItinClass itin, list<dag> pattern> 1245 : I<4, OOL, IOL, asmstr, itin> { 1246 bits<5> VD; 1247 bits<5> VA; 1248 bits<5> VB; 1249 bits<4> SH; 1250 1251 let Pattern = pattern; 1252 1253 let Inst{6-10} = VD; 1254 let Inst{11-15} = VA; 1255 let Inst{16-20} = VB; 1256 let Inst{21} = 0; 1257 let Inst{22-25} = SH; 1258 let Inst{26-31} = xo; 1259} 1260 1261// E-2 VX-Form 1262class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 1263 InstrItinClass itin, list<dag> pattern> 1264 : I<4, OOL, IOL, asmstr, itin> { 1265 bits<5> VD; 1266 bits<5> VA; 1267 bits<5> VB; 1268 1269 let Pattern = pattern; 1270 1271 let Inst{6-10} = VD; 1272 let Inst{11-15} = VA; 1273 let Inst{16-20} = VB; 1274 let Inst{21-31} = xo; 1275} 1276 1277class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 1278 InstrItinClass itin, list<dag> pattern> 1279 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 1280 let VA = VD; 1281 let VB = VD; 1282} 1283 1284 1285class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 1286 InstrItinClass itin, list<dag> pattern> 1287 : I<4, OOL, IOL, asmstr, itin> { 1288 bits<5> VD; 1289 bits<5> VB; 1290 1291 let Pattern = pattern; 1292 1293 let Inst{6-10} = VD; 1294 let Inst{11-15} = 0; 1295 let Inst{16-20} = VB; 1296 let Inst{21-31} = xo; 1297} 1298 1299class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 1300 InstrItinClass itin, list<dag> pattern> 1301 : I<4, OOL, IOL, asmstr, itin> { 1302 bits<5> VD; 1303 bits<5> IMM; 1304 1305 let Pattern = pattern; 1306 1307 let Inst{6-10} = VD; 1308 let Inst{11-15} = IMM; 1309 let Inst{16-20} = 0; 1310 let Inst{21-31} = xo; 1311} 1312 1313/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 1314class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 1315 InstrItinClass itin, list<dag> pattern> 1316 : I<4, OOL, IOL, asmstr, itin> { 1317 bits<5> VD; 1318 1319 let Pattern = pattern; 1320 1321 let Inst{6-10} = VD; 1322 let Inst{11-15} = 0; 1323 let Inst{16-20} = 0; 1324 let Inst{21-31} = xo; 1325} 1326 1327/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 1328class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 1329 InstrItinClass itin, list<dag> pattern> 1330 : I<4, OOL, IOL, asmstr, itin> { 1331 bits<5> VB; 1332 1333 let Pattern = pattern; 1334 1335 let Inst{6-10} = 0; 1336 let Inst{11-15} = 0; 1337 let Inst{16-20} = VB; 1338 let Inst{21-31} = xo; 1339} 1340 1341// E-4 VXR-Form 1342class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 1343 InstrItinClass itin, list<dag> pattern> 1344 : I<4, OOL, IOL, asmstr, itin> { 1345 bits<5> VD; 1346 bits<5> VA; 1347 bits<5> VB; 1348 bit RC = 0; 1349 1350 let Pattern = pattern; 1351 1352 let Inst{6-10} = VD; 1353 let Inst{11-15} = VA; 1354 let Inst{16-20} = VB; 1355 let Inst{21} = RC; 1356 let Inst{22-31} = xo; 1357} 1358 1359//===----------------------------------------------------------------------===// 1360class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 1361 : I<0, OOL, IOL, asmstr, NoItinerary> { 1362 let isCodeGenOnly = 1; 1363 let PPC64 = 0; 1364 let Pattern = pattern; 1365 let Inst{31-0} = 0; 1366} 1367