1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// PowerPC instruction formats 13 14class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 15 : Instruction { 16 field bits<32> Inst; 17 field bits<32> SoftFail = 0; 18 let Size = 4; 19 20 bit PPC64 = 0; // Default value, override with isPPC64 21 22 let Namespace = "PPC"; 23 let Inst{0-5} = opcode; 24 let OutOperandList = OOL; 25 let InOperandList = IOL; 26 let AsmString = asmstr; 27 let Itinerary = itin; 28 29 bits<1> PPC970_First = 0; 30 bits<1> PPC970_Single = 0; 31 bits<1> PPC970_Cracked = 0; 32 bits<3> PPC970_Unit = 0; 33 34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 35 /// these must be reflected there! See comments there for what these are. 36 let TSFlags{0} = PPC970_First; 37 let TSFlags{1} = PPC970_Single; 38 let TSFlags{2} = PPC970_Cracked; 39 let TSFlags{5-3} = PPC970_Unit; 40 41 // Fields used for relation models. 42 string BaseName = ""; 43 44 // For cases where multiple instruction definitions really represent the 45 // same underlying instruction but with one definition for 64-bit arguments 46 // and one for 32-bit arguments, this bit breaks the degeneracy between 47 // the two forms and allows TableGen to generate mapping tables. 48 bit Interpretation64Bit = 0; 49} 50 51class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 52class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 53class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 54class PPC970_MicroCode; 55 56class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 57class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 58class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 59class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 60class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 61class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 62class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 63class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 64 65// Two joined instructions; used to emit two adjacent instructions as one. 66// The itinerary from the first instruction is used for scheduling and 67// classification. 68class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 69 InstrItinClass itin> 70 : Instruction { 71 field bits<64> Inst; 72 field bits<64> SoftFail = 0; 73 let Size = 8; 74 75 bit PPC64 = 0; // Default value, override with isPPC64 76 77 let Namespace = "PPC"; 78 let Inst{0-5} = opcode1; 79 let Inst{32-37} = opcode2; 80 let OutOperandList = OOL; 81 let InOperandList = IOL; 82 let AsmString = asmstr; 83 let Itinerary = itin; 84 85 bits<1> PPC970_First = 0; 86 bits<1> PPC970_Single = 0; 87 bits<1> PPC970_Cracked = 0; 88 bits<3> PPC970_Unit = 0; 89 90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 91 /// these must be reflected there! See comments there for what these are. 92 let TSFlags{0} = PPC970_First; 93 let TSFlags{1} = PPC970_Single; 94 let TSFlags{2} = PPC970_Cracked; 95 let TSFlags{5-3} = PPC970_Unit; 96 97 // Fields used for relation models. 98 string BaseName = ""; 99 bit Interpretation64Bit = 0; 100} 101 102// 1.7.1 I-Form 103class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 104 InstrItinClass itin, list<dag> pattern> 105 : I<opcode, OOL, IOL, asmstr, itin> { 106 let Pattern = pattern; 107 bits<24> LI; 108 109 let Inst{6-29} = LI; 110 let Inst{30} = aa; 111 let Inst{31} = lk; 112} 113 114// 1.7.2 B-Form 115class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 118 bits<3> CR; 119 bits<14> BD; 120 121 bits<5> BI; 122 let BI{0-1} = BIBO{5-6}; 123 let BI{2-4} = CR{0-2}; 124 125 let Inst{6-10} = BIBO{4-0}; 126 let Inst{11-15} = BI; 127 let Inst{16-29} = BD; 128 let Inst{30} = aa; 129 let Inst{31} = lk; 130} 131 132class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 133 string asmstr> 134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 135 let BIBO{4-0} = bo; 136 let BIBO{6-5} = 0; 137 let CR = 0; 138} 139 140class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 141 dag OOL, dag IOL, string asmstr> 142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 143 bits<14> BD; 144 145 let Inst{6-10} = bo; 146 let Inst{11-15} = bi; 147 let Inst{16-29} = BD; 148 let Inst{30} = aa; 149 let Inst{31} = lk; 150} 151 152class BForm_3<bits<6> opcode, bit aa, bit lk, 153 dag OOL, dag IOL, string asmstr> 154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 155 bits<5> BO; 156 bits<5> BI; 157 bits<14> BD; 158 159 let Inst{6-10} = BO; 160 let Inst{11-15} = BI; 161 let Inst{16-29} = BD; 162 let Inst{30} = aa; 163 let Inst{31} = lk; 164} 165 166// 1.7.3 SC-Form 167class SCForm<bits<6> opcode, bits<1> xo, 168 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 169 list<dag> pattern> 170 : I<opcode, OOL, IOL, asmstr, itin> { 171 bits<7> LEV; 172 173 let Pattern = pattern; 174 175 let Inst{20-26} = LEV; 176 let Inst{30} = xo; 177} 178 179// 1.7.4 D-Form 180class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 181 InstrItinClass itin, list<dag> pattern> 182 : I<opcode, OOL, IOL, asmstr, itin> { 183 bits<5> A; 184 bits<5> B; 185 bits<16> C; 186 187 let Pattern = pattern; 188 189 let Inst{6-10} = A; 190 let Inst{11-15} = B; 191 let Inst{16-31} = C; 192} 193 194class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 195 InstrItinClass itin, list<dag> pattern> 196 : I<opcode, OOL, IOL, asmstr, itin> { 197 bits<5> A; 198 bits<21> Addr; 199 200 let Pattern = pattern; 201 202 let Inst{6-10} = A; 203 let Inst{11-15} = Addr{20-16}; // Base Reg 204 let Inst{16-31} = Addr{15-0}; // Displacement 205} 206 207class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 208 InstrItinClass itin, list<dag> pattern> 209 : I<opcode, OOL, IOL, asmstr, itin> { 210 bits<5> A; 211 bits<16> C; 212 bits<5> B; 213 214 let Pattern = pattern; 215 216 let Inst{6-10} = A; 217 let Inst{11-15} = B; 218 let Inst{16-31} = C; 219} 220 221 222class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 223 InstrItinClass itin, list<dag> pattern> 224 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 225 226 // Even though ADDICo does not really have an RC bit, provide 227 // the declaration of one here so that isDOT has something to set. 228 bit RC = 0; 229} 230 231class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 232 InstrItinClass itin, list<dag> pattern> 233 : I<opcode, OOL, IOL, asmstr, itin> { 234 bits<5> A; 235 bits<16> B; 236 237 let Pattern = pattern; 238 239 let Inst{6-10} = A; 240 let Inst{11-15} = 0; 241 let Inst{16-31} = B; 242} 243 244class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 245 InstrItinClass itin, list<dag> pattern> 246 : I<opcode, OOL, IOL, asmstr, itin> { 247 bits<5> B; 248 bits<5> A; 249 bits<16> C; 250 251 let Pattern = pattern; 252 253 let Inst{6-10} = A; 254 let Inst{11-15} = B; 255 let Inst{16-31} = C; 256} 257 258class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 259 InstrItinClass itin, list<dag> pattern> 260 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 261 let A = 0; 262 let Addr = 0; 263} 264 265class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 266 string asmstr, InstrItinClass itin, 267 list<dag> pattern> 268 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 269 let A = R; 270 let B = R; 271 let C = 0; 272} 273 274class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 275 dag OOL, dag IOL, string asmstr, 276 InstrItinClass itin, list<dag> pattern> 277 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 278 bits<5> A; 279 bits<21> Addr; 280 281 let Pattern = pattern; 282 bits<24> LI; 283 284 let Inst{6-29} = LI; 285 let Inst{30} = aa; 286 let Inst{31} = lk; 287 288 let Inst{38-42} = A; 289 let Inst{43-47} = Addr{20-16}; // Base Reg 290 let Inst{48-63} = Addr{15-0}; // Displacement 291} 292 293// This is used to emit BL8+NOP. 294class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 295 dag OOL, dag IOL, string asmstr, 296 InstrItinClass itin, list<dag> pattern> 297 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 298 OOL, IOL, asmstr, itin, pattern> { 299 let A = 0; 300 let Addr = 0; 301} 302 303class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 304 InstrItinClass itin> 305 : I<opcode, OOL, IOL, asmstr, itin> { 306 bits<3> BF; 307 bits<1> L; 308 bits<5> RA; 309 bits<16> I; 310 311 let Inst{6-8} = BF; 312 let Inst{9} = 0; 313 let Inst{10} = L; 314 let Inst{11-15} = RA; 315 let Inst{16-31} = I; 316} 317 318class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 319 InstrItinClass itin> 320 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 321 let L = PPC64; 322} 323 324class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 325 InstrItinClass itin> 326 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 327 328class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 329 InstrItinClass itin> 330 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 331 let L = PPC64; 332} 333 334 335// 1.7.5 DS-Form 336class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 337 InstrItinClass itin, list<dag> pattern> 338 : I<opcode, OOL, IOL, asmstr, itin> { 339 bits<5> RST; 340 bits<19> DS_RA; 341 342 let Pattern = pattern; 343 344 let Inst{6-10} = RST; 345 let Inst{11-15} = DS_RA{18-14}; // Register # 346 let Inst{16-29} = DS_RA{13-0}; // Displacement. 347 let Inst{30-31} = xo; 348} 349 350class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 351 InstrItinClass itin, list<dag> pattern> 352 : I<opcode, OOL, IOL, asmstr, itin> { 353 bits<5> RST; 354 bits<14> DS; 355 bits<5> RA; 356 357 let Pattern = pattern; 358 359 let Inst{6-10} = RST; 360 let Inst{11-15} = RA; 361 let Inst{16-29} = DS; 362 let Inst{30-31} = xo; 363} 364 365// 1.7.6 X-Form 366class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 367 InstrItinClass itin, list<dag> pattern> 368 : I<opcode, OOL, IOL, asmstr, itin> { 369 bits<5> RST; 370 bits<5> A; 371 bits<5> B; 372 373 let Pattern = pattern; 374 375 bit RC = 0; // set by isDOT 376 377 let Inst{6-10} = RST; 378 let Inst{11-15} = A; 379 let Inst{16-20} = B; 380 let Inst{21-30} = xo; 381 let Inst{31} = RC; 382} 383 384// This is the same as XForm_base_r3xo, but the first two operands are swapped 385// when code is emitted. 386class XForm_base_r3xo_swapped 387 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 388 InstrItinClass itin> 389 : I<opcode, OOL, IOL, asmstr, itin> { 390 bits<5> A; 391 bits<5> RST; 392 bits<5> B; 393 394 bit RC = 0; // set by isDOT 395 396 let Inst{6-10} = RST; 397 let Inst{11-15} = A; 398 let Inst{16-20} = B; 399 let Inst{21-30} = xo; 400 let Inst{31} = RC; 401} 402 403 404class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 405 InstrItinClass itin, list<dag> pattern> 406 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 407 408class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 409 InstrItinClass itin, list<dag> pattern> 410 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 411 let RST = 0; 412} 413 414class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 415 InstrItinClass itin, list<dag> pattern> 416 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 417 let A = 0; 418 let B = 0; 419} 420 421class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 422 InstrItinClass itin, list<dag> pattern> 423 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 424 let Pattern = pattern; 425} 426 427class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 428 InstrItinClass itin, list<dag> pattern> 429 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 430 431class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 432 InstrItinClass itin, list<dag> pattern> 433 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 434 let Pattern = pattern; 435} 436 437class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 438 InstrItinClass itin, list<dag> pattern> 439 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 440 let B = 0; 441 let Pattern = pattern; 442} 443 444class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 445 InstrItinClass itin> 446 : I<opcode, OOL, IOL, asmstr, itin> { 447 bits<3> BF; 448 bits<1> L; 449 bits<5> RA; 450 bits<5> RB; 451 452 let Inst{6-8} = BF; 453 let Inst{9} = 0; 454 let Inst{10} = L; 455 let Inst{11-15} = RA; 456 let Inst{16-20} = RB; 457 let Inst{21-30} = xo; 458 let Inst{31} = 0; 459} 460 461class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 462 InstrItinClass itin> 463 : I<opcode, OOL, IOL, asmstr, itin> { 464 bits<5> RS; 465 bits<1> L; 466 467 let Inst{6-10} = RS; 468 let Inst{15} = L; 469 let Inst{21-30} = xo; 470} 471 472class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 473 InstrItinClass itin> 474 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 475 let L = PPC64; 476} 477 478class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 479 InstrItinClass itin> 480 : I<opcode, OOL, IOL, asmstr, itin> { 481 bits<3> BF; 482 bits<5> FRA; 483 bits<5> FRB; 484 485 let Inst{6-8} = BF; 486 let Inst{9-10} = 0; 487 let Inst{11-15} = FRA; 488 let Inst{16-20} = FRB; 489 let Inst{21-30} = xo; 490 let Inst{31} = 0; 491} 492 493class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 494 InstrItinClass itin, list<dag> pattern> 495 : I<opcode, OOL, IOL, asmstr, itin> { 496 let Pattern = pattern; 497 let Inst{6-10} = 31; 498 let Inst{11-15} = 0; 499 let Inst{16-20} = 0; 500 let Inst{21-30} = xo; 501 let Inst{31} = 0; 502} 503 504class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 505 string asmstr, InstrItinClass itin, list<dag> pattern> 506 : I<opcode, OOL, IOL, asmstr, itin> { 507 bits<2> L; 508 509 let Pattern = pattern; 510 let Inst{6-8} = 0; 511 let Inst{9-10} = L; 512 let Inst{11-15} = 0; 513 let Inst{16-20} = 0; 514 let Inst{21-30} = xo; 515 let Inst{31} = 0; 516} 517 518class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 519 string asmstr, InstrItinClass itin, list<dag> pattern> 520 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 521 let L = 0; 522} 523 524class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 525 InstrItinClass itin, list<dag> pattern> 526 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 527} 528 529class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 530 InstrItinClass itin, list<dag> pattern> 531 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 532 let A = 0; 533} 534 535class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 536 InstrItinClass itin, list<dag> pattern> 537 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 538} 539 540// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 541// numbers presumably relates to some document, but I haven't found it. 542class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 543 InstrItinClass itin, list<dag> pattern> 544 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 545 let Pattern = pattern; 546 547 bit RC = 0; // set by isDOT 548 549 let Inst{6-10} = RST; 550 let Inst{11-20} = 0; 551 let Inst{21-30} = xo; 552 let Inst{31} = RC; 553} 554class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 555 InstrItinClass itin, list<dag> pattern> 556 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 557 let Pattern = pattern; 558 bits<5> FM; 559 560 bit RC = 0; // set by isDOT 561 562 let Inst{6-10} = FM; 563 let Inst{11-20} = 0; 564 let Inst{21-30} = xo; 565 let Inst{31} = RC; 566} 567 568class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 569 InstrItinClass itin, list<dag> pattern> 570 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 571 let RST = 0; 572 let A = 0; 573 let B = 0; 574} 575 576class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 577 InstrItinClass itin, list<dag> pattern> 578 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 579 let RST = 0; 580 let A = 0; 581} 582 583// DCB_Form - Form X instruction, used for dcb* instructions. 584class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 585 InstrItinClass itin, list<dag> pattern> 586 : I<31, OOL, IOL, asmstr, itin> { 587 bits<5> A; 588 bits<5> B; 589 590 let Pattern = pattern; 591 592 let Inst{6-10} = immfield; 593 let Inst{11-15} = A; 594 let Inst{16-20} = B; 595 let Inst{21-30} = xo; 596 let Inst{31} = 0; 597} 598 599 600// DSS_Form - Form X instruction, used for altivec dss* instructions. 601class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr, 602 InstrItinClass itin, list<dag> pattern> 603 : I<31, OOL, IOL, asmstr, itin> { 604 bits<1> T; 605 bits<2> STRM; 606 bits<5> A; 607 bits<5> B; 608 609 let Pattern = pattern; 610 611 let Inst{6} = T; 612 let Inst{7-8} = 0; 613 let Inst{9-10} = STRM; 614 let Inst{11-15} = A; 615 let Inst{16-20} = B; 616 let Inst{21-30} = xo; 617 let Inst{31} = 0; 618} 619 620// 1.7.7 XL-Form 621class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 622 InstrItinClass itin, list<dag> pattern> 623 : I<opcode, OOL, IOL, asmstr, itin> { 624 bits<5> CRD; 625 bits<5> CRA; 626 bits<5> CRB; 627 628 let Pattern = pattern; 629 630 let Inst{6-10} = CRD; 631 let Inst{11-15} = CRA; 632 let Inst{16-20} = CRB; 633 let Inst{21-30} = xo; 634 let Inst{31} = 0; 635} 636 637class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 638 InstrItinClass itin, list<dag> pattern> 639 : I<opcode, OOL, IOL, asmstr, itin> { 640 bits<5> CRD; 641 642 let Pattern = pattern; 643 644 let Inst{6-10} = CRD; 645 let Inst{11-15} = CRD; 646 let Inst{16-20} = CRD; 647 let Inst{21-30} = xo; 648 let Inst{31} = 0; 649} 650 651class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 652 InstrItinClass itin, list<dag> pattern> 653 : I<opcode, OOL, IOL, asmstr, itin> { 654 bits<5> BO; 655 bits<5> BI; 656 bits<2> BH; 657 658 let Pattern = pattern; 659 660 let Inst{6-10} = BO; 661 let Inst{11-15} = BI; 662 let Inst{16-18} = 0; 663 let Inst{19-20} = BH; 664 let Inst{21-30} = xo; 665 let Inst{31} = lk; 666} 667 668class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 669 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 670 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 671 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 672 bits<3> CR; 673 674 let BO = BIBO{4-0}; 675 let BI{0-1} = BIBO{5-6}; 676 let BI{2-4} = CR{0-2}; 677 let BH = 0; 678} 679 680 681class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 682 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 683 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 684 let BO = bo; 685 let BI = bi; 686 let BH = 0; 687} 688 689class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 690 InstrItinClass itin> 691 : I<opcode, OOL, IOL, asmstr, itin> { 692 bits<3> BF; 693 bits<3> BFA; 694 695 let Inst{6-8} = BF; 696 let Inst{9-10} = 0; 697 let Inst{11-13} = BFA; 698 let Inst{14-15} = 0; 699 let Inst{16-20} = 0; 700 let Inst{21-30} = xo; 701 let Inst{31} = 0; 702} 703 704// 1.7.8 XFX-Form 705class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 706 InstrItinClass itin> 707 : I<opcode, OOL, IOL, asmstr, itin> { 708 bits<5> RT; 709 bits<10> SPR; 710 711 let Inst{6-10} = RT; 712 let Inst{11} = SPR{4}; 713 let Inst{12} = SPR{3}; 714 let Inst{13} = SPR{2}; 715 let Inst{14} = SPR{1}; 716 let Inst{15} = SPR{0}; 717 let Inst{16} = SPR{9}; 718 let Inst{17} = SPR{8}; 719 let Inst{18} = SPR{7}; 720 let Inst{19} = SPR{6}; 721 let Inst{20} = SPR{5}; 722 let Inst{21-30} = xo; 723 let Inst{31} = 0; 724} 725 726class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 727 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 728 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 729 let SPR = spr; 730} 731 732class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 733 InstrItinClass itin> 734 : I<opcode, OOL, IOL, asmstr, itin> { 735 bits<5> RT; 736 737 let Inst{6-10} = RT; 738 let Inst{11-20} = 0; 739 let Inst{21-30} = xo; 740 let Inst{31} = 0; 741} 742 743class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 744 InstrItinClass itin> 745 : I<opcode, OOL, IOL, asmstr, itin> { 746 bits<8> FXM; 747 bits<5> rS; 748 749 let Inst{6-10} = rS; 750 let Inst{11} = 0; 751 let Inst{12-19} = FXM; 752 let Inst{20} = 0; 753 let Inst{21-30} = xo; 754 let Inst{31} = 0; 755} 756 757class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 758 InstrItinClass itin> 759 : I<opcode, OOL, IOL, asmstr, itin> { 760 bits<5> ST; 761 bits<8> FXM; 762 763 let Inst{6-10} = ST; 764 let Inst{11} = 1; 765 let Inst{12-19} = FXM; 766 let Inst{20} = 0; 767 let Inst{21-30} = xo; 768 let Inst{31} = 0; 769} 770 771class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 772 InstrItinClass itin> 773 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 774 775class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 776 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 777 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 778 let SPR = spr; 779} 780 781// XFL-Form - MTFSF 782// This is probably 1.7.9, but I don't have the reference that uses this 783// numbering scheme... 784class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 785 InstrItinClass itin, list<dag>pattern> 786 : I<opcode, OOL, IOL, asmstr, itin> { 787 bits<8> FM; 788 bits<5> rT; 789 790 bit RC = 0; // set by isDOT 791 let Pattern = pattern; 792 793 let Inst{6} = 0; 794 let Inst{7-14} = FM; 795 let Inst{15} = 0; 796 let Inst{16-20} = rT; 797 let Inst{21-30} = xo; 798 let Inst{31} = RC; 799} 800 801// 1.7.10 XS-Form - SRADI. 802class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 803 InstrItinClass itin, list<dag> pattern> 804 : I<opcode, OOL, IOL, asmstr, itin> { 805 bits<5> A; 806 bits<5> RS; 807 bits<6> SH; 808 809 bit RC = 0; // set by isDOT 810 let Pattern = pattern; 811 812 let Inst{6-10} = RS; 813 let Inst{11-15} = A; 814 let Inst{16-20} = SH{4,3,2,1,0}; 815 let Inst{21-29} = xo; 816 let Inst{30} = SH{5}; 817 let Inst{31} = RC; 818} 819 820// 1.7.11 XO-Form 821class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 822 InstrItinClass itin, list<dag> pattern> 823 : I<opcode, OOL, IOL, asmstr, itin> { 824 bits<5> RT; 825 bits<5> RA; 826 bits<5> RB; 827 828 let Pattern = pattern; 829 830 bit RC = 0; // set by isDOT 831 832 let Inst{6-10} = RT; 833 let Inst{11-15} = RA; 834 let Inst{16-20} = RB; 835 let Inst{21} = oe; 836 let Inst{22-30} = xo; 837 let Inst{31} = RC; 838} 839 840class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 841 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 842 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 843 let RB = 0; 844} 845 846// 1.7.12 A-Form 847class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 848 InstrItinClass itin, list<dag> pattern> 849 : I<opcode, OOL, IOL, asmstr, itin> { 850 bits<5> FRT; 851 bits<5> FRA; 852 bits<5> FRC; 853 bits<5> FRB; 854 855 let Pattern = pattern; 856 857 bit RC = 0; // set by isDOT 858 859 let Inst{6-10} = FRT; 860 let Inst{11-15} = FRA; 861 let Inst{16-20} = FRB; 862 let Inst{21-25} = FRC; 863 let Inst{26-30} = xo; 864 let Inst{31} = RC; 865} 866 867class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 868 InstrItinClass itin, list<dag> pattern> 869 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 870 let FRC = 0; 871} 872 873class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 874 InstrItinClass itin, list<dag> pattern> 875 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 876 let FRB = 0; 877} 878 879class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 880 InstrItinClass itin, list<dag> pattern> 881 : I<opcode, OOL, IOL, asmstr, itin> { 882 bits<5> RT; 883 bits<5> RA; 884 bits<5> RB; 885 bits<5> COND; 886 887 let Pattern = pattern; 888 889 let Inst{6-10} = RT; 890 let Inst{11-15} = RA; 891 let Inst{16-20} = RB; 892 let Inst{21-25} = COND; 893 let Inst{26-30} = xo; 894 let Inst{31} = 0; 895} 896 897// 1.7.13 M-Form 898class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 899 InstrItinClass itin, list<dag> pattern> 900 : I<opcode, OOL, IOL, asmstr, itin> { 901 bits<5> RA; 902 bits<5> RS; 903 bits<5> RB; 904 bits<5> MB; 905 bits<5> ME; 906 907 let Pattern = pattern; 908 909 bit RC = 0; // set by isDOT 910 911 let Inst{6-10} = RS; 912 let Inst{11-15} = RA; 913 let Inst{16-20} = RB; 914 let Inst{21-25} = MB; 915 let Inst{26-30} = ME; 916 let Inst{31} = RC; 917} 918 919class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 920 InstrItinClass itin, list<dag> pattern> 921 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 922} 923 924// 1.7.14 MD-Form 925class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 926 InstrItinClass itin, list<dag> pattern> 927 : I<opcode, OOL, IOL, asmstr, itin> { 928 bits<5> RA; 929 bits<5> RS; 930 bits<6> SH; 931 bits<6> MBE; 932 933 let Pattern = pattern; 934 935 bit RC = 0; // set by isDOT 936 937 let Inst{6-10} = RS; 938 let Inst{11-15} = RA; 939 let Inst{16-20} = SH{4,3,2,1,0}; 940 let Inst{21-26} = MBE{4,3,2,1,0,5}; 941 let Inst{27-29} = xo; 942 let Inst{30} = SH{5}; 943 let Inst{31} = RC; 944} 945 946class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 947 InstrItinClass itin, list<dag> pattern> 948 : I<opcode, OOL, IOL, asmstr, itin> { 949 bits<5> RA; 950 bits<5> RS; 951 bits<5> RB; 952 bits<6> MBE; 953 954 let Pattern = pattern; 955 956 bit RC = 0; // set by isDOT 957 958 let Inst{6-10} = RS; 959 let Inst{11-15} = RA; 960 let Inst{16-20} = RB; 961 let Inst{21-26} = MBE{4,3,2,1,0,5}; 962 let Inst{27-30} = xo; 963 let Inst{31} = RC; 964} 965 966 967// E-1 VA-Form 968 969// VAForm_1 - DACB ordering. 970class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 971 InstrItinClass itin, list<dag> pattern> 972 : I<4, OOL, IOL, asmstr, itin> { 973 bits<5> VD; 974 bits<5> VA; 975 bits<5> VC; 976 bits<5> VB; 977 978 let Pattern = pattern; 979 980 let Inst{6-10} = VD; 981 let Inst{11-15} = VA; 982 let Inst{16-20} = VB; 983 let Inst{21-25} = VC; 984 let Inst{26-31} = xo; 985} 986 987// VAForm_1a - DABC ordering. 988class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 989 InstrItinClass itin, list<dag> pattern> 990 : I<4, OOL, IOL, asmstr, itin> { 991 bits<5> VD; 992 bits<5> VA; 993 bits<5> VB; 994 bits<5> VC; 995 996 let Pattern = pattern; 997 998 let Inst{6-10} = VD; 999 let Inst{11-15} = VA; 1000 let Inst{16-20} = VB; 1001 let Inst{21-25} = VC; 1002 let Inst{26-31} = xo; 1003} 1004 1005class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 1006 InstrItinClass itin, list<dag> pattern> 1007 : I<4, OOL, IOL, asmstr, itin> { 1008 bits<5> VD; 1009 bits<5> VA; 1010 bits<5> VB; 1011 bits<4> SH; 1012 1013 let Pattern = pattern; 1014 1015 let Inst{6-10} = VD; 1016 let Inst{11-15} = VA; 1017 let Inst{16-20} = VB; 1018 let Inst{21} = 0; 1019 let Inst{22-25} = SH; 1020 let Inst{26-31} = xo; 1021} 1022 1023// E-2 VX-Form 1024class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 1025 InstrItinClass itin, list<dag> pattern> 1026 : I<4, OOL, IOL, asmstr, itin> { 1027 bits<5> VD; 1028 bits<5> VA; 1029 bits<5> VB; 1030 1031 let Pattern = pattern; 1032 1033 let Inst{6-10} = VD; 1034 let Inst{11-15} = VA; 1035 let Inst{16-20} = VB; 1036 let Inst{21-31} = xo; 1037} 1038 1039class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 1040 InstrItinClass itin, list<dag> pattern> 1041 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 1042 let VA = VD; 1043 let VB = VD; 1044} 1045 1046 1047class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 1048 InstrItinClass itin, list<dag> pattern> 1049 : I<4, OOL, IOL, asmstr, itin> { 1050 bits<5> VD; 1051 bits<5> VB; 1052 1053 let Pattern = pattern; 1054 1055 let Inst{6-10} = VD; 1056 let Inst{11-15} = 0; 1057 let Inst{16-20} = VB; 1058 let Inst{21-31} = xo; 1059} 1060 1061class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 1062 InstrItinClass itin, list<dag> pattern> 1063 : I<4, OOL, IOL, asmstr, itin> { 1064 bits<5> VD; 1065 bits<5> IMM; 1066 1067 let Pattern = pattern; 1068 1069 let Inst{6-10} = VD; 1070 let Inst{11-15} = IMM; 1071 let Inst{16-20} = 0; 1072 let Inst{21-31} = xo; 1073} 1074 1075/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 1076class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 1077 InstrItinClass itin, list<dag> pattern> 1078 : I<4, OOL, IOL, asmstr, itin> { 1079 bits<5> VD; 1080 1081 let Pattern = pattern; 1082 1083 let Inst{6-10} = VD; 1084 let Inst{11-15} = 0; 1085 let Inst{16-20} = 0; 1086 let Inst{21-31} = xo; 1087} 1088 1089/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 1090class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 1091 InstrItinClass itin, list<dag> pattern> 1092 : I<4, OOL, IOL, asmstr, itin> { 1093 bits<5> VB; 1094 1095 let Pattern = pattern; 1096 1097 let Inst{6-10} = 0; 1098 let Inst{11-15} = 0; 1099 let Inst{16-20} = VB; 1100 let Inst{21-31} = xo; 1101} 1102 1103// E-4 VXR-Form 1104class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 1105 InstrItinClass itin, list<dag> pattern> 1106 : I<4, OOL, IOL, asmstr, itin> { 1107 bits<5> VD; 1108 bits<5> VA; 1109 bits<5> VB; 1110 bit RC = 0; 1111 1112 let Pattern = pattern; 1113 1114 let Inst{6-10} = VD; 1115 let Inst{11-15} = VA; 1116 let Inst{16-20} = VB; 1117 let Inst{21} = RC; 1118 let Inst{22-31} = xo; 1119} 1120 1121//===----------------------------------------------------------------------===// 1122class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 1123 : I<0, OOL, IOL, asmstr, NoItinerary> { 1124 let isCodeGenOnly = 1; 1125 let PPC64 = 0; 1126 let Pattern = pattern; 1127 let Inst{31-0} = 0; 1128} 1129