1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// PowerPC instruction formats 13 14class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 15 : Instruction { 16 field bits<32> Inst; 17 18 bit PPC64 = 0; // Default value, override with isPPC64 19 20 let Namespace = "PPC"; 21 let Inst{0-5} = opcode; 22 let OutOperandList = OOL; 23 let InOperandList = IOL; 24 let AsmString = asmstr; 25 let Itinerary = itin; 26 27 bits<1> PPC970_First = 0; 28 bits<1> PPC970_Single = 0; 29 bits<1> PPC970_Cracked = 0; 30 bits<3> PPC970_Unit = 0; 31 32 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 33 /// these must be reflected there! See comments there for what these are. 34 let TSFlags{0} = PPC970_First; 35 let TSFlags{1} = PPC970_Single; 36 let TSFlags{2} = PPC970_Cracked; 37 let TSFlags{5-3} = PPC970_Unit; 38 39 // Fields used for relation models. 40 string BaseName = ""; 41 42 // For cases where multiple instruction definitions really represent the 43 // same underlying instruction but with one definition for 64-bit arguments 44 // and one for 32-bit arguments, this bit breaks the degeneracy between 45 // the two forms and allows TableGen to generate mapping tables. 46 bit Interpretation64Bit = 0; 47} 48 49class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 50class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 51class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 52class PPC970_MicroCode; 53 54class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 55class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 56class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 57class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 58class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 59class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 60class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 61class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 62 63// Two joined instructions; used to emit two adjacent instructions as one. 64// The itinerary from the first instruction is used for scheduling and 65// classification. 66class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 67 InstrItinClass itin> 68 : Instruction { 69 field bits<64> Inst; 70 71 bit PPC64 = 0; // Default value, override with isPPC64 72 73 let Namespace = "PPC"; 74 let Inst{0-5} = opcode1; 75 let Inst{32-37} = opcode2; 76 let OutOperandList = OOL; 77 let InOperandList = IOL; 78 let AsmString = asmstr; 79 let Itinerary = itin; 80 81 bits<1> PPC970_First = 0; 82 bits<1> PPC970_Single = 0; 83 bits<1> PPC970_Cracked = 0; 84 bits<3> PPC970_Unit = 0; 85 86 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 87 /// these must be reflected there! See comments there for what these are. 88 let TSFlags{0} = PPC970_First; 89 let TSFlags{1} = PPC970_Single; 90 let TSFlags{2} = PPC970_Cracked; 91 let TSFlags{5-3} = PPC970_Unit; 92 93 // Fields used for relation models. 94 string BaseName = ""; 95 bit Interpretation64Bit = 0; 96} 97 98// 1.7.1 I-Form 99class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 100 InstrItinClass itin, list<dag> pattern> 101 : I<opcode, OOL, IOL, asmstr, itin> { 102 let Pattern = pattern; 103 bits<24> LI; 104 105 let Inst{6-29} = LI; 106 let Inst{30} = aa; 107 let Inst{31} = lk; 108} 109 110// 1.7.2 B-Form 111class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 112 : I<opcode, OOL, IOL, asmstr, BrB> { 113 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 114 bits<3> CR; 115 bits<14> BD; 116 117 bits<5> BI; 118 let BI{0-1} = BIBO{5-6}; 119 let BI{2-4} = CR{0-2}; 120 121 let Inst{6-10} = BIBO{4-0}; 122 let Inst{11-15} = BI; 123 let Inst{16-29} = BD; 124 let Inst{30} = aa; 125 let Inst{31} = lk; 126} 127 128class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 129 string asmstr> 130 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 131 let BIBO{4-0} = bo; 132 let BIBO{6-5} = 0; 133 let CR = 0; 134} 135 136class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 137 dag OOL, dag IOL, string asmstr> 138 : I<opcode, OOL, IOL, asmstr, BrB> { 139 bits<14> BD; 140 141 let Inst{6-10} = bo; 142 let Inst{11-15} = bi; 143 let Inst{16-29} = BD; 144 let Inst{30} = aa; 145 let Inst{31} = lk; 146} 147 148// 1.7.3 SC-Form 149class SCForm<bits<6> opcode, bits<1> xo, 150 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 151 list<dag> pattern> 152 : I<opcode, OOL, IOL, asmstr, itin> { 153 bits<7> LEV; 154 155 let Pattern = pattern; 156 157 let Inst{20-26} = LEV; 158 let Inst{30} = xo; 159} 160 161// 1.7.4 D-Form 162class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 163 InstrItinClass itin, list<dag> pattern> 164 : I<opcode, OOL, IOL, asmstr, itin> { 165 bits<5> A; 166 bits<5> B; 167 bits<16> C; 168 169 let Pattern = pattern; 170 171 let Inst{6-10} = A; 172 let Inst{11-15} = B; 173 let Inst{16-31} = C; 174} 175 176class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 177 InstrItinClass itin, list<dag> pattern> 178 : I<opcode, OOL, IOL, asmstr, itin> { 179 bits<5> A; 180 bits<21> Addr; 181 182 let Pattern = pattern; 183 184 let Inst{6-10} = A; 185 let Inst{11-15} = Addr{20-16}; // Base Reg 186 let Inst{16-31} = Addr{15-0}; // Displacement 187} 188 189class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 190 InstrItinClass itin, list<dag> pattern> 191 : I<opcode, OOL, IOL, asmstr, itin> { 192 bits<5> A; 193 bits<16> C; 194 bits<5> B; 195 196 let Pattern = pattern; 197 198 let Inst{6-10} = A; 199 let Inst{11-15} = B; 200 let Inst{16-31} = C; 201} 202 203 204class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 205 InstrItinClass itin, list<dag> pattern> 206 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 207 208 // Even though ADDICo does not really have an RC bit, provide 209 // the declaration of one here so that isDOT has something to set. 210 bit RC = 0; 211} 212 213class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 214 InstrItinClass itin, list<dag> pattern> 215 : I<opcode, OOL, IOL, asmstr, itin> { 216 bits<5> A; 217 bits<16> B; 218 219 let Pattern = pattern; 220 221 let Inst{6-10} = A; 222 let Inst{11-15} = 0; 223 let Inst{16-31} = B; 224} 225 226class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 227 InstrItinClass itin, list<dag> pattern> 228 : I<opcode, OOL, IOL, asmstr, itin> { 229 bits<5> B; 230 bits<5> A; 231 bits<16> C; 232 233 let Pattern = pattern; 234 235 let Inst{6-10} = A; 236 let Inst{11-15} = B; 237 let Inst{16-31} = C; 238} 239 240class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 241 InstrItinClass itin, list<dag> pattern> 242 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 243 let A = 0; 244 let Addr = 0; 245} 246 247class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 248 dag OOL, dag IOL, string asmstr, 249 InstrItinClass itin, list<dag> pattern> 250 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 251 bits<5> A; 252 bits<21> Addr; 253 254 let Pattern = pattern; 255 bits<24> LI; 256 257 let Inst{6-29} = LI; 258 let Inst{30} = aa; 259 let Inst{31} = lk; 260 261 let Inst{38-42} = A; 262 let Inst{43-47} = Addr{20-16}; // Base Reg 263 let Inst{48-63} = Addr{15-0}; // Displacement 264} 265 266// This is used to emit BL8+NOP. 267class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 268 dag OOL, dag IOL, string asmstr, 269 InstrItinClass itin, list<dag> pattern> 270 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 271 OOL, IOL, asmstr, itin, pattern> { 272 let A = 0; 273 let Addr = 0; 274} 275 276class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 277 InstrItinClass itin> 278 : I<opcode, OOL, IOL, asmstr, itin> { 279 bits<3> BF; 280 bits<1> L; 281 bits<5> RA; 282 bits<16> I; 283 284 let Inst{6-8} = BF; 285 let Inst{9} = 0; 286 let Inst{10} = L; 287 let Inst{11-15} = RA; 288 let Inst{16-31} = I; 289} 290 291class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 292 InstrItinClass itin> 293 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 294 let L = PPC64; 295} 296 297class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 298 InstrItinClass itin> 299 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 300 301class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 302 InstrItinClass itin> 303 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 304 let L = PPC64; 305} 306 307 308// 1.7.5 DS-Form 309class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 310 InstrItinClass itin, list<dag> pattern> 311 : I<opcode, OOL, IOL, asmstr, itin> { 312 bits<5> RST; 313 bits<19> DS_RA; 314 315 let Pattern = pattern; 316 317 let Inst{6-10} = RST; 318 let Inst{11-15} = DS_RA{18-14}; // Register # 319 let Inst{16-29} = DS_RA{13-0}; // Displacement. 320 let Inst{30-31} = xo; 321} 322 323class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 324 InstrItinClass itin, list<dag> pattern> 325 : I<opcode, OOL, IOL, asmstr, itin> { 326 bits<5> RST; 327 bits<14> DS; 328 bits<5> RA; 329 330 let Pattern = pattern; 331 332 let Inst{6-10} = RST; 333 let Inst{11-15} = RA; 334 let Inst{16-29} = DS; 335 let Inst{30-31} = xo; 336} 337 338// 1.7.6 X-Form 339class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 340 InstrItinClass itin, list<dag> pattern> 341 : I<opcode, OOL, IOL, asmstr, itin> { 342 bits<5> RST; 343 bits<5> A; 344 bits<5> B; 345 346 let Pattern = pattern; 347 348 bit RC = 0; // set by isDOT 349 350 let Inst{6-10} = RST; 351 let Inst{11-15} = A; 352 let Inst{16-20} = B; 353 let Inst{21-30} = xo; 354 let Inst{31} = RC; 355} 356 357// This is the same as XForm_base_r3xo, but the first two operands are swapped 358// when code is emitted. 359class XForm_base_r3xo_swapped 360 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 361 InstrItinClass itin> 362 : I<opcode, OOL, IOL, asmstr, itin> { 363 bits<5> A; 364 bits<5> RST; 365 bits<5> B; 366 367 bit RC = 0; // set by isDOT 368 369 let Inst{6-10} = RST; 370 let Inst{11-15} = A; 371 let Inst{16-20} = B; 372 let Inst{21-30} = xo; 373 let Inst{31} = RC; 374} 375 376 377class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 378 InstrItinClass itin, list<dag> pattern> 379 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 380 381class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 382 InstrItinClass itin, list<dag> pattern> 383 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 384 let RST = 0; 385} 386 387class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 388 InstrItinClass itin, list<dag> pattern> 389 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 390 let Pattern = pattern; 391} 392 393class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 394 InstrItinClass itin, list<dag> pattern> 395 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 396 397class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 398 InstrItinClass itin, list<dag> pattern> 399 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 400 let Pattern = pattern; 401} 402 403class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 404 InstrItinClass itin, list<dag> pattern> 405 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 406 let B = 0; 407 let Pattern = pattern; 408} 409 410class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 411 InstrItinClass itin> 412 : I<opcode, OOL, IOL, asmstr, itin> { 413 bits<3> BF; 414 bits<1> L; 415 bits<5> RA; 416 bits<5> RB; 417 418 let Inst{6-8} = BF; 419 let Inst{9} = 0; 420 let Inst{10} = L; 421 let Inst{11-15} = RA; 422 let Inst{16-20} = RB; 423 let Inst{21-30} = xo; 424 let Inst{31} = 0; 425} 426 427class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 428 InstrItinClass itin> 429 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 430 let L = PPC64; 431} 432 433class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 434 InstrItinClass itin> 435 : I<opcode, OOL, IOL, asmstr, itin> { 436 bits<3> BF; 437 bits<5> FRA; 438 bits<5> FRB; 439 440 let Inst{6-8} = BF; 441 let Inst{9-10} = 0; 442 let Inst{11-15} = FRA; 443 let Inst{16-20} = FRB; 444 let Inst{21-30} = xo; 445 let Inst{31} = 0; 446} 447 448class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 449 InstrItinClass itin, list<dag> pattern> 450 : I<opcode, OOL, IOL, asmstr, itin> { 451 let Pattern = pattern; 452 let Inst{6-10} = 31; 453 let Inst{11-15} = 0; 454 let Inst{16-20} = 0; 455 let Inst{21-30} = xo; 456 let Inst{31} = 0; 457} 458 459class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 460 string asmstr, InstrItinClass itin, list<dag> pattern> 461 : I<opcode, OOL, IOL, asmstr, itin> { 462 let Pattern = pattern; 463 let Inst{6-10} = 0; 464 let Inst{11-15} = 0; 465 let Inst{16-20} = 0; 466 let Inst{21-30} = xo; 467 let Inst{31} = 0; 468} 469 470class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 471 InstrItinClass itin, list<dag> pattern> 472 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 473} 474 475class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 476 InstrItinClass itin, list<dag> pattern> 477 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 478 let A = 0; 479} 480 481class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 482 InstrItinClass itin, list<dag> pattern> 483 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 484} 485 486// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 487// numbers presumably relates to some document, but I haven't found it. 488class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 489 InstrItinClass itin, list<dag> pattern> 490 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 491 let Pattern = pattern; 492 493 bit RC = 0; // set by isDOT 494 495 let Inst{6-10} = RST; 496 let Inst{11-20} = 0; 497 let Inst{21-30} = xo; 498 let Inst{31} = RC; 499} 500class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 501 InstrItinClass itin, list<dag> pattern> 502 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 503 let Pattern = pattern; 504 bits<5> FM; 505 506 bit RC = 0; // set by isDOT 507 508 let Inst{6-10} = FM; 509 let Inst{11-20} = 0; 510 let Inst{21-30} = xo; 511 let Inst{31} = RC; 512} 513 514// DCB_Form - Form X instruction, used for dcb* instructions. 515class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 516 InstrItinClass itin, list<dag> pattern> 517 : I<31, OOL, IOL, asmstr, itin> { 518 bits<5> A; 519 bits<5> B; 520 521 let Pattern = pattern; 522 523 let Inst{6-10} = immfield; 524 let Inst{11-15} = A; 525 let Inst{16-20} = B; 526 let Inst{21-30} = xo; 527 let Inst{31} = 0; 528} 529 530 531// DSS_Form - Form X instruction, used for altivec dss* instructions. 532class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr, 533 InstrItinClass itin, list<dag> pattern> 534 : I<31, OOL, IOL, asmstr, itin> { 535 bits<1> T; 536 bits<2> STRM; 537 bits<5> A; 538 bits<5> B; 539 540 let Pattern = pattern; 541 542 let Inst{6} = T; 543 let Inst{7-8} = 0; 544 let Inst{9-10} = STRM; 545 let Inst{11-15} = A; 546 let Inst{16-20} = B; 547 let Inst{21-30} = xo; 548 let Inst{31} = 0; 549} 550 551// 1.7.7 XL-Form 552class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 553 InstrItinClass itin, list<dag> pattern> 554 : I<opcode, OOL, IOL, asmstr, itin> { 555 bits<5> CRD; 556 bits<5> CRA; 557 bits<5> CRB; 558 559 let Pattern = pattern; 560 561 let Inst{6-10} = CRD; 562 let Inst{11-15} = CRA; 563 let Inst{16-20} = CRB; 564 let Inst{21-30} = xo; 565 let Inst{31} = 0; 566} 567 568class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 569 InstrItinClass itin, list<dag> pattern> 570 : I<opcode, OOL, IOL, asmstr, itin> { 571 bits<5> CRD; 572 573 let Pattern = pattern; 574 575 let Inst{6-10} = CRD; 576 let Inst{11-15} = CRD; 577 let Inst{16-20} = CRD; 578 let Inst{21-30} = xo; 579 let Inst{31} = 0; 580} 581 582class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 583 InstrItinClass itin, list<dag> pattern> 584 : I<opcode, OOL, IOL, asmstr, itin> { 585 bits<5> BO; 586 bits<5> BI; 587 bits<2> BH; 588 589 let Pattern = pattern; 590 591 let Inst{6-10} = BO; 592 let Inst{11-15} = BI; 593 let Inst{16-18} = 0; 594 let Inst{19-20} = BH; 595 let Inst{21-30} = xo; 596 let Inst{31} = lk; 597} 598 599class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 600 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 601 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 602 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 603 bits<3> CR; 604 605 let BO = BIBO{4-0}; 606 let BI{0-1} = BIBO{5-6}; 607 let BI{2-4} = CR{0-2}; 608 let BH = 0; 609} 610 611 612class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 613 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 614 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 615 let BO = bo; 616 let BI = bi; 617 let BH = 0; 618} 619 620class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 621 InstrItinClass itin> 622 : I<opcode, OOL, IOL, asmstr, itin> { 623 bits<3> BF; 624 bits<3> BFA; 625 626 let Inst{6-8} = BF; 627 let Inst{9-10} = 0; 628 let Inst{11-13} = BFA; 629 let Inst{14-15} = 0; 630 let Inst{16-20} = 0; 631 let Inst{21-30} = xo; 632 let Inst{31} = 0; 633} 634 635// 1.7.8 XFX-Form 636class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 637 InstrItinClass itin> 638 : I<opcode, OOL, IOL, asmstr, itin> { 639 bits<5> RT; 640 bits<10> SPR; 641 642 let Inst{6-10} = RT; 643 let Inst{11} = SPR{4}; 644 let Inst{12} = SPR{3}; 645 let Inst{13} = SPR{2}; 646 let Inst{14} = SPR{1}; 647 let Inst{15} = SPR{0}; 648 let Inst{16} = SPR{9}; 649 let Inst{17} = SPR{8}; 650 let Inst{18} = SPR{7}; 651 let Inst{19} = SPR{6}; 652 let Inst{20} = SPR{5}; 653 let Inst{21-30} = xo; 654 let Inst{31} = 0; 655} 656 657class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 658 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 659 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 660 let SPR = spr; 661} 662 663class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 664 InstrItinClass itin> 665 : I<opcode, OOL, IOL, asmstr, itin> { 666 bits<5> RT; 667 668 let Inst{6-10} = RT; 669 let Inst{11-20} = 0; 670 let Inst{21-30} = xo; 671 let Inst{31} = 0; 672} 673 674class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 675 InstrItinClass itin> 676 : I<opcode, OOL, IOL, asmstr, itin> { 677 bits<8> FXM; 678 bits<5> rS; 679 680 let Inst{6-10} = rS; 681 let Inst{11} = 0; 682 let Inst{12-19} = FXM; 683 let Inst{20} = 0; 684 let Inst{21-30} = xo; 685 let Inst{31} = 0; 686} 687 688class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 689 InstrItinClass itin> 690 : I<opcode, OOL, IOL, asmstr, itin> { 691 bits<5> ST; 692 bits<8> FXM; 693 694 let Inst{6-10} = ST; 695 let Inst{11} = 1; 696 let Inst{12-19} = FXM; 697 let Inst{20} = 0; 698 let Inst{21-30} = xo; 699 let Inst{31} = 0; 700} 701 702class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 703 InstrItinClass itin> 704 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 705 706class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 707 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 708 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 709 let SPR = spr; 710} 711 712// XFL-Form - MTFSF 713// This is probably 1.7.9, but I don't have the reference that uses this 714// numbering scheme... 715class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 716 InstrItinClass itin, list<dag>pattern> 717 : I<opcode, OOL, IOL, asmstr, itin> { 718 bits<8> FM; 719 bits<5> rT; 720 721 bit RC = 0; // set by isDOT 722 let Pattern = pattern; 723 724 let Inst{6} = 0; 725 let Inst{7-14} = FM; 726 let Inst{15} = 0; 727 let Inst{16-20} = rT; 728 let Inst{21-30} = xo; 729 let Inst{31} = RC; 730} 731 732// 1.7.10 XS-Form - SRADI. 733class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 734 InstrItinClass itin, list<dag> pattern> 735 : I<opcode, OOL, IOL, asmstr, itin> { 736 bits<5> A; 737 bits<5> RS; 738 bits<6> SH; 739 740 bit RC = 0; // set by isDOT 741 let Pattern = pattern; 742 743 let Inst{6-10} = RS; 744 let Inst{11-15} = A; 745 let Inst{16-20} = SH{4,3,2,1,0}; 746 let Inst{21-29} = xo; 747 let Inst{30} = SH{5}; 748 let Inst{31} = RC; 749} 750 751// 1.7.11 XO-Form 752class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 753 InstrItinClass itin, list<dag> pattern> 754 : I<opcode, OOL, IOL, asmstr, itin> { 755 bits<5> RT; 756 bits<5> RA; 757 bits<5> RB; 758 759 let Pattern = pattern; 760 761 bit RC = 0; // set by isDOT 762 763 let Inst{6-10} = RT; 764 let Inst{11-15} = RA; 765 let Inst{16-20} = RB; 766 let Inst{21} = oe; 767 let Inst{22-30} = xo; 768 let Inst{31} = RC; 769} 770 771class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 772 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 773 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 774 let RB = 0; 775} 776 777// 1.7.12 A-Form 778class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 779 InstrItinClass itin, list<dag> pattern> 780 : I<opcode, OOL, IOL, asmstr, itin> { 781 bits<5> FRT; 782 bits<5> FRA; 783 bits<5> FRC; 784 bits<5> FRB; 785 786 let Pattern = pattern; 787 788 bit RC = 0; // set by isDOT 789 790 let Inst{6-10} = FRT; 791 let Inst{11-15} = FRA; 792 let Inst{16-20} = FRB; 793 let Inst{21-25} = FRC; 794 let Inst{26-30} = xo; 795 let Inst{31} = RC; 796} 797 798class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 799 InstrItinClass itin, list<dag> pattern> 800 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 801 let FRC = 0; 802} 803 804class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 805 InstrItinClass itin, list<dag> pattern> 806 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 807 let FRB = 0; 808} 809 810class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 811 InstrItinClass itin, list<dag> pattern> 812 : I<opcode, OOL, IOL, asmstr, itin> { 813 bits<5> RT; 814 bits<5> RA; 815 bits<5> RB; 816 bits<5> COND; 817 818 let Pattern = pattern; 819 820 let Inst{6-10} = RT; 821 let Inst{11-15} = RA; 822 let Inst{16-20} = RB; 823 let Inst{21-25} = COND; 824 let Inst{26-30} = xo; 825 let Inst{31} = 0; 826} 827 828// 1.7.13 M-Form 829class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 830 InstrItinClass itin, list<dag> pattern> 831 : I<opcode, OOL, IOL, asmstr, itin> { 832 bits<5> RA; 833 bits<5> RS; 834 bits<5> RB; 835 bits<5> MB; 836 bits<5> ME; 837 838 let Pattern = pattern; 839 840 bit RC = 0; // set by isDOT 841 842 let Inst{6-10} = RS; 843 let Inst{11-15} = RA; 844 let Inst{16-20} = RB; 845 let Inst{21-25} = MB; 846 let Inst{26-30} = ME; 847 let Inst{31} = RC; 848} 849 850class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 851 InstrItinClass itin, list<dag> pattern> 852 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 853} 854 855// 1.7.14 MD-Form 856class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 857 InstrItinClass itin, list<dag> pattern> 858 : I<opcode, OOL, IOL, asmstr, itin> { 859 bits<5> RA; 860 bits<5> RS; 861 bits<6> SH; 862 bits<6> MBE; 863 864 let Pattern = pattern; 865 866 bit RC = 0; // set by isDOT 867 868 let Inst{6-10} = RS; 869 let Inst{11-15} = RA; 870 let Inst{16-20} = SH{4,3,2,1,0}; 871 let Inst{21-26} = MBE{4,3,2,1,0,5}; 872 let Inst{27-29} = xo; 873 let Inst{30} = SH{5}; 874 let Inst{31} = RC; 875} 876 877class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 878 InstrItinClass itin, list<dag> pattern> 879 : I<opcode, OOL, IOL, asmstr, itin> { 880 bits<5> RA; 881 bits<5> RS; 882 bits<5> RB; 883 bits<6> MBE; 884 885 let Pattern = pattern; 886 887 bit RC = 0; // set by isDOT 888 889 let Inst{6-10} = RS; 890 let Inst{11-15} = RA; 891 let Inst{16-20} = RB; 892 let Inst{21-26} = MBE{4,3,2,1,0,5}; 893 let Inst{27-30} = xo; 894 let Inst{31} = RC; 895} 896 897 898// E-1 VA-Form 899 900// VAForm_1 - DACB ordering. 901class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 902 InstrItinClass itin, list<dag> pattern> 903 : I<4, OOL, IOL, asmstr, itin> { 904 bits<5> VD; 905 bits<5> VA; 906 bits<5> VC; 907 bits<5> VB; 908 909 let Pattern = pattern; 910 911 let Inst{6-10} = VD; 912 let Inst{11-15} = VA; 913 let Inst{16-20} = VB; 914 let Inst{21-25} = VC; 915 let Inst{26-31} = xo; 916} 917 918// VAForm_1a - DABC ordering. 919class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 920 InstrItinClass itin, list<dag> pattern> 921 : I<4, OOL, IOL, asmstr, itin> { 922 bits<5> VD; 923 bits<5> VA; 924 bits<5> VB; 925 bits<5> VC; 926 927 let Pattern = pattern; 928 929 let Inst{6-10} = VD; 930 let Inst{11-15} = VA; 931 let Inst{16-20} = VB; 932 let Inst{21-25} = VC; 933 let Inst{26-31} = xo; 934} 935 936class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 937 InstrItinClass itin, list<dag> pattern> 938 : I<4, OOL, IOL, asmstr, itin> { 939 bits<5> VD; 940 bits<5> VA; 941 bits<5> VB; 942 bits<4> SH; 943 944 let Pattern = pattern; 945 946 let Inst{6-10} = VD; 947 let Inst{11-15} = VA; 948 let Inst{16-20} = VB; 949 let Inst{21} = 0; 950 let Inst{22-25} = SH; 951 let Inst{26-31} = xo; 952} 953 954// E-2 VX-Form 955class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 956 InstrItinClass itin, list<dag> pattern> 957 : I<4, OOL, IOL, asmstr, itin> { 958 bits<5> VD; 959 bits<5> VA; 960 bits<5> VB; 961 962 let Pattern = pattern; 963 964 let Inst{6-10} = VD; 965 let Inst{11-15} = VA; 966 let Inst{16-20} = VB; 967 let Inst{21-31} = xo; 968} 969 970class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 971 InstrItinClass itin, list<dag> pattern> 972 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 973 let VA = VD; 974 let VB = VD; 975} 976 977 978class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 979 InstrItinClass itin, list<dag> pattern> 980 : I<4, OOL, IOL, asmstr, itin> { 981 bits<5> VD; 982 bits<5> VB; 983 984 let Pattern = pattern; 985 986 let Inst{6-10} = VD; 987 let Inst{11-15} = 0; 988 let Inst{16-20} = VB; 989 let Inst{21-31} = xo; 990} 991 992class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 993 InstrItinClass itin, list<dag> pattern> 994 : I<4, OOL, IOL, asmstr, itin> { 995 bits<5> VD; 996 bits<5> IMM; 997 998 let Pattern = pattern; 999 1000 let Inst{6-10} = VD; 1001 let Inst{11-15} = IMM; 1002 let Inst{16-20} = 0; 1003 let Inst{21-31} = xo; 1004} 1005 1006/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 1007class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 1008 InstrItinClass itin, list<dag> pattern> 1009 : I<4, OOL, IOL, asmstr, itin> { 1010 bits<5> VD; 1011 1012 let Pattern = pattern; 1013 1014 let Inst{6-10} = VD; 1015 let Inst{11-15} = 0; 1016 let Inst{16-20} = 0; 1017 let Inst{21-31} = xo; 1018} 1019 1020/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 1021class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 1022 InstrItinClass itin, list<dag> pattern> 1023 : I<4, OOL, IOL, asmstr, itin> { 1024 bits<5> VB; 1025 1026 let Pattern = pattern; 1027 1028 let Inst{6-10} = 0; 1029 let Inst{11-15} = 0; 1030 let Inst{16-20} = VB; 1031 let Inst{21-31} = xo; 1032} 1033 1034// E-4 VXR-Form 1035class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 1036 InstrItinClass itin, list<dag> pattern> 1037 : I<4, OOL, IOL, asmstr, itin> { 1038 bits<5> VD; 1039 bits<5> VA; 1040 bits<5> VB; 1041 bit RC = 0; 1042 1043 let Pattern = pattern; 1044 1045 let Inst{6-10} = VD; 1046 let Inst{11-15} = VA; 1047 let Inst{16-20} = VB; 1048 let Inst{21} = RC; 1049 let Inst{22-31} = xo; 1050} 1051 1052//===----------------------------------------------------------------------===// 1053class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 1054 : I<0, OOL, IOL, asmstr, NoItinerary> { 1055 let isCodeGenOnly = 1; 1056 let PPC64 = 0; 1057 let Pattern = pattern; 1058 let Inst{31-0} = 0; 1059} 1060