1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// PowerPC instruction formats 13 14class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 15 : Instruction { 16 field bits<32> Inst; 17 field bits<32> SoftFail = 0; 18 let Size = 4; 19 20 bit PPC64 = 0; // Default value, override with isPPC64 21 22 let Namespace = "PPC"; 23 let Inst{0-5} = opcode; 24 let OutOperandList = OOL; 25 let InOperandList = IOL; 26 let AsmString = asmstr; 27 let Itinerary = itin; 28 29 bits<1> PPC970_First = 0; 30 bits<1> PPC970_Single = 0; 31 bits<1> PPC970_Cracked = 0; 32 bits<3> PPC970_Unit = 0; 33 34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 35 /// these must be reflected there! See comments there for what these are. 36 let TSFlags{0} = PPC970_First; 37 let TSFlags{1} = PPC970_Single; 38 let TSFlags{2} = PPC970_Cracked; 39 let TSFlags{5-3} = PPC970_Unit; 40 41 // Fields used for relation models. 42 string BaseName = ""; 43 44 // For cases where multiple instruction definitions really represent the 45 // same underlying instruction but with one definition for 64-bit arguments 46 // and one for 32-bit arguments, this bit breaks the degeneracy between 47 // the two forms and allows TableGen to generate mapping tables. 48 bit Interpretation64Bit = 0; 49} 50 51class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 52class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 53class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 54class PPC970_MicroCode; 55 56class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 57class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 58class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 59class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 60class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 61class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 62class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 63class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 64 65// Two joined instructions; used to emit two adjacent instructions as one. 66// The itinerary from the first instruction is used for scheduling and 67// classification. 68class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 69 InstrItinClass itin> 70 : Instruction { 71 field bits<64> Inst; 72 field bits<64> SoftFail = 0; 73 let Size = 8; 74 75 bit PPC64 = 0; // Default value, override with isPPC64 76 77 let Namespace = "PPC"; 78 let Inst{0-5} = opcode1; 79 let Inst{32-37} = opcode2; 80 let OutOperandList = OOL; 81 let InOperandList = IOL; 82 let AsmString = asmstr; 83 let Itinerary = itin; 84 85 bits<1> PPC970_First = 0; 86 bits<1> PPC970_Single = 0; 87 bits<1> PPC970_Cracked = 0; 88 bits<3> PPC970_Unit = 0; 89 90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 91 /// these must be reflected there! See comments there for what these are. 92 let TSFlags{0} = PPC970_First; 93 let TSFlags{1} = PPC970_Single; 94 let TSFlags{2} = PPC970_Cracked; 95 let TSFlags{5-3} = PPC970_Unit; 96 97 // Fields used for relation models. 98 string BaseName = ""; 99 bit Interpretation64Bit = 0; 100} 101 102// 1.7.1 I-Form 103class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 104 InstrItinClass itin, list<dag> pattern> 105 : I<opcode, OOL, IOL, asmstr, itin> { 106 let Pattern = pattern; 107 bits<24> LI; 108 109 let Inst{6-29} = LI; 110 let Inst{30} = aa; 111 let Inst{31} = lk; 112} 113 114// 1.7.2 B-Form 115class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 118 bits<3> CR; 119 bits<14> BD; 120 121 bits<5> BI; 122 let BI{0-1} = BIBO{5-6}; 123 let BI{2-4} = CR{0-2}; 124 125 let Inst{6-10} = BIBO{4-0}; 126 let Inst{11-15} = BI; 127 let Inst{16-29} = BD; 128 let Inst{30} = aa; 129 let Inst{31} = lk; 130} 131 132class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 133 string asmstr> 134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 135 let BIBO{4-0} = bo; 136 let BIBO{6-5} = 0; 137 let CR = 0; 138} 139 140class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 141 dag OOL, dag IOL, string asmstr> 142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 143 bits<14> BD; 144 145 let Inst{6-10} = bo; 146 let Inst{11-15} = bi; 147 let Inst{16-29} = BD; 148 let Inst{30} = aa; 149 let Inst{31} = lk; 150} 151 152class BForm_3<bits<6> opcode, bit aa, bit lk, 153 dag OOL, dag IOL, string asmstr> 154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 155 bits<5> BO; 156 bits<5> BI; 157 bits<14> BD; 158 159 let Inst{6-10} = BO; 160 let Inst{11-15} = BI; 161 let Inst{16-29} = BD; 162 let Inst{30} = aa; 163 let Inst{31} = lk; 164} 165 166class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, 167 dag OOL, dag IOL, string asmstr> 168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 169 bits<5> BI; 170 bits<14> BD; 171 172 let Inst{6-10} = bo; 173 let Inst{11-15} = BI; 174 let Inst{16-29} = BD; 175 let Inst{30} = aa; 176 let Inst{31} = lk; 177} 178 179// 1.7.3 SC-Form 180class SCForm<bits<6> opcode, bits<1> xo, 181 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 182 list<dag> pattern> 183 : I<opcode, OOL, IOL, asmstr, itin> { 184 bits<7> LEV; 185 186 let Pattern = pattern; 187 188 let Inst{20-26} = LEV; 189 let Inst{30} = xo; 190} 191 192// 1.7.4 D-Form 193class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 194 InstrItinClass itin, list<dag> pattern> 195 : I<opcode, OOL, IOL, asmstr, itin> { 196 bits<5> A; 197 bits<5> B; 198 bits<16> C; 199 200 let Pattern = pattern; 201 202 let Inst{6-10} = A; 203 let Inst{11-15} = B; 204 let Inst{16-31} = C; 205} 206 207class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 208 InstrItinClass itin, list<dag> pattern> 209 : I<opcode, OOL, IOL, asmstr, itin> { 210 bits<5> A; 211 bits<21> Addr; 212 213 let Pattern = pattern; 214 215 let Inst{6-10} = A; 216 let Inst{11-15} = Addr{20-16}; // Base Reg 217 let Inst{16-31} = Addr{15-0}; // Displacement 218} 219 220class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 221 InstrItinClass itin, list<dag> pattern> 222 : I<opcode, OOL, IOL, asmstr, itin> { 223 bits<5> A; 224 bits<16> C; 225 bits<5> B; 226 227 let Pattern = pattern; 228 229 let Inst{6-10} = A; 230 let Inst{11-15} = B; 231 let Inst{16-31} = C; 232} 233 234 235class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 236 InstrItinClass itin, list<dag> pattern> 237 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 238 239 // Even though ADDICo does not really have an RC bit, provide 240 // the declaration of one here so that isDOT has something to set. 241 bit RC = 0; 242} 243 244class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 245 InstrItinClass itin, list<dag> pattern> 246 : I<opcode, OOL, IOL, asmstr, itin> { 247 bits<5> A; 248 bits<16> B; 249 250 let Pattern = pattern; 251 252 let Inst{6-10} = A; 253 let Inst{11-15} = 0; 254 let Inst{16-31} = B; 255} 256 257class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 258 InstrItinClass itin, list<dag> pattern> 259 : I<opcode, OOL, IOL, asmstr, itin> { 260 bits<5> B; 261 bits<5> A; 262 bits<16> C; 263 264 let Pattern = pattern; 265 266 let Inst{6-10} = A; 267 let Inst{11-15} = B; 268 let Inst{16-31} = C; 269} 270 271class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 272 InstrItinClass itin, list<dag> pattern> 273 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 274 let A = 0; 275 let Addr = 0; 276} 277 278class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 279 string asmstr, InstrItinClass itin, 280 list<dag> pattern> 281 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 282 let A = R; 283 let B = R; 284 let C = 0; 285} 286 287class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 288 dag OOL, dag IOL, string asmstr, 289 InstrItinClass itin, list<dag> pattern> 290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 291 bits<5> A; 292 bits<21> Addr; 293 294 let Pattern = pattern; 295 bits<24> LI; 296 297 let Inst{6-29} = LI; 298 let Inst{30} = aa; 299 let Inst{31} = lk; 300 301 let Inst{38-42} = A; 302 let Inst{43-47} = Addr{20-16}; // Base Reg 303 let Inst{48-63} = Addr{15-0}; // Displacement 304} 305 306// This is used to emit BL8+NOP. 307class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 308 dag OOL, dag IOL, string asmstr, 309 InstrItinClass itin, list<dag> pattern> 310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 311 OOL, IOL, asmstr, itin, pattern> { 312 let A = 0; 313 let Addr = 0; 314} 315 316class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 317 InstrItinClass itin> 318 : I<opcode, OOL, IOL, asmstr, itin> { 319 bits<3> BF; 320 bits<1> L; 321 bits<5> RA; 322 bits<16> I; 323 324 let Inst{6-8} = BF; 325 let Inst{9} = 0; 326 let Inst{10} = L; 327 let Inst{11-15} = RA; 328 let Inst{16-31} = I; 329} 330 331class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 332 InstrItinClass itin> 333 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 334 let L = PPC64; 335} 336 337class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 338 InstrItinClass itin> 339 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 340 341class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 342 InstrItinClass itin> 343 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 344 let L = PPC64; 345} 346 347 348// 1.7.5 DS-Form 349class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 350 InstrItinClass itin, list<dag> pattern> 351 : I<opcode, OOL, IOL, asmstr, itin> { 352 bits<5> RST; 353 bits<19> DS_RA; 354 355 let Pattern = pattern; 356 357 let Inst{6-10} = RST; 358 let Inst{11-15} = DS_RA{18-14}; // Register # 359 let Inst{16-29} = DS_RA{13-0}; // Displacement. 360 let Inst{30-31} = xo; 361} 362 363 364// 1.7.6 X-Form 365class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 366 InstrItinClass itin, list<dag> pattern> 367 : I<opcode, OOL, IOL, asmstr, itin> { 368 bits<5> RST; 369 bits<5> A; 370 bits<5> B; 371 372 let Pattern = pattern; 373 374 bit RC = 0; // set by isDOT 375 376 let Inst{6-10} = RST; 377 let Inst{11-15} = A; 378 let Inst{16-20} = B; 379 let Inst{21-30} = xo; 380 let Inst{31} = RC; 381} 382 383class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr, 384 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 385 let RST = 0; 386} 387 388class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 389 InstrItinClass itin> 390 : I<opcode, OOL, IOL, asmstr, itin> { 391 let Inst{21-30} = xo; 392} 393 394// This is the same as XForm_base_r3xo, but the first two operands are swapped 395// when code is emitted. 396class XForm_base_r3xo_swapped 397 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 398 InstrItinClass itin> 399 : I<opcode, OOL, IOL, asmstr, itin> { 400 bits<5> A; 401 bits<5> RST; 402 bits<5> B; 403 404 bit RC = 0; // set by isDOT 405 406 let Inst{6-10} = RST; 407 let Inst{11-15} = A; 408 let Inst{16-20} = B; 409 let Inst{21-30} = xo; 410 let Inst{31} = RC; 411} 412 413 414class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 415 InstrItinClass itin, list<dag> pattern> 416 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 417 418class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 419 InstrItinClass itin, list<dag> pattern> 420 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 421 let RST = 0; 422} 423 424class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 425 InstrItinClass itin, list<dag> pattern> 426 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 427 let A = 0; 428 let B = 0; 429} 430 431class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 432 InstrItinClass itin, list<dag> pattern> 433 : I<opcode, OOL, IOL, asmstr, itin> { 434 bits<5> RST; 435 bits<5> A; 436 bits<1> WS; 437 438 let Pattern = pattern; 439 440 let Inst{6-10} = RST; 441 let Inst{11-15} = A; 442 let Inst{20} = WS; 443 let Inst{21-30} = xo; 444 let Inst{31} = 0; 445} 446 447class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 448 InstrItinClass itin, list<dag> pattern> 449 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 450 let Pattern = pattern; 451} 452 453class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 454 InstrItinClass itin, list<dag> pattern> 455 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 456 457class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 458 InstrItinClass itin, list<dag> pattern> 459 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 460 let Pattern = pattern; 461} 462 463class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 464 InstrItinClass itin, list<dag> pattern> 465 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 466 let B = 0; 467 let Pattern = pattern; 468} 469 470class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 471 InstrItinClass itin> 472 : I<opcode, OOL, IOL, asmstr, itin> { 473 bits<3> BF; 474 bits<1> L; 475 bits<5> RA; 476 bits<5> RB; 477 478 let Inst{6-8} = BF; 479 let Inst{9} = 0; 480 let Inst{10} = L; 481 let Inst{11-15} = RA; 482 let Inst{16-20} = RB; 483 let Inst{21-30} = xo; 484 let Inst{31} = 0; 485} 486 487class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 488 InstrItinClass itin> 489 : I<opcode, OOL, IOL, asmstr, itin> { 490 bits<4> CT; 491 bits<5> RA; 492 bits<5> RB; 493 494 let Inst{6} = 0; 495 let Inst{7-10} = CT; 496 let Inst{11-15} = RA; 497 let Inst{16-20} = RB; 498 let Inst{21-30} = xo; 499 let Inst{31} = 0; 500} 501 502class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 503 InstrItinClass itin> 504 : I<opcode, OOL, IOL, asmstr, itin> { 505 bits<5> RS; 506 bits<4> SR; 507 508 let Inst{6-10} = RS; 509 let Inst{12-15} = SR; 510 let Inst{21-30} = xo; 511} 512 513class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 514 InstrItinClass itin> 515 : I<opcode, OOL, IOL, asmstr, itin> { 516 bits<5> MO; 517 518 let Inst{6-10} = MO; 519 let Inst{21-30} = xo; 520} 521 522class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 523 InstrItinClass itin> 524 : I<opcode, OOL, IOL, asmstr, itin> { 525 bits<5> RS; 526 bits<5> RB; 527 528 let Inst{6-10} = RS; 529 let Inst{16-20} = RB; 530 let Inst{21-30} = xo; 531} 532 533class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 534 InstrItinClass itin> 535 : I<opcode, OOL, IOL, asmstr, itin> { 536 bits<5> RS; 537 bits<1> L; 538 539 let Inst{6-10} = RS; 540 let Inst{15} = L; 541 let Inst{21-30} = xo; 542} 543 544class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 545 InstrItinClass itin> 546 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 547 let L = PPC64; 548} 549 550class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 551 InstrItinClass itin> 552 : I<opcode, OOL, IOL, asmstr, itin> { 553 bits<3> BF; 554 bits<5> FRA; 555 bits<5> FRB; 556 557 let Inst{6-8} = BF; 558 let Inst{9-10} = 0; 559 let Inst{11-15} = FRA; 560 let Inst{16-20} = FRB; 561 let Inst{21-30} = xo; 562 let Inst{31} = 0; 563} 564 565// Used for QPX 566class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 567 InstrItinClass itin, list<dag> pattern> 568 : I<opcode, OOL, IOL, asmstr, itin> { 569 bits<5> FRT; 570 bits<5> FRA; 571 bits<5> FRB; 572 573 let Pattern = pattern; 574 575 let Inst{6-10} = FRT; 576 let Inst{11-15} = FRA; 577 let Inst{16-20} = FRB; 578 let Inst{21-30} = xo; 579 let Inst{31} = 0; 580} 581 582class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 583 InstrItinClass itin, list<dag> pattern> 584 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 585 let FRA = 0; 586} 587 588class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr, 589 InstrItinClass itin, list<dag> pattern> 590 : I<opcode, OOL, IOL, asmstr, itin> { 591 bits<5> FRT; 592 bits<5> FRA; 593 bits<5> FRB; 594 bits<4> tttt; 595 596 let Pattern = pattern; 597 598 let Inst{6-10} = FRT; 599 let Inst{11-15} = FRA; 600 let Inst{16-20} = FRB; 601 let Inst{21-24} = tttt; 602 let Inst{25-30} = xo; 603 let Inst{31} = 0; 604} 605 606class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 607 InstrItinClass itin, list<dag> pattern> 608 : I<opcode, OOL, IOL, asmstr, itin> { 609 let Pattern = pattern; 610 let Inst{6-10} = 31; 611 let Inst{11-15} = 0; 612 let Inst{16-20} = 0; 613 let Inst{21-30} = xo; 614 let Inst{31} = 0; 615} 616 617class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 618 string asmstr, InstrItinClass itin, list<dag> pattern> 619 : I<opcode, OOL, IOL, asmstr, itin> { 620 bits<2> L; 621 622 let Pattern = pattern; 623 let Inst{6-8} = 0; 624 let Inst{9-10} = L; 625 let Inst{11-15} = 0; 626 let Inst{16-20} = 0; 627 let Inst{21-30} = xo; 628 let Inst{31} = 0; 629} 630 631class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 632 string asmstr, InstrItinClass itin, list<dag> pattern> 633 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 634 let L = 0; 635} 636 637class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 638 InstrItinClass itin, list<dag> pattern> 639 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 640} 641 642class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 643 InstrItinClass itin, list<dag> pattern> 644 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 645 let A = 0; 646} 647 648class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 649 InstrItinClass itin, list<dag> pattern> 650 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 651} 652 653// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 654// numbers presumably relates to some document, but I haven't found it. 655class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 656 InstrItinClass itin, list<dag> pattern> 657 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 658 let Pattern = pattern; 659 660 bit RC = 0; // set by isDOT 661 662 let Inst{6-10} = RST; 663 let Inst{11-20} = 0; 664 let Inst{21-30} = xo; 665 let Inst{31} = RC; 666} 667class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 668 InstrItinClass itin, list<dag> pattern> 669 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 670 let Pattern = pattern; 671 bits<5> FM; 672 673 bit RC = 0; // set by isDOT 674 675 let Inst{6-10} = FM; 676 let Inst{11-20} = 0; 677 let Inst{21-30} = xo; 678 let Inst{31} = RC; 679} 680 681class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 682 InstrItinClass itin, list<dag> pattern> 683 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 684 let RST = 0; 685 let A = 0; 686 let B = 0; 687} 688 689class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 690 InstrItinClass itin, list<dag> pattern> 691 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 692 let RST = 0; 693 let A = 0; 694} 695 696// XX*-Form (VSX) 697class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 698 InstrItinClass itin, list<dag> pattern> 699 : I<opcode, OOL, IOL, asmstr, itin> { 700 bits<6> XT; 701 bits<5> A; 702 bits<5> B; 703 704 let Pattern = pattern; 705 706 let Inst{6-10} = XT{4-0}; 707 let Inst{11-15} = A; 708 let Inst{16-20} = B; 709 let Inst{21-30} = xo; 710 let Inst{31} = XT{5}; 711} 712 713class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 714 InstrItinClass itin, list<dag> pattern> 715 : I<opcode, OOL, IOL, asmstr, itin> { 716 bits<6> XT; 717 bits<6> XB; 718 719 let Pattern = pattern; 720 721 let Inst{6-10} = XT{4-0}; 722 let Inst{11-15} = 0; 723 let Inst{16-20} = XB{4-0}; 724 let Inst{21-29} = xo; 725 let Inst{30} = XB{5}; 726 let Inst{31} = XT{5}; 727} 728 729class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 730 InstrItinClass itin, list<dag> pattern> 731 : I<opcode, OOL, IOL, asmstr, itin> { 732 bits<3> CR; 733 bits<6> XB; 734 735 let Pattern = pattern; 736 737 let Inst{6-8} = CR; 738 let Inst{9-15} = 0; 739 let Inst{16-20} = XB{4-0}; 740 let Inst{21-29} = xo; 741 let Inst{30} = XB{5}; 742 let Inst{31} = 0; 743} 744 745class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 746 InstrItinClass itin, list<dag> pattern> 747 : I<opcode, OOL, IOL, asmstr, itin> { 748 bits<6> XT; 749 bits<6> XB; 750 bits<2> D; 751 752 let Pattern = pattern; 753 754 let Inst{6-10} = XT{4-0}; 755 let Inst{11-13} = 0; 756 let Inst{14-15} = D; 757 let Inst{16-20} = XB{4-0}; 758 let Inst{21-29} = xo; 759 let Inst{30} = XB{5}; 760 let Inst{31} = XT{5}; 761} 762 763class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 764 InstrItinClass itin, list<dag> pattern> 765 : I<opcode, OOL, IOL, asmstr, itin> { 766 bits<6> XT; 767 bits<6> XA; 768 bits<6> XB; 769 770 let Pattern = pattern; 771 772 let Inst{6-10} = XT{4-0}; 773 let Inst{11-15} = XA{4-0}; 774 let Inst{16-20} = XB{4-0}; 775 let Inst{21-28} = xo; 776 let Inst{29} = XA{5}; 777 let Inst{30} = XB{5}; 778 let Inst{31} = XT{5}; 779} 780 781class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 782 InstrItinClass itin, list<dag> pattern> 783 : I<opcode, OOL, IOL, asmstr, itin> { 784 bits<3> CR; 785 bits<6> XA; 786 bits<6> XB; 787 788 let Pattern = pattern; 789 790 let Inst{6-8} = CR; 791 let Inst{9-10} = 0; 792 let Inst{11-15} = XA{4-0}; 793 let Inst{16-20} = XB{4-0}; 794 let Inst{21-28} = xo; 795 let Inst{29} = XA{5}; 796 let Inst{30} = XB{5}; 797 let Inst{31} = 0; 798} 799 800class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 801 InstrItinClass itin, list<dag> pattern> 802 : I<opcode, OOL, IOL, asmstr, itin> { 803 bits<6> XT; 804 bits<6> XA; 805 bits<6> XB; 806 bits<2> D; 807 808 let Pattern = pattern; 809 810 let Inst{6-10} = XT{4-0}; 811 let Inst{11-15} = XA{4-0}; 812 let Inst{16-20} = XB{4-0}; 813 let Inst{21} = 0; 814 let Inst{22-23} = D; 815 let Inst{24-28} = xo; 816 let Inst{29} = XA{5}; 817 let Inst{30} = XB{5}; 818 let Inst{31} = XT{5}; 819} 820 821class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr, 822 InstrItinClass itin, list<dag> pattern> 823 : I<opcode, OOL, IOL, asmstr, itin> { 824 bits<6> XT; 825 bits<6> XA; 826 bits<6> XB; 827 828 let Pattern = pattern; 829 830 bit RC = 0; // set by isDOT 831 832 let Inst{6-10} = XT{4-0}; 833 let Inst{11-15} = XA{4-0}; 834 let Inst{16-20} = XB{4-0}; 835 let Inst{21} = RC; 836 let Inst{22-28} = xo; 837 let Inst{29} = XA{5}; 838 let Inst{30} = XB{5}; 839 let Inst{31} = XT{5}; 840} 841 842class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 843 InstrItinClass itin, list<dag> pattern> 844 : I<opcode, OOL, IOL, asmstr, itin> { 845 bits<6> XT; 846 bits<6> XA; 847 bits<6> XB; 848 bits<6> XC; 849 850 let Pattern = pattern; 851 852 let Inst{6-10} = XT{4-0}; 853 let Inst{11-15} = XA{4-0}; 854 let Inst{16-20} = XB{4-0}; 855 let Inst{21-25} = XC{4-0}; 856 let Inst{26-27} = xo; 857 let Inst{28} = XC{5}; 858 let Inst{29} = XA{5}; 859 let Inst{30} = XB{5}; 860 let Inst{31} = XT{5}; 861} 862 863// DCB_Form - Form X instruction, used for dcb* instructions. 864class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 865 InstrItinClass itin, list<dag> pattern> 866 : I<31, OOL, IOL, asmstr, itin> { 867 bits<5> A; 868 bits<5> B; 869 870 let Pattern = pattern; 871 872 let Inst{6-10} = immfield; 873 let Inst{11-15} = A; 874 let Inst{16-20} = B; 875 let Inst{21-30} = xo; 876 let Inst{31} = 0; 877} 878 879 880// DSS_Form - Form X instruction, used for altivec dss* instructions. 881class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr, 882 InstrItinClass itin, list<dag> pattern> 883 : I<31, OOL, IOL, asmstr, itin> { 884 bits<2> STRM; 885 bits<5> A; 886 bits<5> B; 887 888 let Pattern = pattern; 889 890 let Inst{6} = T; 891 let Inst{7-8} = 0; 892 let Inst{9-10} = STRM; 893 let Inst{11-15} = A; 894 let Inst{16-20} = B; 895 let Inst{21-30} = xo; 896 let Inst{31} = 0; 897} 898 899// 1.7.7 XL-Form 900class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 901 InstrItinClass itin, list<dag> pattern> 902 : I<opcode, OOL, IOL, asmstr, itin> { 903 bits<5> CRD; 904 bits<5> CRA; 905 bits<5> CRB; 906 907 let Pattern = pattern; 908 909 let Inst{6-10} = CRD; 910 let Inst{11-15} = CRA; 911 let Inst{16-20} = CRB; 912 let Inst{21-30} = xo; 913 let Inst{31} = 0; 914} 915 916class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 917 InstrItinClass itin, list<dag> pattern> 918 : I<opcode, OOL, IOL, asmstr, itin> { 919 bits<5> CRD; 920 921 let Pattern = pattern; 922 923 let Inst{6-10} = CRD; 924 let Inst{11-15} = CRD; 925 let Inst{16-20} = CRD; 926 let Inst{21-30} = xo; 927 let Inst{31} = 0; 928} 929 930class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 931 InstrItinClass itin, list<dag> pattern> 932 : I<opcode, OOL, IOL, asmstr, itin> { 933 bits<5> BO; 934 bits<5> BI; 935 bits<2> BH; 936 937 let Pattern = pattern; 938 939 let Inst{6-10} = BO; 940 let Inst{11-15} = BI; 941 let Inst{16-18} = 0; 942 let Inst{19-20} = BH; 943 let Inst{21-30} = xo; 944 let Inst{31} = lk; 945} 946 947class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 948 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 949 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 950 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 951 bits<3> CR; 952 953 let BO = BIBO{4-0}; 954 let BI{0-1} = BIBO{5-6}; 955 let BI{2-4} = CR{0-2}; 956 let BH = 0; 957} 958 959class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk, 960 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 961 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 962 let BO = bo; 963 let BH = 0; 964} 965 966class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 967 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 968 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 969 let BO = bo; 970 let BI = bi; 971 let BH = 0; 972} 973 974class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 975 InstrItinClass itin> 976 : I<opcode, OOL, IOL, asmstr, itin> { 977 bits<3> BF; 978 bits<3> BFA; 979 980 let Inst{6-8} = BF; 981 let Inst{9-10} = 0; 982 let Inst{11-13} = BFA; 983 let Inst{14-15} = 0; 984 let Inst{16-20} = 0; 985 let Inst{21-30} = xo; 986 let Inst{31} = 0; 987} 988 989class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 990 InstrItinClass itin> 991 : I<opcode, OOL, IOL, asmstr, itin> { 992 bits<3> BF; 993 bit W; 994 bits<4> U; 995 996 bit RC = 0; 997 998 let Inst{6-8} = BF; 999 let Inst{9-10} = 0; 1000 let Inst{11-14} = 0; 1001 let Inst{15} = W; 1002 let Inst{16-19} = U; 1003 let Inst{20} = 0; 1004 let Inst{21-30} = xo; 1005 let Inst{31} = RC; 1006} 1007 1008class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk, 1009 bits<6> opcode2, bits<2> xo2, 1010 dag OOL, dag IOL, string asmstr, 1011 InstrItinClass itin, list<dag> pattern> 1012 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1013 bits<5> BO; 1014 bits<5> BI; 1015 bits<2> BH; 1016 1017 bits<5> RST; 1018 bits<19> DS_RA; 1019 1020 let Pattern = pattern; 1021 1022 let Inst{6-10} = BO; 1023 let Inst{11-15} = BI; 1024 let Inst{16-18} = 0; 1025 let Inst{19-20} = BH; 1026 let Inst{21-30} = xo1; 1027 let Inst{31} = lk; 1028 1029 let Inst{38-42} = RST; 1030 let Inst{43-47} = DS_RA{18-14}; // Register # 1031 let Inst{48-61} = DS_RA{13-0}; // Displacement. 1032 let Inst{62-63} = xo2; 1033} 1034 1035class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1, 1036 bits<5> bo, bits<5> bi, bit lk, 1037 bits<6> opcode2, bits<2> xo2, 1038 dag OOL, dag IOL, string asmstr, 1039 InstrItinClass itin, list<dag> pattern> 1040 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2, 1041 OOL, IOL, asmstr, itin, pattern> { 1042 let BO = bo; 1043 let BI = bi; 1044 let BH = 0; 1045} 1046 1047// 1.7.8 XFX-Form 1048class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1049 InstrItinClass itin> 1050 : I<opcode, OOL, IOL, asmstr, itin> { 1051 bits<5> RT; 1052 bits<10> SPR; 1053 1054 let Inst{6-10} = RT; 1055 let Inst{11} = SPR{4}; 1056 let Inst{12} = SPR{3}; 1057 let Inst{13} = SPR{2}; 1058 let Inst{14} = SPR{1}; 1059 let Inst{15} = SPR{0}; 1060 let Inst{16} = SPR{9}; 1061 let Inst{17} = SPR{8}; 1062 let Inst{18} = SPR{7}; 1063 let Inst{19} = SPR{6}; 1064 let Inst{20} = SPR{5}; 1065 let Inst{21-30} = xo; 1066 let Inst{31} = 0; 1067} 1068 1069class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1070 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1071 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 1072 let SPR = spr; 1073} 1074 1075class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1076 InstrItinClass itin> 1077 : I<opcode, OOL, IOL, asmstr, itin> { 1078 bits<5> RT; 1079 1080 let Inst{6-10} = RT; 1081 let Inst{11-20} = 0; 1082 let Inst{21-30} = xo; 1083 let Inst{31} = 0; 1084} 1085 1086class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1087 InstrItinClass itin> 1088 : I<opcode, OOL, IOL, asmstr, itin> { 1089 bits<8> FXM; 1090 bits<5> rS; 1091 1092 let Inst{6-10} = rS; 1093 let Inst{11} = 0; 1094 let Inst{12-19} = FXM; 1095 let Inst{20} = 0; 1096 let Inst{21-30} = xo; 1097 let Inst{31} = 0; 1098} 1099 1100class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1101 InstrItinClass itin> 1102 : I<opcode, OOL, IOL, asmstr, itin> { 1103 bits<5> ST; 1104 bits<8> FXM; 1105 1106 let Inst{6-10} = ST; 1107 let Inst{11} = 1; 1108 let Inst{12-19} = FXM; 1109 let Inst{20} = 0; 1110 let Inst{21-30} = xo; 1111 let Inst{31} = 0; 1112} 1113 1114class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1115 InstrItinClass itin> 1116 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 1117 1118class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1119 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1120 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 1121 let SPR = spr; 1122} 1123 1124// XFL-Form - MTFSF 1125// This is probably 1.7.9, but I don't have the reference that uses this 1126// numbering scheme... 1127class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1128 InstrItinClass itin, list<dag>pattern> 1129 : I<opcode, OOL, IOL, asmstr, itin> { 1130 bits<8> FM; 1131 bits<5> rT; 1132 1133 bit RC = 0; // set by isDOT 1134 let Pattern = pattern; 1135 1136 let Inst{6} = 0; 1137 let Inst{7-14} = FM; 1138 let Inst{15} = 0; 1139 let Inst{16-20} = rT; 1140 let Inst{21-30} = xo; 1141 let Inst{31} = RC; 1142} 1143 1144class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1145 InstrItinClass itin, list<dag>pattern> 1146 : I<opcode, OOL, IOL, asmstr, itin> { 1147 bit L; 1148 bits<8> FLM; 1149 bit W; 1150 bits<5> FRB; 1151 1152 bit RC = 0; // set by isDOT 1153 let Pattern = pattern; 1154 1155 let Inst{6} = L; 1156 let Inst{7-14} = FLM; 1157 let Inst{15} = W; 1158 let Inst{16-20} = FRB; 1159 let Inst{21-30} = xo; 1160 let Inst{31} = RC; 1161} 1162 1163// 1.7.10 XS-Form - SRADI. 1164class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1165 InstrItinClass itin, list<dag> pattern> 1166 : I<opcode, OOL, IOL, asmstr, itin> { 1167 bits<5> A; 1168 bits<5> RS; 1169 bits<6> SH; 1170 1171 bit RC = 0; // set by isDOT 1172 let Pattern = pattern; 1173 1174 let Inst{6-10} = RS; 1175 let Inst{11-15} = A; 1176 let Inst{16-20} = SH{4,3,2,1,0}; 1177 let Inst{21-29} = xo; 1178 let Inst{30} = SH{5}; 1179 let Inst{31} = RC; 1180} 1181 1182// 1.7.11 XO-Form 1183class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 1184 InstrItinClass itin, list<dag> pattern> 1185 : I<opcode, OOL, IOL, asmstr, itin> { 1186 bits<5> RT; 1187 bits<5> RA; 1188 bits<5> RB; 1189 1190 let Pattern = pattern; 1191 1192 bit RC = 0; // set by isDOT 1193 1194 let Inst{6-10} = RT; 1195 let Inst{11-15} = RA; 1196 let Inst{16-20} = RB; 1197 let Inst{21} = oe; 1198 let Inst{22-30} = xo; 1199 let Inst{31} = RC; 1200} 1201 1202class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 1203 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1204 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 1205 let RB = 0; 1206} 1207 1208// 1.7.12 A-Form 1209class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1210 InstrItinClass itin, list<dag> pattern> 1211 : I<opcode, OOL, IOL, asmstr, itin> { 1212 bits<5> FRT; 1213 bits<5> FRA; 1214 bits<5> FRC; 1215 bits<5> FRB; 1216 1217 let Pattern = pattern; 1218 1219 bit RC = 0; // set by isDOT 1220 1221 let Inst{6-10} = FRT; 1222 let Inst{11-15} = FRA; 1223 let Inst{16-20} = FRB; 1224 let Inst{21-25} = FRC; 1225 let Inst{26-30} = xo; 1226 let Inst{31} = RC; 1227} 1228 1229class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1230 InstrItinClass itin, list<dag> pattern> 1231 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1232 let FRC = 0; 1233} 1234 1235class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1236 InstrItinClass itin, list<dag> pattern> 1237 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1238 let FRB = 0; 1239} 1240 1241class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1242 InstrItinClass itin, list<dag> pattern> 1243 : I<opcode, OOL, IOL, asmstr, itin> { 1244 bits<5> RT; 1245 bits<5> RA; 1246 bits<5> RB; 1247 bits<5> COND; 1248 1249 let Pattern = pattern; 1250 1251 let Inst{6-10} = RT; 1252 let Inst{11-15} = RA; 1253 let Inst{16-20} = RB; 1254 let Inst{21-25} = COND; 1255 let Inst{26-30} = xo; 1256 let Inst{31} = 0; 1257} 1258 1259// Used for QPX 1260class AForm_4a<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1261 InstrItinClass itin, list<dag> pattern> 1262 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1263 let FRA = 0; 1264 let FRC = 0; 1265} 1266 1267// 1.7.13 M-Form 1268class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1269 InstrItinClass itin, list<dag> pattern> 1270 : I<opcode, OOL, IOL, asmstr, itin> { 1271 bits<5> RA; 1272 bits<5> RS; 1273 bits<5> RB; 1274 bits<5> MB; 1275 bits<5> ME; 1276 1277 let Pattern = pattern; 1278 1279 bit RC = 0; // set by isDOT 1280 1281 let Inst{6-10} = RS; 1282 let Inst{11-15} = RA; 1283 let Inst{16-20} = RB; 1284 let Inst{21-25} = MB; 1285 let Inst{26-30} = ME; 1286 let Inst{31} = RC; 1287} 1288 1289class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1290 InstrItinClass itin, list<dag> pattern> 1291 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 1292} 1293 1294// 1.7.14 MD-Form 1295class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 1296 InstrItinClass itin, list<dag> pattern> 1297 : I<opcode, OOL, IOL, asmstr, itin> { 1298 bits<5> RA; 1299 bits<5> RS; 1300 bits<6> SH; 1301 bits<6> MBE; 1302 1303 let Pattern = pattern; 1304 1305 bit RC = 0; // set by isDOT 1306 1307 let Inst{6-10} = RS; 1308 let Inst{11-15} = RA; 1309 let Inst{16-20} = SH{4,3,2,1,0}; 1310 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1311 let Inst{27-29} = xo; 1312 let Inst{30} = SH{5}; 1313 let Inst{31} = RC; 1314} 1315 1316class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 1317 InstrItinClass itin, list<dag> pattern> 1318 : I<opcode, OOL, IOL, asmstr, itin> { 1319 bits<5> RA; 1320 bits<5> RS; 1321 bits<5> RB; 1322 bits<6> MBE; 1323 1324 let Pattern = pattern; 1325 1326 bit RC = 0; // set by isDOT 1327 1328 let Inst{6-10} = RS; 1329 let Inst{11-15} = RA; 1330 let Inst{16-20} = RB; 1331 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1332 let Inst{27-30} = xo; 1333 let Inst{31} = RC; 1334} 1335 1336 1337// E-1 VA-Form 1338 1339// VAForm_1 - DACB ordering. 1340class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 1341 InstrItinClass itin, list<dag> pattern> 1342 : I<4, OOL, IOL, asmstr, itin> { 1343 bits<5> VD; 1344 bits<5> VA; 1345 bits<5> VC; 1346 bits<5> VB; 1347 1348 let Pattern = pattern; 1349 1350 let Inst{6-10} = VD; 1351 let Inst{11-15} = VA; 1352 let Inst{16-20} = VB; 1353 let Inst{21-25} = VC; 1354 let Inst{26-31} = xo; 1355} 1356 1357// VAForm_1a - DABC ordering. 1358class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 1359 InstrItinClass itin, list<dag> pattern> 1360 : I<4, OOL, IOL, asmstr, itin> { 1361 bits<5> VD; 1362 bits<5> VA; 1363 bits<5> VB; 1364 bits<5> VC; 1365 1366 let Pattern = pattern; 1367 1368 let Inst{6-10} = VD; 1369 let Inst{11-15} = VA; 1370 let Inst{16-20} = VB; 1371 let Inst{21-25} = VC; 1372 let Inst{26-31} = xo; 1373} 1374 1375class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 1376 InstrItinClass itin, list<dag> pattern> 1377 : I<4, OOL, IOL, asmstr, itin> { 1378 bits<5> VD; 1379 bits<5> VA; 1380 bits<5> VB; 1381 bits<4> SH; 1382 1383 let Pattern = pattern; 1384 1385 let Inst{6-10} = VD; 1386 let Inst{11-15} = VA; 1387 let Inst{16-20} = VB; 1388 let Inst{21} = 0; 1389 let Inst{22-25} = SH; 1390 let Inst{26-31} = xo; 1391} 1392 1393// E-2 VX-Form 1394class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 1395 InstrItinClass itin, list<dag> pattern> 1396 : I<4, OOL, IOL, asmstr, itin> { 1397 bits<5> VD; 1398 bits<5> VA; 1399 bits<5> VB; 1400 1401 let Pattern = pattern; 1402 1403 let Inst{6-10} = VD; 1404 let Inst{11-15} = VA; 1405 let Inst{16-20} = VB; 1406 let Inst{21-31} = xo; 1407} 1408 1409class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 1410 InstrItinClass itin, list<dag> pattern> 1411 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 1412 let VA = VD; 1413 let VB = VD; 1414} 1415 1416 1417class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 1418 InstrItinClass itin, list<dag> pattern> 1419 : I<4, OOL, IOL, asmstr, itin> { 1420 bits<5> VD; 1421 bits<5> VB; 1422 1423 let Pattern = pattern; 1424 1425 let Inst{6-10} = VD; 1426 let Inst{11-15} = 0; 1427 let Inst{16-20} = VB; 1428 let Inst{21-31} = xo; 1429} 1430 1431class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 1432 InstrItinClass itin, list<dag> pattern> 1433 : I<4, OOL, IOL, asmstr, itin> { 1434 bits<5> VD; 1435 bits<5> IMM; 1436 1437 let Pattern = pattern; 1438 1439 let Inst{6-10} = VD; 1440 let Inst{11-15} = IMM; 1441 let Inst{16-20} = 0; 1442 let Inst{21-31} = xo; 1443} 1444 1445/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 1446class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 1447 InstrItinClass itin, list<dag> pattern> 1448 : I<4, OOL, IOL, asmstr, itin> { 1449 bits<5> VD; 1450 1451 let Pattern = pattern; 1452 1453 let Inst{6-10} = VD; 1454 let Inst{11-15} = 0; 1455 let Inst{16-20} = 0; 1456 let Inst{21-31} = xo; 1457} 1458 1459/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 1460class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 1461 InstrItinClass itin, list<dag> pattern> 1462 : I<4, OOL, IOL, asmstr, itin> { 1463 bits<5> VB; 1464 1465 let Pattern = pattern; 1466 1467 let Inst{6-10} = 0; 1468 let Inst{11-15} = 0; 1469 let Inst{16-20} = VB; 1470 let Inst{21-31} = xo; 1471} 1472 1473// E-4 VXR-Form 1474class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 1475 InstrItinClass itin, list<dag> pattern> 1476 : I<4, OOL, IOL, asmstr, itin> { 1477 bits<5> VD; 1478 bits<5> VA; 1479 bits<5> VB; 1480 bit RC = 0; 1481 1482 let Pattern = pattern; 1483 1484 let Inst{6-10} = VD; 1485 let Inst{11-15} = VA; 1486 let Inst{16-20} = VB; 1487 let Inst{21} = RC; 1488 let Inst{22-31} = xo; 1489} 1490 1491// Z23-Form (used by QPX) 1492class Z23Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1493 InstrItinClass itin, list<dag> pattern> 1494 : I<opcode, OOL, IOL, asmstr, itin> { 1495 bits<5> FRT; 1496 bits<5> FRA; 1497 bits<5> FRB; 1498 bits<2> idx; 1499 1500 let Pattern = pattern; 1501 1502 bit RC = 0; // set by isDOT 1503 1504 let Inst{6-10} = FRT; 1505 let Inst{11-15} = FRA; 1506 let Inst{16-20} = FRB; 1507 let Inst{21-22} = idx; 1508 let Inst{23-30} = xo; 1509 let Inst{31} = RC; 1510} 1511 1512class Z23Form_2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1513 InstrItinClass itin, list<dag> pattern> 1514 : Z23Form_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1515 let FRB = 0; 1516} 1517 1518class Z23Form_3<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1519 InstrItinClass itin, list<dag> pattern> 1520 : I<opcode, OOL, IOL, asmstr, itin> { 1521 bits<5> FRT; 1522 bits<12> idx; 1523 1524 let Pattern = pattern; 1525 1526 bit RC = 0; // set by isDOT 1527 1528 let Inst{6-10} = FRT; 1529 let Inst{11-22} = idx; 1530 let Inst{23-30} = xo; 1531 let Inst{31} = RC; 1532} 1533 1534//===----------------------------------------------------------------------===// 1535class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 1536 : I<0, OOL, IOL, asmstr, NoItinerary> { 1537 let isCodeGenOnly = 1; 1538 let PPC64 = 0; 1539 let Pattern = pattern; 1540 let Inst{31-0} = 0; 1541} 1542