1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// PowerPC instruction formats 13 14class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 15 : Instruction { 16 field bits<32> Inst; 17 18 bit PPC64 = 0; // Default value, override with isPPC64 19 20 let Namespace = "PPC"; 21 let Inst{0-5} = opcode; 22 let OutOperandList = OOL; 23 let InOperandList = IOL; 24 let AsmString = asmstr; 25 let Itinerary = itin; 26 27 bits<1> PPC970_First = 0; 28 bits<1> PPC970_Single = 0; 29 bits<1> PPC970_Cracked = 0; 30 bits<3> PPC970_Unit = 0; 31 32 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 33 /// these must be reflected there! See comments there for what these are. 34 let TSFlags{0} = PPC970_First; 35 let TSFlags{1} = PPC970_Single; 36 let TSFlags{2} = PPC970_Cracked; 37 let TSFlags{5-3} = PPC970_Unit; 38 39 // Fields used for relation models. 40 string BaseName = ""; 41 42 // For cases where multiple instruction definitions really represent the 43 // same underlying instruction but with one definition for 64-bit arguments 44 // and one for 32-bit arguments, this bit breaks the degeneracy between 45 // the two forms and allows TableGen to generate mapping tables. 46 bit Interpretation64Bit = 0; 47} 48 49class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 50class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 51class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 52class PPC970_MicroCode; 53 54class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 55class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 56class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 57class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 58class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 59class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 60class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 61class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 62 63// Two joined instructions; used to emit two adjacent instructions as one. 64// The itinerary from the first instruction is used for scheduling and 65// classification. 66class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 67 InstrItinClass itin> 68 : Instruction { 69 field bits<64> Inst; 70 71 bit PPC64 = 0; // Default value, override with isPPC64 72 73 let Namespace = "PPC"; 74 let Inst{0-5} = opcode1; 75 let Inst{32-37} = opcode2; 76 let OutOperandList = OOL; 77 let InOperandList = IOL; 78 let AsmString = asmstr; 79 let Itinerary = itin; 80 81 bits<1> PPC970_First = 0; 82 bits<1> PPC970_Single = 0; 83 bits<1> PPC970_Cracked = 0; 84 bits<3> PPC970_Unit = 0; 85 86 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 87 /// these must be reflected there! See comments there for what these are. 88 let TSFlags{0} = PPC970_First; 89 let TSFlags{1} = PPC970_Single; 90 let TSFlags{2} = PPC970_Cracked; 91 let TSFlags{5-3} = PPC970_Unit; 92 93 // Fields used for relation models. 94 string BaseName = ""; 95 bit Interpretation64Bit = 0; 96} 97 98// 1.7.1 I-Form 99class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 100 InstrItinClass itin, list<dag> pattern> 101 : I<opcode, OOL, IOL, asmstr, itin> { 102 let Pattern = pattern; 103 bits<24> LI; 104 105 let Inst{6-29} = LI; 106 let Inst{30} = aa; 107 let Inst{31} = lk; 108} 109 110// 1.7.2 B-Form 111class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 112 : I<opcode, OOL, IOL, asmstr, BrB> { 113 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 114 bits<3> CR; 115 bits<14> BD; 116 117 bits<5> BI; 118 let BI{0-1} = BIBO{5-6}; 119 let BI{2-4} = CR{0-2}; 120 121 let Inst{6-10} = BIBO{4-0}; 122 let Inst{11-15} = BI; 123 let Inst{16-29} = BD; 124 let Inst{30} = aa; 125 let Inst{31} = lk; 126} 127 128class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 129 string asmstr> 130 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 131 let BIBO{4-0} = bo; 132 let BIBO{6-5} = 0; 133 let CR = 0; 134} 135 136class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 137 dag OOL, dag IOL, string asmstr> 138 : I<opcode, OOL, IOL, asmstr, BrB> { 139 bits<14> BD; 140 141 let Inst{6-10} = bo; 142 let Inst{11-15} = bi; 143 let Inst{16-29} = BD; 144 let Inst{30} = aa; 145 let Inst{31} = lk; 146} 147 148// 1.7.4 D-Form 149class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 150 InstrItinClass itin, list<dag> pattern> 151 : I<opcode, OOL, IOL, asmstr, itin> { 152 bits<5> A; 153 bits<5> B; 154 bits<16> C; 155 156 let Pattern = pattern; 157 158 let Inst{6-10} = A; 159 let Inst{11-15} = B; 160 let Inst{16-31} = C; 161} 162 163class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 164 InstrItinClass itin, list<dag> pattern> 165 : I<opcode, OOL, IOL, asmstr, itin> { 166 bits<5> A; 167 bits<21> Addr; 168 169 let Pattern = pattern; 170 171 let Inst{6-10} = A; 172 let Inst{11-15} = Addr{20-16}; // Base Reg 173 let Inst{16-31} = Addr{15-0}; // Displacement 174} 175 176class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 177 InstrItinClass itin, list<dag> pattern> 178 : I<opcode, OOL, IOL, asmstr, itin> { 179 bits<5> A; 180 bits<16> C; 181 bits<5> B; 182 183 let Pattern = pattern; 184 185 let Inst{6-10} = A; 186 let Inst{11-15} = B; 187 let Inst{16-31} = C; 188} 189 190 191class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 192 InstrItinClass itin, list<dag> pattern> 193 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 194 195 // Even though ADDICo does not really have an RC bit, provide 196 // the declaration of one here so that isDOT has something to set. 197 bit RC = 0; 198} 199 200class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 201 InstrItinClass itin, list<dag> pattern> 202 : I<opcode, OOL, IOL, asmstr, itin> { 203 bits<5> A; 204 bits<16> B; 205 206 let Pattern = pattern; 207 208 let Inst{6-10} = A; 209 let Inst{11-15} = 0; 210 let Inst{16-31} = B; 211} 212 213class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 214 InstrItinClass itin, list<dag> pattern> 215 : I<opcode, OOL, IOL, asmstr, itin> { 216 bits<5> B; 217 bits<5> A; 218 bits<16> C; 219 220 let Pattern = pattern; 221 222 let Inst{6-10} = A; 223 let Inst{11-15} = B; 224 let Inst{16-31} = C; 225} 226 227class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 228 InstrItinClass itin, list<dag> pattern> 229 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 230 let A = 0; 231 let Addr = 0; 232} 233 234class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 235 dag OOL, dag IOL, string asmstr, 236 InstrItinClass itin, list<dag> pattern> 237 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 238 bits<5> A; 239 bits<21> Addr; 240 241 let Pattern = pattern; 242 bits<24> LI; 243 244 let Inst{6-29} = LI; 245 let Inst{30} = aa; 246 let Inst{31} = lk; 247 248 let Inst{38-42} = A; 249 let Inst{43-47} = Addr{20-16}; // Base Reg 250 let Inst{48-63} = Addr{15-0}; // Displacement 251} 252 253// This is used to emit BL8+NOP. 254class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 255 dag OOL, dag IOL, string asmstr, 256 InstrItinClass itin, list<dag> pattern> 257 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 258 OOL, IOL, asmstr, itin, pattern> { 259 let A = 0; 260 let Addr = 0; 261} 262 263class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 264 InstrItinClass itin> 265 : I<opcode, OOL, IOL, asmstr, itin> { 266 bits<3> BF; 267 bits<1> L; 268 bits<5> RA; 269 bits<16> I; 270 271 let Inst{6-8} = BF; 272 let Inst{9} = 0; 273 let Inst{10} = L; 274 let Inst{11-15} = RA; 275 let Inst{16-31} = I; 276} 277 278class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 279 InstrItinClass itin> 280 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 281 let L = PPC64; 282} 283 284class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 285 InstrItinClass itin> 286 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 287 288class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 289 InstrItinClass itin> 290 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 291 let L = PPC64; 292} 293 294 295// 1.7.5 DS-Form 296class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 297 InstrItinClass itin, list<dag> pattern> 298 : I<opcode, OOL, IOL, asmstr, itin> { 299 bits<5> RST; 300 bits<19> DS_RA; 301 302 let Pattern = pattern; 303 304 let Inst{6-10} = RST; 305 let Inst{11-15} = DS_RA{18-14}; // Register # 306 let Inst{16-29} = DS_RA{13-0}; // Displacement. 307 let Inst{30-31} = xo; 308} 309 310class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 311 InstrItinClass itin, list<dag> pattern> 312 : I<opcode, OOL, IOL, asmstr, itin> { 313 bits<5> RST; 314 bits<14> DS; 315 bits<5> RA; 316 317 let Pattern = pattern; 318 319 let Inst{6-10} = RST; 320 let Inst{11-15} = RA; 321 let Inst{16-29} = DS; 322 let Inst{30-31} = xo; 323} 324 325// 1.7.6 X-Form 326class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 327 InstrItinClass itin, list<dag> pattern> 328 : I<opcode, OOL, IOL, asmstr, itin> { 329 bits<5> RST; 330 bits<5> A; 331 bits<5> B; 332 333 let Pattern = pattern; 334 335 bit RC = 0; // set by isDOT 336 337 let Inst{6-10} = RST; 338 let Inst{11-15} = A; 339 let Inst{16-20} = B; 340 let Inst{21-30} = xo; 341 let Inst{31} = RC; 342} 343 344// This is the same as XForm_base_r3xo, but the first two operands are swapped 345// when code is emitted. 346class XForm_base_r3xo_swapped 347 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 348 InstrItinClass itin> 349 : I<opcode, OOL, IOL, asmstr, itin> { 350 bits<5> A; 351 bits<5> RST; 352 bits<5> B; 353 354 bit RC = 0; // set by isDOT 355 356 let Inst{6-10} = RST; 357 let Inst{11-15} = A; 358 let Inst{16-20} = B; 359 let Inst{21-30} = xo; 360 let Inst{31} = RC; 361} 362 363 364class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 365 InstrItinClass itin, list<dag> pattern> 366 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 367 368class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 369 InstrItinClass itin, list<dag> pattern> 370 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 371 let RST = 0; 372} 373 374class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 375 InstrItinClass itin, list<dag> pattern> 376 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 377 let Pattern = pattern; 378} 379 380class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 381 InstrItinClass itin, list<dag> pattern> 382 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 383 384class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 385 InstrItinClass itin, list<dag> pattern> 386 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 387 let Pattern = pattern; 388} 389 390class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 391 InstrItinClass itin, list<dag> pattern> 392 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 393 let B = 0; 394 let Pattern = pattern; 395} 396 397class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 398 InstrItinClass itin> 399 : I<opcode, OOL, IOL, asmstr, itin> { 400 bits<3> BF; 401 bits<1> L; 402 bits<5> RA; 403 bits<5> RB; 404 405 let Inst{6-8} = BF; 406 let Inst{9} = 0; 407 let Inst{10} = L; 408 let Inst{11-15} = RA; 409 let Inst{16-20} = RB; 410 let Inst{21-30} = xo; 411 let Inst{31} = 0; 412} 413 414class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 415 InstrItinClass itin> 416 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 417 let L = PPC64; 418} 419 420class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 421 InstrItinClass itin> 422 : I<opcode, OOL, IOL, asmstr, itin> { 423 bits<3> BF; 424 bits<5> FRA; 425 bits<5> FRB; 426 427 let Inst{6-8} = BF; 428 let Inst{9-10} = 0; 429 let Inst{11-15} = FRA; 430 let Inst{16-20} = FRB; 431 let Inst{21-30} = xo; 432 let Inst{31} = 0; 433} 434 435class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 436 InstrItinClass itin, list<dag> pattern> 437 : I<opcode, OOL, IOL, asmstr, itin> { 438 let Pattern = pattern; 439 let Inst{6-10} = 31; 440 let Inst{11-15} = 0; 441 let Inst{16-20} = 0; 442 let Inst{21-30} = xo; 443 let Inst{31} = 0; 444} 445 446class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 447 string asmstr, InstrItinClass itin, list<dag> pattern> 448 : I<opcode, OOL, IOL, asmstr, itin> { 449 let Pattern = pattern; 450 let Inst{6-10} = 0; 451 let Inst{11-15} = 0; 452 let Inst{16-20} = 0; 453 let Inst{21-30} = xo; 454 let Inst{31} = 0; 455} 456 457class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 458 InstrItinClass itin, list<dag> pattern> 459 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 460} 461 462class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 463 InstrItinClass itin, list<dag> pattern> 464 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 465 let A = 0; 466} 467 468class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 469 InstrItinClass itin, list<dag> pattern> 470 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 471} 472 473// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 474// numbers presumably relates to some document, but I haven't found it. 475class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 476 InstrItinClass itin, list<dag> pattern> 477 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 478 let Pattern = pattern; 479 480 bit RC = 0; // set by isDOT 481 482 let Inst{6-10} = RST; 483 let Inst{11-20} = 0; 484 let Inst{21-30} = xo; 485 let Inst{31} = RC; 486} 487class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 488 InstrItinClass itin, list<dag> pattern> 489 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 490 let Pattern = pattern; 491 bits<5> FM; 492 493 bit RC = 0; // set by isDOT 494 495 let Inst{6-10} = FM; 496 let Inst{11-20} = 0; 497 let Inst{21-30} = xo; 498 let Inst{31} = RC; 499} 500 501// DCB_Form - Form X instruction, used for dcb* instructions. 502class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 503 InstrItinClass itin, list<dag> pattern> 504 : I<31, OOL, IOL, asmstr, itin> { 505 bits<5> A; 506 bits<5> B; 507 508 let Pattern = pattern; 509 510 let Inst{6-10} = immfield; 511 let Inst{11-15} = A; 512 let Inst{16-20} = B; 513 let Inst{21-30} = xo; 514 let Inst{31} = 0; 515} 516 517 518// DSS_Form - Form X instruction, used for altivec dss* instructions. 519class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr, 520 InstrItinClass itin, list<dag> pattern> 521 : I<31, OOL, IOL, asmstr, itin> { 522 bits<1> T; 523 bits<2> STRM; 524 bits<5> A; 525 bits<5> B; 526 527 let Pattern = pattern; 528 529 let Inst{6} = T; 530 let Inst{7-8} = 0; 531 let Inst{9-10} = STRM; 532 let Inst{11-15} = A; 533 let Inst{16-20} = B; 534 let Inst{21-30} = xo; 535 let Inst{31} = 0; 536} 537 538// 1.7.7 XL-Form 539class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 540 InstrItinClass itin, list<dag> pattern> 541 : I<opcode, OOL, IOL, asmstr, itin> { 542 bits<5> CRD; 543 bits<5> CRA; 544 bits<5> CRB; 545 546 let Pattern = pattern; 547 548 let Inst{6-10} = CRD; 549 let Inst{11-15} = CRA; 550 let Inst{16-20} = CRB; 551 let Inst{21-30} = xo; 552 let Inst{31} = 0; 553} 554 555class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 556 InstrItinClass itin, list<dag> pattern> 557 : I<opcode, OOL, IOL, asmstr, itin> { 558 bits<5> CRD; 559 560 let Pattern = pattern; 561 562 let Inst{6-10} = CRD; 563 let Inst{11-15} = CRD; 564 let Inst{16-20} = CRD; 565 let Inst{21-30} = xo; 566 let Inst{31} = 0; 567} 568 569class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 570 InstrItinClass itin, list<dag> pattern> 571 : I<opcode, OOL, IOL, asmstr, itin> { 572 bits<5> BO; 573 bits<5> BI; 574 bits<2> BH; 575 576 let Pattern = pattern; 577 578 let Inst{6-10} = BO; 579 let Inst{11-15} = BI; 580 let Inst{16-18} = 0; 581 let Inst{19-20} = BH; 582 let Inst{21-30} = xo; 583 let Inst{31} = lk; 584} 585 586class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 587 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 588 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 589 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 590 bits<3> CR; 591 592 let BO = BIBO{4-0}; 593 let BI{0-1} = BIBO{5-6}; 594 let BI{2-4} = CR{0-2}; 595 let BH = 0; 596} 597 598 599class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 600 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 601 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 602 let BO = bo; 603 let BI = bi; 604 let BH = 0; 605} 606 607class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 608 InstrItinClass itin> 609 : I<opcode, OOL, IOL, asmstr, itin> { 610 bits<3> BF; 611 bits<3> BFA; 612 613 let Inst{6-8} = BF; 614 let Inst{9-10} = 0; 615 let Inst{11-13} = BFA; 616 let Inst{14-15} = 0; 617 let Inst{16-20} = 0; 618 let Inst{21-30} = xo; 619 let Inst{31} = 0; 620} 621 622// 1.7.8 XFX-Form 623class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 624 InstrItinClass itin> 625 : I<opcode, OOL, IOL, asmstr, itin> { 626 bits<5> RT; 627 bits<10> SPR; 628 629 let Inst{6-10} = RT; 630 let Inst{11} = SPR{4}; 631 let Inst{12} = SPR{3}; 632 let Inst{13} = SPR{2}; 633 let Inst{14} = SPR{1}; 634 let Inst{15} = SPR{0}; 635 let Inst{16} = SPR{9}; 636 let Inst{17} = SPR{8}; 637 let Inst{18} = SPR{7}; 638 let Inst{19} = SPR{6}; 639 let Inst{20} = SPR{5}; 640 let Inst{21-30} = xo; 641 let Inst{31} = 0; 642} 643 644class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 645 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 646 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 647 let SPR = spr; 648} 649 650class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 651 InstrItinClass itin> 652 : I<opcode, OOL, IOL, asmstr, itin> { 653 bits<5> RT; 654 655 let Inst{6-10} = RT; 656 let Inst{11-20} = 0; 657 let Inst{21-30} = xo; 658 let Inst{31} = 0; 659} 660 661class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 662 InstrItinClass itin> 663 : I<opcode, OOL, IOL, asmstr, itin> { 664 bits<8> FXM; 665 bits<5> rS; 666 667 let Inst{6-10} = rS; 668 let Inst{11} = 0; 669 let Inst{12-19} = FXM; 670 let Inst{20} = 0; 671 let Inst{21-30} = xo; 672 let Inst{31} = 0; 673} 674 675class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 676 InstrItinClass itin> 677 : I<opcode, OOL, IOL, asmstr, itin> { 678 bits<5> ST; 679 bits<8> FXM; 680 681 let Inst{6-10} = ST; 682 let Inst{11} = 1; 683 let Inst{12-19} = FXM; 684 let Inst{20} = 0; 685 let Inst{21-30} = xo; 686 let Inst{31} = 0; 687} 688 689class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 690 InstrItinClass itin> 691 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 692 693class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 694 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 695 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 696 let SPR = spr; 697} 698 699// XFL-Form - MTFSF 700// This is probably 1.7.9, but I don't have the reference that uses this 701// numbering scheme... 702class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 703 InstrItinClass itin, list<dag>pattern> 704 : I<opcode, OOL, IOL, asmstr, itin> { 705 bits<8> FM; 706 bits<5> rT; 707 708 bit RC = 0; // set by isDOT 709 let Pattern = pattern; 710 711 let Inst{6} = 0; 712 let Inst{7-14} = FM; 713 let Inst{15} = 0; 714 let Inst{16-20} = rT; 715 let Inst{21-30} = xo; 716 let Inst{31} = RC; 717} 718 719// 1.7.10 XS-Form - SRADI. 720class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 721 InstrItinClass itin, list<dag> pattern> 722 : I<opcode, OOL, IOL, asmstr, itin> { 723 bits<5> A; 724 bits<5> RS; 725 bits<6> SH; 726 727 bit RC = 0; // set by isDOT 728 let Pattern = pattern; 729 730 let Inst{6-10} = RS; 731 let Inst{11-15} = A; 732 let Inst{16-20} = SH{4,3,2,1,0}; 733 let Inst{21-29} = xo; 734 let Inst{30} = SH{5}; 735 let Inst{31} = RC; 736} 737 738// 1.7.11 XO-Form 739class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 740 InstrItinClass itin, list<dag> pattern> 741 : I<opcode, OOL, IOL, asmstr, itin> { 742 bits<5> RT; 743 bits<5> RA; 744 bits<5> RB; 745 746 let Pattern = pattern; 747 748 bit RC = 0; // set by isDOT 749 750 let Inst{6-10} = RT; 751 let Inst{11-15} = RA; 752 let Inst{16-20} = RB; 753 let Inst{21} = oe; 754 let Inst{22-30} = xo; 755 let Inst{31} = RC; 756} 757 758class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 759 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 760 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 761 let RB = 0; 762} 763 764// 1.7.12 A-Form 765class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 766 InstrItinClass itin, list<dag> pattern> 767 : I<opcode, OOL, IOL, asmstr, itin> { 768 bits<5> FRT; 769 bits<5> FRA; 770 bits<5> FRC; 771 bits<5> FRB; 772 773 let Pattern = pattern; 774 775 bit RC = 0; // set by isDOT 776 777 let Inst{6-10} = FRT; 778 let Inst{11-15} = FRA; 779 let Inst{16-20} = FRB; 780 let Inst{21-25} = FRC; 781 let Inst{26-30} = xo; 782 let Inst{31} = RC; 783} 784 785class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 786 InstrItinClass itin, list<dag> pattern> 787 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 788 let FRC = 0; 789} 790 791class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 792 InstrItinClass itin, list<dag> pattern> 793 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 794 let FRB = 0; 795} 796 797class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 798 InstrItinClass itin, list<dag> pattern> 799 : I<opcode, OOL, IOL, asmstr, itin> { 800 bits<5> RT; 801 bits<5> RA; 802 bits<5> RB; 803 bits<5> COND; 804 805 let Pattern = pattern; 806 807 let Inst{6-10} = RT; 808 let Inst{11-15} = RA; 809 let Inst{16-20} = RB; 810 let Inst{21-25} = COND; 811 let Inst{26-30} = xo; 812 let Inst{31} = 0; 813} 814 815// 1.7.13 M-Form 816class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 817 InstrItinClass itin, list<dag> pattern> 818 : I<opcode, OOL, IOL, asmstr, itin> { 819 bits<5> RA; 820 bits<5> RS; 821 bits<5> RB; 822 bits<5> MB; 823 bits<5> ME; 824 825 let Pattern = pattern; 826 827 bit RC = 0; // set by isDOT 828 829 let Inst{6-10} = RS; 830 let Inst{11-15} = RA; 831 let Inst{16-20} = RB; 832 let Inst{21-25} = MB; 833 let Inst{26-30} = ME; 834 let Inst{31} = RC; 835} 836 837class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 838 InstrItinClass itin, list<dag> pattern> 839 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 840} 841 842// 1.7.14 MD-Form 843class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 844 InstrItinClass itin, list<dag> pattern> 845 : I<opcode, OOL, IOL, asmstr, itin> { 846 bits<5> RA; 847 bits<5> RS; 848 bits<6> SH; 849 bits<6> MBE; 850 851 let Pattern = pattern; 852 853 bit RC = 0; // set by isDOT 854 855 let Inst{6-10} = RS; 856 let Inst{11-15} = RA; 857 let Inst{16-20} = SH{4,3,2,1,0}; 858 let Inst{21-26} = MBE{4,3,2,1,0,5}; 859 let Inst{27-29} = xo; 860 let Inst{30} = SH{5}; 861 let Inst{31} = RC; 862} 863 864class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 865 InstrItinClass itin, list<dag> pattern> 866 : I<opcode, OOL, IOL, asmstr, itin> { 867 bits<5> RA; 868 bits<5> RS; 869 bits<5> RB; 870 bits<6> MBE; 871 872 let Pattern = pattern; 873 874 bit RC = 0; // set by isDOT 875 876 let Inst{6-10} = RS; 877 let Inst{11-15} = RA; 878 let Inst{16-20} = RB; 879 let Inst{21-26} = MBE{4,3,2,1,0,5}; 880 let Inst{27-30} = xo; 881 let Inst{31} = RC; 882} 883 884 885// E-1 VA-Form 886 887// VAForm_1 - DACB ordering. 888class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 889 InstrItinClass itin, list<dag> pattern> 890 : I<4, OOL, IOL, asmstr, itin> { 891 bits<5> VD; 892 bits<5> VA; 893 bits<5> VC; 894 bits<5> VB; 895 896 let Pattern = pattern; 897 898 let Inst{6-10} = VD; 899 let Inst{11-15} = VA; 900 let Inst{16-20} = VB; 901 let Inst{21-25} = VC; 902 let Inst{26-31} = xo; 903} 904 905// VAForm_1a - DABC ordering. 906class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 907 InstrItinClass itin, list<dag> pattern> 908 : I<4, OOL, IOL, asmstr, itin> { 909 bits<5> VD; 910 bits<5> VA; 911 bits<5> VB; 912 bits<5> VC; 913 914 let Pattern = pattern; 915 916 let Inst{6-10} = VD; 917 let Inst{11-15} = VA; 918 let Inst{16-20} = VB; 919 let Inst{21-25} = VC; 920 let Inst{26-31} = xo; 921} 922 923class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 924 InstrItinClass itin, list<dag> pattern> 925 : I<4, OOL, IOL, asmstr, itin> { 926 bits<5> VD; 927 bits<5> VA; 928 bits<5> VB; 929 bits<4> SH; 930 931 let Pattern = pattern; 932 933 let Inst{6-10} = VD; 934 let Inst{11-15} = VA; 935 let Inst{16-20} = VB; 936 let Inst{21} = 0; 937 let Inst{22-25} = SH; 938 let Inst{26-31} = xo; 939} 940 941// E-2 VX-Form 942class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 943 InstrItinClass itin, list<dag> pattern> 944 : I<4, OOL, IOL, asmstr, itin> { 945 bits<5> VD; 946 bits<5> VA; 947 bits<5> VB; 948 949 let Pattern = pattern; 950 951 let Inst{6-10} = VD; 952 let Inst{11-15} = VA; 953 let Inst{16-20} = VB; 954 let Inst{21-31} = xo; 955} 956 957class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 958 InstrItinClass itin, list<dag> pattern> 959 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 960 let VA = VD; 961 let VB = VD; 962} 963 964 965class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 966 InstrItinClass itin, list<dag> pattern> 967 : I<4, OOL, IOL, asmstr, itin> { 968 bits<5> VD; 969 bits<5> VB; 970 971 let Pattern = pattern; 972 973 let Inst{6-10} = VD; 974 let Inst{11-15} = 0; 975 let Inst{16-20} = VB; 976 let Inst{21-31} = xo; 977} 978 979class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 980 InstrItinClass itin, list<dag> pattern> 981 : I<4, OOL, IOL, asmstr, itin> { 982 bits<5> VD; 983 bits<5> IMM; 984 985 let Pattern = pattern; 986 987 let Inst{6-10} = VD; 988 let Inst{11-15} = IMM; 989 let Inst{16-20} = 0; 990 let Inst{21-31} = xo; 991} 992 993/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 994class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 995 InstrItinClass itin, list<dag> pattern> 996 : I<4, OOL, IOL, asmstr, itin> { 997 bits<5> VD; 998 999 let Pattern = pattern; 1000 1001 let Inst{6-10} = VD; 1002 let Inst{11-15} = 0; 1003 let Inst{16-20} = 0; 1004 let Inst{21-31} = xo; 1005} 1006 1007/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 1008class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 1009 InstrItinClass itin, list<dag> pattern> 1010 : I<4, OOL, IOL, asmstr, itin> { 1011 bits<5> VB; 1012 1013 let Pattern = pattern; 1014 1015 let Inst{6-10} = 0; 1016 let Inst{11-15} = 0; 1017 let Inst{16-20} = VB; 1018 let Inst{21-31} = xo; 1019} 1020 1021// E-4 VXR-Form 1022class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 1023 InstrItinClass itin, list<dag> pattern> 1024 : I<4, OOL, IOL, asmstr, itin> { 1025 bits<5> VD; 1026 bits<5> VA; 1027 bits<5> VB; 1028 bit RC = 0; 1029 1030 let Pattern = pattern; 1031 1032 let Inst{6-10} = VD; 1033 let Inst{11-15} = VA; 1034 let Inst{16-20} = VB; 1035 let Inst{21} = RC; 1036 let Inst{22-31} = xo; 1037} 1038 1039//===----------------------------------------------------------------------===// 1040class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 1041 : I<0, OOL, IOL, asmstr, NoItinerary> { 1042 let isCodeGenOnly = 1; 1043 let PPC64 = 0; 1044 let Pattern = pattern; 1045 let Inst{31-0} = 0; 1046} 1047