1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// PowerPC instruction formats 13 14class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 15 : Instruction { 16 field bits<32> Inst; 17 field bits<32> SoftFail = 0; 18 let Size = 4; 19 20 bit PPC64 = 0; // Default value, override with isPPC64 21 22 let Namespace = "PPC"; 23 let Inst{0-5} = opcode; 24 let OutOperandList = OOL; 25 let InOperandList = IOL; 26 let AsmString = asmstr; 27 let Itinerary = itin; 28 29 bits<1> PPC970_First = 0; 30 bits<1> PPC970_Single = 0; 31 bits<1> PPC970_Cracked = 0; 32 bits<3> PPC970_Unit = 0; 33 34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 35 /// these must be reflected there! See comments there for what these are. 36 let TSFlags{0} = PPC970_First; 37 let TSFlags{1} = PPC970_Single; 38 let TSFlags{2} = PPC970_Cracked; 39 let TSFlags{5-3} = PPC970_Unit; 40 41 /// Indicate that the VSX instruction is to use VSX numbering/encoding. 42 /// Since ISA 3.0, there are scalar instructions that use the upper 43 /// half of the VSX register set only. Rather than adding further complexity 44 /// to the register class set, the VSX registers just include the Altivec 45 /// registers and this flag decides the numbering to be used for them. 46 bits<1> UseVSXReg = 0; 47 let TSFlags{6} = UseVSXReg; 48 49 // Fields used for relation models. 50 string BaseName = ""; 51 52 // For cases where multiple instruction definitions really represent the 53 // same underlying instruction but with one definition for 64-bit arguments 54 // and one for 32-bit arguments, this bit breaks the degeneracy between 55 // the two forms and allows TableGen to generate mapping tables. 56 bit Interpretation64Bit = 0; 57} 58 59class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 60class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 61class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 62class PPC970_MicroCode; 63 64class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 65class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 66class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 67class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 68class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 69class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 70class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 71class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 72 73class UseVSXReg { bits<1> UseVSXReg = 1; } 74 75// Two joined instructions; used to emit two adjacent instructions as one. 76// The itinerary from the first instruction is used for scheduling and 77// classification. 78class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 79 InstrItinClass itin> 80 : Instruction { 81 field bits<64> Inst; 82 field bits<64> SoftFail = 0; 83 let Size = 8; 84 85 bit PPC64 = 0; // Default value, override with isPPC64 86 87 let Namespace = "PPC"; 88 let Inst{0-5} = opcode1; 89 let Inst{32-37} = opcode2; 90 let OutOperandList = OOL; 91 let InOperandList = IOL; 92 let AsmString = asmstr; 93 let Itinerary = itin; 94 95 bits<1> PPC970_First = 0; 96 bits<1> PPC970_Single = 0; 97 bits<1> PPC970_Cracked = 0; 98 bits<3> PPC970_Unit = 0; 99 100 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 101 /// these must be reflected there! See comments there for what these are. 102 let TSFlags{0} = PPC970_First; 103 let TSFlags{1} = PPC970_Single; 104 let TSFlags{2} = PPC970_Cracked; 105 let TSFlags{5-3} = PPC970_Unit; 106 107 // Fields used for relation models. 108 string BaseName = ""; 109 bit Interpretation64Bit = 0; 110} 111 112// 1.7.1 I-Form 113class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 114 InstrItinClass itin, list<dag> pattern> 115 : I<opcode, OOL, IOL, asmstr, itin> { 116 let Pattern = pattern; 117 bits<24> LI; 118 119 let Inst{6-29} = LI; 120 let Inst{30} = aa; 121 let Inst{31} = lk; 122} 123 124// 1.7.2 B-Form 125class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 126 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 127 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 128 bits<3> CR; 129 bits<14> BD; 130 131 bits<5> BI; 132 let BI{0-1} = BIBO{5-6}; 133 let BI{2-4} = CR{0-2}; 134 135 let Inst{6-10} = BIBO{4-0}; 136 let Inst{11-15} = BI; 137 let Inst{16-29} = BD; 138 let Inst{30} = aa; 139 let Inst{31} = lk; 140} 141 142class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 143 string asmstr> 144 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 145 let BIBO{4-0} = bo; 146 let BIBO{6-5} = 0; 147 let CR = 0; 148} 149 150class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 151 dag OOL, dag IOL, string asmstr> 152 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 153 bits<14> BD; 154 155 let Inst{6-10} = bo; 156 let Inst{11-15} = bi; 157 let Inst{16-29} = BD; 158 let Inst{30} = aa; 159 let Inst{31} = lk; 160} 161 162class BForm_3<bits<6> opcode, bit aa, bit lk, 163 dag OOL, dag IOL, string asmstr> 164 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 165 bits<5> BO; 166 bits<5> BI; 167 bits<14> BD; 168 169 let Inst{6-10} = BO; 170 let Inst{11-15} = BI; 171 let Inst{16-29} = BD; 172 let Inst{30} = aa; 173 let Inst{31} = lk; 174} 175 176class BForm_3_at<bits<6> opcode, bit aa, bit lk, 177 dag OOL, dag IOL, string asmstr> 178 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 179 bits<5> BO; 180 bits<2> at; 181 bits<5> BI; 182 bits<14> BD; 183 184 let Inst{6-8} = BO{4-2}; 185 let Inst{9-10} = at; 186 let Inst{11-15} = BI; 187 let Inst{16-29} = BD; 188 let Inst{30} = aa; 189 let Inst{31} = lk; 190} 191 192class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, 193 dag OOL, dag IOL, string asmstr> 194 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 195 bits<5> BI; 196 bits<14> BD; 197 198 let Inst{6-10} = bo; 199 let Inst{11-15} = BI; 200 let Inst{16-29} = BD; 201 let Inst{30} = aa; 202 let Inst{31} = lk; 203} 204 205// 1.7.3 SC-Form 206class SCForm<bits<6> opcode, bits<1> xo, 207 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 208 list<dag> pattern> 209 : I<opcode, OOL, IOL, asmstr, itin> { 210 bits<7> LEV; 211 212 let Pattern = pattern; 213 214 let Inst{20-26} = LEV; 215 let Inst{30} = xo; 216} 217 218// 1.7.4 D-Form 219class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 220 InstrItinClass itin, list<dag> pattern> 221 : I<opcode, OOL, IOL, asmstr, itin> { 222 bits<5> A; 223 bits<5> B; 224 bits<16> C; 225 226 let Pattern = pattern; 227 228 let Inst{6-10} = A; 229 let Inst{11-15} = B; 230 let Inst{16-31} = C; 231} 232 233class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 234 InstrItinClass itin, list<dag> pattern> 235 : I<opcode, OOL, IOL, asmstr, itin> { 236 bits<5> A; 237 bits<21> Addr; 238 239 let Pattern = pattern; 240 241 let Inst{6-10} = A; 242 let Inst{11-15} = Addr{20-16}; // Base Reg 243 let Inst{16-31} = Addr{15-0}; // Displacement 244} 245 246class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 247 InstrItinClass itin, list<dag> pattern> 248 : I<opcode, OOL, IOL, asmstr, itin> { 249 bits<5> A; 250 bits<16> C; 251 bits<5> B; 252 253 let Pattern = pattern; 254 255 let Inst{6-10} = A; 256 let Inst{11-15} = B; 257 let Inst{16-31} = C; 258} 259 260 261class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 262 InstrItinClass itin, list<dag> pattern> 263 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 264 265 // Even though ADDICo does not really have an RC bit, provide 266 // the declaration of one here so that isDOT has something to set. 267 bit RC = 0; 268} 269 270class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 271 InstrItinClass itin, list<dag> pattern> 272 : I<opcode, OOL, IOL, asmstr, itin> { 273 bits<5> A; 274 bits<16> B; 275 276 let Pattern = pattern; 277 278 let Inst{6-10} = A; 279 let Inst{11-15} = 0; 280 let Inst{16-31} = B; 281} 282 283class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 284 InstrItinClass itin, list<dag> pattern> 285 : I<opcode, OOL, IOL, asmstr, itin> { 286 bits<5> B; 287 bits<5> A; 288 bits<16> C; 289 290 let Pattern = pattern; 291 292 let Inst{6-10} = A; 293 let Inst{11-15} = B; 294 let Inst{16-31} = C; 295} 296 297class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 298 InstrItinClass itin, list<dag> pattern> 299 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 300 let A = 0; 301 let Addr = 0; 302} 303 304class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 305 string asmstr, InstrItinClass itin, 306 list<dag> pattern> 307 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 308 let A = R; 309 let B = R; 310 let C = 0; 311} 312 313class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 314 dag OOL, dag IOL, string asmstr, 315 InstrItinClass itin, list<dag> pattern> 316 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 317 bits<5> A; 318 bits<21> Addr; 319 320 let Pattern = pattern; 321 bits<24> LI; 322 323 let Inst{6-29} = LI; 324 let Inst{30} = aa; 325 let Inst{31} = lk; 326 327 let Inst{38-42} = A; 328 let Inst{43-47} = Addr{20-16}; // Base Reg 329 let Inst{48-63} = Addr{15-0}; // Displacement 330} 331 332// This is used to emit BL8+NOP. 333class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 334 dag OOL, dag IOL, string asmstr, 335 InstrItinClass itin, list<dag> pattern> 336 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 337 OOL, IOL, asmstr, itin, pattern> { 338 let A = 0; 339 let Addr = 0; 340} 341 342class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 343 InstrItinClass itin> 344 : I<opcode, OOL, IOL, asmstr, itin> { 345 bits<3> BF; 346 bits<1> L; 347 bits<5> RA; 348 bits<16> I; 349 350 let Inst{6-8} = BF; 351 let Inst{9} = 0; 352 let Inst{10} = L; 353 let Inst{11-15} = RA; 354 let Inst{16-31} = I; 355} 356 357class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 358 InstrItinClass itin> 359 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 360 let L = PPC64; 361} 362 363class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 364 InstrItinClass itin> 365 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 366 367class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 368 InstrItinClass itin> 369 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 370 let L = PPC64; 371} 372 373 374// 1.7.5 DS-Form 375class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 376 InstrItinClass itin, list<dag> pattern> 377 : I<opcode, OOL, IOL, asmstr, itin> { 378 bits<5> RST; 379 bits<19> DS_RA; 380 381 let Pattern = pattern; 382 383 let Inst{6-10} = RST; 384 let Inst{11-15} = DS_RA{18-14}; // Register # 385 let Inst{16-29} = DS_RA{13-0}; // Displacement. 386 let Inst{30-31} = xo; 387} 388 389// DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO] 390class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 391 string asmstr, InstrItinClass itin, list<dag> pattern> 392 : I<opcode, OOL, IOL, asmstr, itin> { 393 bits<6> XT; 394 bits<17> DS_RA; 395 396 let Pattern = pattern; 397 398 let Inst{6-10} = XT{4-0}; 399 let Inst{11-15} = DS_RA{16-12}; // Register # 400 let Inst{16-27} = DS_RA{11-0}; // Displacement. 401 let Inst{28} = XT{5}; 402 let Inst{29-31} = xo; 403} 404 405// 1.7.6 X-Form 406class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 407 InstrItinClass itin, list<dag> pattern> 408 : I<opcode, OOL, IOL, asmstr, itin> { 409 bits<5> RST; 410 bits<5> A; 411 bits<5> B; 412 413 let Pattern = pattern; 414 415 bit RC = 0; // set by isDOT 416 417 let Inst{6-10} = RST; 418 let Inst{11-15} = A; 419 let Inst{16-20} = B; 420 let Inst{21-30} = xo; 421 let Inst{31} = RC; 422} 423 424class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr, 425 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 426 let RST = 0; 427} 428 429class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 430 InstrItinClass itin> 431 : I<opcode, OOL, IOL, asmstr, itin> { 432 let Inst{21-30} = xo; 433} 434 435// This is the same as XForm_base_r3xo, but the first two operands are swapped 436// when code is emitted. 437class XForm_base_r3xo_swapped 438 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 439 InstrItinClass itin> 440 : I<opcode, OOL, IOL, asmstr, itin> { 441 bits<5> A; 442 bits<5> RST; 443 bits<5> B; 444 445 bit RC = 0; // set by isDOT 446 447 let Inst{6-10} = RST; 448 let Inst{11-15} = A; 449 let Inst{16-20} = B; 450 let Inst{21-30} = xo; 451 let Inst{31} = RC; 452} 453 454 455class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 456 InstrItinClass itin, list<dag> pattern> 457 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 458 459class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 460 InstrItinClass itin, list<dag> pattern> 461 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 462 let RST = 0; 463} 464 465class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 466 InstrItinClass itin, list<dag> pattern> 467 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 468 let A = 0; 469 let B = 0; 470} 471 472class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 473 InstrItinClass itin, list<dag> pattern> 474 : I<opcode, OOL, IOL, asmstr, itin> { 475 bits<5> RST; 476 bits<5> A; 477 bits<1> WS; 478 479 let Pattern = pattern; 480 481 let Inst{6-10} = RST; 482 let Inst{11-15} = A; 483 let Inst{20} = WS; 484 let Inst{21-30} = xo; 485 let Inst{31} = 0; 486} 487 488class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 489 InstrItinClass itin, list<dag> pattern> 490 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 491 let Pattern = pattern; 492} 493 494class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 495 InstrItinClass itin, list<dag> pattern> 496 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 497 498class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 499 InstrItinClass itin, list<dag> pattern> 500 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 501 let Pattern = pattern; 502} 503 504class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 505 InstrItinClass itin, list<dag> pattern> 506 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 507 let B = 0; 508 let Pattern = pattern; 509} 510 511class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 512 InstrItinClass itin> 513 : I<opcode, OOL, IOL, asmstr, itin> { 514 bits<3> BF; 515 bits<1> L; 516 bits<5> RA; 517 bits<5> RB; 518 519 let Inst{6-8} = BF; 520 let Inst{9} = 0; 521 let Inst{10} = L; 522 let Inst{11-15} = RA; 523 let Inst{16-20} = RB; 524 let Inst{21-30} = xo; 525 let Inst{31} = 0; 526} 527 528class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 529 InstrItinClass itin> 530 : I<opcode, OOL, IOL, asmstr, itin> { 531 bits<4> CT; 532 bits<5> RA; 533 bits<5> RB; 534 535 let Inst{6} = 0; 536 let Inst{7-10} = CT; 537 let Inst{11-15} = RA; 538 let Inst{16-20} = RB; 539 let Inst{21-30} = xo; 540 let Inst{31} = 0; 541} 542 543class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 544 InstrItinClass itin> 545 : I<opcode, OOL, IOL, asmstr, itin> { 546 bits<5> RS; 547 bits<4> SR; 548 549 let Inst{6-10} = RS; 550 let Inst{12-15} = SR; 551 let Inst{21-30} = xo; 552} 553 554class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 555 InstrItinClass itin> 556 : I<opcode, OOL, IOL, asmstr, itin> { 557 bits<5> MO; 558 559 let Inst{6-10} = MO; 560 let Inst{21-30} = xo; 561} 562 563class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 564 InstrItinClass itin> 565 : I<opcode, OOL, IOL, asmstr, itin> { 566 bits<5> RS; 567 bits<5> RB; 568 569 let Inst{6-10} = RS; 570 let Inst{16-20} = RB; 571 let Inst{21-30} = xo; 572} 573 574class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 575 InstrItinClass itin> 576 : I<opcode, OOL, IOL, asmstr, itin> { 577 bits<5> RS; 578 bits<1> L; 579 580 let Inst{6-10} = RS; 581 let Inst{15} = L; 582 let Inst{21-30} = xo; 583} 584 585class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 586 InstrItinClass itin> 587 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 588 let L = PPC64; 589} 590 591class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 592 InstrItinClass itin> 593 : I<opcode, OOL, IOL, asmstr, itin> { 594 bits<3> BF; 595 bits<5> FRA; 596 bits<5> FRB; 597 598 let Inst{6-8} = BF; 599 let Inst{9-10} = 0; 600 let Inst{11-15} = FRA; 601 let Inst{16-20} = FRB; 602 let Inst{21-30} = xo; 603 let Inst{31} = 0; 604} 605 606class XForm_17a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 607 InstrItinClass itin> 608 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin > { 609 let FRA = 0; 610} 611 612// Used for QPX 613class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 614 InstrItinClass itin, list<dag> pattern> 615 : I<opcode, OOL, IOL, asmstr, itin> { 616 bits<5> FRT; 617 bits<5> FRA; 618 bits<5> FRB; 619 620 let Pattern = pattern; 621 622 let Inst{6-10} = FRT; 623 let Inst{11-15} = FRA; 624 let Inst{16-20} = FRB; 625 let Inst{21-30} = xo; 626 let Inst{31} = 0; 627} 628 629class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 630 InstrItinClass itin, list<dag> pattern> 631 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 632 let FRA = 0; 633} 634 635class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr, 636 InstrItinClass itin, list<dag> pattern> 637 : I<opcode, OOL, IOL, asmstr, itin> { 638 bits<5> FRT; 639 bits<5> FRA; 640 bits<5> FRB; 641 bits<4> tttt; 642 643 let Pattern = pattern; 644 645 let Inst{6-10} = FRT; 646 let Inst{11-15} = FRA; 647 let Inst{16-20} = FRB; 648 let Inst{21-24} = tttt; 649 let Inst{25-30} = xo; 650 let Inst{31} = 0; 651} 652 653class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 654 InstrItinClass itin, list<dag> pattern> 655 : I<opcode, OOL, IOL, asmstr, itin> { 656 let Pattern = pattern; 657 let Inst{6-10} = 31; 658 let Inst{11-15} = 0; 659 let Inst{16-20} = 0; 660 let Inst{21-30} = xo; 661 let Inst{31} = 0; 662} 663 664class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 665 string asmstr, InstrItinClass itin, list<dag> pattern> 666 : I<opcode, OOL, IOL, asmstr, itin> { 667 bits<2> L; 668 669 let Pattern = pattern; 670 let Inst{6-8} = 0; 671 let Inst{9-10} = L; 672 let Inst{11-15} = 0; 673 let Inst{16-20} = 0; 674 let Inst{21-30} = xo; 675 let Inst{31} = 0; 676} 677 678class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 679 string asmstr, InstrItinClass itin, list<dag> pattern> 680 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 681 let L = 0; 682} 683 684class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 685 InstrItinClass itin, list<dag> pattern> 686 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 687} 688 689class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 690 InstrItinClass itin, list<dag> pattern> 691 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 692 let A = 0; 693} 694 695class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 696 InstrItinClass itin, list<dag> pattern> 697 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 698} 699 700// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 701// numbers presumably relates to some document, but I haven't found it. 702class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 703 InstrItinClass itin, list<dag> pattern> 704 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 705 let Pattern = pattern; 706 707 bit RC = 0; // set by isDOT 708 709 let Inst{6-10} = RST; 710 let Inst{11-20} = 0; 711 let Inst{21-30} = xo; 712 let Inst{31} = RC; 713} 714class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 715 InstrItinClass itin, list<dag> pattern> 716 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 717 let Pattern = pattern; 718 bits<5> FM; 719 720 bit RC = 0; // set by isDOT 721 722 let Inst{6-10} = FM; 723 let Inst{11-20} = 0; 724 let Inst{21-30} = xo; 725 let Inst{31} = RC; 726} 727 728class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 729 InstrItinClass itin, list<dag> pattern> 730 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 731 let RST = 0; 732 let A = 0; 733 let B = 0; 734} 735 736class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 737 InstrItinClass itin, list<dag> pattern> 738 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 739 let RST = 0; 740 let A = 0; 741} 742 743class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 744 string asmstr, InstrItinClass itin, list<dag> pattern> 745 : I<opcode, OOL, IOL, asmstr, itin> { 746 bit R; 747 748 bit RC = 1; 749 750 let Inst{6-9} = 0; 751 let Inst{10} = R; 752 let Inst{11-20} = 0; 753 let Inst{21-30} = xo; 754 let Inst{31} = RC; 755} 756 757class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 758 string asmstr, InstrItinClass itin, list<dag> pattern> 759 : I<opcode, OOL, IOL, asmstr, itin> { 760 bit A; 761 762 bit RC = 1; 763 764 let Inst{6} = A; 765 let Inst{7-20} = 0; 766 let Inst{21-30} = xo; 767 let Inst{31} = RC; 768} 769 770class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 771 InstrItinClass itin, list<dag> pattern> 772 : I<opcode, OOL, IOL, asmstr, itin> { 773 bit L; 774 775 bit RC = 0; // set by isDOT 776 777 let Inst{7-9} = 0; 778 let Inst{10} = L; 779 let Inst{11-20} = 0; 780 let Inst{21-30} = xo; 781 let Inst{31} = RC; 782} 783 784class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 785 InstrItinClass itin, list<dag> pattern> 786 : I<opcode, OOL, IOL, asmstr, itin> { 787 bits<3> BF; 788 789 bit RC = 0; 790 791 let Inst{6-8} = BF; 792 let Inst{9-20} = 0; 793 let Inst{21-30} = xo; 794 let Inst{31} = RC; 795} 796 797// [PO RT RA RB XO /] 798class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 799 string asmstr, InstrItinClass itin, list<dag> pattern> 800 : I<opcode, OOL, IOL, asmstr, itin> { 801 bits<3> BF; 802 bits<1> L; 803 bits<5> RA; 804 bits<5> RB; 805 806 let Pattern = pattern; 807 808 let Inst{6-8} = BF; 809 let Inst{9} = 0; 810 let Inst{10} = L; 811 let Inst{11-15} = RA; 812 let Inst{16-20} = RB; 813 let Inst{21-30} = xo; 814 let Inst{31} = 0; 815} 816 817// Same as XForm_17 but with GPR's and new naming convention 818class X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 819 string asmstr, InstrItinClass itin, list<dag> pattern> 820 : I<opcode, OOL, IOL, asmstr, itin> { 821 bits<3> BF; 822 bits<5> RA; 823 bits<5> RB; 824 825 let Pattern = pattern; 826 827 let Inst{6-8} = BF; 828 let Inst{9-10} = 0; 829 let Inst{11-15} = RA; 830 let Inst{16-20} = RB; 831 let Inst{21-30} = xo; 832 let Inst{31} = 0; 833} 834 835// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO] 836class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, 837 string asmstr, InstrItinClass itin, list<dag> pattern> 838 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 839 let A = xo2; 840} 841 842class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 843 string asmstr, InstrItinClass itin, list<dag> pattern> 844 : I<opcode, OOL, IOL, asmstr, itin> { 845 bits<3> BF; 846 bits<7> DCMX; 847 bits<5> VB; 848 849 let Pattern = pattern; 850 851 let Inst{6-8} = BF; 852 let Inst{9-15} = DCMX; 853 let Inst{16-20} = VB; 854 let Inst{21-30} = xo; 855 let Inst{31} = 0; 856} 857 858class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 859 string asmstr, InstrItinClass itin, list<dag> pattern> 860 : I<opcode, OOL, IOL, asmstr, itin> { 861 bits<6> XT; 862 bits<8> IMM8; 863 864 let Pattern = pattern; 865 866 let Inst{6-10} = XT{4-0}; 867 let Inst{11-12} = 0; 868 let Inst{13-20} = IMM8; 869 let Inst{21-30} = xo; 870 let Inst{31} = XT{5}; 871} 872 873// XForm_base_r3xo for instructions such as P9 atomics where we don't want 874// to specify an SDAG pattern for matching. 875class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 876 string asmstr, InstrItinClass itin> 877 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, []> { 878} 879 880class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 881 InstrItinClass itin> 882 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> { 883 let FRA = 0; 884 let FRB = 0; 885} 886 887// [PO /// L RA RB XO /] 888class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 889 string asmstr, InstrItinClass itin, list<dag> pattern> 890 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 891 let BF = 0; 892 let Pattern = pattern; 893 894 bit RC = 0; 895 let Inst{31} = RC; 896} 897 898// XX*-Form (VSX) 899class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 900 InstrItinClass itin, list<dag> pattern> 901 : I<opcode, OOL, IOL, asmstr, itin> { 902 bits<6> XT; 903 bits<5> A; 904 bits<5> B; 905 906 let Pattern = pattern; 907 908 let Inst{6-10} = XT{4-0}; 909 let Inst{11-15} = A; 910 let Inst{16-20} = B; 911 let Inst{21-30} = xo; 912 let Inst{31} = XT{5}; 913} 914 915class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 916 string asmstr, InstrItinClass itin, list<dag> pattern> 917 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 918 let B = 0; 919} 920 921class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 922 InstrItinClass itin, list<dag> pattern> 923 : I<opcode, OOL, IOL, asmstr, itin> { 924 bits<6> XT; 925 bits<6> XB; 926 927 let Pattern = pattern; 928 929 let Inst{6-10} = XT{4-0}; 930 let Inst{11-15} = 0; 931 let Inst{16-20} = XB{4-0}; 932 let Inst{21-29} = xo; 933 let Inst{30} = XB{5}; 934 let Inst{31} = XT{5}; 935} 936 937class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 938 InstrItinClass itin, list<dag> pattern> 939 : I<opcode, OOL, IOL, asmstr, itin> { 940 bits<3> CR; 941 bits<6> XB; 942 943 let Pattern = pattern; 944 945 let Inst{6-8} = CR; 946 let Inst{9-15} = 0; 947 let Inst{16-20} = XB{4-0}; 948 let Inst{21-29} = xo; 949 let Inst{30} = XB{5}; 950 let Inst{31} = 0; 951} 952 953class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 954 InstrItinClass itin, list<dag> pattern> 955 : I<opcode, OOL, IOL, asmstr, itin> { 956 bits<6> XT; 957 bits<6> XB; 958 bits<2> D; 959 960 let Pattern = pattern; 961 962 let Inst{6-10} = XT{4-0}; 963 let Inst{11-13} = 0; 964 let Inst{14-15} = D; 965 let Inst{16-20} = XB{4-0}; 966 let Inst{21-29} = xo; 967 let Inst{30} = XB{5}; 968 let Inst{31} = XT{5}; 969} 970 971class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 972 string asmstr, InstrItinClass itin, list<dag> pattern> 973 : I<opcode, OOL, IOL, asmstr, itin> { 974 bits<6> XT; 975 bits<6> XB; 976 bits<5> UIM5; 977 978 let Pattern = pattern; 979 980 let Inst{6-10} = XT{4-0}; 981 let Inst{11-15} = UIM5; 982 let Inst{16-20} = XB{4-0}; 983 let Inst{21-29} = xo; 984 let Inst{30} = XB{5}; 985 let Inst{31} = XT{5}; 986} 987 988// [PO T XO B XO BX /] 989class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 990 string asmstr, InstrItinClass itin, list<dag> pattern> 991 : I<opcode, OOL, IOL, asmstr, itin> { 992 bits<5> RT; 993 bits<6> XB; 994 995 let Pattern = pattern; 996 997 let Inst{6-10} = RT; 998 let Inst{11-15} = xo2; 999 let Inst{16-20} = XB{4-0}; 1000 let Inst{21-29} = xo; 1001 let Inst{30} = XB{5}; 1002 let Inst{31} = 0; 1003} 1004 1005// [PO T XO B XO BX TX] 1006class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1007 string asmstr, InstrItinClass itin, list<dag> pattern> 1008 : I<opcode, OOL, IOL, asmstr, itin> { 1009 bits<6> XT; 1010 bits<6> XB; 1011 1012 let Pattern = pattern; 1013 1014 let Inst{6-10} = XT{4-0}; 1015 let Inst{11-15} = xo2; 1016 let Inst{16-20} = XB{4-0}; 1017 let Inst{21-29} = xo; 1018 let Inst{30} = XB{5}; 1019 let Inst{31} = XT{5}; 1020} 1021 1022class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1023 string asmstr, InstrItinClass itin, list<dag> pattern> 1024 : I<opcode, OOL, IOL, asmstr, itin> { 1025 bits<3> BF; 1026 bits<7> DCMX; 1027 bits<6> XB; 1028 1029 let Pattern = pattern; 1030 1031 let Inst{6-8} = BF; 1032 let Inst{9-15} = DCMX; 1033 let Inst{16-20} = XB{4-0}; 1034 let Inst{21-29} = xo; 1035 let Inst{30} = XB{5}; 1036 let Inst{31} = 0; 1037} 1038 1039class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2, 1040 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 1041 list<dag> pattern> 1042 : I<opcode, OOL, IOL, asmstr, itin> { 1043 bits<6> XT; 1044 bits<7> DCMX; 1045 bits<6> XB; 1046 1047 let Pattern = pattern; 1048 1049 let Inst{6-10} = XT{4-0}; 1050 let Inst{11-15} = DCMX{4-0}; 1051 let Inst{16-20} = XB{4-0}; 1052 let Inst{21-24} = xo1; 1053 let Inst{25} = DCMX{5}; 1054 let Inst{26-28} = xo2; 1055 let Inst{29} = DCMX{6}; 1056 let Inst{30} = XB{5}; 1057 let Inst{31} = XT{5}; 1058} 1059 1060class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1061 InstrItinClass itin, list<dag> pattern> 1062 : I<opcode, OOL, IOL, asmstr, itin> { 1063 bits<6> XT; 1064 bits<6> XA; 1065 bits<6> XB; 1066 1067 let Pattern = pattern; 1068 1069 let Inst{6-10} = XT{4-0}; 1070 let Inst{11-15} = XA{4-0}; 1071 let Inst{16-20} = XB{4-0}; 1072 let Inst{21-28} = xo; 1073 let Inst{29} = XA{5}; 1074 let Inst{30} = XB{5}; 1075 let Inst{31} = XT{5}; 1076} 1077 1078class XX3Form_Zero<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1079 InstrItinClass itin, list<dag> pattern> 1080 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1081 let XA = XT; 1082 let XB = XT; 1083} 1084 1085class XX3Form_SetZero<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1086 InstrItinClass itin, list<dag> pattern> 1087 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1088 let XB = XT; 1089 let XA = XT; 1090} 1091 1092class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1093 InstrItinClass itin, list<dag> pattern> 1094 : I<opcode, OOL, IOL, asmstr, itin> { 1095 bits<3> CR; 1096 bits<6> XA; 1097 bits<6> XB; 1098 1099 let Pattern = pattern; 1100 1101 let Inst{6-8} = CR; 1102 let Inst{9-10} = 0; 1103 let Inst{11-15} = XA{4-0}; 1104 let Inst{16-20} = XB{4-0}; 1105 let Inst{21-28} = xo; 1106 let Inst{29} = XA{5}; 1107 let Inst{30} = XB{5}; 1108 let Inst{31} = 0; 1109} 1110 1111class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1112 InstrItinClass itin, list<dag> pattern> 1113 : I<opcode, OOL, IOL, asmstr, itin> { 1114 bits<6> XT; 1115 bits<6> XA; 1116 bits<6> XB; 1117 bits<2> D; 1118 1119 let Pattern = pattern; 1120 1121 let Inst{6-10} = XT{4-0}; 1122 let Inst{11-15} = XA{4-0}; 1123 let Inst{16-20} = XB{4-0}; 1124 let Inst{21} = 0; 1125 let Inst{22-23} = D; 1126 let Inst{24-28} = xo; 1127 let Inst{29} = XA{5}; 1128 let Inst{30} = XB{5}; 1129 let Inst{31} = XT{5}; 1130} 1131 1132class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr, 1133 InstrItinClass itin, list<dag> pattern> 1134 : I<opcode, OOL, IOL, asmstr, itin> { 1135 bits<6> XT; 1136 bits<6> XA; 1137 bits<6> XB; 1138 1139 let Pattern = pattern; 1140 1141 bit RC = 0; // set by isDOT 1142 1143 let Inst{6-10} = XT{4-0}; 1144 let Inst{11-15} = XA{4-0}; 1145 let Inst{16-20} = XB{4-0}; 1146 let Inst{21} = RC; 1147 let Inst{22-28} = xo; 1148 let Inst{29} = XA{5}; 1149 let Inst{30} = XB{5}; 1150 let Inst{31} = XT{5}; 1151} 1152 1153class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 1154 InstrItinClass itin, list<dag> pattern> 1155 : I<opcode, OOL, IOL, asmstr, itin> { 1156 bits<6> XT; 1157 bits<6> XA; 1158 bits<6> XB; 1159 bits<6> XC; 1160 1161 let Pattern = pattern; 1162 1163 let Inst{6-10} = XT{4-0}; 1164 let Inst{11-15} = XA{4-0}; 1165 let Inst{16-20} = XB{4-0}; 1166 let Inst{21-25} = XC{4-0}; 1167 let Inst{26-27} = xo; 1168 let Inst{28} = XC{5}; 1169 let Inst{29} = XA{5}; 1170 let Inst{30} = XB{5}; 1171 let Inst{31} = XT{5}; 1172} 1173 1174// DCB_Form - Form X instruction, used for dcb* instructions. 1175class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 1176 InstrItinClass itin, list<dag> pattern> 1177 : I<31, OOL, IOL, asmstr, itin> { 1178 bits<5> A; 1179 bits<5> B; 1180 1181 let Pattern = pattern; 1182 1183 let Inst{6-10} = immfield; 1184 let Inst{11-15} = A; 1185 let Inst{16-20} = B; 1186 let Inst{21-30} = xo; 1187 let Inst{31} = 0; 1188} 1189 1190class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr, 1191 InstrItinClass itin, list<dag> pattern> 1192 : I<31, OOL, IOL, asmstr, itin> { 1193 bits<5> TH; 1194 bits<5> A; 1195 bits<5> B; 1196 1197 let Pattern = pattern; 1198 1199 let Inst{6-10} = TH; 1200 let Inst{11-15} = A; 1201 let Inst{16-20} = B; 1202 let Inst{21-30} = xo; 1203 let Inst{31} = 0; 1204} 1205 1206// DSS_Form - Form X instruction, used for altivec dss* instructions. 1207class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr, 1208 InstrItinClass itin, list<dag> pattern> 1209 : I<31, OOL, IOL, asmstr, itin> { 1210 bits<2> STRM; 1211 bits<5> A; 1212 bits<5> B; 1213 1214 let Pattern = pattern; 1215 1216 let Inst{6} = T; 1217 let Inst{7-8} = 0; 1218 let Inst{9-10} = STRM; 1219 let Inst{11-15} = A; 1220 let Inst{16-20} = B; 1221 let Inst{21-30} = xo; 1222 let Inst{31} = 0; 1223} 1224 1225// 1.7.7 XL-Form 1226class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1227 InstrItinClass itin, list<dag> pattern> 1228 : I<opcode, OOL, IOL, asmstr, itin> { 1229 bits<5> CRD; 1230 bits<5> CRA; 1231 bits<5> CRB; 1232 1233 let Pattern = pattern; 1234 1235 let Inst{6-10} = CRD; 1236 let Inst{11-15} = CRA; 1237 let Inst{16-20} = CRB; 1238 let Inst{21-30} = xo; 1239 let Inst{31} = 0; 1240} 1241 1242class XLForm_1_np<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1243 InstrItinClass itin, list<dag> pattern> 1244 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1245 let CRD = 0; 1246 let CRA = 0; 1247 let CRB = 0; 1248} 1249 1250class XLForm_1_gen<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1251 InstrItinClass itin, list<dag> pattern> 1252 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1253 bits<5> RT; 1254 bits<5> RB; 1255 1256 let CRD = RT; 1257 let CRA = 0; 1258 let CRB = RB; 1259} 1260 1261class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1262 InstrItinClass itin, list<dag> pattern> 1263 : I<opcode, OOL, IOL, asmstr, itin> { 1264 bits<5> CRD; 1265 1266 let Pattern = pattern; 1267 1268 let Inst{6-10} = CRD; 1269 let Inst{11-15} = CRD; 1270 let Inst{16-20} = CRD; 1271 let Inst{21-30} = xo; 1272 let Inst{31} = 0; 1273} 1274 1275class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 1276 InstrItinClass itin, list<dag> pattern> 1277 : I<opcode, OOL, IOL, asmstr, itin> { 1278 bits<5> BO; 1279 bits<5> BI; 1280 bits<2> BH; 1281 1282 let Pattern = pattern; 1283 1284 let Inst{6-10} = BO; 1285 let Inst{11-15} = BI; 1286 let Inst{16-18} = 0; 1287 let Inst{19-20} = BH; 1288 let Inst{21-30} = xo; 1289 let Inst{31} = lk; 1290} 1291 1292class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 1293 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1294 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1295 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 1296 bits<3> CR; 1297 1298 let BO = BIBO{4-0}; 1299 let BI{0-1} = BIBO{5-6}; 1300 let BI{2-4} = CR{0-2}; 1301 let BH = 0; 1302} 1303 1304class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk, 1305 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1306 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1307 let BO = bo; 1308 let BH = 0; 1309} 1310 1311class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 1312 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1313 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1314 let BO = bo; 1315 let BI = bi; 1316 let BH = 0; 1317} 1318 1319class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1320 InstrItinClass itin> 1321 : I<opcode, OOL, IOL, asmstr, itin> { 1322 bits<3> BF; 1323 bits<3> BFA; 1324 1325 let Inst{6-8} = BF; 1326 let Inst{9-10} = 0; 1327 let Inst{11-13} = BFA; 1328 let Inst{14-15} = 0; 1329 let Inst{16-20} = 0; 1330 let Inst{21-30} = xo; 1331 let Inst{31} = 0; 1332} 1333 1334class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1335 InstrItinClass itin> 1336 : I<opcode, OOL, IOL, asmstr, itin> { 1337 bits<3> BF; 1338 bit W; 1339 bits<4> U; 1340 1341 bit RC = 0; 1342 1343 let Inst{6-8} = BF; 1344 let Inst{9-10} = 0; 1345 let Inst{11-14} = 0; 1346 let Inst{15} = W; 1347 let Inst{16-19} = U; 1348 let Inst{20} = 0; 1349 let Inst{21-30} = xo; 1350 let Inst{31} = RC; 1351} 1352 1353class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1354 InstrItinClass itin, list<dag> pattern> 1355 : I<opcode, OOL, IOL, asmstr, itin> { 1356 bits<1> S; 1357 1358 let Pattern = pattern; 1359 1360 let Inst{6-19} = 0; 1361 let Inst{20} = S; 1362 let Inst{21-30} = xo; 1363 let Inst{31} = 0; 1364} 1365 1366class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk, 1367 bits<6> opcode2, bits<2> xo2, 1368 dag OOL, dag IOL, string asmstr, 1369 InstrItinClass itin, list<dag> pattern> 1370 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1371 bits<5> BO; 1372 bits<5> BI; 1373 bits<2> BH; 1374 1375 bits<5> RST; 1376 bits<19> DS_RA; 1377 1378 let Pattern = pattern; 1379 1380 let Inst{6-10} = BO; 1381 let Inst{11-15} = BI; 1382 let Inst{16-18} = 0; 1383 let Inst{19-20} = BH; 1384 let Inst{21-30} = xo1; 1385 let Inst{31} = lk; 1386 1387 let Inst{38-42} = RST; 1388 let Inst{43-47} = DS_RA{18-14}; // Register # 1389 let Inst{48-61} = DS_RA{13-0}; // Displacement. 1390 let Inst{62-63} = xo2; 1391} 1392 1393class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1, 1394 bits<5> bo, bits<5> bi, bit lk, 1395 bits<6> opcode2, bits<2> xo2, 1396 dag OOL, dag IOL, string asmstr, 1397 InstrItinClass itin, list<dag> pattern> 1398 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2, 1399 OOL, IOL, asmstr, itin, pattern> { 1400 let BO = bo; 1401 let BI = bi; 1402 let BH = 0; 1403} 1404 1405// 1.7.8 XFX-Form 1406class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1407 InstrItinClass itin> 1408 : I<opcode, OOL, IOL, asmstr, itin> { 1409 bits<5> RT; 1410 bits<10> SPR; 1411 1412 let Inst{6-10} = RT; 1413 let Inst{11} = SPR{4}; 1414 let Inst{12} = SPR{3}; 1415 let Inst{13} = SPR{2}; 1416 let Inst{14} = SPR{1}; 1417 let Inst{15} = SPR{0}; 1418 let Inst{16} = SPR{9}; 1419 let Inst{17} = SPR{8}; 1420 let Inst{18} = SPR{7}; 1421 let Inst{19} = SPR{6}; 1422 let Inst{20} = SPR{5}; 1423 let Inst{21-30} = xo; 1424 let Inst{31} = 0; 1425} 1426 1427class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1428 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1429 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 1430 let SPR = spr; 1431} 1432 1433class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1434 InstrItinClass itin> 1435 : I<opcode, OOL, IOL, asmstr, itin> { 1436 bits<5> RT; 1437 1438 let Inst{6-10} = RT; 1439 let Inst{11-20} = 0; 1440 let Inst{21-30} = xo; 1441 let Inst{31} = 0; 1442} 1443 1444class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1445 InstrItinClass itin, list<dag> pattern> 1446 : I<opcode, OOL, IOL, asmstr, itin> { 1447 bits<5> RT; 1448 bits<10> Entry; 1449 let Pattern = pattern; 1450 1451 let Inst{6-10} = RT; 1452 let Inst{11-20} = Entry; 1453 let Inst{21-30} = xo; 1454 let Inst{31} = 0; 1455} 1456 1457class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1458 InstrItinClass itin> 1459 : I<opcode, OOL, IOL, asmstr, itin> { 1460 bits<8> FXM; 1461 bits<5> rS; 1462 1463 let Inst{6-10} = rS; 1464 let Inst{11} = 0; 1465 let Inst{12-19} = FXM; 1466 let Inst{20} = 0; 1467 let Inst{21-30} = xo; 1468 let Inst{31} = 0; 1469} 1470 1471class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1472 InstrItinClass itin> 1473 : I<opcode, OOL, IOL, asmstr, itin> { 1474 bits<5> ST; 1475 bits<8> FXM; 1476 1477 let Inst{6-10} = ST; 1478 let Inst{11} = 1; 1479 let Inst{12-19} = FXM; 1480 let Inst{20} = 0; 1481 let Inst{21-30} = xo; 1482 let Inst{31} = 0; 1483} 1484 1485class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1486 InstrItinClass itin> 1487 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 1488 1489class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1490 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1491 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 1492 let SPR = spr; 1493} 1494 1495// XFL-Form - MTFSF 1496// This is probably 1.7.9, but I don't have the reference that uses this 1497// numbering scheme... 1498class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1499 InstrItinClass itin, list<dag>pattern> 1500 : I<opcode, OOL, IOL, asmstr, itin> { 1501 bits<8> FM; 1502 bits<5> rT; 1503 1504 bit RC = 0; // set by isDOT 1505 let Pattern = pattern; 1506 1507 let Inst{6} = 0; 1508 let Inst{7-14} = FM; 1509 let Inst{15} = 0; 1510 let Inst{16-20} = rT; 1511 let Inst{21-30} = xo; 1512 let Inst{31} = RC; 1513} 1514 1515class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1516 InstrItinClass itin, list<dag>pattern> 1517 : I<opcode, OOL, IOL, asmstr, itin> { 1518 bit L; 1519 bits<8> FLM; 1520 bit W; 1521 bits<5> FRB; 1522 1523 bit RC = 0; // set by isDOT 1524 let Pattern = pattern; 1525 1526 let Inst{6} = L; 1527 let Inst{7-14} = FLM; 1528 let Inst{15} = W; 1529 let Inst{16-20} = FRB; 1530 let Inst{21-30} = xo; 1531 let Inst{31} = RC; 1532} 1533 1534// 1.7.10 XS-Form - SRADI. 1535class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1536 InstrItinClass itin, list<dag> pattern> 1537 : I<opcode, OOL, IOL, asmstr, itin> { 1538 bits<5> A; 1539 bits<5> RS; 1540 bits<6> SH; 1541 1542 bit RC = 0; // set by isDOT 1543 let Pattern = pattern; 1544 1545 let Inst{6-10} = RS; 1546 let Inst{11-15} = A; 1547 let Inst{16-20} = SH{4,3,2,1,0}; 1548 let Inst{21-29} = xo; 1549 let Inst{30} = SH{5}; 1550 let Inst{31} = RC; 1551} 1552 1553// 1.7.11 XO-Form 1554class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 1555 InstrItinClass itin, list<dag> pattern> 1556 : I<opcode, OOL, IOL, asmstr, itin> { 1557 bits<5> RT; 1558 bits<5> RA; 1559 bits<5> RB; 1560 1561 let Pattern = pattern; 1562 1563 bit RC = 0; // set by isDOT 1564 1565 let Inst{6-10} = RT; 1566 let Inst{11-15} = RA; 1567 let Inst{16-20} = RB; 1568 let Inst{21} = oe; 1569 let Inst{22-30} = xo; 1570 let Inst{31} = RC; 1571} 1572 1573class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 1574 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1575 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 1576 let RB = 0; 1577} 1578 1579// 1.7.12 A-Form 1580class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1581 InstrItinClass itin, list<dag> pattern> 1582 : I<opcode, OOL, IOL, asmstr, itin> { 1583 bits<5> FRT; 1584 bits<5> FRA; 1585 bits<5> FRC; 1586 bits<5> FRB; 1587 1588 let Pattern = pattern; 1589 1590 bit RC = 0; // set by isDOT 1591 1592 let Inst{6-10} = FRT; 1593 let Inst{11-15} = FRA; 1594 let Inst{16-20} = FRB; 1595 let Inst{21-25} = FRC; 1596 let Inst{26-30} = xo; 1597 let Inst{31} = RC; 1598} 1599 1600class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1601 InstrItinClass itin, list<dag> pattern> 1602 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1603 let FRC = 0; 1604} 1605 1606class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1607 InstrItinClass itin, list<dag> pattern> 1608 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1609 let FRB = 0; 1610} 1611 1612class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1613 InstrItinClass itin, list<dag> pattern> 1614 : I<opcode, OOL, IOL, asmstr, itin> { 1615 bits<5> RT; 1616 bits<5> RA; 1617 bits<5> RB; 1618 bits<5> COND; 1619 1620 let Pattern = pattern; 1621 1622 let Inst{6-10} = RT; 1623 let Inst{11-15} = RA; 1624 let Inst{16-20} = RB; 1625 let Inst{21-25} = COND; 1626 let Inst{26-30} = xo; 1627 let Inst{31} = 0; 1628} 1629 1630// Used for QPX 1631class AForm_4a<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1632 InstrItinClass itin, list<dag> pattern> 1633 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1634 let FRA = 0; 1635 let FRC = 0; 1636} 1637 1638// 1.7.13 M-Form 1639class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1640 InstrItinClass itin, list<dag> pattern> 1641 : I<opcode, OOL, IOL, asmstr, itin> { 1642 bits<5> RA; 1643 bits<5> RS; 1644 bits<5> RB; 1645 bits<5> MB; 1646 bits<5> ME; 1647 1648 let Pattern = pattern; 1649 1650 bit RC = 0; // set by isDOT 1651 1652 let Inst{6-10} = RS; 1653 let Inst{11-15} = RA; 1654 let Inst{16-20} = RB; 1655 let Inst{21-25} = MB; 1656 let Inst{26-30} = ME; 1657 let Inst{31} = RC; 1658} 1659 1660class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1661 InstrItinClass itin, list<dag> pattern> 1662 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 1663} 1664 1665// 1.7.14 MD-Form 1666class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 1667 InstrItinClass itin, list<dag> pattern> 1668 : I<opcode, OOL, IOL, asmstr, itin> { 1669 bits<5> RA; 1670 bits<5> RS; 1671 bits<6> SH; 1672 bits<6> MBE; 1673 1674 let Pattern = pattern; 1675 1676 bit RC = 0; // set by isDOT 1677 1678 let Inst{6-10} = RS; 1679 let Inst{11-15} = RA; 1680 let Inst{16-20} = SH{4,3,2,1,0}; 1681 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1682 let Inst{27-29} = xo; 1683 let Inst{30} = SH{5}; 1684 let Inst{31} = RC; 1685} 1686 1687class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 1688 InstrItinClass itin, list<dag> pattern> 1689 : I<opcode, OOL, IOL, asmstr, itin> { 1690 bits<5> RA; 1691 bits<5> RS; 1692 bits<5> RB; 1693 bits<6> MBE; 1694 1695 let Pattern = pattern; 1696 1697 bit RC = 0; // set by isDOT 1698 1699 let Inst{6-10} = RS; 1700 let Inst{11-15} = RA; 1701 let Inst{16-20} = RB; 1702 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1703 let Inst{27-30} = xo; 1704 let Inst{31} = RC; 1705} 1706 1707 1708// E-1 VA-Form 1709 1710// VAForm_1 - DACB ordering. 1711class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 1712 InstrItinClass itin, list<dag> pattern> 1713 : I<4, OOL, IOL, asmstr, itin> { 1714 bits<5> VD; 1715 bits<5> VA; 1716 bits<5> VC; 1717 bits<5> VB; 1718 1719 let Pattern = pattern; 1720 1721 let Inst{6-10} = VD; 1722 let Inst{11-15} = VA; 1723 let Inst{16-20} = VB; 1724 let Inst{21-25} = VC; 1725 let Inst{26-31} = xo; 1726} 1727 1728// VAForm_1a - DABC ordering. 1729class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 1730 InstrItinClass itin, list<dag> pattern> 1731 : I<4, OOL, IOL, asmstr, itin> { 1732 bits<5> VD; 1733 bits<5> VA; 1734 bits<5> VB; 1735 bits<5> VC; 1736 1737 let Pattern = pattern; 1738 1739 let Inst{6-10} = VD; 1740 let Inst{11-15} = VA; 1741 let Inst{16-20} = VB; 1742 let Inst{21-25} = VC; 1743 let Inst{26-31} = xo; 1744} 1745 1746class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 1747 InstrItinClass itin, list<dag> pattern> 1748 : I<4, OOL, IOL, asmstr, itin> { 1749 bits<5> VD; 1750 bits<5> VA; 1751 bits<5> VB; 1752 bits<4> SH; 1753 1754 let Pattern = pattern; 1755 1756 let Inst{6-10} = VD; 1757 let Inst{11-15} = VA; 1758 let Inst{16-20} = VB; 1759 let Inst{21} = 0; 1760 let Inst{22-25} = SH; 1761 let Inst{26-31} = xo; 1762} 1763 1764// E-2 VX-Form 1765class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 1766 InstrItinClass itin, list<dag> pattern> 1767 : I<4, OOL, IOL, asmstr, itin> { 1768 bits<5> VD; 1769 bits<5> VA; 1770 bits<5> VB; 1771 1772 let Pattern = pattern; 1773 1774 let Inst{6-10} = VD; 1775 let Inst{11-15} = VA; 1776 let Inst{16-20} = VB; 1777 let Inst{21-31} = xo; 1778} 1779 1780class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 1781 InstrItinClass itin, list<dag> pattern> 1782 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 1783 let VA = VD; 1784 let VB = VD; 1785} 1786 1787 1788class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 1789 InstrItinClass itin, list<dag> pattern> 1790 : I<4, OOL, IOL, asmstr, itin> { 1791 bits<5> VD; 1792 bits<5> VB; 1793 1794 let Pattern = pattern; 1795 1796 let Inst{6-10} = VD; 1797 let Inst{11-15} = 0; 1798 let Inst{16-20} = VB; 1799 let Inst{21-31} = xo; 1800} 1801 1802class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 1803 InstrItinClass itin, list<dag> pattern> 1804 : I<4, OOL, IOL, asmstr, itin> { 1805 bits<5> VD; 1806 bits<5> IMM; 1807 1808 let Pattern = pattern; 1809 1810 let Inst{6-10} = VD; 1811 let Inst{11-15} = IMM; 1812 let Inst{16-20} = 0; 1813 let Inst{21-31} = xo; 1814} 1815 1816/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 1817class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 1818 InstrItinClass itin, list<dag> pattern> 1819 : I<4, OOL, IOL, asmstr, itin> { 1820 bits<5> VD; 1821 1822 let Pattern = pattern; 1823 1824 let Inst{6-10} = VD; 1825 let Inst{11-15} = 0; 1826 let Inst{16-20} = 0; 1827 let Inst{21-31} = xo; 1828} 1829 1830/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 1831class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 1832 InstrItinClass itin, list<dag> pattern> 1833 : I<4, OOL, IOL, asmstr, itin> { 1834 bits<5> VB; 1835 1836 let Pattern = pattern; 1837 1838 let Inst{6-10} = 0; 1839 let Inst{11-15} = 0; 1840 let Inst{16-20} = VB; 1841 let Inst{21-31} = xo; 1842} 1843 1844// e.g. [PO VRT EO VRB XO] 1845class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL, 1846 string asmstr, InstrItinClass itin, list<dag> pattern> 1847 : I<4, OOL, IOL, asmstr, itin> { 1848 bits<5> RD; 1849 bits<5> VB; 1850 1851 let Pattern = pattern; 1852 1853 let Inst{6-10} = RD; 1854 let Inst{11-15} = eo; 1855 let Inst{16-20} = VB; 1856 let Inst{21-31} = xo; 1857} 1858 1859/// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX" 1860class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr, 1861 InstrItinClass itin, list<dag> pattern> 1862 : I<4, OOL, IOL, asmstr, itin> { 1863 bits<5> VD; 1864 bits<5> VA; 1865 bits<1> ST; 1866 bits<4> SIX; 1867 1868 let Pattern = pattern; 1869 1870 let Inst{6-10} = VD; 1871 let Inst{11-15} = VA; 1872 let Inst{16} = ST; 1873 let Inst{17-20} = SIX; 1874 let Inst{21-31} = xo; 1875} 1876 1877/// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox" 1878class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr, 1879 InstrItinClass itin, list<dag> pattern> 1880 : I<4, OOL, IOL, asmstr, itin> { 1881 bits<5> VD; 1882 bits<5> VA; 1883 1884 let Pattern = pattern; 1885 1886 let Inst{6-10} = VD; 1887 let Inst{11-15} = VA; 1888 let Inst{16-20} = 0; 1889 let Inst{21-31} = xo; 1890} 1891 1892// E-4 VXR-Form 1893class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 1894 InstrItinClass itin, list<dag> pattern> 1895 : I<4, OOL, IOL, asmstr, itin> { 1896 bits<5> VD; 1897 bits<5> VA; 1898 bits<5> VB; 1899 bit RC = 0; 1900 1901 let Pattern = pattern; 1902 1903 let Inst{6-10} = VD; 1904 let Inst{11-15} = VA; 1905 let Inst{16-20} = VB; 1906 let Inst{21} = RC; 1907 let Inst{22-31} = xo; 1908} 1909 1910// VX-Form: [PO VRT EO VRB 1 PS XO] 1911class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo, 1912 dag OOL, dag IOL, string asmstr, 1913 InstrItinClass itin, list<dag> pattern> 1914 : I<4, OOL, IOL, asmstr, itin> { 1915 bits<5> VD; 1916 bits<5> VB; 1917 bit PS; 1918 1919 let Pattern = pattern; 1920 1921 let Inst{6-10} = VD; 1922 let Inst{11-15} = eo; 1923 let Inst{16-20} = VB; 1924 let Inst{21} = 1; 1925 let Inst{22} = PS; 1926 let Inst{23-31} = xo; 1927} 1928 1929// VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO] 1930class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr, 1931 InstrItinClass itin, list<dag> pattern> 1932 : I<4, OOL, IOL, asmstr, itin> { 1933 bits<5> VD; 1934 bits<5> VA; 1935 bits<5> VB; 1936 bit PS; 1937 1938 let Pattern = pattern; 1939 1940 let Inst{6-10} = VD; 1941 let Inst{11-15} = VA; 1942 let Inst{16-20} = VB; 1943 let Inst{21} = 1; 1944 let Inst{22} = PS; 1945 let Inst{23-31} = xo; 1946} 1947 1948// Z23-Form (used by QPX) 1949class Z23Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1950 InstrItinClass itin, list<dag> pattern> 1951 : I<opcode, OOL, IOL, asmstr, itin> { 1952 bits<5> FRT; 1953 bits<5> FRA; 1954 bits<5> FRB; 1955 bits<2> idx; 1956 1957 let Pattern = pattern; 1958 1959 bit RC = 0; // set by isDOT 1960 1961 let Inst{6-10} = FRT; 1962 let Inst{11-15} = FRA; 1963 let Inst{16-20} = FRB; 1964 let Inst{21-22} = idx; 1965 let Inst{23-30} = xo; 1966 let Inst{31} = RC; 1967} 1968 1969class Z23Form_2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1970 InstrItinClass itin, list<dag> pattern> 1971 : Z23Form_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1972 let FRB = 0; 1973} 1974 1975class Z23Form_3<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1976 InstrItinClass itin, list<dag> pattern> 1977 : I<opcode, OOL, IOL, asmstr, itin> { 1978 bits<5> FRT; 1979 bits<12> idx; 1980 1981 let Pattern = pattern; 1982 1983 bit RC = 0; // set by isDOT 1984 1985 let Inst{6-10} = FRT; 1986 let Inst{11-22} = idx; 1987 let Inst{23-30} = xo; 1988 let Inst{31} = RC; 1989} 1990 1991//===----------------------------------------------------------------------===// 1992class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 1993 : I<0, OOL, IOL, asmstr, NoItinerary> { 1994 let isCodeGenOnly = 1; 1995 let PPC64 = 0; 1996 let Pattern = pattern; 1997 let Inst{31-0} = 0; 1998} 1999