1//===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Altivec extension to the PowerPC instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Altivec transformation functions and pattern fragments. 16// 17 18// Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be 19// of that type. 20def vnot_ppc : PatFrag<(ops node:$in), 21 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>; 22 23def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 24 (vector_shuffle node:$lhs, node:$rhs), [{ 25 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false); 26}]>; 27def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 28 (vector_shuffle node:$lhs, node:$rhs), [{ 29 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false); 30}]>; 31def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 32 (vector_shuffle node:$lhs, node:$rhs), [{ 33 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true); 34}]>; 35def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 36 (vector_shuffle node:$lhs, node:$rhs), [{ 37 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true); 38}]>; 39 40 41def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 42 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 43 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); 44}]>; 45def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 46 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 47 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); 48}]>; 49def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 50 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 51 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); 52}]>; 53def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 54 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 55 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); 56}]>; 57def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 58 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 59 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); 60}]>; 61def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 62 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 63 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); 64}]>; 65 66 67def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 68 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 69 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); 70}]>; 71def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 72 (vector_shuffle node:$lhs, node:$rhs), [{ 73 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true); 74}]>; 75def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 76 (vector_shuffle node:$lhs, node:$rhs), [{ 77 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true); 78}]>; 79def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 80 (vector_shuffle node:$lhs, node:$rhs), [{ 81 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); 82}]>; 83def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 84 (vector_shuffle node:$lhs, node:$rhs), [{ 85 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true); 86}]>; 87def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 88 (vector_shuffle node:$lhs, node:$rhs), [{ 89 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true); 90}]>; 91 92 93def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{ 94 return getI32Imm(PPC::isVSLDOIShuffleMask(N, false)); 95}]>; 96def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 97 (vector_shuffle node:$lhs, node:$rhs), [{ 98 return PPC::isVSLDOIShuffleMask(N, false) != -1; 99}], VSLDOI_get_imm>; 100 101 102/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into 103/// vector_shuffle(X,undef,mask) by the dag combiner. 104def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{ 105 return getI32Imm(PPC::isVSLDOIShuffleMask(N, true)); 106}]>; 107def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 108 (vector_shuffle node:$lhs, node:$rhs), [{ 109 return PPC::isVSLDOIShuffleMask(N, true) != -1; 110}], VSLDOI_unary_get_imm>; 111 112 113// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. 114def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{ 115 return getI32Imm(PPC::getVSPLTImmediate(N, 1)); 116}]>; 117def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 118 (vector_shuffle node:$lhs, node:$rhs), [{ 119 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1); 120}], VSPLTB_get_imm>; 121def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{ 122 return getI32Imm(PPC::getVSPLTImmediate(N, 2)); 123}]>; 124def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 125 (vector_shuffle node:$lhs, node:$rhs), [{ 126 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2); 127}], VSPLTH_get_imm>; 128def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{ 129 return getI32Imm(PPC::getVSPLTImmediate(N, 4)); 130}]>; 131def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 132 (vector_shuffle node:$lhs, node:$rhs), [{ 133 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4); 134}], VSPLTW_get_imm>; 135 136 137// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. 138def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{ 139 return PPC::get_VSPLTI_elt(N, 1, *CurDAG); 140}]>; 141def vecspltisb : PatLeaf<(build_vector), [{ 142 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0; 143}], VSPLTISB_get_imm>; 144 145// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm. 146def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{ 147 return PPC::get_VSPLTI_elt(N, 2, *CurDAG); 148}]>; 149def vecspltish : PatLeaf<(build_vector), [{ 150 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0; 151}], VSPLTISH_get_imm>; 152 153// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm. 154def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{ 155 return PPC::get_VSPLTI_elt(N, 4, *CurDAG); 156}]>; 157def vecspltisw : PatLeaf<(build_vector), [{ 158 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0; 159}], VSPLTISW_get_imm>; 160 161//===----------------------------------------------------------------------===// 162// Helpers for defining instructions that directly correspond to intrinsics. 163 164// VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type. 165class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty> 166 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 167 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 168 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>; 169 170// VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the 171// inputs doesn't match the type of the output. 172class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 173 ValueType InTy> 174 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 175 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 176 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>; 177 178// VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two 179// input types and an output type. 180class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 181 ValueType In1Ty, ValueType In2Ty> 182 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 183 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 184 [(set OutTy:$vD, 185 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>; 186 187// VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type. 188class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 189 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 190 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 191 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>; 192 193// VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the 194// inputs doesn't match the type of the output. 195class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 196 ValueType InTy> 197 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 198 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 199 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>; 200 201// VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two 202// input types and an output type. 203class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 204 ValueType In1Ty, ValueType In2Ty> 205 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 206 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 207 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>; 208 209// VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type. 210class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID> 211 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 212 !strconcat(opc, " $vD, $vB"), IIC_VecFP, 213 [(set v4f32:$vD, (IntID v4f32:$vB))]>; 214 215// VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the 216// inputs doesn't match the type of the output. 217class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 218 ValueType InTy> 219 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 220 !strconcat(opc, " $vD, $vB"), IIC_VecFP, 221 [(set OutTy:$vD, (IntID InTy:$vB))]>; 222 223//===----------------------------------------------------------------------===// 224// Instruction Definitions. 225 226def HasAltivec : Predicate<"PPCSubTarget.hasAltivec()">; 227let Predicates = [HasAltivec] in { 228 229let isCodeGenOnly = 1 in { 230def DSS : DSS_Form<822, (outs), 231 (ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), 232 "dss $STRM", IIC_LdStLoad /*FIXME*/, []>, 233 Deprecated<DeprecatedDST>; 234def DSSALL : DSS_Form<822, (outs), 235 (ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2), 236 "dssall", IIC_LdStLoad /*FIXME*/, []>, 237 Deprecated<DeprecatedDST>; 238def DST : DSS_Form<342, (outs), 239 (ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB), 240 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 241 Deprecated<DeprecatedDST>; 242def DSTT : DSS_Form<342, (outs), 243 (ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB), 244 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 245 Deprecated<DeprecatedDST>; 246def DSTST : DSS_Form<374, (outs), 247 (ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB), 248 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 249 Deprecated<DeprecatedDST>; 250def DSTSTT : DSS_Form<374, (outs), 251 (ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB), 252 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 253 Deprecated<DeprecatedDST>; 254 255def DST64 : DSS_Form<342, (outs), 256 (ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB), 257 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 258 Deprecated<DeprecatedDST>; 259def DSTT64 : DSS_Form<342, (outs), 260 (ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB), 261 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 262 Deprecated<DeprecatedDST>; 263def DSTST64 : DSS_Form<374, (outs), 264 (ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB), 265 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 266 Deprecated<DeprecatedDST>; 267def DSTSTT64 : DSS_Form<374, (outs), 268 (ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB), 269 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 270 Deprecated<DeprecatedDST>; 271} 272 273def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins), 274 "mfvscr $vD", IIC_LdStStore, 275 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>; 276def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB), 277 "mtvscr $vB", IIC_LdStLoad, 278 [(int_ppc_altivec_mtvscr v4i32:$vB)]>; 279 280let canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads. 281def LVEBX: XForm_1<31, 7, (outs vrrc:$vD), (ins memrr:$src), 282 "lvebx $vD, $src", IIC_LdStLoad, 283 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; 284def LVEHX: XForm_1<31, 39, (outs vrrc:$vD), (ins memrr:$src), 285 "lvehx $vD, $src", IIC_LdStLoad, 286 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>; 287def LVEWX: XForm_1<31, 71, (outs vrrc:$vD), (ins memrr:$src), 288 "lvewx $vD, $src", IIC_LdStLoad, 289 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; 290def LVX : XForm_1<31, 103, (outs vrrc:$vD), (ins memrr:$src), 291 "lvx $vD, $src", IIC_LdStLoad, 292 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; 293def LVXL : XForm_1<31, 359, (outs vrrc:$vD), (ins memrr:$src), 294 "lvxl $vD, $src", IIC_LdStLoad, 295 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; 296} 297 298def LVSL : XForm_1<31, 6, (outs vrrc:$vD), (ins memrr:$src), 299 "lvsl $vD, $src", IIC_LdStLoad, 300 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, 301 PPC970_Unit_LSU; 302def LVSR : XForm_1<31, 38, (outs vrrc:$vD), (ins memrr:$src), 303 "lvsr $vD, $src", IIC_LdStLoad, 304 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, 305 PPC970_Unit_LSU; 306 307let PPC970_Unit = 2 in { // Stores. 308def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS, memrr:$dst), 309 "stvebx $rS, $dst", IIC_LdStStore, 310 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>; 311def STVEHX: XForm_8<31, 167, (outs), (ins vrrc:$rS, memrr:$dst), 312 "stvehx $rS, $dst", IIC_LdStStore, 313 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>; 314def STVEWX: XForm_8<31, 199, (outs), (ins vrrc:$rS, memrr:$dst), 315 "stvewx $rS, $dst", IIC_LdStStore, 316 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>; 317def STVX : XForm_8<31, 231, (outs), (ins vrrc:$rS, memrr:$dst), 318 "stvx $rS, $dst", IIC_LdStStore, 319 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>; 320def STVXL : XForm_8<31, 487, (outs), (ins vrrc:$rS, memrr:$dst), 321 "stvxl $rS, $dst", IIC_LdStStore, 322 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>; 323} 324 325let PPC970_Unit = 5 in { // VALU Operations. 326// VA-Form instructions. 3-input AltiVec ops. 327let isCommutable = 1 in { 328def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 329 "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP, 330 [(set v4f32:$vD, 331 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>; 332 333// FIXME: The fma+fneg pattern won't match because fneg is not legal. 334def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 335 "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP, 336 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC, 337 (fneg v4f32:$vB))))]>; 338 339def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>; 340def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs, 341 v8i16>; 342def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>; 343} // isCommutable 344 345def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm, 346 v4i32, v4i32, v16i8>; 347def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>; 348 349// Shuffles. 350def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u5imm:$SH), 351 "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP, 352 [(set v16i8:$vD, 353 (vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>; 354 355// VX-Form instructions. AltiVec arithmetic ops. 356let isCommutable = 1 in { 357def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 358 "vaddfp $vD, $vA, $vB", IIC_VecFP, 359 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>; 360 361def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 362 "vaddubm $vD, $vA, $vB", IIC_VecGeneral, 363 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>; 364def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 365 "vadduhm $vD, $vA, $vB", IIC_VecGeneral, 366 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>; 367def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 368 "vadduwm $vD, $vA, $vB", IIC_VecGeneral, 369 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>; 370 371def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>; 372def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>; 373def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>; 374def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>; 375def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>; 376def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>; 377def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>; 378} // isCommutable 379 380let isCommutable = 1 in 381def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 382 "vand $vD, $vA, $vB", IIC_VecFP, 383 [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>; 384def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 385 "vandc $vD, $vA, $vB", IIC_VecFP, 386 [(set v4i32:$vD, (and v4i32:$vA, 387 (vnot_ppc v4i32:$vB)))]>; 388 389def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 390 "vcfsx $vD, $vB, $UIMM", IIC_VecFP, 391 [(set v4f32:$vD, 392 (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>; 393def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 394 "vcfux $vD, $vB, $UIMM", IIC_VecFP, 395 [(set v4f32:$vD, 396 (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>; 397def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 398 "vctsxs $vD, $vB, $UIMM", IIC_VecFP, 399 [(set v4i32:$vD, 400 (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>; 401def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 402 "vctuxs $vD, $vB, $UIMM", IIC_VecFP, 403 [(set v4i32:$vD, 404 (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>; 405 406// Defines with the UIM field set to 0 for floating-point 407// to integer (fp_to_sint/fp_to_uint) conversions and integer 408// to floating-point (sint_to_fp/uint_to_fp) conversions. 409let isCodeGenOnly = 1, VA = 0 in { 410def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB), 411 "vcfsx $vD, $vB, 0", IIC_VecFP, 412 [(set v4f32:$vD, 413 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>; 414def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB), 415 "vctuxs $vD, $vB, 0", IIC_VecFP, 416 [(set v4i32:$vD, 417 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>; 418def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB), 419 "vcfux $vD, $vB, 0", IIC_VecFP, 420 [(set v4f32:$vD, 421 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>; 422def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB), 423 "vctsxs $vD, $vB, 0", IIC_VecFP, 424 [(set v4i32:$vD, 425 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>; 426} 427def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>; 428def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>; 429 430let isCommutable = 1 in { 431def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>; 432def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>; 433def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>; 434def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>; 435def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>; 436def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>; 437 438def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>; 439def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>; 440def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>; 441def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>; 442def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>; 443def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>; 444def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>; 445def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>; 446def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>; 447def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>; 448def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>; 449def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>; 450def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>; 451def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>; 452} // isCommutable 453 454def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 455 "vmrghb $vD, $vA, $vB", IIC_VecFP, 456 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>; 457def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 458 "vmrghh $vD, $vA, $vB", IIC_VecFP, 459 [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>; 460def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 461 "vmrghw $vD, $vA, $vB", IIC_VecFP, 462 [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>; 463def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 464 "vmrglb $vD, $vA, $vB", IIC_VecFP, 465 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>; 466def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 467 "vmrglh $vD, $vA, $vB", IIC_VecFP, 468 [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>; 469def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 470 "vmrglw $vD, $vA, $vB", IIC_VecFP, 471 [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>; 472 473def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm, 474 v4i32, v16i8, v4i32>; 475def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm, 476 v4i32, v8i16, v4i32>; 477def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs, 478 v4i32, v8i16, v4i32>; 479def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm, 480 v4i32, v16i8, v4i32>; 481def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm, 482 v4i32, v8i16, v4i32>; 483def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs, 484 v4i32, v8i16, v4i32>; 485 486let isCommutable = 1 in { 487def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb, 488 v8i16, v16i8>; 489def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh, 490 v4i32, v8i16>; 491def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub, 492 v8i16, v16i8>; 493def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh, 494 v4i32, v8i16>; 495def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb, 496 v8i16, v16i8>; 497def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh, 498 v4i32, v8i16>; 499def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub, 500 v8i16, v16i8>; 501def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh, 502 v4i32, v8i16>; 503} // isCommutable 504 505def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>; 506def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>; 507def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>; 508def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>; 509def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>; 510def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; 511 512def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>; 513 514def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 515 "vsubfp $vD, $vA, $vB", IIC_VecGeneral, 516 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>; 517def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 518 "vsububm $vD, $vA, $vB", IIC_VecGeneral, 519 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>; 520def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 521 "vsubuhm $vD, $vA, $vB", IIC_VecGeneral, 522 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>; 523def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 524 "vsubuwm $vD, $vA, $vB", IIC_VecGeneral, 525 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>; 526 527def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>; 528def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>; 529def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>; 530def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>; 531def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>; 532def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>; 533 534def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>; 535def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>; 536 537def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs, 538 v4i32, v16i8, v4i32>; 539def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs, 540 v4i32, v8i16, v4i32>; 541def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs, 542 v4i32, v16i8, v4i32>; 543 544def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 545 "vnor $vD, $vA, $vB", IIC_VecFP, 546 [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA, 547 v4i32:$vB)))]>; 548let isCommutable = 1 in { 549def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 550 "vor $vD, $vA, $vB", IIC_VecFP, 551 [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>; 552def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 553 "vxor $vD, $vA, $vB", IIC_VecFP, 554 [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>; 555} // isCommutable 556 557def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>; 558def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>; 559def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>; 560 561def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >; 562def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>; 563 564def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>; 565def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>; 566def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>; 567 568def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 569 "vspltb $vD, $vB, $UIMM", IIC_VecPerm, 570 [(set v16i8:$vD, 571 (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>; 572def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 573 "vsplth $vD, $vB, $UIMM", IIC_VecPerm, 574 [(set v16i8:$vD, 575 (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>; 576def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 577 "vspltw $vD, $vB, $UIMM", IIC_VecPerm, 578 [(set v16i8:$vD, 579 (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>; 580 581def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>; 582def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>; 583 584def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>; 585def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>; 586def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>; 587def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>; 588def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>; 589def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>; 590 591 592def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM), 593 "vspltisb $vD, $SIMM", IIC_VecPerm, 594 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>; 595def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM), 596 "vspltish $vD, $SIMM", IIC_VecPerm, 597 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>; 598def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM), 599 "vspltisw $vD, $SIMM", IIC_VecPerm, 600 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>; 601 602// Vector Pack. 603def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx, 604 v8i16, v4i32>; 605def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss, 606 v16i8, v8i16>; 607def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus, 608 v16i8, v8i16>; 609def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss, 610 v16i8, v4i32>; 611def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus, 612 v8i16, v4i32>; 613def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 614 "vpkuhum $vD, $vA, $vB", IIC_VecFP, 615 [(set v16i8:$vD, 616 (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>; 617def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus, 618 v16i8, v8i16>; 619def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 620 "vpkuwum $vD, $vA, $vB", IIC_VecFP, 621 [(set v16i8:$vD, 622 (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>; 623def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus, 624 v8i16, v4i32>; 625 626// Vector Unpack. 627def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx, 628 v4i32, v8i16>; 629def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb, 630 v8i16, v16i8>; 631def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh, 632 v4i32, v8i16>; 633def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx, 634 v4i32, v8i16>; 635def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb, 636 v8i16, v16i8>; 637def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh, 638 v4i32, v8i16>; 639 640 641// Altivec Comparisons. 642 643class VCMP<bits<10> xo, string asmstr, ValueType Ty> 644 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, 645 IIC_VecFPCompare, 646 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>; 647class VCMPo<bits<10> xo, string asmstr, ValueType Ty> 648 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, 649 IIC_VecFPCompare, 650 [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> { 651 let Defs = [CR6]; 652 let RC = 1; 653} 654 655// f32 element comparisons.0 656def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; 657def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>; 658def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>; 659def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>; 660def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>; 661def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>; 662def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>; 663def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>; 664 665// i8 element comparisons. 666def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>; 667def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>; 668def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>; 669def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>; 670def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>; 671def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>; 672 673// i16 element comparisons. 674def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>; 675def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>; 676def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>; 677def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>; 678def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>; 679def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>; 680 681// i32 element comparisons. 682def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>; 683def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>; 684def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>; 685def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; 686def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; 687def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; 688 689let isCodeGenOnly = 1 in { 690def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 691 "vxor $vD, $vD, $vD", IIC_VecFP, 692 [(set v16i8:$vD, (v16i8 immAllZerosV))]>; 693def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 694 "vxor $vD, $vD, $vD", IIC_VecFP, 695 [(set v8i16:$vD, (v8i16 immAllZerosV))]>; 696def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 697 "vxor $vD, $vD, $vD", IIC_VecFP, 698 [(set v4i32:$vD, (v4i32 immAllZerosV))]>; 699 700let IMM=-1 in { 701def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins), 702 "vspltisw $vD, -1", IIC_VecFP, 703 [(set v16i8:$vD, (v16i8 immAllOnesV))]>; 704def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins), 705 "vspltisw $vD, -1", IIC_VecFP, 706 [(set v8i16:$vD, (v8i16 immAllOnesV))]>; 707def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins), 708 "vspltisw $vD, -1", IIC_VecFP, 709 [(set v4i32:$vD, (v4i32 immAllOnesV))]>; 710} 711} 712} // VALU Operations. 713 714//===----------------------------------------------------------------------===// 715// Additional Altivec Patterns 716// 717 718// DS* intrinsics 719def : Pat<(int_ppc_altivec_dssall), (DSSALL 1, 0, 0, 0)>; 720def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>; 721 722// * 32-bit 723def : Pat<(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM), 724 (DST 0, imm:$STRM, $rA, $rB)>; 725def : Pat<(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM), 726 (DSTT 1, imm:$STRM, $rA, $rB)>; 727def : Pat<(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM), 728 (DSTST 0, imm:$STRM, $rA, $rB)>; 729def : Pat<(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM), 730 (DSTSTT 1, imm:$STRM, $rA, $rB)>; 731 732// * 64-bit 733def : Pat<(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM), 734 (DST64 0, imm:$STRM, $rA, $rB)>; 735def : Pat<(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM), 736 (DSTT64 1, imm:$STRM, $rA, $rB)>; 737def : Pat<(int_ppc_altivec_dstst i64:$rA, i32:$rB, imm:$STRM), 738 (DSTST64 0, imm:$STRM, $rA, $rB)>; 739def : Pat<(int_ppc_altivec_dststt i64:$rA, i32:$rB, imm:$STRM), 740 (DSTSTT64 1, imm:$STRM, $rA, $rB)>; 741 742// Loads. 743def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; 744 745// Stores. 746def : Pat<(store v4i32:$rS, xoaddr:$dst), 747 (STVX $rS, xoaddr:$dst)>; 748 749// Bit conversions. 750def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>; 751def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>; 752def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>; 753 754def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>; 755def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>; 756def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>; 757 758def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>; 759def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>; 760def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>; 761 762def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>; 763def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>; 764def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>; 765 766// Shuffles. 767 768// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x) 769def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef), 770 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>; 771def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef), 772 (VPKUWUM $vA, $vA)>; 773def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef), 774 (VPKUHUM $vA, $vA)>; 775 776// Match vmrg*(x,x) 777def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef), 778 (VMRGLB $vA, $vA)>; 779def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef), 780 (VMRGLH $vA, $vA)>; 781def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef), 782 (VMRGLW $vA, $vA)>; 783def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef), 784 (VMRGHB $vA, $vA)>; 785def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef), 786 (VMRGHH $vA, $vA)>; 787def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef), 788 (VMRGHW $vA, $vA)>; 789 790// Logical Operations 791def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>; 792 793def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)), 794 (VNOR $A, $B)>; 795def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)), 796 (VANDC $A, $B)>; 797 798def : Pat<(fmul v4f32:$vA, v4f32:$vB), 799 (VMADDFP $vA, $vB, 800 (v4i32 (VSLW (V_SETALLONES), (V_SETALLONES))))>; 801 802// Fused multiply add and multiply sub for packed float. These are represented 803// separately from the real instructions above, for operations that must have 804// the additional precision, such as Newton-Rhapson (used by divide, sqrt) 805def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 806 (VMADDFP $A, $B, $C)>; 807def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 808 (VNMSUBFP $A, $B, $C)>; 809 810def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 811 (VMADDFP $A, $B, $C)>; 812def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 813 (VNMSUBFP $A, $B, $C)>; 814 815def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC), 816 (VPERM $vA, $vB, $vC)>; 817 818def : Pat<(PPCfre v4f32:$A), (VREFP $A)>; 819def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>; 820 821// Vector shifts 822def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)), 823 (v16i8 (VSLB $vA, $vB))>; 824def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)), 825 (v8i16 (VSLH $vA, $vB))>; 826def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)), 827 (v4i32 (VSLW $vA, $vB))>; 828 829def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)), 830 (v16i8 (VSRB $vA, $vB))>; 831def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)), 832 (v8i16 (VSRH $vA, $vB))>; 833def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)), 834 (v4i32 (VSRW $vA, $vB))>; 835 836def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)), 837 (v16i8 (VSRAB $vA, $vB))>; 838def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)), 839 (v8i16 (VSRAH $vA, $vB))>; 840def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)), 841 (v4i32 (VSRAW $vA, $vB))>; 842 843// Float to integer and integer to float conversions 844def : Pat<(v4i32 (fp_to_sint v4f32:$vA)), 845 (VCTSXS_0 $vA)>; 846def : Pat<(v4i32 (fp_to_uint v4f32:$vA)), 847 (VCTUXS_0 $vA)>; 848def : Pat<(v4f32 (sint_to_fp v4i32:$vA)), 849 (VCFSX_0 $vA)>; 850def : Pat<(v4f32 (uint_to_fp v4i32:$vA)), 851 (VCFUX_0 $vA)>; 852 853// Floating-point rounding 854def : Pat<(v4f32 (ffloor v4f32:$vA)), 855 (VRFIM $vA)>; 856def : Pat<(v4f32 (fceil v4f32:$vA)), 857 (VRFIP $vA)>; 858def : Pat<(v4f32 (ftrunc v4f32:$vA)), 859 (VRFIZ $vA)>; 860def : Pat<(v4f32 (fnearbyint v4f32:$vA)), 861 (VRFIN $vA)>; 862 863} // end HasAltivec 864 865