1//===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Altivec extension to the PowerPC instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14// *********************************** NOTE *********************************** 15// ** For POWER8 Little Endian, the VSX swap optimization relies on knowing ** 16// ** which VMX and VSX instructions are lane-sensitive and which are not. ** 17// ** A lane-sensitive instruction relies, implicitly or explicitly, on ** 18// ** whether lanes are numbered from left to right. An instruction like ** 19// ** VADDFP is not lane-sensitive, because each lane of the result vector ** 20// ** relies only on the corresponding lane of the source vectors. However, ** 21// ** an instruction like VMULESB is lane-sensitive, because "even" and ** 22// ** "odd" lanes are different for big-endian and little-endian numbering. ** 23// ** ** 24// ** When adding new VMX and VSX instructions, please consider whether they ** 25// ** are lane-sensitive. If so, they must be added to a switch statement ** 26// ** in PPCVSXSwapRemoval::gatherVectorInstructions(). ** 27// **************************************************************************** 28 29//===----------------------------------------------------------------------===// 30// Altivec transformation functions and pattern fragments. 31// 32 33// Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be 34// of that type. 35def vnot_ppc : PatFrag<(ops node:$in), 36 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>; 37 38def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 39 (vector_shuffle node:$lhs, node:$rhs), [{ 40 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 41}]>; 42def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 43 (vector_shuffle node:$lhs, node:$rhs), [{ 44 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 45}]>; 46def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 47 (vector_shuffle node:$lhs, node:$rhs), [{ 48 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 49}]>; 50def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 51 (vector_shuffle node:$lhs, node:$rhs), [{ 52 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 53}]>; 54 55// These fragments are provided for little-endian, where the inputs must be 56// swapped for correct semantics. 57def vpkuhum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 58 (vector_shuffle node:$lhs, node:$rhs), [{ 59 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 60}]>; 61def vpkuwum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 62 (vector_shuffle node:$lhs, node:$rhs), [{ 63 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 64}]>; 65 66def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 67 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 68 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG); 69}]>; 70def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 71 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 72 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG); 73}]>; 74def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 75 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 76 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG); 77}]>; 78def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 79 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 80 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG); 81}]>; 82def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 83 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 84 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG); 85}]>; 86def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 87 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 88 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG); 89}]>; 90 91 92def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 93 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 94 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG); 95}]>; 96def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 97 (vector_shuffle node:$lhs, node:$rhs), [{ 98 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG); 99}]>; 100def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 101 (vector_shuffle node:$lhs, node:$rhs), [{ 102 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG); 103}]>; 104def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 105 (vector_shuffle node:$lhs, node:$rhs), [{ 106 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG); 107}]>; 108def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 109 (vector_shuffle node:$lhs, node:$rhs), [{ 110 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG); 111}]>; 112def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 113 (vector_shuffle node:$lhs, node:$rhs), [{ 114 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG); 115}]>; 116 117 118// These fragments are provided for little-endian, where the inputs must be 119// swapped for correct semantics. 120def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 121 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 122 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG); 123}]>; 124def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 125 (vector_shuffle node:$lhs, node:$rhs), [{ 126 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG); 127}]>; 128def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 129 (vector_shuffle node:$lhs, node:$rhs), [{ 130 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG); 131}]>; 132def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 133 (vector_shuffle node:$lhs, node:$rhs), [{ 134 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG); 135}]>; 136def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 137 (vector_shuffle node:$lhs, node:$rhs), [{ 138 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG); 139}]>; 140def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 141 (vector_shuffle node:$lhs, node:$rhs), [{ 142 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG); 143}]>; 144 145 146def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{ 147 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 0, *CurDAG), SDLoc(N)); 148}]>; 149def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 150 (vector_shuffle node:$lhs, node:$rhs), [{ 151 return PPC::isVSLDOIShuffleMask(N, 0, *CurDAG) != -1; 152}], VSLDOI_get_imm>; 153 154 155/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into 156/// vector_shuffle(X,undef,mask) by the dag combiner. 157def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{ 158 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 1, *CurDAG), SDLoc(N)); 159}]>; 160def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 161 (vector_shuffle node:$lhs, node:$rhs), [{ 162 return PPC::isVSLDOIShuffleMask(N, 1, *CurDAG) != -1; 163}], VSLDOI_unary_get_imm>; 164 165 166/// VSLDOI_swapped* - These fragments are provided for little-endian, where 167/// the inputs must be swapped for correct semantics. 168def VSLDOI_swapped_get_imm : SDNodeXForm<vector_shuffle, [{ 169 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 2, *CurDAG), SDLoc(N)); 170}]>; 171def vsldoi_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 172 (vector_shuffle node:$lhs, node:$rhs), [{ 173 return PPC::isVSLDOIShuffleMask(N, 2, *CurDAG) != -1; 174}], VSLDOI_get_imm>; 175 176 177// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. 178def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{ 179 return getI32Imm(PPC::getVSPLTImmediate(N, 1, *CurDAG), SDLoc(N)); 180}]>; 181def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 182 (vector_shuffle node:$lhs, node:$rhs), [{ 183 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1); 184}], VSPLTB_get_imm>; 185def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{ 186 return getI32Imm(PPC::getVSPLTImmediate(N, 2, *CurDAG), SDLoc(N)); 187}]>; 188def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 189 (vector_shuffle node:$lhs, node:$rhs), [{ 190 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2); 191}], VSPLTH_get_imm>; 192def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{ 193 return getI32Imm(PPC::getVSPLTImmediate(N, 4, *CurDAG), SDLoc(N)); 194}]>; 195def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 196 (vector_shuffle node:$lhs, node:$rhs), [{ 197 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4); 198}], VSPLTW_get_imm>; 199 200 201// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. 202def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{ 203 return PPC::get_VSPLTI_elt(N, 1, *CurDAG); 204}]>; 205def vecspltisb : PatLeaf<(build_vector), [{ 206 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0; 207}], VSPLTISB_get_imm>; 208 209// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm. 210def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{ 211 return PPC::get_VSPLTI_elt(N, 2, *CurDAG); 212}]>; 213def vecspltish : PatLeaf<(build_vector), [{ 214 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0; 215}], VSPLTISH_get_imm>; 216 217// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm. 218def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{ 219 return PPC::get_VSPLTI_elt(N, 4, *CurDAG); 220}]>; 221def vecspltisw : PatLeaf<(build_vector), [{ 222 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0; 223}], VSPLTISW_get_imm>; 224 225//===----------------------------------------------------------------------===// 226// Helpers for defining instructions that directly correspond to intrinsics. 227 228// VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type. 229class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty> 230 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 231 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 232 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>; 233 234// VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the 235// inputs doesn't match the type of the output. 236class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 237 ValueType InTy> 238 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 239 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 240 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>; 241 242// VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two 243// input types and an output type. 244class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 245 ValueType In1Ty, ValueType In2Ty> 246 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 247 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 248 [(set OutTy:$vD, 249 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>; 250 251// VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type. 252class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 253 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 254 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 255 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>; 256 257// VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the 258// inputs doesn't match the type of the output. 259class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 260 ValueType InTy> 261 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 262 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 263 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>; 264 265// VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two 266// input types and an output type. 267class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 268 ValueType In1Ty, ValueType In2Ty> 269 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 270 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 271 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>; 272 273// VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type. 274class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID> 275 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 276 !strconcat(opc, " $vD, $vB"), IIC_VecFP, 277 [(set v4f32:$vD, (IntID v4f32:$vB))]>; 278 279// VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the 280// inputs doesn't match the type of the output. 281class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 282 ValueType InTy> 283 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 284 !strconcat(opc, " $vD, $vB"), IIC_VecFP, 285 [(set OutTy:$vD, (IntID InTy:$vB))]>; 286 287class VXBX_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 288 : VXForm_BX<xo, (outs vrrc:$vD), (ins vrrc:$vA), 289 !strconcat(opc, " $vD, $vA"), IIC_VecFP, 290 [(set Ty:$vD, (IntID Ty:$vA))]>; 291 292class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 293 : VXForm_CR<xo, (outs vrrc:$vD), (ins vrrc:$vA, u1imm:$ST, u4imm:$SIX), 294 !strconcat(opc, " $vD, $vA, $ST, $SIX"), IIC_VecFP, 295 [(set Ty:$vD, (IntID Ty:$vA, imm:$ST, imm:$SIX))]>; 296 297//===----------------------------------------------------------------------===// 298// Instruction Definitions. 299 300def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">; 301let Predicates = [HasAltivec] in { 302 303def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM), 304 "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>, 305 Deprecated<DeprecatedDST> { 306 let A = 0; 307 let B = 0; 308} 309 310def DSSALL : DSS_Form<1, 822, (outs), (ins), 311 "dssall", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dssall)]>, 312 Deprecated<DeprecatedDST> { 313 let STRM = 0; 314 let A = 0; 315 let B = 0; 316} 317 318def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 319 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 320 [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>, 321 Deprecated<DeprecatedDST>; 322 323def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 324 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 325 [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>, 326 Deprecated<DeprecatedDST>; 327 328def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 329 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 330 [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>, 331 Deprecated<DeprecatedDST>; 332 333def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 334 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 335 [(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>, 336 Deprecated<DeprecatedDST>; 337 338let isCodeGenOnly = 1 in { 339 // The very same instructions as above, but formally matching 64bit registers. 340 def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 341 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 342 [(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>, 343 Deprecated<DeprecatedDST>; 344 345 def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 346 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 347 [(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>, 348 Deprecated<DeprecatedDST>; 349 350 def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 351 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 352 [(int_ppc_altivec_dstst i64:$rA, i32:$rB, 353 imm:$STRM)]>, 354 Deprecated<DeprecatedDST>; 355 356 def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 357 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 358 [(int_ppc_altivec_dststt i64:$rA, i32:$rB, 359 imm:$STRM)]>, 360 Deprecated<DeprecatedDST>; 361} 362 363def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins), 364 "mfvscr $vD", IIC_LdStStore, 365 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>; 366def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB), 367 "mtvscr $vB", IIC_LdStLoad, 368 [(int_ppc_altivec_mtvscr v4i32:$vB)]>; 369 370let PPC970_Unit = 2 in { // Loads. 371def LVEBX: XForm_1<31, 7, (outs vrrc:$vD), (ins memrr:$src), 372 "lvebx $vD, $src", IIC_LdStLoad, 373 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; 374def LVEHX: XForm_1<31, 39, (outs vrrc:$vD), (ins memrr:$src), 375 "lvehx $vD, $src", IIC_LdStLoad, 376 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>; 377def LVEWX: XForm_1<31, 71, (outs vrrc:$vD), (ins memrr:$src), 378 "lvewx $vD, $src", IIC_LdStLoad, 379 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; 380def LVX : XForm_1<31, 103, (outs vrrc:$vD), (ins memrr:$src), 381 "lvx $vD, $src", IIC_LdStLoad, 382 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; 383def LVXL : XForm_1<31, 359, (outs vrrc:$vD), (ins memrr:$src), 384 "lvxl $vD, $src", IIC_LdStLoad, 385 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; 386} 387 388def LVSL : XForm_1<31, 6, (outs vrrc:$vD), (ins memrr:$src), 389 "lvsl $vD, $src", IIC_LdStLoad, 390 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, 391 PPC970_Unit_LSU; 392def LVSR : XForm_1<31, 38, (outs vrrc:$vD), (ins memrr:$src), 393 "lvsr $vD, $src", IIC_LdStLoad, 394 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, 395 PPC970_Unit_LSU; 396 397let PPC970_Unit = 2 in { // Stores. 398def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS, memrr:$dst), 399 "stvebx $rS, $dst", IIC_LdStStore, 400 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>; 401def STVEHX: XForm_8<31, 167, (outs), (ins vrrc:$rS, memrr:$dst), 402 "stvehx $rS, $dst", IIC_LdStStore, 403 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>; 404def STVEWX: XForm_8<31, 199, (outs), (ins vrrc:$rS, memrr:$dst), 405 "stvewx $rS, $dst", IIC_LdStStore, 406 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>; 407def STVX : XForm_8<31, 231, (outs), (ins vrrc:$rS, memrr:$dst), 408 "stvx $rS, $dst", IIC_LdStStore, 409 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>; 410def STVXL : XForm_8<31, 487, (outs), (ins vrrc:$rS, memrr:$dst), 411 "stvxl $rS, $dst", IIC_LdStStore, 412 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>; 413} 414 415let PPC970_Unit = 5 in { // VALU Operations. 416// VA-Form instructions. 3-input AltiVec ops. 417let isCommutable = 1 in { 418def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 419 "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP, 420 [(set v4f32:$vD, 421 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>; 422 423// FIXME: The fma+fneg pattern won't match because fneg is not legal. 424def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 425 "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP, 426 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC, 427 (fneg v4f32:$vB))))]>; 428 429def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>; 430def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs, 431 v8i16>; 432def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>; 433} // isCommutable 434 435def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm, 436 v4i32, v4i32, v16i8>; 437def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>; 438 439// Shuffles. 440def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u5imm:$SH), 441 "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP, 442 [(set v16i8:$vD, 443 (vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>; 444 445// VX-Form instructions. AltiVec arithmetic ops. 446let isCommutable = 1 in { 447def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 448 "vaddfp $vD, $vA, $vB", IIC_VecFP, 449 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>; 450 451def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 452 "vaddubm $vD, $vA, $vB", IIC_VecGeneral, 453 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>; 454def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 455 "vadduhm $vD, $vA, $vB", IIC_VecGeneral, 456 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>; 457def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 458 "vadduwm $vD, $vA, $vB", IIC_VecGeneral, 459 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>; 460 461def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>; 462def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>; 463def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>; 464def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>; 465def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>; 466def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>; 467def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>; 468} // isCommutable 469 470let isCommutable = 1 in 471def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 472 "vand $vD, $vA, $vB", IIC_VecFP, 473 [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>; 474def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 475 "vandc $vD, $vA, $vB", IIC_VecFP, 476 [(set v4i32:$vD, (and v4i32:$vA, 477 (vnot_ppc v4i32:$vB)))]>; 478 479def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 480 "vcfsx $vD, $vB, $UIMM", IIC_VecFP, 481 [(set v4f32:$vD, 482 (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>; 483def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 484 "vcfux $vD, $vB, $UIMM", IIC_VecFP, 485 [(set v4f32:$vD, 486 (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>; 487def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 488 "vctsxs $vD, $vB, $UIMM", IIC_VecFP, 489 [(set v4i32:$vD, 490 (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>; 491def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 492 "vctuxs $vD, $vB, $UIMM", IIC_VecFP, 493 [(set v4i32:$vD, 494 (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>; 495 496// Defines with the UIM field set to 0 for floating-point 497// to integer (fp_to_sint/fp_to_uint) conversions and integer 498// to floating-point (sint_to_fp/uint_to_fp) conversions. 499let isCodeGenOnly = 1, VA = 0 in { 500def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB), 501 "vcfsx $vD, $vB, 0", IIC_VecFP, 502 [(set v4f32:$vD, 503 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>; 504def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB), 505 "vctuxs $vD, $vB, 0", IIC_VecFP, 506 [(set v4i32:$vD, 507 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>; 508def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB), 509 "vcfux $vD, $vB, 0", IIC_VecFP, 510 [(set v4f32:$vD, 511 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>; 512def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB), 513 "vctsxs $vD, $vB, 0", IIC_VecFP, 514 [(set v4i32:$vD, 515 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>; 516} 517def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>; 518def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>; 519 520let isCommutable = 1 in { 521def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>; 522def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>; 523def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>; 524def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>; 525def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>; 526def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>; 527 528def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>; 529def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>; 530def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>; 531def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>; 532def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>; 533def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>; 534def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>; 535def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>; 536def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>; 537def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>; 538def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>; 539def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>; 540def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>; 541def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>; 542} // isCommutable 543 544def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 545 "vmrghb $vD, $vA, $vB", IIC_VecFP, 546 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>; 547def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 548 "vmrghh $vD, $vA, $vB", IIC_VecFP, 549 [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>; 550def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 551 "vmrghw $vD, $vA, $vB", IIC_VecFP, 552 [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>; 553def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 554 "vmrglb $vD, $vA, $vB", IIC_VecFP, 555 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>; 556def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 557 "vmrglh $vD, $vA, $vB", IIC_VecFP, 558 [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>; 559def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 560 "vmrglw $vD, $vA, $vB", IIC_VecFP, 561 [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>; 562 563def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm, 564 v4i32, v16i8, v4i32>; 565def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm, 566 v4i32, v8i16, v4i32>; 567def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs, 568 v4i32, v8i16, v4i32>; 569def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm, 570 v4i32, v16i8, v4i32>; 571def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm, 572 v4i32, v8i16, v4i32>; 573def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs, 574 v4i32, v8i16, v4i32>; 575 576let isCommutable = 1 in { 577def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb, 578 v8i16, v16i8>; 579def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh, 580 v4i32, v8i16>; 581def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub, 582 v8i16, v16i8>; 583def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh, 584 v4i32, v8i16>; 585def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb, 586 v8i16, v16i8>; 587def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh, 588 v4i32, v8i16>; 589def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub, 590 v8i16, v16i8>; 591def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh, 592 v4i32, v8i16>; 593} // isCommutable 594 595def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>; 596def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>; 597def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>; 598def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>; 599def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>; 600def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; 601 602def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>; 603 604def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 605 "vsubfp $vD, $vA, $vB", IIC_VecGeneral, 606 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>; 607def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 608 "vsububm $vD, $vA, $vB", IIC_VecGeneral, 609 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>; 610def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 611 "vsubuhm $vD, $vA, $vB", IIC_VecGeneral, 612 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>; 613def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 614 "vsubuwm $vD, $vA, $vB", IIC_VecGeneral, 615 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>; 616 617def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>; 618def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>; 619def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>; 620def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>; 621def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>; 622def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>; 623 624def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>; 625def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>; 626 627def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs, 628 v4i32, v16i8, v4i32>; 629def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs, 630 v4i32, v8i16, v4i32>; 631def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs, 632 v4i32, v16i8, v4i32>; 633 634def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 635 "vnor $vD, $vA, $vB", IIC_VecFP, 636 [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA, 637 v4i32:$vB)))]>; 638let isCommutable = 1 in { 639def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 640 "vor $vD, $vA, $vB", IIC_VecFP, 641 [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>; 642def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 643 "vxor $vD, $vA, $vB", IIC_VecFP, 644 [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>; 645} // isCommutable 646 647def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>; 648def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>; 649def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>; 650 651def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >; 652def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>; 653 654def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>; 655def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>; 656def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>; 657 658def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 659 "vspltb $vD, $vB, $UIMM", IIC_VecPerm, 660 [(set v16i8:$vD, 661 (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>; 662def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 663 "vsplth $vD, $vB, $UIMM", IIC_VecPerm, 664 [(set v16i8:$vD, 665 (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>; 666def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 667 "vspltw $vD, $vB, $UIMM", IIC_VecPerm, 668 [(set v16i8:$vD, 669 (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>; 670 671def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>; 672def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>; 673 674def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>; 675def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>; 676def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>; 677def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>; 678def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>; 679def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>; 680 681 682def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM), 683 "vspltisb $vD, $SIMM", IIC_VecPerm, 684 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>; 685def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM), 686 "vspltish $vD, $SIMM", IIC_VecPerm, 687 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>; 688def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM), 689 "vspltisw $vD, $SIMM", IIC_VecPerm, 690 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>; 691 692// Vector Pack. 693def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx, 694 v8i16, v4i32>; 695def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss, 696 v16i8, v8i16>; 697def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus, 698 v16i8, v8i16>; 699def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss, 700 v16i8, v4i32>; 701def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus, 702 v8i16, v4i32>; 703def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 704 "vpkuhum $vD, $vA, $vB", IIC_VecFP, 705 [(set v16i8:$vD, 706 (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>; 707def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus, 708 v16i8, v8i16>; 709def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 710 "vpkuwum $vD, $vA, $vB", IIC_VecFP, 711 [(set v16i8:$vD, 712 (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>; 713def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus, 714 v8i16, v4i32>; 715 716// Vector Unpack. 717def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx, 718 v4i32, v8i16>; 719def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb, 720 v8i16, v16i8>; 721def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh, 722 v4i32, v8i16>; 723def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx, 724 v4i32, v8i16>; 725def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb, 726 v8i16, v16i8>; 727def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh, 728 v4i32, v8i16>; 729 730 731// Altivec Comparisons. 732 733class VCMP<bits<10> xo, string asmstr, ValueType Ty> 734 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, 735 IIC_VecFPCompare, 736 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>; 737class VCMPo<bits<10> xo, string asmstr, ValueType Ty> 738 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, 739 IIC_VecFPCompare, 740 [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> { 741 let Defs = [CR6]; 742 let RC = 1; 743} 744 745// f32 element comparisons.0 746def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; 747def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>; 748def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>; 749def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>; 750def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>; 751def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>; 752def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>; 753def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>; 754 755// i8 element comparisons. 756def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>; 757def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>; 758def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>; 759def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>; 760def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>; 761def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>; 762 763// i16 element comparisons. 764def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>; 765def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>; 766def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>; 767def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>; 768def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>; 769def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>; 770 771// i32 element comparisons. 772def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>; 773def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>; 774def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>; 775def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; 776def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; 777def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; 778 779let isCodeGenOnly = 1 in { 780def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 781 "vxor $vD, $vD, $vD", IIC_VecFP, 782 [(set v16i8:$vD, (v16i8 immAllZerosV))]>; 783def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 784 "vxor $vD, $vD, $vD", IIC_VecFP, 785 [(set v8i16:$vD, (v8i16 immAllZerosV))]>; 786def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 787 "vxor $vD, $vD, $vD", IIC_VecFP, 788 [(set v4i32:$vD, (v4i32 immAllZerosV))]>; 789 790let IMM=-1 in { 791def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins), 792 "vspltisw $vD, -1", IIC_VecFP, 793 [(set v16i8:$vD, (v16i8 immAllOnesV))]>; 794def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins), 795 "vspltisw $vD, -1", IIC_VecFP, 796 [(set v8i16:$vD, (v8i16 immAllOnesV))]>; 797def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins), 798 "vspltisw $vD, -1", IIC_VecFP, 799 [(set v4i32:$vD, (v4i32 immAllOnesV))]>; 800} 801} 802} // VALU Operations. 803 804//===----------------------------------------------------------------------===// 805// Additional Altivec Patterns 806// 807 808// Loads. 809def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; 810 811// Stores. 812def : Pat<(store v4i32:$rS, xoaddr:$dst), 813 (STVX $rS, xoaddr:$dst)>; 814 815// Bit conversions. 816def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>; 817def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>; 818def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>; 819def : Pat<(v16i8 (bitconvert (v2i64 VRRC:$src))), (v16i8 VRRC:$src)>; 820 821def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>; 822def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>; 823def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>; 824def : Pat<(v8i16 (bitconvert (v2i64 VRRC:$src))), (v8i16 VRRC:$src)>; 825 826def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>; 827def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>; 828def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>; 829def : Pat<(v4i32 (bitconvert (v2i64 VRRC:$src))), (v4i32 VRRC:$src)>; 830 831def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>; 832def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>; 833def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>; 834def : Pat<(v4f32 (bitconvert (v2i64 VRRC:$src))), (v4f32 VRRC:$src)>; 835 836def : Pat<(v2i64 (bitconvert (v16i8 VRRC:$src))), (v2i64 VRRC:$src)>; 837def : Pat<(v2i64 (bitconvert (v8i16 VRRC:$src))), (v2i64 VRRC:$src)>; 838def : Pat<(v2i64 (bitconvert (v4i32 VRRC:$src))), (v2i64 VRRC:$src)>; 839def : Pat<(v2i64 (bitconvert (v4f32 VRRC:$src))), (v2i64 VRRC:$src)>; 840 841// Shuffles. 842 843// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x) 844def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef), 845 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>; 846def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef), 847 (VPKUWUM $vA, $vA)>; 848def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef), 849 (VPKUHUM $vA, $vA)>; 850 851// Match vsldoi(y,x), vpkuwum(y,x), vpkuhum(y,x), i.e., swapped operands. 852// These fragments are matched for little-endian, where the inputs must 853// be swapped for correct semantics. 854def:Pat<(vsldoi_swapped_shuffle:$in v16i8:$vA, v16i8:$vB), 855 (VSLDOI $vB, $vA, (VSLDOI_swapped_get_imm $in))>; 856def:Pat<(vpkuwum_swapped_shuffle v16i8:$vA, v16i8:$vB), 857 (VPKUWUM $vB, $vA)>; 858def:Pat<(vpkuhum_swapped_shuffle v16i8:$vA, v16i8:$vB), 859 (VPKUHUM $vB, $vA)>; 860 861// Match vmrg*(x,x) 862def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef), 863 (VMRGLB $vA, $vA)>; 864def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef), 865 (VMRGLH $vA, $vA)>; 866def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef), 867 (VMRGLW $vA, $vA)>; 868def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef), 869 (VMRGHB $vA, $vA)>; 870def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef), 871 (VMRGHH $vA, $vA)>; 872def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef), 873 (VMRGHW $vA, $vA)>; 874 875// Match vmrg*(y,x), i.e., swapped operands. These fragments 876// are matched for little-endian, where the inputs must be 877// swapped for correct semantics. 878def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB), 879 (VMRGLB $vB, $vA)>; 880def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB), 881 (VMRGLH $vB, $vA)>; 882def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB), 883 (VMRGLW $vB, $vA)>; 884def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB), 885 (VMRGHB $vB, $vA)>; 886def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB), 887 (VMRGHH $vB, $vA)>; 888def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB), 889 (VMRGHW $vB, $vA)>; 890 891// Logical Operations 892def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>; 893 894def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)), 895 (VNOR $A, $B)>; 896def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)), 897 (VANDC $A, $B)>; 898 899def : Pat<(fmul v4f32:$vA, v4f32:$vB), 900 (VMADDFP $vA, $vB, 901 (v4i32 (VSLW (V_SETALLONES), (V_SETALLONES))))>; 902 903// Fused multiply add and multiply sub for packed float. These are represented 904// separately from the real instructions above, for operations that must have 905// the additional precision, such as Newton-Rhapson (used by divide, sqrt) 906def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 907 (VMADDFP $A, $B, $C)>; 908def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 909 (VNMSUBFP $A, $B, $C)>; 910 911def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 912 (VMADDFP $A, $B, $C)>; 913def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 914 (VNMSUBFP $A, $B, $C)>; 915 916def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC), 917 (VPERM $vA, $vB, $vC)>; 918 919def : Pat<(PPCfre v4f32:$A), (VREFP $A)>; 920def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>; 921 922// Vector shifts 923def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)), 924 (v16i8 (VSLB $vA, $vB))>; 925def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)), 926 (v8i16 (VSLH $vA, $vB))>; 927def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)), 928 (v4i32 (VSLW $vA, $vB))>; 929 930def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)), 931 (v16i8 (VSRB $vA, $vB))>; 932def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)), 933 (v8i16 (VSRH $vA, $vB))>; 934def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)), 935 (v4i32 (VSRW $vA, $vB))>; 936 937def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)), 938 (v16i8 (VSRAB $vA, $vB))>; 939def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)), 940 (v8i16 (VSRAH $vA, $vB))>; 941def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)), 942 (v4i32 (VSRAW $vA, $vB))>; 943 944// Float to integer and integer to float conversions 945def : Pat<(v4i32 (fp_to_sint v4f32:$vA)), 946 (VCTSXS_0 $vA)>; 947def : Pat<(v4i32 (fp_to_uint v4f32:$vA)), 948 (VCTUXS_0 $vA)>; 949def : Pat<(v4f32 (sint_to_fp v4i32:$vA)), 950 (VCFSX_0 $vA)>; 951def : Pat<(v4f32 (uint_to_fp v4i32:$vA)), 952 (VCFUX_0 $vA)>; 953 954// Floating-point rounding 955def : Pat<(v4f32 (ffloor v4f32:$vA)), 956 (VRFIM $vA)>; 957def : Pat<(v4f32 (fceil v4f32:$vA)), 958 (VRFIP $vA)>; 959def : Pat<(v4f32 (ftrunc v4f32:$vA)), 960 (VRFIZ $vA)>; 961def : Pat<(v4f32 (fnearbyint v4f32:$vA)), 962 (VRFIN $vA)>; 963 964} // end HasAltivec 965 966def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">; 967def HasP8Crypto : Predicate<"PPCSubTarget->hasP8Crypto()">; 968let Predicates = [HasP8Altivec] in { 969 970let isCommutable = 1 in { 971def VMULESW : VX1_Int_Ty2<904, "vmulesw", int_ppc_altivec_vmulesw, 972 v2i64, v4i32>; 973def VMULEUW : VX1_Int_Ty2<648, "vmuleuw", int_ppc_altivec_vmuleuw, 974 v2i64, v4i32>; 975def VMULOSW : VX1_Int_Ty2<392, "vmulosw", int_ppc_altivec_vmulosw, 976 v2i64, v4i32>; 977def VMULOUW : VX1_Int_Ty2<136, "vmulouw", int_ppc_altivec_vmulouw, 978 v2i64, v4i32>; 979def VMULUWM : VXForm_1<137, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 980 "vmuluwm $vD, $vA, $vB", IIC_VecGeneral, 981 [(set v4i32:$vD, (mul v4i32:$vA, v4i32:$vB))]>; 982def VMAXSD : VX1_Int_Ty<450, "vmaxsd", int_ppc_altivec_vmaxsd, v2i64>; 983def VMAXUD : VX1_Int_Ty<194, "vmaxud", int_ppc_altivec_vmaxud, v2i64>; 984def VMINSD : VX1_Int_Ty<962, "vminsd", int_ppc_altivec_vminsd, v2i64>; 985def VMINUD : VX1_Int_Ty<706, "vminud", int_ppc_altivec_vminud, v2i64>; 986} // isCommutable 987 988// Vector shifts 989def VRLD : VX1_Int_Ty<196, "vrld", int_ppc_altivec_vrld, v2i64>; 990def VSLD : VXForm_1<1476, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 991 "vsld $vD, $vA, $vB", IIC_VecGeneral, 992 [(set v2i64:$vD, (shl v2i64:$vA, v2i64:$vB))]>; 993def VSRD : VXForm_1<1732, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 994 "vsrd $vD, $vA, $vB", IIC_VecGeneral, 995 [(set v2i64:$vD, (srl v2i64:$vA, v2i64:$vB))]>; 996def VSRAD : VXForm_1<964, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 997 "vsrad $vD, $vA, $vB", IIC_VecGeneral, 998 [(set v2i64:$vD, (sra v2i64:$vA, v2i64:$vB))]>; 999 1000// Vector Integer Arithmetic Instructions 1001let isCommutable = 1 in { 1002def VADDUDM : VXForm_1<192, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1003 "vaddudm $vD, $vA, $vB", IIC_VecGeneral, 1004 [(set v2i64:$vD, (add v2i64:$vA, v2i64:$vB))]>; 1005} // isCommutable 1006 1007def VSUBUDM : VXForm_1<1216, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1008 "vsubudm $vD, $vA, $vB", IIC_VecGeneral, 1009 [(set v2i64:$vD, (sub v2i64:$vA, v2i64:$vB))]>; 1010 1011// Count Leading Zeros 1012def VCLZB : VXForm_2<1794, (outs vrrc:$vD), (ins vrrc:$vB), 1013 "vclzb $vD, $vB", IIC_VecGeneral, 1014 [(set v16i8:$vD, (ctlz v16i8:$vB))]>; 1015def VCLZH : VXForm_2<1858, (outs vrrc:$vD), (ins vrrc:$vB), 1016 "vclzh $vD, $vB", IIC_VecGeneral, 1017 [(set v8i16:$vD, (ctlz v8i16:$vB))]>; 1018def VCLZW : VXForm_2<1922, (outs vrrc:$vD), (ins vrrc:$vB), 1019 "vclzw $vD, $vB", IIC_VecGeneral, 1020 [(set v4i32:$vD, (ctlz v4i32:$vB))]>; 1021def VCLZD : VXForm_2<1986, (outs vrrc:$vD), (ins vrrc:$vB), 1022 "vclzd $vD, $vB", IIC_VecGeneral, 1023 [(set v2i64:$vD, (ctlz v2i64:$vB))]>; 1024 1025// Population Count 1026def VPOPCNTB : VXForm_2<1795, (outs vrrc:$vD), (ins vrrc:$vB), 1027 "vpopcntb $vD, $vB", IIC_VecGeneral, 1028 [(set v16i8:$vD, (ctpop v16i8:$vB))]>; 1029def VPOPCNTH : VXForm_2<1859, (outs vrrc:$vD), (ins vrrc:$vB), 1030 "vpopcnth $vD, $vB", IIC_VecGeneral, 1031 [(set v8i16:$vD, (ctpop v8i16:$vB))]>; 1032def VPOPCNTW : VXForm_2<1923, (outs vrrc:$vD), (ins vrrc:$vB), 1033 "vpopcntw $vD, $vB", IIC_VecGeneral, 1034 [(set v4i32:$vD, (ctpop v4i32:$vB))]>; 1035def VPOPCNTD : VXForm_2<1987, (outs vrrc:$vD), (ins vrrc:$vB), 1036 "vpopcntd $vD, $vB", IIC_VecGeneral, 1037 [(set v2i64:$vD, (ctpop v2i64:$vB))]>; 1038 1039let isCommutable = 1 in { 1040// FIXME: Use AddedComplexity > 400 to ensure these patterns match before the 1041// VSX equivalents. We need to fix this up at some point. Two possible 1042// solutions for this problem: 1043// 1. Disable Altivec patterns that compete with VSX patterns using the 1044// !HasVSX predicate. This essentially favours VSX over Altivec, in 1045// hopes of reducing register pressure (larger register set using VSX 1046// instructions than VMX instructions) 1047// 2. Employ a more disciplined use of AddedComplexity, which would provide 1048// more fine-grained control than option 1. This would be beneficial 1049// if we find situations where Altivec is really preferred over VSX. 1050def VEQV : VXForm_1<1668, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1051 "veqv $vD, $vA, $vB", IIC_VecGeneral, 1052 [(set v4i32:$vD, (vnot_ppc (xor v4i32:$vA, v4i32:$vB)))]>; 1053def VNAND : VXForm_1<1412, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1054 "vnand $vD, $vA, $vB", IIC_VecGeneral, 1055 [(set v4i32:$vD, (vnot_ppc (and v4i32:$vA, v4i32:$vB)))]>; 1056} // isCommutable 1057 1058def VORC : VXForm_1<1348, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1059 "vorc $vD, $vA, $vB", IIC_VecGeneral, 1060 [(set v4i32:$vD, (or v4i32:$vA, 1061 (vnot_ppc v4i32:$vB)))]>; 1062 1063// i64 element comparisons. 1064def VCMPEQUD : VCMP <199, "vcmpequd $vD, $vA, $vB" , v2i64>; 1065def VCMPEQUDo : VCMPo<199, "vcmpequd. $vD, $vA, $vB", v2i64>; 1066def VCMPGTSD : VCMP <967, "vcmpgtsd $vD, $vA, $vB" , v2i64>; 1067def VCMPGTSDo : VCMPo<967, "vcmpgtsd. $vD, $vA, $vB", v2i64>; 1068def VCMPGTUD : VCMP <711, "vcmpgtud $vD, $vA, $vB" , v2i64>; 1069def VCMPGTUDo : VCMPo<711, "vcmpgtud. $vD, $vA, $vB", v2i64>; 1070 1071// The cryptography instructions that do not require Category:Vector.Crypto 1072def VPMSUMB : VX1_Int_Ty<1032, "vpmsumb", 1073 int_ppc_altivec_crypto_vpmsumb, v16i8>; 1074def VPMSUMH : VX1_Int_Ty<1096, "vpmsumh", 1075 int_ppc_altivec_crypto_vpmsumh, v8i16>; 1076def VPMSUMW : VX1_Int_Ty<1160, "vpmsumw", 1077 int_ppc_altivec_crypto_vpmsumw, v4i32>; 1078def VPMSUMD : VX1_Int_Ty<1224, "vpmsumd", 1079 int_ppc_altivec_crypto_vpmsumd, v2i64>; 1080def VPERMXOR : VA1a_Int_Ty<45, "vpermxor", 1081 int_ppc_altivec_crypto_vpermxor, v16i8>; 1082 1083} // end HasP8Altivec 1084 1085// Crypto instructions (from builtins) 1086let Predicates = [HasP8Crypto] in { 1087def VSHASIGMAW : VXCR_Int_Ty<1666, "vshasigmaw", 1088 int_ppc_altivec_crypto_vshasigmaw, v4i32>; 1089def VSHASIGMAD : VXCR_Int_Ty<1730, "vshasigmad", 1090 int_ppc_altivec_crypto_vshasigmad, v2i64>; 1091def VCIPHER : VX1_Int_Ty<1288, "vcipher", int_ppc_altivec_crypto_vcipher, 1092 v2i64>; 1093def VCIPHERLAST : VX1_Int_Ty<1289, "vcipherlast", 1094 int_ppc_altivec_crypto_vcipherlast, v2i64>; 1095def VNCIPHER : VX1_Int_Ty<1352, "vncipher", 1096 int_ppc_altivec_crypto_vncipher, v2i64>; 1097def VNCIPHERLAST : VX1_Int_Ty<1353, "vncipherlast", 1098 int_ppc_altivec_crypto_vncipherlast, v2i64>; 1099def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>; 1100} // HasP8Crypto 1101