1//===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Altivec extension to the PowerPC instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Altivec transformation functions and pattern fragments. 16// 17 18// Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be 19// of that type. 20def vnot_ppc : PatFrag<(ops node:$in), 21 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>; 22 23def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 24 (vector_shuffle node:$lhs, node:$rhs), [{ 25 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 26}]>; 27def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 28 (vector_shuffle node:$lhs, node:$rhs), [{ 29 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 30}]>; 31def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 32 (vector_shuffle node:$lhs, node:$rhs), [{ 33 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 34}]>; 35def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 36 (vector_shuffle node:$lhs, node:$rhs), [{ 37 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 38}]>; 39 40// These fragments are provided for little-endian, where the inputs must be 41// swapped for correct semantics. 42def vpkuhum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 43 (vector_shuffle node:$lhs, node:$rhs), [{ 44 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 45}]>; 46def vpkuwum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 47 (vector_shuffle node:$lhs, node:$rhs), [{ 48 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 49}]>; 50 51def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 52 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 53 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG); 54}]>; 55def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 56 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 57 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG); 58}]>; 59def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 60 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 61 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG); 62}]>; 63def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 64 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 65 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG); 66}]>; 67def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 68 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 69 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG); 70}]>; 71def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 72 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 73 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG); 74}]>; 75 76 77def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 78 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 79 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG); 80}]>; 81def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 82 (vector_shuffle node:$lhs, node:$rhs), [{ 83 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG); 84}]>; 85def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 86 (vector_shuffle node:$lhs, node:$rhs), [{ 87 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG); 88}]>; 89def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 90 (vector_shuffle node:$lhs, node:$rhs), [{ 91 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG); 92}]>; 93def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 94 (vector_shuffle node:$lhs, node:$rhs), [{ 95 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG); 96}]>; 97def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 98 (vector_shuffle node:$lhs, node:$rhs), [{ 99 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG); 100}]>; 101 102 103// These fragments are provided for little-endian, where the inputs must be 104// swapped for correct semantics. 105def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 106 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 107 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG); 108}]>; 109def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 110 (vector_shuffle node:$lhs, node:$rhs), [{ 111 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG); 112}]>; 113def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 114 (vector_shuffle node:$lhs, node:$rhs), [{ 115 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG); 116}]>; 117def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 118 (vector_shuffle node:$lhs, node:$rhs), [{ 119 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG); 120}]>; 121def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 122 (vector_shuffle node:$lhs, node:$rhs), [{ 123 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG); 124}]>; 125def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 126 (vector_shuffle node:$lhs, node:$rhs), [{ 127 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG); 128}]>; 129 130 131def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{ 132 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 0, *CurDAG)); 133}]>; 134def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 135 (vector_shuffle node:$lhs, node:$rhs), [{ 136 return PPC::isVSLDOIShuffleMask(N, 0, *CurDAG) != -1; 137}], VSLDOI_get_imm>; 138 139 140/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into 141/// vector_shuffle(X,undef,mask) by the dag combiner. 142def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{ 143 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 1, *CurDAG)); 144}]>; 145def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 146 (vector_shuffle node:$lhs, node:$rhs), [{ 147 return PPC::isVSLDOIShuffleMask(N, 1, *CurDAG) != -1; 148}], VSLDOI_unary_get_imm>; 149 150 151/// VSLDOI_swapped* - These fragments are provided for little-endian, where 152/// the inputs must be swapped for correct semantics. 153def VSLDOI_swapped_get_imm : SDNodeXForm<vector_shuffle, [{ 154 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 2, *CurDAG)); 155}]>; 156def vsldoi_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 157 (vector_shuffle node:$lhs, node:$rhs), [{ 158 return PPC::isVSLDOIShuffleMask(N, 2, *CurDAG) != -1; 159}], VSLDOI_get_imm>; 160 161 162// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. 163def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{ 164 return getI32Imm(PPC::getVSPLTImmediate(N, 1, *CurDAG)); 165}]>; 166def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 167 (vector_shuffle node:$lhs, node:$rhs), [{ 168 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1); 169}], VSPLTB_get_imm>; 170def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{ 171 return getI32Imm(PPC::getVSPLTImmediate(N, 2, *CurDAG)); 172}]>; 173def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 174 (vector_shuffle node:$lhs, node:$rhs), [{ 175 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2); 176}], VSPLTH_get_imm>; 177def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{ 178 return getI32Imm(PPC::getVSPLTImmediate(N, 4, *CurDAG)); 179}]>; 180def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 181 (vector_shuffle node:$lhs, node:$rhs), [{ 182 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4); 183}], VSPLTW_get_imm>; 184 185 186// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. 187def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{ 188 return PPC::get_VSPLTI_elt(N, 1, *CurDAG); 189}]>; 190def vecspltisb : PatLeaf<(build_vector), [{ 191 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0; 192}], VSPLTISB_get_imm>; 193 194// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm. 195def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{ 196 return PPC::get_VSPLTI_elt(N, 2, *CurDAG); 197}]>; 198def vecspltish : PatLeaf<(build_vector), [{ 199 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0; 200}], VSPLTISH_get_imm>; 201 202// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm. 203def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{ 204 return PPC::get_VSPLTI_elt(N, 4, *CurDAG); 205}]>; 206def vecspltisw : PatLeaf<(build_vector), [{ 207 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0; 208}], VSPLTISW_get_imm>; 209 210//===----------------------------------------------------------------------===// 211// Helpers for defining instructions that directly correspond to intrinsics. 212 213// VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type. 214class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty> 215 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 216 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 217 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>; 218 219// VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the 220// inputs doesn't match the type of the output. 221class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 222 ValueType InTy> 223 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 224 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 225 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>; 226 227// VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two 228// input types and an output type. 229class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 230 ValueType In1Ty, ValueType In2Ty> 231 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 232 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 233 [(set OutTy:$vD, 234 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>; 235 236// VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type. 237class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 238 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 239 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 240 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>; 241 242// VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the 243// inputs doesn't match the type of the output. 244class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 245 ValueType InTy> 246 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 247 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 248 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>; 249 250// VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two 251// input types and an output type. 252class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 253 ValueType In1Ty, ValueType In2Ty> 254 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 255 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 256 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>; 257 258// VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type. 259class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID> 260 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 261 !strconcat(opc, " $vD, $vB"), IIC_VecFP, 262 [(set v4f32:$vD, (IntID v4f32:$vB))]>; 263 264// VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the 265// inputs doesn't match the type of the output. 266class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 267 ValueType InTy> 268 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 269 !strconcat(opc, " $vD, $vB"), IIC_VecFP, 270 [(set OutTy:$vD, (IntID InTy:$vB))]>; 271 272//===----------------------------------------------------------------------===// 273// Instruction Definitions. 274 275def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">; 276let Predicates = [HasAltivec] in { 277 278def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM), 279 "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>, 280 Deprecated<DeprecatedDST> { 281 let A = 0; 282 let B = 0; 283} 284 285def DSSALL : DSS_Form<1, 822, (outs), (ins), 286 "dssall", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dssall)]>, 287 Deprecated<DeprecatedDST> { 288 let STRM = 0; 289 let A = 0; 290 let B = 0; 291} 292 293def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 294 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 295 [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>, 296 Deprecated<DeprecatedDST>; 297 298def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 299 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 300 [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>, 301 Deprecated<DeprecatedDST>; 302 303def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 304 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 305 [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>, 306 Deprecated<DeprecatedDST>; 307 308def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 309 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 310 [(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>, 311 Deprecated<DeprecatedDST>; 312 313let isCodeGenOnly = 1 in { 314 // The very same instructions as above, but formally matching 64bit registers. 315 def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 316 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 317 [(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>, 318 Deprecated<DeprecatedDST>; 319 320 def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 321 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 322 [(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>, 323 Deprecated<DeprecatedDST>; 324 325 def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 326 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 327 [(int_ppc_altivec_dstst i64:$rA, i32:$rB, 328 imm:$STRM)]>, 329 Deprecated<DeprecatedDST>; 330 331 def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 332 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 333 [(int_ppc_altivec_dststt i64:$rA, i32:$rB, 334 imm:$STRM)]>, 335 Deprecated<DeprecatedDST>; 336} 337 338def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins), 339 "mfvscr $vD", IIC_LdStStore, 340 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>; 341def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB), 342 "mtvscr $vB", IIC_LdStLoad, 343 [(int_ppc_altivec_mtvscr v4i32:$vB)]>; 344 345let canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads. 346def LVEBX: XForm_1<31, 7, (outs vrrc:$vD), (ins memrr:$src), 347 "lvebx $vD, $src", IIC_LdStLoad, 348 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; 349def LVEHX: XForm_1<31, 39, (outs vrrc:$vD), (ins memrr:$src), 350 "lvehx $vD, $src", IIC_LdStLoad, 351 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>; 352def LVEWX: XForm_1<31, 71, (outs vrrc:$vD), (ins memrr:$src), 353 "lvewx $vD, $src", IIC_LdStLoad, 354 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; 355def LVX : XForm_1<31, 103, (outs vrrc:$vD), (ins memrr:$src), 356 "lvx $vD, $src", IIC_LdStLoad, 357 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; 358def LVXL : XForm_1<31, 359, (outs vrrc:$vD), (ins memrr:$src), 359 "lvxl $vD, $src", IIC_LdStLoad, 360 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; 361} 362 363def LVSL : XForm_1<31, 6, (outs vrrc:$vD), (ins memrr:$src), 364 "lvsl $vD, $src", IIC_LdStLoad, 365 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, 366 PPC970_Unit_LSU; 367def LVSR : XForm_1<31, 38, (outs vrrc:$vD), (ins memrr:$src), 368 "lvsr $vD, $src", IIC_LdStLoad, 369 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, 370 PPC970_Unit_LSU; 371 372let PPC970_Unit = 2 in { // Stores. 373def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS, memrr:$dst), 374 "stvebx $rS, $dst", IIC_LdStStore, 375 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>; 376def STVEHX: XForm_8<31, 167, (outs), (ins vrrc:$rS, memrr:$dst), 377 "stvehx $rS, $dst", IIC_LdStStore, 378 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>; 379def STVEWX: XForm_8<31, 199, (outs), (ins vrrc:$rS, memrr:$dst), 380 "stvewx $rS, $dst", IIC_LdStStore, 381 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>; 382def STVX : XForm_8<31, 231, (outs), (ins vrrc:$rS, memrr:$dst), 383 "stvx $rS, $dst", IIC_LdStStore, 384 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>; 385def STVXL : XForm_8<31, 487, (outs), (ins vrrc:$rS, memrr:$dst), 386 "stvxl $rS, $dst", IIC_LdStStore, 387 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>; 388} 389 390let PPC970_Unit = 5 in { // VALU Operations. 391// VA-Form instructions. 3-input AltiVec ops. 392let isCommutable = 1 in { 393def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 394 "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP, 395 [(set v4f32:$vD, 396 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>; 397 398// FIXME: The fma+fneg pattern won't match because fneg is not legal. 399def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 400 "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP, 401 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC, 402 (fneg v4f32:$vB))))]>; 403 404def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>; 405def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs, 406 v8i16>; 407def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>; 408} // isCommutable 409 410def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm, 411 v4i32, v4i32, v16i8>; 412def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>; 413 414// Shuffles. 415def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u5imm:$SH), 416 "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP, 417 [(set v16i8:$vD, 418 (vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>; 419 420// VX-Form instructions. AltiVec arithmetic ops. 421let isCommutable = 1 in { 422def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 423 "vaddfp $vD, $vA, $vB", IIC_VecFP, 424 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>; 425 426def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 427 "vaddubm $vD, $vA, $vB", IIC_VecGeneral, 428 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>; 429def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 430 "vadduhm $vD, $vA, $vB", IIC_VecGeneral, 431 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>; 432def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 433 "vadduwm $vD, $vA, $vB", IIC_VecGeneral, 434 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>; 435 436def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>; 437def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>; 438def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>; 439def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>; 440def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>; 441def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>; 442def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>; 443} // isCommutable 444 445let isCommutable = 1 in 446def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 447 "vand $vD, $vA, $vB", IIC_VecFP, 448 [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>; 449def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 450 "vandc $vD, $vA, $vB", IIC_VecFP, 451 [(set v4i32:$vD, (and v4i32:$vA, 452 (vnot_ppc v4i32:$vB)))]>; 453 454def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 455 "vcfsx $vD, $vB, $UIMM", IIC_VecFP, 456 [(set v4f32:$vD, 457 (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>; 458def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 459 "vcfux $vD, $vB, $UIMM", IIC_VecFP, 460 [(set v4f32:$vD, 461 (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>; 462def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 463 "vctsxs $vD, $vB, $UIMM", IIC_VecFP, 464 [(set v4i32:$vD, 465 (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>; 466def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 467 "vctuxs $vD, $vB, $UIMM", IIC_VecFP, 468 [(set v4i32:$vD, 469 (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>; 470 471// Defines with the UIM field set to 0 for floating-point 472// to integer (fp_to_sint/fp_to_uint) conversions and integer 473// to floating-point (sint_to_fp/uint_to_fp) conversions. 474let isCodeGenOnly = 1, VA = 0 in { 475def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB), 476 "vcfsx $vD, $vB, 0", IIC_VecFP, 477 [(set v4f32:$vD, 478 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>; 479def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB), 480 "vctuxs $vD, $vB, 0", IIC_VecFP, 481 [(set v4i32:$vD, 482 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>; 483def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB), 484 "vcfux $vD, $vB, 0", IIC_VecFP, 485 [(set v4f32:$vD, 486 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>; 487def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB), 488 "vctsxs $vD, $vB, 0", IIC_VecFP, 489 [(set v4i32:$vD, 490 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>; 491} 492def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>; 493def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>; 494 495let isCommutable = 1 in { 496def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>; 497def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>; 498def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>; 499def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>; 500def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>; 501def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>; 502 503def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>; 504def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>; 505def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>; 506def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>; 507def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>; 508def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>; 509def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>; 510def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>; 511def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>; 512def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>; 513def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>; 514def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>; 515def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>; 516def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>; 517} // isCommutable 518 519def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 520 "vmrghb $vD, $vA, $vB", IIC_VecFP, 521 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>; 522def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 523 "vmrghh $vD, $vA, $vB", IIC_VecFP, 524 [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>; 525def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 526 "vmrghw $vD, $vA, $vB", IIC_VecFP, 527 [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>; 528def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 529 "vmrglb $vD, $vA, $vB", IIC_VecFP, 530 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>; 531def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 532 "vmrglh $vD, $vA, $vB", IIC_VecFP, 533 [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>; 534def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 535 "vmrglw $vD, $vA, $vB", IIC_VecFP, 536 [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>; 537 538def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm, 539 v4i32, v16i8, v4i32>; 540def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm, 541 v4i32, v8i16, v4i32>; 542def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs, 543 v4i32, v8i16, v4i32>; 544def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm, 545 v4i32, v16i8, v4i32>; 546def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm, 547 v4i32, v8i16, v4i32>; 548def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs, 549 v4i32, v8i16, v4i32>; 550 551let isCommutable = 1 in { 552def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb, 553 v8i16, v16i8>; 554def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh, 555 v4i32, v8i16>; 556def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub, 557 v8i16, v16i8>; 558def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh, 559 v4i32, v8i16>; 560def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb, 561 v8i16, v16i8>; 562def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh, 563 v4i32, v8i16>; 564def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub, 565 v8i16, v16i8>; 566def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh, 567 v4i32, v8i16>; 568} // isCommutable 569 570def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>; 571def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>; 572def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>; 573def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>; 574def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>; 575def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; 576 577def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>; 578 579def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 580 "vsubfp $vD, $vA, $vB", IIC_VecGeneral, 581 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>; 582def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 583 "vsububm $vD, $vA, $vB", IIC_VecGeneral, 584 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>; 585def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 586 "vsubuhm $vD, $vA, $vB", IIC_VecGeneral, 587 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>; 588def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 589 "vsubuwm $vD, $vA, $vB", IIC_VecGeneral, 590 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>; 591 592def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>; 593def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>; 594def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>; 595def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>; 596def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>; 597def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>; 598 599def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>; 600def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>; 601 602def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs, 603 v4i32, v16i8, v4i32>; 604def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs, 605 v4i32, v8i16, v4i32>; 606def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs, 607 v4i32, v16i8, v4i32>; 608 609def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 610 "vnor $vD, $vA, $vB", IIC_VecFP, 611 [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA, 612 v4i32:$vB)))]>; 613let isCommutable = 1 in { 614def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 615 "vor $vD, $vA, $vB", IIC_VecFP, 616 [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>; 617def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 618 "vxor $vD, $vA, $vB", IIC_VecFP, 619 [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>; 620} // isCommutable 621 622def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>; 623def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>; 624def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>; 625 626def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >; 627def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>; 628 629def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>; 630def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>; 631def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>; 632 633def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 634 "vspltb $vD, $vB, $UIMM", IIC_VecPerm, 635 [(set v16i8:$vD, 636 (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>; 637def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 638 "vsplth $vD, $vB, $UIMM", IIC_VecPerm, 639 [(set v16i8:$vD, 640 (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>; 641def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 642 "vspltw $vD, $vB, $UIMM", IIC_VecPerm, 643 [(set v16i8:$vD, 644 (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>; 645 646def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>; 647def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>; 648 649def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>; 650def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>; 651def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>; 652def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>; 653def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>; 654def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>; 655 656 657def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM), 658 "vspltisb $vD, $SIMM", IIC_VecPerm, 659 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>; 660def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM), 661 "vspltish $vD, $SIMM", IIC_VecPerm, 662 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>; 663def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM), 664 "vspltisw $vD, $SIMM", IIC_VecPerm, 665 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>; 666 667// Vector Pack. 668def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx, 669 v8i16, v4i32>; 670def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss, 671 v16i8, v8i16>; 672def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus, 673 v16i8, v8i16>; 674def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss, 675 v16i8, v4i32>; 676def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus, 677 v8i16, v4i32>; 678def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 679 "vpkuhum $vD, $vA, $vB", IIC_VecFP, 680 [(set v16i8:$vD, 681 (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>; 682def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus, 683 v16i8, v8i16>; 684def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 685 "vpkuwum $vD, $vA, $vB", IIC_VecFP, 686 [(set v16i8:$vD, 687 (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>; 688def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus, 689 v8i16, v4i32>; 690 691// Vector Unpack. 692def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx, 693 v4i32, v8i16>; 694def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb, 695 v8i16, v16i8>; 696def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh, 697 v4i32, v8i16>; 698def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx, 699 v4i32, v8i16>; 700def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb, 701 v8i16, v16i8>; 702def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh, 703 v4i32, v8i16>; 704 705 706// Altivec Comparisons. 707 708class VCMP<bits<10> xo, string asmstr, ValueType Ty> 709 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, 710 IIC_VecFPCompare, 711 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>; 712class VCMPo<bits<10> xo, string asmstr, ValueType Ty> 713 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, 714 IIC_VecFPCompare, 715 [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> { 716 let Defs = [CR6]; 717 let RC = 1; 718} 719 720// f32 element comparisons.0 721def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; 722def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>; 723def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>; 724def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>; 725def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>; 726def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>; 727def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>; 728def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>; 729 730// i8 element comparisons. 731def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>; 732def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>; 733def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>; 734def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>; 735def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>; 736def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>; 737 738// i16 element comparisons. 739def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>; 740def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>; 741def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>; 742def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>; 743def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>; 744def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>; 745 746// i32 element comparisons. 747def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>; 748def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>; 749def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>; 750def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; 751def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; 752def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; 753 754let isCodeGenOnly = 1 in { 755def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 756 "vxor $vD, $vD, $vD", IIC_VecFP, 757 [(set v16i8:$vD, (v16i8 immAllZerosV))]>; 758def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 759 "vxor $vD, $vD, $vD", IIC_VecFP, 760 [(set v8i16:$vD, (v8i16 immAllZerosV))]>; 761def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 762 "vxor $vD, $vD, $vD", IIC_VecFP, 763 [(set v4i32:$vD, (v4i32 immAllZerosV))]>; 764 765let IMM=-1 in { 766def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins), 767 "vspltisw $vD, -1", IIC_VecFP, 768 [(set v16i8:$vD, (v16i8 immAllOnesV))]>; 769def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins), 770 "vspltisw $vD, -1", IIC_VecFP, 771 [(set v8i16:$vD, (v8i16 immAllOnesV))]>; 772def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins), 773 "vspltisw $vD, -1", IIC_VecFP, 774 [(set v4i32:$vD, (v4i32 immAllOnesV))]>; 775} 776} 777} // VALU Operations. 778 779//===----------------------------------------------------------------------===// 780// Additional Altivec Patterns 781// 782 783// Loads. 784def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; 785 786// Stores. 787def : Pat<(store v4i32:$rS, xoaddr:$dst), 788 (STVX $rS, xoaddr:$dst)>; 789 790// Bit conversions. 791def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>; 792def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>; 793def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>; 794def : Pat<(v16i8 (bitconvert (v2i64 VRRC:$src))), (v16i8 VRRC:$src)>; 795 796def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>; 797def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>; 798def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>; 799def : Pat<(v8i16 (bitconvert (v2i64 VRRC:$src))), (v8i16 VRRC:$src)>; 800 801def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>; 802def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>; 803def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>; 804def : Pat<(v4i32 (bitconvert (v2i64 VRRC:$src))), (v4i32 VRRC:$src)>; 805 806def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>; 807def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>; 808def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>; 809def : Pat<(v4f32 (bitconvert (v2i64 VRRC:$src))), (v4f32 VRRC:$src)>; 810 811def : Pat<(v2i64 (bitconvert (v16i8 VRRC:$src))), (v2i64 VRRC:$src)>; 812def : Pat<(v2i64 (bitconvert (v8i16 VRRC:$src))), (v2i64 VRRC:$src)>; 813def : Pat<(v2i64 (bitconvert (v4i32 VRRC:$src))), (v2i64 VRRC:$src)>; 814def : Pat<(v2i64 (bitconvert (v4f32 VRRC:$src))), (v2i64 VRRC:$src)>; 815 816// Shuffles. 817 818// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x) 819def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef), 820 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>; 821def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef), 822 (VPKUWUM $vA, $vA)>; 823def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef), 824 (VPKUHUM $vA, $vA)>; 825 826// Match vsldoi(y,x), vpkuwum(y,x), vpkuhum(y,x), i.e., swapped operands. 827// These fragments are matched for little-endian, where the inputs must 828// be swapped for correct semantics. 829def:Pat<(vsldoi_swapped_shuffle:$in v16i8:$vA, v16i8:$vB), 830 (VSLDOI $vB, $vA, (VSLDOI_swapped_get_imm $in))>; 831def:Pat<(vpkuwum_swapped_shuffle v16i8:$vA, v16i8:$vB), 832 (VPKUWUM $vB, $vA)>; 833def:Pat<(vpkuhum_swapped_shuffle v16i8:$vA, v16i8:$vB), 834 (VPKUHUM $vB, $vA)>; 835 836// Match vmrg*(x,x) 837def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef), 838 (VMRGLB $vA, $vA)>; 839def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef), 840 (VMRGLH $vA, $vA)>; 841def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef), 842 (VMRGLW $vA, $vA)>; 843def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef), 844 (VMRGHB $vA, $vA)>; 845def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef), 846 (VMRGHH $vA, $vA)>; 847def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef), 848 (VMRGHW $vA, $vA)>; 849 850// Match vmrg*(y,x), i.e., swapped operands. These fragments 851// are matched for little-endian, where the inputs must be 852// swapped for correct semantics. 853def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB), 854 (VMRGLB $vB, $vA)>; 855def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB), 856 (VMRGLH $vB, $vA)>; 857def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB), 858 (VMRGLW $vB, $vA)>; 859def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB), 860 (VMRGHB $vB, $vA)>; 861def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB), 862 (VMRGHH $vB, $vA)>; 863def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB), 864 (VMRGHW $vB, $vA)>; 865 866// Logical Operations 867def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>; 868 869def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)), 870 (VNOR $A, $B)>; 871def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)), 872 (VANDC $A, $B)>; 873 874def : Pat<(fmul v4f32:$vA, v4f32:$vB), 875 (VMADDFP $vA, $vB, 876 (v4i32 (VSLW (V_SETALLONES), (V_SETALLONES))))>; 877 878// Fused multiply add and multiply sub for packed float. These are represented 879// separately from the real instructions above, for operations that must have 880// the additional precision, such as Newton-Rhapson (used by divide, sqrt) 881def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 882 (VMADDFP $A, $B, $C)>; 883def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 884 (VNMSUBFP $A, $B, $C)>; 885 886def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 887 (VMADDFP $A, $B, $C)>; 888def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 889 (VNMSUBFP $A, $B, $C)>; 890 891def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC), 892 (VPERM $vA, $vB, $vC)>; 893 894def : Pat<(PPCfre v4f32:$A), (VREFP $A)>; 895def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>; 896 897// Vector shifts 898def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)), 899 (v16i8 (VSLB $vA, $vB))>; 900def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)), 901 (v8i16 (VSLH $vA, $vB))>; 902def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)), 903 (v4i32 (VSLW $vA, $vB))>; 904 905def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)), 906 (v16i8 (VSRB $vA, $vB))>; 907def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)), 908 (v8i16 (VSRH $vA, $vB))>; 909def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)), 910 (v4i32 (VSRW $vA, $vB))>; 911 912def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)), 913 (v16i8 (VSRAB $vA, $vB))>; 914def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)), 915 (v8i16 (VSRAH $vA, $vB))>; 916def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)), 917 (v4i32 (VSRAW $vA, $vB))>; 918 919// Float to integer and integer to float conversions 920def : Pat<(v4i32 (fp_to_sint v4f32:$vA)), 921 (VCTSXS_0 $vA)>; 922def : Pat<(v4i32 (fp_to_uint v4f32:$vA)), 923 (VCTUXS_0 $vA)>; 924def : Pat<(v4f32 (sint_to_fp v4i32:$vA)), 925 (VCFSX_0 $vA)>; 926def : Pat<(v4f32 (uint_to_fp v4i32:$vA)), 927 (VCFUX_0 $vA)>; 928 929// Floating-point rounding 930def : Pat<(v4f32 (ffloor v4f32:$vA)), 931 (VRFIM $vA)>; 932def : Pat<(v4f32 (fceil v4f32:$vA)), 933 (VRFIP $vA)>; 934def : Pat<(v4f32 (ftrunc v4f32:$vA)), 935 (VRFIZ $vA)>; 936def : Pat<(v4f32 (fnearbyint v4f32:$vA)), 937 (VRFIN $vA)>; 938 939} // end HasAltivec 940 941def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">; 942let Predicates = [HasP8Altivec] in { 943 944let isCommutable = 1 in { 945def VMULESW : VX1_Int_Ty2<904, "vmulesw", int_ppc_altivec_vmulesw, 946 v2i64, v4i32>; 947def VMULEUW : VX1_Int_Ty2<648, "vmuleuw", int_ppc_altivec_vmuleuw, 948 v2i64, v4i32>; 949def VMULOSW : VX1_Int_Ty2<392, "vmulosw", int_ppc_altivec_vmulosw, 950 v2i64, v4i32>; 951def VMULOUW : VX1_Int_Ty2<136, "vmulouw", int_ppc_altivec_vmulouw, 952 v2i64, v4i32>; 953def VMULUWM : VX1_Int_Ty<137, "vmuluwm", int_ppc_altivec_vmuluwm, 954 v4i32>; 955def VMAXSD : VX1_Int_Ty<450, "vmaxsd", int_ppc_altivec_vmaxsd, v2i64>; 956def VMAXUD : VX1_Int_Ty<194, "vmaxud", int_ppc_altivec_vmaxud, v2i64>; 957def VMINSD : VX1_Int_Ty<962, "vminsd", int_ppc_altivec_vminsd, v2i64>; 958def VMIDUD : VX1_Int_Ty<706, "vminud", int_ppc_altivec_vminud, v2i64>; 959} // isCommutable 960 961def VRLD : VX1_Int_Ty<196, "vrld", int_ppc_altivec_vrld, v2i64>; 962def VSLD : VX1_Int_Ty<1476, "vsld", int_ppc_altivec_vsld, v2i64>; 963def VSRD : VX1_Int_Ty<1732, "vsrd", int_ppc_altivec_vsrd, v2i64>; 964def VSRAD : VX1_Int_Ty<964, "vsrad", int_ppc_altivec_vsrad, v2i64>; 965 966 967// Vector Integer Arithmetic Instructions 968let isCommutable = 1 in { 969def VADDUDM : VXForm_1<192, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 970 "vaddudm $vD, $vA, $vB", IIC_VecGeneral, 971 [(set v2i64:$vD, (add v2i64:$vA, v2i64:$vB))]>; 972} // isCommutable 973 974def VSUBUDM : VXForm_1<1216, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 975 "vsubudm $vD, $vA, $vB", IIC_VecGeneral, 976 [(set v2i64:$vD, (sub v2i64:$vA, v2i64:$vB))]>; 977 978// Count Leading Zeros 979def VCLZB : VXForm_2<1794, (outs vrrc:$vD), (ins vrrc:$vB), 980 "vclzb $vD, $vB", IIC_VecGeneral, 981 [(set v16i8:$vD, (ctlz v16i8:$vB))]>; 982def VCLZH : VXForm_2<1858, (outs vrrc:$vD), (ins vrrc:$vB), 983 "vclzh $vD, $vB", IIC_VecGeneral, 984 [(set v8i16:$vD, (ctlz v8i16:$vB))]>; 985def VCLZW : VXForm_2<1922, (outs vrrc:$vD), (ins vrrc:$vB), 986 "vclzw $vD, $vB", IIC_VecGeneral, 987 [(set v4i32:$vD, (ctlz v4i32:$vB))]>; 988def VCLZD : VXForm_2<1986, (outs vrrc:$vD), (ins vrrc:$vB), 989 "vclzd $vD, $vB", IIC_VecGeneral, 990 [(set v2i64:$vD, (ctlz v2i64:$vB))]>; 991 992// Population Count 993def VPOPCNTB : VXForm_2<1795, (outs vrrc:$vD), (ins vrrc:$vB), 994 "vpopcntb $vD, $vB", IIC_VecGeneral, 995 [(set v16i8:$vD, (ctpop v16i8:$vB))]>; 996def VPOPCNTH : VXForm_2<1859, (outs vrrc:$vD), (ins vrrc:$vB), 997 "vpopcnth $vD, $vB", IIC_VecGeneral, 998 [(set v8i16:$vD, (ctpop v8i16:$vB))]>; 999def VPOPCNTW : VXForm_2<1923, (outs vrrc:$vD), (ins vrrc:$vB), 1000 "vpopcntw $vD, $vB", IIC_VecGeneral, 1001 [(set v4i32:$vD, (ctpop v4i32:$vB))]>; 1002def VPOPCNTD : VXForm_2<1987, (outs vrrc:$vD), (ins vrrc:$vB), 1003 "vpopcntd $vD, $vB", IIC_VecGeneral, 1004 [(set v2i64:$vD, (ctpop v2i64:$vB))]>; 1005 1006let isCommutable = 1 in { 1007// FIXME: Use AddedComplexity > 400 to ensure these patterns match before the 1008// VSX equivalents. We need to fix this up at some point. Two possible 1009// solutions for this problem: 1010// 1. Disable Altivec patterns that compete with VSX patterns using the 1011// !HasVSX predicate. This essentially favours VSX over Altivec, in 1012// hopes of reducing register pressure (larger register set using VSX 1013// instructions than VMX instructions) 1014// 2. Employ a more disciplined use of AddedComplexity, which would provide 1015// more fine-grained control than option 1. This would be beneficial 1016// if we find situations where Altivec is really preferred over VSX. 1017def VEQV : VXForm_1<1668, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1018 "veqv $vD, $vA, $vB", IIC_VecGeneral, 1019 [(set v4i32:$vD, (vnot_ppc (xor v4i32:$vA, v4i32:$vB)))]>; 1020def VNAND : VXForm_1<1412, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1021 "vnand $vD, $vA, $vB", IIC_VecGeneral, 1022 [(set v4i32:$vD, (vnot_ppc (and v4i32:$vA, v4i32:$vB)))]>; 1023} // isCommutable 1024 1025def VORC : VXForm_1<1348, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1026 "vorc $vD, $vA, $vB", IIC_VecGeneral, 1027 [(set v4i32:$vD, (or v4i32:$vA, 1028 (vnot_ppc v4i32:$vB)))]>; 1029 1030// i64 element comparisons. 1031def VCMPEQUD : VCMP <199, "vcmpequd $vD, $vA, $vB" , v2i64>; 1032def VCMPEQUDo : VCMPo<199, "vcmpequd. $vD, $vA, $vB", v2i64>; 1033def VCMPGTSD : VCMP <967, "vcmpgtsd $vD, $vA, $vB" , v2i64>; 1034def VCMPGTSDo : VCMPo<967, "vcmpgtsd. $vD, $vA, $vB", v2i64>; 1035def VCMPGTUD : VCMP <711, "vcmpgtud $vD, $vA, $vB" , v2i64>; 1036def VCMPGTUDo : VCMPo<711, "vcmpgtud. $vD, $vA, $vB", v2i64>; 1037 1038} // end HasP8Altivec 1039