1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20} 21def u16imm64 : Operand<i64> { 22 let PrintMethod = "printU16ImmOperand"; 23} 24def symbolHi64 : Operand<i64> { 25 let PrintMethod = "printSymbolHi"; 26 let EncoderMethod = "getHA16Encoding"; 27} 28def symbolLo64 : Operand<i64> { 29 let PrintMethod = "printSymbolLo"; 30 let EncoderMethod = "getLO16Encoding"; 31} 32 33//===----------------------------------------------------------------------===// 34// 64-bit transformation functions. 35// 36 37def SHL64 : SDNodeXForm<imm, [{ 38 // Transformation function: 63 - imm 39 return getI32Imm(63 - N->getZExtValue()); 40}]>; 41 42def SRL64 : SDNodeXForm<imm, [{ 43 // Transformation function: 64 - imm 44 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 45}]>; 46 47def HI32_48 : SDNodeXForm<imm, [{ 48 // Transformation function: shift the immediate value down into the low bits. 49 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 50}]>; 51 52def HI48_64 : SDNodeXForm<imm, [{ 53 // Transformation function: shift the immediate value down into the low bits. 54 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 55}]>; 56 57 58//===----------------------------------------------------------------------===// 59// Calls. 60// 61 62let Defs = [LR8] in 63 def MovePCtoLR8 : Pseudo<(outs), (ins), "", []>, 64 PPC970_Unit_BRU; 65 66// Darwin ABI Calls. 67let isCall = 1, PPC970_Unit = 7, 68 // All calls clobber the PPC64 non-callee saved registers. 69 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12, 70 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 71 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 72 LR8,CTR8, 73 CR0,CR1,CR5,CR6,CR7,CARRY] in { 74 // Convenient aliases for call instructions 75 let Uses = [RM] in { 76 def BL8_Darwin : IForm<18, 0, 1, 77 (outs), (ins calltarget:$func, variable_ops), 78 "bl $func", BrB, []>; // See Pat patterns below. 79 def BLA8_Darwin : IForm<18, 1, 1, 80 (outs), (ins aaddr:$func, variable_ops), 81 "bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>; 82 } 83 let Uses = [CTR8, RM] in { 84 def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 85 (outs), (ins variable_ops), 86 "bctrl", BrB, 87 [(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>; 88 } 89} 90 91// ELF 64 ABI Calls = Darwin ABI Calls 92// Used to define BL8_ELF and BLA8_ELF 93let isCall = 1, PPC970_Unit = 7, 94 // All calls clobber the PPC64 non-callee saved registers. 95 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12, 96 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 97 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 98 LR8,CTR8, 99 CR0,CR1,CR5,CR6,CR7,CARRY] in { 100 // Convenient aliases for call instructions 101 let Uses = [RM] in { 102 def BL8_ELF : IForm<18, 0, 1, 103 (outs), (ins calltarget:$func, variable_ops), 104 "bl $func", BrB, []>; // See Pat patterns below. 105 def BLA8_ELF : IForm<18, 1, 1, 106 (outs), (ins aaddr:$func, variable_ops), 107 "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>; 108 } 109 let Uses = [CTR8, RM] in { 110 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1, 111 (outs), (ins variable_ops), 112 "bctrl", BrB, 113 [(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>; 114 } 115} 116 117 118// Calls 119def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)), 120 (BL8_Darwin tglobaladdr:$dst)>; 121def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)), 122 (BL8_Darwin texternalsym:$dst)>; 123 124def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)), 125 (BL8_ELF tglobaladdr:$dst)>; 126def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)), 127 (BL8_ELF texternalsym:$dst)>; 128def : Pat<(PPCnop), 129 (NOP)>; 130 131// Atomic operations 132let usesCustomInserter = 1 in { 133 let Defs = [CR0] in { 134 def ATOMIC_LOAD_ADD_I64 : Pseudo< 135 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 136 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>; 137 def ATOMIC_LOAD_SUB_I64 : Pseudo< 138 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 139 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>; 140 def ATOMIC_LOAD_OR_I64 : Pseudo< 141 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 142 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>; 143 def ATOMIC_LOAD_XOR_I64 : Pseudo< 144 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 145 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>; 146 def ATOMIC_LOAD_AND_I64 : Pseudo< 147 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 148 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>; 149 def ATOMIC_LOAD_NAND_I64 : Pseudo< 150 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 151 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>; 152 153 def ATOMIC_CMP_SWAP_I64 : Pseudo< 154 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "", 155 [(set G8RC:$dst, 156 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>; 157 158 def ATOMIC_SWAP_I64 : Pseudo< 159 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "", 160 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>; 161 } 162} 163 164// Instructions to support atomic operations 165def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), 166 "ldarx $rD, $ptr", LdStLDARX, 167 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; 168 169let Defs = [CR0] in 170def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), 171 "stdcx. $rS, $dst", LdStSTDCX, 172 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>, 173 isDOT; 174 175let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 176def TCRETURNdi8 :Pseudo< (outs), 177 (ins calltarget:$dst, i32imm:$offset, variable_ops), 178 "#TC_RETURNd8 $dst $offset", 179 []>; 180 181let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 182def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops), 183 "#TC_RETURNa8 $func $offset", 184 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 185 186let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 187def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset, variable_ops), 188 "#TC_RETURNr8 $dst $offset", 189 []>; 190 191 192let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 193 isIndirectBranch = 1, isCall = 1, Uses = [CTR8, RM] in { 194 let isReturn = 1 in { 195 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 196 Requires<[In64BitMode]>; 197 } 198 199 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 200 Requires<[In64BitMode]>; 201} 202 203 204let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 205 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 206def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 207 "b $dst", BrB, 208 []>; 209 210 211let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 212 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 213def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 214 "ba $dst", BrB, 215 []>; 216 217def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 218 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 219 220def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 221 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 222 223def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 224 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 225 226// 64-but CR instructions 227def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS), 228 "mtcrf $FXM, $rS", BrMCRX>, 229 PPC970_MicroCode, PPC970_Unit_CRU; 230 231def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM), 232 "", SprMFCR>, 233 PPC970_MicroCode, PPC970_Unit_CRU; 234 235def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins), 236 "mfcr $rT", SprMFCR>, 237 PPC970_MicroCode, PPC970_Unit_CRU; 238 239//===----------------------------------------------------------------------===// 240// 64-bit SPR manipulation instrs. 241 242let Uses = [CTR8] in { 243def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins), 244 "mfctr $rT", SprMFSPR>, 245 PPC970_DGroup_First, PPC970_Unit_FXU; 246} 247let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in { 248def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS), 249 "mtctr $rS", SprMTSPR>, 250 PPC970_DGroup_First, PPC970_Unit_FXU; 251} 252 253let Defs = [X1], Uses = [X1] in 254def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"", 255 [(set G8RC:$result, 256 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>; 257 258let Defs = [LR8] in { 259def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS), 260 "mtlr $rS", SprMTSPR>, 261 PPC970_DGroup_First, PPC970_Unit_FXU; 262} 263let Uses = [LR8] in { 264def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins), 265 "mflr $rT", SprMFSPR>, 266 PPC970_DGroup_First, PPC970_Unit_FXU; 267} 268 269//===----------------------------------------------------------------------===// 270// Fixed point instructions. 271// 272 273let PPC970_Unit = 1 in { // FXU Operations. 274 275// Copies, extends, truncates. 276def OR4To8 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB), 277 "or $rA, $rS, $rB", IntGeneral, 278 []>; 279def OR8To4 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB), 280 "or $rA, $rS, $rB", IntGeneral, 281 []>; 282 283def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm), 284 "li $rD, $imm", IntGeneral, 285 [(set G8RC:$rD, immSExt16:$imm)]>; 286def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm), 287 "lis $rD, $imm", IntGeneral, 288 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>; 289 290// Logical ops. 291def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 292 "nand $rA, $rS, $rB", IntGeneral, 293 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>; 294def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 295 "and $rA, $rS, $rB", IntGeneral, 296 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>; 297def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 298 "andc $rA, $rS, $rB", IntGeneral, 299 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>; 300def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 301 "or $rA, $rS, $rB", IntGeneral, 302 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; 303def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 304 "nor $rA, $rS, $rB", IntGeneral, 305 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>; 306def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 307 "orc $rA, $rS, $rB", IntGeneral, 308 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>; 309def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 310 "eqv $rA, $rS, $rB", IntGeneral, 311 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>; 312def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 313 "xor $rA, $rS, $rB", IntGeneral, 314 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>; 315 316// Logical ops with immediate. 317def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 318 "andi. $dst, $src1, $src2", IntGeneral, 319 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>, 320 isDOT; 321def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 322 "andis. $dst, $src1, $src2", IntGeneral, 323 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>, 324 isDOT; 325def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 326 "ori $dst, $src1, $src2", IntGeneral, 327 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>; 328def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 329 "oris $dst, $src1, $src2", IntGeneral, 330 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>; 331def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 332 "xori $dst, $src1, $src2", IntGeneral, 333 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>; 334def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 335 "xoris $dst, $src1, $src2", IntGeneral, 336 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>; 337 338def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 339 "add $rT, $rA, $rB", IntGeneral, 340 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; 341 342let Defs = [CARRY] in { 343def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 344 "addc $rT, $rA, $rB", IntGeneral, 345 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>, 346 PPC970_DGroup_Cracked; 347def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 348 "addic $rD, $rA, $imm", IntGeneral, 349 [(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>; 350} 351def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 352 "addi $rD, $rA, $imm", IntGeneral, 353 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>; 354def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm), 355 "addis $rD, $rA, $imm", IntGeneral, 356 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>; 357 358let Defs = [CARRY] in { 359def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 360 "subfic $rD, $rA, $imm", IntGeneral, 361 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>; 362def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 363 "subfc $rT, $rA, $rB", IntGeneral, 364 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>, 365 PPC970_DGroup_Cracked; 366} 367def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 368 "subf $rT, $rA, $rB", IntGeneral, 369 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>; 370def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA), 371 "neg $rT, $rA", IntGeneral, 372 [(set G8RC:$rT, (ineg G8RC:$rA))]>; 373let Uses = [CARRY], Defs = [CARRY] in { 374def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 375 "adde $rT, $rA, $rB", IntGeneral, 376 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>; 377def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA), 378 "addme $rT, $rA", IntGeneral, 379 [(set G8RC:$rT, (adde G8RC:$rA, -1))]>; 380def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA), 381 "addze $rT, $rA", IntGeneral, 382 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>; 383def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 384 "subfe $rT, $rA, $rB", IntGeneral, 385 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>; 386def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA), 387 "subfme $rT, $rA", IntGeneral, 388 [(set G8RC:$rT, (sube -1, G8RC:$rA))]>; 389def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA), 390 "subfze $rT, $rA", IntGeneral, 391 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>; 392} 393 394 395def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 396 "mulhd $rT, $rA, $rB", IntMulHW, 397 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; 398def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 399 "mulhdu $rT, $rA, $rB", IntMulHWU, 400 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; 401 402def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 403 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 404def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 405 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 406def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm), 407 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 408def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2), 409 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 410 411def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 412 "sld $rA, $rS, $rB", IntRotateD, 413 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64; 414def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 415 "srd $rA, $rS, $rB", IntRotateD, 416 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64; 417let Defs = [CARRY] in { 418def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 419 "srad $rA, $rS, $rB", IntRotateD, 420 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64; 421} 422 423def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS), 424 "extsb $rA, $rS", IntGeneral, 425 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>; 426def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS), 427 "extsh $rA, $rS", IntGeneral, 428 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>; 429 430def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS), 431 "extsw $rA, $rS", IntGeneral, 432 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; 433/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers. 434def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS), 435 "extsw $rA, $rS", IntGeneral, 436 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64; 437def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS), 438 "extsw $rA, $rS", IntGeneral, 439 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64; 440 441let Defs = [CARRY] in { 442def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH), 443 "sradi $rA, $rS, $SH", IntRotateD, 444 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64; 445} 446def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS), 447 "cntlzd $rA, $rS", IntGeneral, 448 [(set G8RC:$rA, (ctlz G8RC:$rS))]>; 449 450def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 451 "divd $rT, $rA, $rB", IntDivD, 452 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 453 PPC970_DGroup_First, PPC970_DGroup_Cracked; 454def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 455 "divdu $rT, $rA, $rB", IntDivD, 456 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 457 PPC970_DGroup_First, PPC970_DGroup_Cracked; 458def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 459 "mulld $rT, $rA, $rB", IntMulHD, 460 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; 461 462 463let isCommutable = 1 in { 464def RLDIMI : MDForm_1<30, 3, 465 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), 466 "rldimi $rA, $rS, $SH, $MB", IntRotateD, 467 []>, isPPC64, RegConstraint<"$rSi = $rA">, 468 NoEncode<"$rSi">; 469} 470 471// Rotate instructions. 472def RLDCL : MDForm_1<30, 0, 473 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MB), 474 "rldcl $rA, $rS, $rB, $MB", IntRotateD, 475 []>, isPPC64; 476def RLDICL : MDForm_1<30, 0, 477 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB), 478 "rldicl $rA, $rS, $SH, $MB", IntRotateD, 479 []>, isPPC64; 480def RLDICR : MDForm_1<30, 1, 481 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME), 482 "rldicr $rA, $rS, $SH, $ME", IntRotateD, 483 []>, isPPC64; 484 485def RLWINM8 : MForm_2<21, 486 (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 487 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 488 []>; 489 490} // End FXU Operations. 491 492 493//===----------------------------------------------------------------------===// 494// Load/Store instructions. 495// 496 497 498// Sign extending loads. 499let canFoldAsLoad = 1, PPC970_Unit = 2 in { 500def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src), 501 "lha $rD, $src", LdStLHA, 502 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>, 503 PPC970_DGroup_Cracked; 504def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src), 505 "lwa $rD, $src", LdStLWA, 506 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64, 507 PPC970_DGroup_Cracked; 508def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src), 509 "lhax $rD, $src", LdStLHA, 510 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>, 511 PPC970_DGroup_Cracked; 512def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src), 513 "lwax $rD, $src", LdStLHA, 514 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 515 PPC970_DGroup_Cracked; 516 517// Update forms. 518let mayLoad = 1 in 519def LHAU8 : DForm_1a<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp, 520 ptr_rc:$rA), 521 "lhau $rD, $disp($rA)", LdStGeneral, 522 []>, RegConstraint<"$rA = $ea_result">, 523 NoEncode<"$ea_result">; 524// NO LWAU! 525 526} 527 528// Zero extending loads. 529let canFoldAsLoad = 1, PPC970_Unit = 2 in { 530def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src), 531 "lbz $rD, $src", LdStGeneral, 532 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>; 533def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src), 534 "lhz $rD, $src", LdStGeneral, 535 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>; 536def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src), 537 "lwz $rD, $src", LdStGeneral, 538 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 539 540def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src), 541 "lbzx $rD, $src", LdStGeneral, 542 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>; 543def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src), 544 "lhzx $rD, $src", LdStGeneral, 545 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>; 546def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src), 547 "lwzx $rD, $src", LdStGeneral, 548 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>; 549 550 551// Update forms. 552let mayLoad = 1 in { 553def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 554 "lbzu $rD, $addr", LdStGeneral, 555 []>, RegConstraint<"$addr.reg = $ea_result">, 556 NoEncode<"$ea_result">; 557def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 558 "lhzu $rD, $addr", LdStGeneral, 559 []>, RegConstraint<"$addr.reg = $ea_result">, 560 NoEncode<"$ea_result">; 561def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 562 "lwzu $rD, $addr", LdStGeneral, 563 []>, RegConstraint<"$addr.reg = $ea_result">, 564 NoEncode<"$ea_result">; 565} 566} 567 568 569// Full 8-byte loads. 570let canFoldAsLoad = 1, PPC970_Unit = 2 in { 571def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src), 572 "ld $rD, $src", LdStLD, 573 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64; 574def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 575 "", 576 [(set G8RC:$rD, 577 (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64; 578 579let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo. 580def LDinto_toc: DSForm_1<58, 0, (outs), (ins G8RC:$reg), 581 "ld 2, 8($reg)", LdStLD, 582 [(PPCload_toc G8RC:$reg)]>, isPPC64; 583 584let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo. 585def LDtoc_restore : DSForm_1<58, 0, (outs), (ins), 586 "ld 2, 40(1)", LdStLD, 587 [(PPCtoc_restore)]>, isPPC64; 588def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), 589 "ldx $rD, $src", LdStLD, 590 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; 591 592let mayLoad = 1 in 593def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr), 594 "ldu $rD, $addr", LdStLD, 595 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 596 NoEncode<"$ea_result">; 597 598} 599 600def : Pat<(PPCload ixaddr:$src), 601 (LD ixaddr:$src)>; 602def : Pat<(PPCload xaddr:$src), 603 (LDX xaddr:$src)>; 604 605let PPC970_Unit = 2 in { 606// Truncating stores. 607def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src), 608 "stb $rS, $src", LdStGeneral, 609 [(truncstorei8 G8RC:$rS, iaddr:$src)]>; 610def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src), 611 "sth $rS, $src", LdStGeneral, 612 [(truncstorei16 G8RC:$rS, iaddr:$src)]>; 613def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src), 614 "stw $rS, $src", LdStGeneral, 615 [(truncstorei32 G8RC:$rS, iaddr:$src)]>; 616def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst), 617 "stbx $rS, $dst", LdStGeneral, 618 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>, 619 PPC970_DGroup_Cracked; 620def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst), 621 "sthx $rS, $dst", LdStGeneral, 622 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>, 623 PPC970_DGroup_Cracked; 624def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst), 625 "stwx $rS, $dst", LdStGeneral, 626 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>, 627 PPC970_DGroup_Cracked; 628// Normal 8-byte stores. 629def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst), 630 "std $rS, $dst", LdStSTD, 631 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64; 632def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst), 633 "stdx $rS, $dst", LdStSTD, 634 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64, 635 PPC970_DGroup_Cracked; 636} 637 638let PPC970_Unit = 2 in { 639 640def STBU8 : DForm_1a<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 641 symbolLo:$ptroff, ptr_rc:$ptrreg), 642 "stbu $rS, $ptroff($ptrreg)", LdStGeneral, 643 [(set ptr_rc:$ea_res, 644 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg, 645 iaddroff:$ptroff))]>, 646 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 647def STHU8 : DForm_1a<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 648 symbolLo:$ptroff, ptr_rc:$ptrreg), 649 "sthu $rS, $ptroff($ptrreg)", LdStGeneral, 650 [(set ptr_rc:$ea_res, 651 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg, 652 iaddroff:$ptroff))]>, 653 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 654 655def STDU : DSForm_1a<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 656 s16immX4:$ptroff, ptr_rc:$ptrreg), 657 "stdu $rS, $ptroff($ptrreg)", LdStSTD, 658 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg, 659 iaddroff:$ptroff))]>, 660 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">, 661 isPPC64; 662 663let mayStore = 1 in 664def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst), 665 "stdux $rS, $dst", LdStSTD, 666 []>, isPPC64; 667 668// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. 669def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst), 670 "std $rT, $dst", LdStSTD, 671 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64; 672def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst), 673 "stdx $rT, $dst", LdStSTD, 674 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64, 675 PPC970_DGroup_Cracked; 676} 677 678 679 680//===----------------------------------------------------------------------===// 681// Floating point instructions. 682// 683 684 685let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations. 686def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB), 687 "fcfid $frD, $frB", FPGeneral, 688 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; 689def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB), 690 "fctidz $frD, $frB", FPGeneral, 691 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; 692} 693 694 695//===----------------------------------------------------------------------===// 696// Instruction Patterns 697// 698 699// Extensions and truncates to/from 32-bit regs. 700def : Pat<(i64 (zext GPRC:$in)), 701 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>; 702def : Pat<(i64 (anyext GPRC:$in)), 703 (OR4To8 GPRC:$in, GPRC:$in)>; 704def : Pat<(i32 (trunc G8RC:$in)), 705 (OR8To4 G8RC:$in, G8RC:$in)>; 706 707// Extending loads with i64 targets. 708def : Pat<(zextloadi1 iaddr:$src), 709 (LBZ8 iaddr:$src)>; 710def : Pat<(zextloadi1 xaddr:$src), 711 (LBZX8 xaddr:$src)>; 712def : Pat<(extloadi1 iaddr:$src), 713 (LBZ8 iaddr:$src)>; 714def : Pat<(extloadi1 xaddr:$src), 715 (LBZX8 xaddr:$src)>; 716def : Pat<(extloadi8 iaddr:$src), 717 (LBZ8 iaddr:$src)>; 718def : Pat<(extloadi8 xaddr:$src), 719 (LBZX8 xaddr:$src)>; 720def : Pat<(extloadi16 iaddr:$src), 721 (LHZ8 iaddr:$src)>; 722def : Pat<(extloadi16 xaddr:$src), 723 (LHZX8 xaddr:$src)>; 724def : Pat<(extloadi32 iaddr:$src), 725 (LWZ8 iaddr:$src)>; 726def : Pat<(extloadi32 xaddr:$src), 727 (LWZX8 xaddr:$src)>; 728 729// Standard shifts. These are represented separately from the real shifts above 730// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 731// amounts. 732def : Pat<(sra G8RC:$rS, GPRC:$rB), 733 (SRAD G8RC:$rS, GPRC:$rB)>; 734def : Pat<(srl G8RC:$rS, GPRC:$rB), 735 (SRD G8RC:$rS, GPRC:$rB)>; 736def : Pat<(shl G8RC:$rS, GPRC:$rB), 737 (SLD G8RC:$rS, GPRC:$rB)>; 738 739// SHL/SRL 740def : Pat<(shl G8RC:$in, (i32 imm:$imm)), 741 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>; 742def : Pat<(srl G8RC:$in, (i32 imm:$imm)), 743 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>; 744 745// ROTL 746def : Pat<(rotl G8RC:$in, GPRC:$sh), 747 (RLDCL G8RC:$in, GPRC:$sh, 0)>; 748def : Pat<(rotl G8RC:$in, (i32 imm:$imm)), 749 (RLDICL G8RC:$in, imm:$imm, 0)>; 750 751// Hi and Lo for Darwin Global Addresses. 752def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 753def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 754def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 755def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 756def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 757def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 758def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 759def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 760def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)), 761 (ADDIS8 G8RC:$in, tglobaladdr:$g)>; 762def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)), 763 (ADDIS8 G8RC:$in, tconstpool:$g)>; 764def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)), 765 (ADDIS8 G8RC:$in, tjumptable:$g)>; 766def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)), 767 (ADDIS8 G8RC:$in, tblockaddress:$g)>; 768