1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the PowerPC 64-bit instructions. These patterns are used 10// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// 64-bit operands. 16// 17def s16imm64 : Operand<i64> { 18 let PrintMethod = "printS16ImmOperand"; 19 let EncoderMethod = "getImm16Encoding"; 20 let ParserMatchClass = PPCS16ImmAsmOperand; 21 let DecoderMethod = "decodeSImmOperand<16>"; 22} 23def u16imm64 : Operand<i64> { 24 let PrintMethod = "printU16ImmOperand"; 25 let EncoderMethod = "getImm16Encoding"; 26 let ParserMatchClass = PPCU16ImmAsmOperand; 27 let DecoderMethod = "decodeUImmOperand<16>"; 28} 29def s17imm64 : Operand<i64> { 30 // This operand type is used for addis/lis to allow the assembler parser 31 // to accept immediates in the range -65536..65535 for compatibility with 32 // the GNU assembler. The operand is treated as 16-bit otherwise. 33 let PrintMethod = "printS16ImmOperand"; 34 let EncoderMethod = "getImm16Encoding"; 35 let ParserMatchClass = PPCS17ImmAsmOperand; 36 let DecoderMethod = "decodeSImmOperand<16>"; 37} 38def tocentry : Operand<iPTR> { 39 let MIOperandInfo = (ops i64imm:$imm); 40} 41def tlsreg : Operand<i64> { 42 let EncoderMethod = "getTLSRegEncoding"; 43 let ParserMatchClass = PPCTLSRegOperand; 44} 45def tlsgd : Operand<i64> {} 46def tlscall : Operand<i64> { 47 let PrintMethod = "printTLSCall"; 48 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 49 let EncoderMethod = "getTLSCallEncoding"; 50} 51 52//===----------------------------------------------------------------------===// 53// 64-bit transformation functions. 54// 55 56def SHL64 : SDNodeXForm<imm, [{ 57 // Transformation function: 63 - imm 58 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 59}]>; 60 61def SRL64 : SDNodeXForm<imm, [{ 62 // Transformation function: 64 - imm 63 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 64 : getI32Imm(0, SDLoc(N)); 65}]>; 66 67 68//===----------------------------------------------------------------------===// 69// Calls. 70// 71 72let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 73let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 74 let isReturn = 1, Uses = [LR8, RM] in 75 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 76 [(retflag)]>, Requires<[In64BitMode]>; 77 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 78 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 79 []>, 80 Requires<[In64BitMode]>; 81 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 82 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 83 []>, 84 Requires<[In64BitMode]>; 85 86 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 87 "bcctr 12, $bi, 0", IIC_BrB, []>, 88 Requires<[In64BitMode]>; 89 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 90 "bcctr 4, $bi, 0", IIC_BrB, []>, 91 Requires<[In64BitMode]>; 92 } 93} 94 95let Defs = [LR8] in 96 def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>, 97 PPC970_Unit_BRU; 98 99let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 100 let Defs = [CTR8], Uses = [CTR8] in { 101 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 102 "bdz $dst">; 103 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 104 "bdnz $dst">; 105 } 106 107 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 108 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 109 "bdzlr", IIC_BrB, []>; 110 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 111 "bdnzlr", IIC_BrB, []>; 112 } 113} 114 115 116 117let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 118 // Convenient aliases for call instructions 119 let Uses = [RM] in { 120 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 121 "bl $func", IIC_BrB, []>; // See Pat patterns below. 122 123 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 124 "bl $func", IIC_BrB, []>; 125 126 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 127 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 128 } 129 let Uses = [RM], isCodeGenOnly = 1 in { 130 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 131 (outs), (ins calltarget:$func), 132 "bl $func\n\tnop", IIC_BrB, []>; 133 134 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 135 (outs), (ins tlscall:$func), 136 "bl $func\n\tnop", IIC_BrB, []>; 137 138 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 139 (outs), (ins abscalltarget:$func), 140 "bla $func\n\tnop", IIC_BrB, 141 [(PPCcall_nop (i64 imm:$func))]>; 142 } 143 let Uses = [CTR8, RM] in { 144 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 145 "bctrl", IIC_BrB, [(PPCbctrl)]>, 146 Requires<[In64BitMode]>; 147 148 let isCodeGenOnly = 1 in { 149 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 150 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 151 []>, 152 Requires<[In64BitMode]>; 153 154 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 155 "bcctrl 12, $bi, 0", IIC_BrB, []>, 156 Requires<[In64BitMode]>; 157 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 158 "bcctrl 4, $bi, 0", IIC_BrB, []>, 159 Requires<[In64BitMode]>; 160 } 161 } 162} 163 164let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 165 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 166 def BCTRL8_LDinto_toc : 167 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 168 (ins memrix:$src), 169 "bctrl\n\tld 2, $src", IIC_BrB, 170 [(PPCbctrl_load_toc iaddrX4:$src)]>, 171 Requires<[In64BitMode]>; 172} 173 174} // Interpretation64Bit 175 176// FIXME: Duplicating this for the asm parser should be unnecessary, but the 177// previous definition must be marked as CodeGen only to prevent decoding 178// conflicts. 179let Interpretation64Bit = 1, isAsmParserOnly = 1 in 180let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 181def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 182 "bl $func", IIC_BrB, []>; 183 184// Calls 185def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 186 (BL8 tglobaladdr:$dst)>; 187def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 188 (BL8_NOP tglobaladdr:$dst)>; 189 190def : Pat<(PPCcall (i64 texternalsym:$dst)), 191 (BL8 texternalsym:$dst)>; 192def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 193 (BL8_NOP texternalsym:$dst)>; 194 195// Atomic operations 196// FIXME: some of these might be used with constant operands. This will result 197// in constant materialization instructions that may be redundant. We currently 198// clean this up in PPCMIPeephole with calls to 199// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 200// in the first place. 201let Defs = [CR0] in { 202 def ATOMIC_LOAD_ADD_I64 : PPCCustomInserterPseudo< 203 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 204 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 205 def ATOMIC_LOAD_SUB_I64 : PPCCustomInserterPseudo< 206 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 207 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 208 def ATOMIC_LOAD_OR_I64 : PPCCustomInserterPseudo< 209 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 210 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 211 def ATOMIC_LOAD_XOR_I64 : PPCCustomInserterPseudo< 212 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 213 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 214 def ATOMIC_LOAD_AND_I64 : PPCCustomInserterPseudo< 215 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 216 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 217 def ATOMIC_LOAD_NAND_I64 : PPCCustomInserterPseudo< 218 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 219 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 220 def ATOMIC_LOAD_MIN_I64 : PPCCustomInserterPseudo< 221 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", 222 [(set i64:$dst, (atomic_load_min_64 xoaddr:$ptr, i64:$incr))]>; 223 def ATOMIC_LOAD_MAX_I64 : PPCCustomInserterPseudo< 224 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", 225 [(set i64:$dst, (atomic_load_max_64 xoaddr:$ptr, i64:$incr))]>; 226 def ATOMIC_LOAD_UMIN_I64 : PPCCustomInserterPseudo< 227 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", 228 [(set i64:$dst, (atomic_load_umin_64 xoaddr:$ptr, i64:$incr))]>; 229 def ATOMIC_LOAD_UMAX_I64 : PPCCustomInserterPseudo< 230 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", 231 [(set i64:$dst, (atomic_load_umax_64 xoaddr:$ptr, i64:$incr))]>; 232 233 def ATOMIC_CMP_SWAP_I64 : PPCCustomInserterPseudo< 234 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 235 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 236 237 def ATOMIC_SWAP_I64 : PPCCustomInserterPseudo< 238 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 239 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 240} 241 242// Instructions to support atomic operations 243let mayLoad = 1, hasSideEffects = 0 in { 244def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 245 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 246 247// Instruction to support lock versions of atomics 248// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 249def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 250 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT; 251 252let hasExtraDefRegAllocReq = 1 in 253def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), 254 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, 255 Requires<[IsISA3_0]>; 256} 257 258let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 259def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 260 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT; 261 262let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 263def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), 264 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, 265 Requires<[IsISA3_0]>; 266 267let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 268let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 269def TCRETURNdi8 :PPCEmitTimePseudo< (outs), 270 (ins calltarget:$dst, i32imm:$offset), 271 "#TC_RETURNd8 $dst $offset", 272 []>; 273 274let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 275def TCRETURNai8 :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 276 "#TC_RETURNa8 $func $offset", 277 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 278 279let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 280def TCRETURNri8 : PPCEmitTimePseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 281 "#TC_RETURNr8 $dst $offset", 282 []>; 283 284let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 285 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 286def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 287 []>, 288 Requires<[In64BitMode]>; 289 290let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 291 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 292def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 293 "b $dst", IIC_BrB, 294 []>; 295 296let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 297 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 298def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 299 "ba $dst", IIC_BrB, 300 []>; 301} // Interpretation64Bit 302 303def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 304 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 305 306def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 307 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 308 309def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 310 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 311 312 313// 64-bit CR instructions 314let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 315let hasSideEffects = 0 in { 316// mtocrf's input needs to be prepared by shifting by an amount dependent 317// on the cr register selected. Thus, post-ra anti-dep breaking must not 318// later change that register assignment. 319let hasExtraDefRegAllocReq = 1 in { 320def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 321 "mtocrf $FXM, $ST", IIC_BrMCRX>, 322 PPC970_DGroup_First, PPC970_Unit_CRU; 323 324// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 325// is dependent on the cr fields being set. 326def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 327 "mtcrf $FXM, $rS", IIC_BrMCRX>, 328 PPC970_MicroCode, PPC970_Unit_CRU; 329} // hasExtraDefRegAllocReq = 1 330 331// mfocrf's input needs to be prepared by shifting by an amount dependent 332// on the cr register selected. Thus, post-ra anti-dep breaking must not 333// later change that register assignment. 334let hasExtraSrcRegAllocReq = 1 in { 335def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 336 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 337 PPC970_DGroup_First, PPC970_Unit_CRU; 338 339// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 340// is dependent on the cr fields being copied. 341def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 342 "mfcr $rT", IIC_SprMFCR>, 343 PPC970_MicroCode, PPC970_Unit_CRU; 344} // hasExtraSrcRegAllocReq = 1 345} // hasSideEffects = 0 346 347// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 348// is not. 349let hasSideEffects = 1 in { 350 let Defs = [CTR8] in 351 def EH_SjLj_SetJmp64 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 352 "#EH_SJLJ_SETJMP64", 353 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 354 Requires<[In64BitMode]>; 355} 356 357let hasSideEffects = 1, isBarrier = 1 in { 358 let isTerminator = 1 in 359 def EH_SjLj_LongJmp64 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 360 "#EH_SJLJ_LONGJMP64", 361 [(PPCeh_sjlj_longjmp addr:$buf)]>, 362 Requires<[In64BitMode]>; 363} 364 365def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 366 "mfspr $RT, $SPR", IIC_SprMFSPR>; 367def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 368 "mtspr $SPR, $RT", IIC_SprMTSPR>; 369 370 371//===----------------------------------------------------------------------===// 372// 64-bit SPR manipulation instrs. 373 374let Uses = [CTR8] in { 375def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 376 "mfctr $rT", IIC_SprMFSPR>, 377 PPC970_DGroup_First, PPC970_Unit_FXU; 378} 379let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 380def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 381 "mtctr $rS", IIC_SprMTSPR>, 382 PPC970_DGroup_First, PPC970_Unit_FXU; 383} 384let hasSideEffects = 1, Defs = [CTR8] in { 385let Pattern = [(int_ppc_mtctr i64:$rS)] in 386def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 387 "mtctr $rS", IIC_SprMTSPR>, 388 PPC970_DGroup_First, PPC970_Unit_FXU; 389} 390 391let Pattern = [(set i64:$rT, readcyclecounter)] in 392def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 393 "mfspr $rT, 268", IIC_SprMFTB>, 394 PPC970_DGroup_First, PPC970_Unit_FXU; 395// Note that encoding mftb using mfspr is now the preferred form, 396// and has been since at least ISA v2.03. The mftb instruction has 397// now been phased out. Using mfspr, however, is known not to work on 398// the POWER3. 399 400let Defs = [X1], Uses = [X1] in 401def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 402 [(set i64:$result, 403 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 404def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 405 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 406 407let Defs = [LR8] in { 408def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 409 "mtlr $rS", IIC_SprMTSPR>, 410 PPC970_DGroup_First, PPC970_Unit_FXU; 411} 412let Uses = [LR8] in { 413def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 414 "mflr $rT", IIC_SprMFSPR>, 415 PPC970_DGroup_First, PPC970_Unit_FXU; 416} 417} // Interpretation64Bit 418 419//===----------------------------------------------------------------------===// 420// Fixed point instructions. 421// 422 423let PPC970_Unit = 1 in { // FXU Operations. 424let Interpretation64Bit = 1 in { 425let hasSideEffects = 0 in { 426let isCodeGenOnly = 1 in { 427 428let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 429def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 430 "li $rD, $imm", IIC_IntSimple, 431 [(set i64:$rD, imm64SExt16:$imm)]>; 432def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 433 "lis $rD, $imm", IIC_IntSimple, 434 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 435} 436 437// Logical ops. 438let isCommutable = 1 in { 439defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 440 "nand", "$rA, $rS, $rB", IIC_IntSimple, 441 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 442defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 443 "and", "$rA, $rS, $rB", IIC_IntSimple, 444 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 445} // isCommutable 446defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 447 "andc", "$rA, $rS, $rB", IIC_IntSimple, 448 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 449let isCommutable = 1 in { 450defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 451 "or", "$rA, $rS, $rB", IIC_IntSimple, 452 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 453defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 454 "nor", "$rA, $rS, $rB", IIC_IntSimple, 455 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 456} // isCommutable 457defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 458 "orc", "$rA, $rS, $rB", IIC_IntSimple, 459 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 460let isCommutable = 1 in { 461defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 462 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 463 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 464defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 465 "xor", "$rA, $rS, $rB", IIC_IntSimple, 466 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 467} // let isCommutable = 1 468 469// Logical ops with immediate. 470let Defs = [CR0] in { 471def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 472 "andi. $dst, $src1, $src2", IIC_IntGeneral, 473 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 474 isDOT; 475def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 476 "andis. $dst, $src1, $src2", IIC_IntGeneral, 477 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 478 isDOT; 479} 480def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 481 "ori $dst, $src1, $src2", IIC_IntSimple, 482 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 483def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 484 "oris $dst, $src1, $src2", IIC_IntSimple, 485 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 486def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 487 "xori $dst, $src1, $src2", IIC_IntSimple, 488 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 489def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 490 "xoris $dst, $src1, $src2", IIC_IntSimple, 491 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 492 493let isCommutable = 1 in 494defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 495 "add", "$rT, $rA, $rB", IIC_IntSimple, 496 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 497// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 498// initial-exec thread-local storage model. We need to forbid r0 here - 499// while it works for add just fine, the linker can relax this to local-exec 500// addi, which won't work for r0. 501def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), 502 "add $rT, $rA, $rB", IIC_IntSimple, 503 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 504let mayLoad = 1 in { 505def LBZXTLS : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 506 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 507def LHZXTLS : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 508 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 509def LWZXTLS : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 510 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 511def LDXTLS : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 512 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 513def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 514 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 515def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 516 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 517def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 518 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 519 520} 521 522let mayStore = 1 in { 523def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 524 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 525 PPC970_DGroup_Cracked; 526def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 527 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 528 PPC970_DGroup_Cracked; 529def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 530 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 531 PPC970_DGroup_Cracked; 532def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 533 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 534 PPC970_DGroup_Cracked; 535def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 536 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 537 PPC970_DGroup_Cracked; 538def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 539 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 540 PPC970_DGroup_Cracked; 541def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 542 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 543 PPC970_DGroup_Cracked; 544 545} 546 547let isCommutable = 1 in 548defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 549 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 550 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 551 PPC970_DGroup_Cracked; 552 553let Defs = [CARRY] in 554def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 555 "addic $rD, $rA, $imm", IIC_IntGeneral, 556 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 557def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 558 "addi $rD, $rA, $imm", IIC_IntSimple, 559 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 560def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 561 "addis $rD, $rA, $imm", IIC_IntSimple, 562 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 563 564let Defs = [CARRY] in { 565def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 566 "subfic $rD, $rA, $imm", IIC_IntGeneral, 567 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 568} 569defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 570 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 571 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 572 PPC970_DGroup_Cracked; 573defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 574 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 575 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 576defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 577 "neg", "$rT, $rA", IIC_IntSimple, 578 [(set i64:$rT, (ineg i64:$rA))]>; 579let Uses = [CARRY] in { 580let isCommutable = 1 in 581defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 582 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 583 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 584defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 585 "addme", "$rT, $rA", IIC_IntGeneral, 586 [(set i64:$rT, (adde i64:$rA, -1))]>; 587defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 588 "addze", "$rT, $rA", IIC_IntGeneral, 589 [(set i64:$rT, (adde i64:$rA, 0))]>; 590defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 591 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 592 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 593defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 594 "subfme", "$rT, $rA", IIC_IntGeneral, 595 [(set i64:$rT, (sube -1, i64:$rA))]>; 596defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 597 "subfze", "$rT, $rA", IIC_IntGeneral, 598 [(set i64:$rT, (sube 0, i64:$rA))]>; 599} 600} // isCodeGenOnly 601 602// FIXME: Duplicating this for the asm parser should be unnecessary, but the 603// previous definition must be marked as CodeGen only to prevent decoding 604// conflicts. 605let isAsmParserOnly = 1 in { 606def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 607 "add $rT, $rA, $rB", IIC_IntSimple, []>; 608 609let mayLoad = 1 in { 610def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 611 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 612def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 613 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 614def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 615 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 616def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 617 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 618} 619 620let mayStore = 1 in { 621def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 622 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 623 PPC970_DGroup_Cracked; 624def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 625 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 626 PPC970_DGroup_Cracked; 627def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 628 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 629 PPC970_DGroup_Cracked; 630def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 631 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 632 PPC970_DGroup_Cracked; 633} 634} 635 636let isCommutable = 1 in { 637defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 638 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 639 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 640defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 641 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 642 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 643} // isCommutable 644} 645} // Interpretation64Bit 646 647let isCompare = 1, hasSideEffects = 0 in { 648 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 649 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 650 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 651 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 652 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 653 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 654 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 655 "cmpldi $dst, $src1, $src2", 656 IIC_IntCompare>, isPPC64; 657 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 658 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF), 659 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 660 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 661 Requires<[IsISA3_0]>; 662 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crbitrc:$BF), 663 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", 664 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 665} 666 667let hasSideEffects = 0 in { 668defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 669 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 670 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 671defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 672 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 673 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 674defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 675 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 676 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 677 678let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 679defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 680 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 681defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), 682 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>, 683 Requires<[IsISA3_0]>; 684 685defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 686 "extsb", "$rA, $rS", IIC_IntSimple, 687 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 688defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 689 "extsh", "$rA, $rS", IIC_IntSimple, 690 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 691 692defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 693 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 694defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 695 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 696} // Interpretation64Bit 697 698// For fast-isel: 699let isCodeGenOnly = 1 in { 700def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 701 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 702def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 703 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 704} // isCodeGenOnly for fast-isel 705 706defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 707 "extsw", "$rA, $rS", IIC_IntSimple, 708 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 709let Interpretation64Bit = 1, isCodeGenOnly = 1 in 710defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 711 "extsw", "$rA, $rS", IIC_IntSimple, 712 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 713let isCodeGenOnly = 1 in 714def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS), 715 "extsw $rA, $rS", IIC_IntSimple, 716 []>, isPPC64; 717 718defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 719 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 720 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 721 722defm EXTSWSLI : XSForm_1r<31, 445, (outs g8rc:$rA), (ins gprc:$rS, u6imm:$SH), 723 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 724 [(set i64:$rA, (PPCextswsli i32:$rS, (i32 imm:$SH)))]>, 725 isPPC64, Requires<[IsISA3_0]>; 726 727// For fast-isel: 728let isCodeGenOnly = 1, Defs = [CARRY] in 729def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH), 730 "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64; 731 732defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 733 "cntlzd", "$rA, $rS", IIC_IntGeneral, 734 [(set i64:$rA, (ctlz i64:$rS))]>; 735defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), 736 "cnttzd", "$rA, $rS", IIC_IntGeneral, 737 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>; 738def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 739 "popcntd $rA, $rS", IIC_IntGeneral, 740 [(set i64:$rA, (ctpop i64:$rS))]>; 741def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 742 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 743 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 744 isPPC64, Requires<[HasBPERMD]>; 745 746let isCodeGenOnly = 1, isCommutable = 1 in 747def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 748 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 749 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 750 751// popcntw also does a population count on the high 32 bits (storing the 752// results in the high 32-bits of the output). We'll ignore that here (which is 753// safe because we never separately use the high part of the 64-bit registers). 754def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 755 "popcntw $rA, $rS", IIC_IntGeneral, 756 [(set i32:$rA, (ctpop i32:$rS))]>; 757 758def POPCNTB : XForm_11<31, 122, (outs gprc:$rA), (ins gprc:$rS), 759 "popcntb $rA, $rS", IIC_IntGeneral, []>; 760 761defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 762 "divd", "$rT, $rA, $rB", IIC_IntDivD, 763 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 764defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 765 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 766 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 767def DIVDE : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 768 "divde $rT, $rA, $rB", IIC_IntDivD, 769 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 770 isPPC64, Requires<[HasExtDiv]>; 771 772let Predicates = [IsISA3_0] in { 773def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 774 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 775def MADDHDU : VAForm_1a<49, 776 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 777 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 778def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC), 779 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 780 [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>, 781 isPPC64; 782def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA), 783 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 784let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 785 def MADDLD8 : VAForm_1a<51, 786 (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 787 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, 788 [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>, 789 isPPC64; 790 def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA), 791 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 792} 793def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins i32imm:$L), 794 "darn $RT, $L", IIC_LdStLD>, isPPC64; 795def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D), 796 "addpcis $RT, $D", IIC_BrB, []>, isPPC64; 797def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 798 "modsd $rT, $rA, $rB", IIC_IntDivW, 799 [(set i64:$rT, (srem i64:$rA, i64:$rB))]>; 800def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 801 "modud $rT, $rA, $rB", IIC_IntDivW, 802 [(set i64:$rT, (urem i64:$rA, i64:$rB))]>; 803} 804 805let Defs = [CR0] in 806def DIVDEo : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 807 "divde. $rT, $rA, $rB", IIC_IntDivD, 808 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 809 isPPC64, Requires<[HasExtDiv]>; 810def DIVDEU : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 811 "divdeu $rT, $rA, $rB", IIC_IntDivD, 812 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 813 isPPC64, Requires<[HasExtDiv]>; 814let Defs = [CR0] in 815def DIVDEUo : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 816 "divdeu. $rT, $rA, $rB", IIC_IntDivD, 817 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 818 isPPC64, Requires<[HasExtDiv]>; 819let isCommutable = 1 in 820defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 821 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 822 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 823let Interpretation64Bit = 1, isCodeGenOnly = 1 in 824def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 825 "mulli $rD, $rA, $imm", IIC_IntMulLI, 826 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 827} 828 829let hasSideEffects = 0 in { 830defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 831 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 832 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 833 []>, isPPC64, RegConstraint<"$rSi = $rA">, 834 NoEncode<"$rSi">; 835 836// Rotate instructions. 837defm RLDCL : MDSForm_1r<30, 8, 838 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 839 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 840 []>, isPPC64; 841defm RLDCR : MDSForm_1r<30, 9, 842 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 843 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 844 []>, isPPC64; 845defm RLDICL : MDForm_1r<30, 0, 846 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 847 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 848 []>, isPPC64; 849// For fast-isel: 850let isCodeGenOnly = 1 in 851def RLDICL_32_64 : MDForm_1<30, 0, 852 (outs g8rc:$rA), 853 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 854 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 855 []>, isPPC64; 856// End fast-isel. 857let Interpretation64Bit = 1, isCodeGenOnly = 1 in 858defm RLDICL_32 : MDForm_1r<30, 0, 859 (outs gprc:$rA), 860 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 861 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 862 []>, isPPC64; 863defm RLDICR : MDForm_1r<30, 1, 864 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 865 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 866 []>, isPPC64; 867let isCodeGenOnly = 1 in 868def RLDICR_32 : MDForm_1<30, 1, 869 (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 870 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 871 []>, isPPC64; 872defm RLDIC : MDForm_1r<30, 2, 873 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 874 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 875 []>, isPPC64; 876 877let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 878defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 879 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 880 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 881 []>; 882 883defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 884 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 885 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 886 []>; 887 888// RLWIMI can be commuted if the rotate amount is zero. 889let Interpretation64Bit = 1, isCodeGenOnly = 1 in 890defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 891 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 892 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 893 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 894 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 895 896let isSelect = 1 in 897def ISEL8 : AForm_4<31, 15, 898 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 899 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 900 []>; 901} // Interpretation64Bit 902} // hasSideEffects = 0 903} // End FXU Operations. 904 905 906//===----------------------------------------------------------------------===// 907// Load/Store instructions. 908// 909 910 911// Sign extending loads. 912let PPC970_Unit = 2 in { 913let Interpretation64Bit = 1, isCodeGenOnly = 1 in 914def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 915 "lha $rD, $src", IIC_LdStLHA, 916 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 917 PPC970_DGroup_Cracked; 918def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 919 "lwa $rD, $src", IIC_LdStLWA, 920 [(set i64:$rD, 921 (aligned4sextloadi32 iaddrX4:$src))]>, isPPC64, 922 PPC970_DGroup_Cracked; 923let Interpretation64Bit = 1, isCodeGenOnly = 1 in 924def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src), 925 "lhax $rD, $src", IIC_LdStLHA, 926 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 927 PPC970_DGroup_Cracked; 928def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src), 929 "lwax $rD, $src", IIC_LdStLHA, 930 [(set i64:$rD, (sextloadi32 xaddrX4:$src))]>, isPPC64, 931 PPC970_DGroup_Cracked; 932// For fast-isel: 933let isCodeGenOnly = 1, mayLoad = 1 in { 934def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 935 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 936 PPC970_DGroup_Cracked; 937def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src), 938 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 939 PPC970_DGroup_Cracked; 940} // end fast-isel isCodeGenOnly 941 942// Update forms. 943let mayLoad = 1, hasSideEffects = 0 in { 944let Interpretation64Bit = 1, isCodeGenOnly = 1 in 945def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 946 (ins memri:$addr), 947 "lhau $rD, $addr", IIC_LdStLHAU, 948 []>, RegConstraint<"$addr.reg = $ea_result">, 949 NoEncode<"$ea_result">; 950// NO LWAU! 951 952let Interpretation64Bit = 1, isCodeGenOnly = 1 in 953def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 954 (ins memrr:$addr), 955 "lhaux $rD, $addr", IIC_LdStLHAUX, 956 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 957 NoEncode<"$ea_result">; 958def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 959 (ins memrr:$addr), 960 "lwaux $rD, $addr", IIC_LdStLHAUX, 961 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 962 NoEncode<"$ea_result">, isPPC64; 963} 964} 965 966let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 967// Zero extending loads. 968let PPC970_Unit = 2 in { 969def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 970 "lbz $rD, $src", IIC_LdStLoad, 971 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 972def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 973 "lhz $rD, $src", IIC_LdStLoad, 974 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 975def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 976 "lwz $rD, $src", IIC_LdStLoad, 977 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 978 979def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src), 980 "lbzx $rD, $src", IIC_LdStLoad, 981 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 982def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src), 983 "lhzx $rD, $src", IIC_LdStLoad, 984 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 985def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src), 986 "lwzx $rD, $src", IIC_LdStLoad, 987 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 988 989 990// Update forms. 991let mayLoad = 1, hasSideEffects = 0 in { 992def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 993 (ins memri:$addr), 994 "lbzu $rD, $addr", IIC_LdStLoadUpd, 995 []>, RegConstraint<"$addr.reg = $ea_result">, 996 NoEncode<"$ea_result">; 997def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 998 (ins memri:$addr), 999 "lhzu $rD, $addr", IIC_LdStLoadUpd, 1000 []>, RegConstraint<"$addr.reg = $ea_result">, 1001 NoEncode<"$ea_result">; 1002def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1003 (ins memri:$addr), 1004 "lwzu $rD, $addr", IIC_LdStLoadUpd, 1005 []>, RegConstraint<"$addr.reg = $ea_result">, 1006 NoEncode<"$ea_result">; 1007 1008def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1009 (ins memrr:$addr), 1010 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1011 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1012 NoEncode<"$ea_result">; 1013def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1014 (ins memrr:$addr), 1015 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1016 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1017 NoEncode<"$ea_result">; 1018def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1019 (ins memrr:$addr), 1020 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1021 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1022 NoEncode<"$ea_result">; 1023} 1024} 1025} // Interpretation64Bit 1026 1027 1028// Full 8-byte loads. 1029let PPC970_Unit = 2 in { 1030def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 1031 "ld $rD, $src", IIC_LdStLD, 1032 [(set i64:$rD, (aligned4load iaddrX4:$src))]>, isPPC64; 1033// The following four definitions are selected for small code model only. 1034// Otherwise, we need to create two instructions to form a 32-bit offset, 1035// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 1036def LDtoc: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1037 "#LDtoc", 1038 [(set i64:$rD, 1039 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 1040def LDtocJTI: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1041 "#LDtocJTI", 1042 [(set i64:$rD, 1043 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 1044def LDtocCPT: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1045 "#LDtocCPT", 1046 [(set i64:$rD, 1047 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 1048def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1049 "#LDtocCPT", 1050 [(set i64:$rD, 1051 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 1052 1053def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src), 1054 "ldx $rD, $src", IIC_LdStLD, 1055 [(set i64:$rD, (load xaddrX4:$src))]>, isPPC64; 1056def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src), 1057 "ldbrx $rD, $src", IIC_LdStLoad, 1058 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 1059 1060let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 1061def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src), 1062 "lhbrx $rD, $src", IIC_LdStLoad, []>; 1063def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src), 1064 "lwbrx $rD, $src", IIC_LdStLoad, []>; 1065} 1066 1067let mayLoad = 1, hasSideEffects = 0 in { 1068def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1069 (ins memrix:$addr), 1070 "ldu $rD, $addr", IIC_LdStLDU, 1071 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 1072 NoEncode<"$ea_result">; 1073 1074def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1075 (ins memrr:$addr), 1076 "ldux $rD, $addr", IIC_LdStLDUX, 1077 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1078 NoEncode<"$ea_result">, isPPC64; 1079 1080def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src), 1081 "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64, 1082 Requires<[IsISA3_0]>; 1083} 1084} 1085 1086// Support for medium and large code model. 1087let hasSideEffects = 0 in { 1088let isReMaterializable = 1 in { 1089def ADDIStocHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1090 "#ADDIStocHA", []>, isPPC64; 1091def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1092 "#ADDItocL", []>, isPPC64; 1093} 1094let mayLoad = 1 in 1095def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1096 "#LDtocL", []>, isPPC64; 1097} 1098 1099// Support for thread-local storage. 1100def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1101 "#ADDISgotTprelHA", 1102 [(set i64:$rD, 1103 (PPCaddisGotTprelHA i64:$reg, 1104 tglobaltlsaddr:$disp))]>, 1105 isPPC64; 1106def LDgotTprelL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 1107 "#LDgotTprelL", 1108 [(set i64:$rD, 1109 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 1110 isPPC64; 1111 1112let Defs = [CR7], Itinerary = IIC_LdStSync in 1113def CFENCE8 : PPCPostRAExpPseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>; 1114 1115def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 1116 (ADD8TLS $in, tglobaltlsaddr:$g)>; 1117def ADDIStlsgdHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1118 "#ADDIStlsgdHA", 1119 [(set i64:$rD, 1120 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 1121 isPPC64; 1122def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1123 "#ADDItlsgdL", 1124 [(set i64:$rD, 1125 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 1126 isPPC64; 1127// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1128// explicitly defined when this op is created, so not mentioned here. 1129// This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be 1130// correct because the branch select pass is relying on it. 1131let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, Size = 8, 1132 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1133def GETtlsADDR : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1134 "#GETtlsADDR", 1135 [(set i64:$rD, 1136 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1137 isPPC64; 1138// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 1139// are true defines while the rest of the Defs are clobbers. 1140let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1141 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1142 in 1143def ADDItlsgdLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1144 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1145 "#ADDItlsgdLADDR", 1146 [(set i64:$rD, 1147 (PPCaddiTlsgdLAddr i64:$reg, 1148 tglobaltlsaddr:$disp, 1149 tglobaltlsaddr:$sym))]>, 1150 isPPC64; 1151def ADDIStlsldHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1152 "#ADDIStlsldHA", 1153 [(set i64:$rD, 1154 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1155 isPPC64; 1156def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1157 "#ADDItlsldL", 1158 [(set i64:$rD, 1159 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1160 isPPC64; 1161// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1162// explicitly defined when this op is created, so not mentioned here. 1163let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1164 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1165def GETtlsldADDR : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1166 "#GETtlsldADDR", 1167 [(set i64:$rD, 1168 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1169 isPPC64; 1170// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1171// are true defines, while the rest of the Defs are clobbers. 1172let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1173 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1174 in 1175def ADDItlsldLADDR : PPCEmitTimePseudo<(outs g8rc:$rD), 1176 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1177 "#ADDItlsldLADDR", 1178 [(set i64:$rD, 1179 (PPCaddiTlsldLAddr i64:$reg, 1180 tglobaltlsaddr:$disp, 1181 tglobaltlsaddr:$sym))]>, 1182 isPPC64; 1183def ADDISdtprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1184 "#ADDISdtprelHA", 1185 [(set i64:$rD, 1186 (PPCaddisDtprelHA i64:$reg, 1187 tglobaltlsaddr:$disp))]>, 1188 isPPC64; 1189def ADDIdtprelL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1190 "#ADDIdtprelL", 1191 [(set i64:$rD, 1192 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1193 isPPC64; 1194 1195let PPC970_Unit = 2 in { 1196let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1197// Truncating stores. 1198def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1199 "stb $rS, $src", IIC_LdStStore, 1200 [(truncstorei8 i64:$rS, iaddr:$src)]>; 1201def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1202 "sth $rS, $src", IIC_LdStStore, 1203 [(truncstorei16 i64:$rS, iaddr:$src)]>; 1204def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1205 "stw $rS, $src", IIC_LdStStore, 1206 [(truncstorei32 i64:$rS, iaddr:$src)]>; 1207def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1208 "stbx $rS, $dst", IIC_LdStStore, 1209 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 1210 PPC970_DGroup_Cracked; 1211def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1212 "sthx $rS, $dst", IIC_LdStStore, 1213 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 1214 PPC970_DGroup_Cracked; 1215def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1216 "stwx $rS, $dst", IIC_LdStStore, 1217 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 1218 PPC970_DGroup_Cracked; 1219} // Interpretation64Bit 1220 1221// Normal 8-byte stores. 1222def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1223 "std $rS, $dst", IIC_LdStSTD, 1224 [(aligned4store i64:$rS, iaddrX4:$dst)]>, isPPC64; 1225def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1226 "stdx $rS, $dst", IIC_LdStSTD, 1227 [(store i64:$rS, xaddrX4:$dst)]>, isPPC64, 1228 PPC970_DGroup_Cracked; 1229def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1230 "stdbrx $rS, $dst", IIC_LdStStore, 1231 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 1232 PPC970_DGroup_Cracked; 1233} 1234 1235// Stores with Update (pre-inc). 1236let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1237let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1238def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1239 "stbu $rS, $dst", IIC_LdStSTU, []>, 1240 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1241def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1242 "sthu $rS, $dst", IIC_LdStSTU, []>, 1243 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1244def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1245 "stwu $rS, $dst", IIC_LdStSTU, []>, 1246 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1247 1248def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 1249 (ins g8rc:$rS, memrr:$dst), 1250 "stbux $rS, $dst", IIC_LdStSTUX, []>, 1251 RegConstraint<"$dst.ptrreg = $ea_res">, 1252 NoEncode<"$ea_res">, 1253 PPC970_DGroup_Cracked; 1254def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 1255 (ins g8rc:$rS, memrr:$dst), 1256 "sthux $rS, $dst", IIC_LdStSTUX, []>, 1257 RegConstraint<"$dst.ptrreg = $ea_res">, 1258 NoEncode<"$ea_res">, 1259 PPC970_DGroup_Cracked; 1260def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 1261 (ins g8rc:$rS, memrr:$dst), 1262 "stwux $rS, $dst", IIC_LdStSTUX, []>, 1263 RegConstraint<"$dst.ptrreg = $ea_res">, 1264 NoEncode<"$ea_res">, 1265 PPC970_DGroup_Cracked; 1266} // Interpretation64Bit 1267 1268def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), 1269 (ins g8rc:$rS, memrix:$dst), 1270 "stdu $rS, $dst", IIC_LdStSTU, []>, 1271 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1272 isPPC64; 1273 1274def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), 1275 (ins g8rc:$rS, memrr:$dst), 1276 "stdux $rS, $dst", IIC_LdStSTUX, []>, 1277 RegConstraint<"$dst.ptrreg = $ea_res">, 1278 NoEncode<"$ea_res">, 1279 PPC970_DGroup_Cracked, isPPC64; 1280} 1281 1282// Patterns to match the pre-inc stores. We can't put the patterns on 1283// the instruction definitions directly as ISel wants the address base 1284// and offset to be separate operands, not a single complex operand. 1285def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1286 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1287def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1288 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1289def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1290 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1291def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1292 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1293 1294def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1295 (STBUX8 $rS, $ptrreg, $ptroff)>; 1296def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1297 (STHUX8 $rS, $ptrreg, $ptroff)>; 1298def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1299 (STWUX8 $rS, $ptrreg, $ptroff)>; 1300def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1301 (STDUX $rS, $ptrreg, $ptroff)>; 1302 1303 1304//===----------------------------------------------------------------------===// 1305// Floating point instructions. 1306// 1307 1308 1309let PPC970_Unit = 3, hasSideEffects = 0, 1310 Uses = [RM] in { // FPU Operations. 1311defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1312 "fcfid", "$frD, $frB", IIC_FPGeneral, 1313 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 1314defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1315 "fctid", "$frD, $frB", IIC_FPGeneral, 1316 []>, isPPC64; 1317defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB), 1318 "fctidu", "$frD, $frB", IIC_FPGeneral, 1319 []>, isPPC64; 1320defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1321 "fctidz", "$frD, $frB", IIC_FPGeneral, 1322 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 1323 1324defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1325 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1326 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 1327defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1328 "fcfids", "$frD, $frB", IIC_FPGeneral, 1329 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 1330defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1331 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1332 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 1333defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1334 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1335 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 1336defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1337 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1338 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 1339} 1340 1341 1342//===----------------------------------------------------------------------===// 1343// Instruction Patterns 1344// 1345 1346// Extensions and truncates to/from 32-bit regs. 1347def : Pat<(i64 (zext i32:$in)), 1348 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1349 0, 32)>; 1350def : Pat<(i64 (anyext i32:$in)), 1351 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1352def : Pat<(i32 (trunc i64:$in)), 1353 (EXTRACT_SUBREG $in, sub_32)>; 1354 1355// Implement the 'not' operation with the NOR instruction. 1356// (we could use the default xori pattern, but nor has lower latency on some 1357// cores (such as the A2)). 1358def i64not : OutPatFrag<(ops node:$in), 1359 (NOR8 $in, $in)>; 1360def : Pat<(not i64:$in), 1361 (i64not $in)>; 1362 1363// Extending loads with i64 targets. 1364def : Pat<(zextloadi1 iaddr:$src), 1365 (LBZ8 iaddr:$src)>; 1366def : Pat<(zextloadi1 xaddr:$src), 1367 (LBZX8 xaddr:$src)>; 1368def : Pat<(extloadi1 iaddr:$src), 1369 (LBZ8 iaddr:$src)>; 1370def : Pat<(extloadi1 xaddr:$src), 1371 (LBZX8 xaddr:$src)>; 1372def : Pat<(extloadi8 iaddr:$src), 1373 (LBZ8 iaddr:$src)>; 1374def : Pat<(extloadi8 xaddr:$src), 1375 (LBZX8 xaddr:$src)>; 1376def : Pat<(extloadi16 iaddr:$src), 1377 (LHZ8 iaddr:$src)>; 1378def : Pat<(extloadi16 xaddr:$src), 1379 (LHZX8 xaddr:$src)>; 1380def : Pat<(extloadi32 iaddr:$src), 1381 (LWZ8 iaddr:$src)>; 1382def : Pat<(extloadi32 xaddr:$src), 1383 (LWZX8 xaddr:$src)>; 1384 1385// Standard shifts. These are represented separately from the real shifts above 1386// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1387// amounts. 1388def : Pat<(sra i64:$rS, i32:$rB), 1389 (SRAD $rS, $rB)>; 1390def : Pat<(srl i64:$rS, i32:$rB), 1391 (SRD $rS, $rB)>; 1392def : Pat<(shl i64:$rS, i32:$rB), 1393 (SLD $rS, $rB)>; 1394 1395// SUBFIC 1396def : Pat<(sub imm64SExt16:$imm, i64:$in), 1397 (SUBFIC8 $in, imm:$imm)>; 1398 1399// SHL/SRL 1400def : Pat<(shl i64:$in, (i32 imm:$imm)), 1401 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1402def : Pat<(srl i64:$in, (i32 imm:$imm)), 1403 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1404 1405// ROTL 1406def : Pat<(rotl i64:$in, i32:$sh), 1407 (RLDCL $in, $sh, 0)>; 1408def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1409 (RLDICL $in, imm:$imm, 0)>; 1410 1411// Hi and Lo for Darwin Global Addresses. 1412def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1413def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1414def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1415def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1416def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1417def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1418def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1419def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1420def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1421 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1422def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1423 (ADDI8 $in, tglobaltlsaddr:$g)>; 1424def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1425 (ADDIS8 $in, tglobaladdr:$g)>; 1426def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1427 (ADDIS8 $in, tconstpool:$g)>; 1428def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1429 (ADDIS8 $in, tjumptable:$g)>; 1430def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1431 (ADDIS8 $in, tblockaddress:$g)>; 1432 1433// Patterns to match r+r indexed loads and stores for 1434// addresses without at least 4-byte alignment. 1435def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1436 (LWAX xoaddr:$src)>; 1437def : Pat<(i64 (unaligned4load xoaddr:$src)), 1438 (LDX xoaddr:$src)>; 1439def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1440 (STDX $rS, xoaddr:$dst)>; 1441 1442// 64-bits atomic loads and stores 1443def : Pat<(atomic_load_64 iaddrX4:$src), (LD memrix:$src)>; 1444def : Pat<(atomic_load_64 xaddrX4:$src), (LDX memrr:$src)>; 1445 1446def : Pat<(atomic_store_64 iaddrX4:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1447def : Pat<(atomic_store_64 xaddrX4:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1448 1449let Predicates = [IsISA3_0] in { 1450 1451class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1452 InstrItinClass itin, list<dag> pattern> 1453 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1454 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>; 1455 1456let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1457def CP_COPY8 : X_L1_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 1458def CP_PASTE8 : X_L1_RA5_RB5<31, 902, "paste" , g8rc, IIC_LdStPASTE, []>; 1459def CP_PASTE8o : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isDOT; 1460} 1461 1462// SLB Invalidate Entry Global 1463def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), 1464 "slbieg $RS, $RB", IIC_SprSLBIEG, []>; 1465// SLB Synchronize 1466def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 1467 1468} // IsISA3_0 1469