1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20 let EncoderMethod = "getImm16Encoding"; 21 let ParserMatchClass = PPCS16ImmAsmOperand; 22} 23def u16imm64 : Operand<i64> { 24 let PrintMethod = "printU16ImmOperand"; 25 let EncoderMethod = "getImm16Encoding"; 26 let ParserMatchClass = PPCU16ImmAsmOperand; 27} 28def s17imm64 : Operand<i64> { 29 // This operand type is used for addis/lis to allow the assembler parser 30 // to accept immediates in the range -65536..65535 for compatibility with 31 // the GNU assembler. The operand is treated as 16-bit otherwise. 32 let PrintMethod = "printS16ImmOperand"; 33 let EncoderMethod = "getImm16Encoding"; 34 let ParserMatchClass = PPCS17ImmAsmOperand; 35} 36def tocentry : Operand<iPTR> { 37 let MIOperandInfo = (ops i64imm:$imm); 38} 39def tlsreg : Operand<i64> { 40 let EncoderMethod = "getTLSRegEncoding"; 41} 42def tlsgd : Operand<i64> {} 43 44//===----------------------------------------------------------------------===// 45// 64-bit transformation functions. 46// 47 48def SHL64 : SDNodeXForm<imm, [{ 49 // Transformation function: 63 - imm 50 return getI32Imm(63 - N->getZExtValue()); 51}]>; 52 53def SRL64 : SDNodeXForm<imm, [{ 54 // Transformation function: 64 - imm 55 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 56}]>; 57 58def HI32_48 : SDNodeXForm<imm, [{ 59 // Transformation function: shift the immediate value down into the low bits. 60 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 61}]>; 62 63def HI48_64 : SDNodeXForm<imm, [{ 64 // Transformation function: shift the immediate value down into the low bits. 65 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 66}]>; 67 68 69//===----------------------------------------------------------------------===// 70// Calls. 71// 72 73let Interpretation64Bit = 1 in { 74let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 75 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 76 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 77 Requires<[In64BitMode]>; 78 79 let isCodeGenOnly = 1 in 80 def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 81 "b${cond:cc}ctr${cond:pm} ${cond:reg}", BrB, []>, 82 Requires<[In64BitMode]>; 83 } 84} 85 86let Defs = [LR8] in 87 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 88 PPC970_Unit_BRU; 89 90let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 91 let Defs = [CTR8], Uses = [CTR8] in { 92 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 93 "bdz $dst">; 94 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 95 "bdnz $dst">; 96 } 97 98 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 99 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 100 "bdzlr", BrB, []>; 101 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 102 "bdnzlr", BrB, []>; 103 } 104} 105 106 107 108let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 109 // Convenient aliases for call instructions 110 let Uses = [RM] in { 111 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 112 "bl $func", BrB, []>; // See Pat patterns below. 113 114 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 115 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>; 116 } 117 let Uses = [RM], isCodeGenOnly = 1 in { 118 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 119 (outs), (ins calltarget:$func), 120 "bl $func\n\tnop", BrB, []>; 121 122 def BL8_NOP_TLSGD : IForm_and_DForm_4_zero<18, 0, 1, 24, 123 (outs), (ins calltarget:$func, tlsgd:$sym), 124 "bl $func($sym)\n\tnop", BrB, []>; 125 126 def BL8_NOP_TLSLD : IForm_and_DForm_4_zero<18, 0, 1, 24, 127 (outs), (ins calltarget:$func, tlsgd:$sym), 128 "bl $func($sym)\n\tnop", BrB, []>; 129 130 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 131 (outs), (ins abscalltarget:$func), 132 "bla $func\n\tnop", BrB, 133 [(PPCcall_nop (i64 imm:$func))]>; 134 } 135 let Uses = [CTR8, RM] in { 136 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 137 "bctrl", BrB, [(PPCbctrl)]>, 138 Requires<[In64BitMode]>; 139 140 let isCodeGenOnly = 1 in 141 def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 142 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", BrB, []>, 143 Requires<[In64BitMode]>; 144 } 145} 146} // Interpretation64Bit 147 148// Calls 149def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 150 (BL8 tglobaladdr:$dst)>; 151def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 152 (BL8_NOP tglobaladdr:$dst)>; 153 154def : Pat<(PPCcall (i64 texternalsym:$dst)), 155 (BL8 texternalsym:$dst)>; 156def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 157 (BL8_NOP texternalsym:$dst)>; 158 159// Atomic operations 160let usesCustomInserter = 1 in { 161 let Defs = [CR0] in { 162 def ATOMIC_LOAD_ADD_I64 : Pseudo< 163 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 164 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 165 def ATOMIC_LOAD_SUB_I64 : Pseudo< 166 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 167 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 168 def ATOMIC_LOAD_OR_I64 : Pseudo< 169 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 170 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 171 def ATOMIC_LOAD_XOR_I64 : Pseudo< 172 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 173 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 174 def ATOMIC_LOAD_AND_I64 : Pseudo< 175 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 176 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 177 def ATOMIC_LOAD_NAND_I64 : Pseudo< 178 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 179 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 180 181 def ATOMIC_CMP_SWAP_I64 : Pseudo< 182 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 183 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 184 185 def ATOMIC_SWAP_I64 : Pseudo< 186 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 187 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 188 } 189} 190 191// Instructions to support atomic operations 192def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 193 "ldarx $rD, $ptr", LdStLDARX, 194 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>; 195 196let Defs = [CR0] in 197def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 198 "stdcx. $rS, $dst", LdStSTDCX, 199 [(PPCstcx i64:$rS, xoaddr:$dst)]>, 200 isDOT; 201 202let Interpretation64Bit = 1 in { 203let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 204def TCRETURNdi8 :Pseudo< (outs), 205 (ins calltarget:$dst, i32imm:$offset), 206 "#TC_RETURNd8 $dst $offset", 207 []>; 208 209let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 210def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 211 "#TC_RETURNa8 $func $offset", 212 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 213 214let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 215def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 216 "#TC_RETURNr8 $dst $offset", 217 []>; 218 219let isCodeGenOnly = 1 in { 220 221let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 222 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 223def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 224 Requires<[In64BitMode]>; 225 226 227let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 228 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 229def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 230 "b $dst", BrB, 231 []>; 232 233 234let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 235 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 236def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 237 "ba $dst", BrB, 238 []>; 239 240} 241} // Interpretation64Bit 242 243def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 244 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 245 246def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 247 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 248 249def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 250 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 251 252 253// 64-bit CR instructions 254let Interpretation64Bit = 1 in { 255let neverHasSideEffects = 1 in { 256def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins g8rc:$rS), 257 "mtcrf $FXM, $rS", BrMCRX>, 258 PPC970_MicroCode, PPC970_Unit_CRU; 259 260let isCodeGenOnly = 1 in 261def MFCR8pseud: XFXForm_3<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 262 "#MFCR8pseud", SprMFCR>, 263 PPC970_MicroCode, PPC970_Unit_CRU; 264} // neverHasSideEffects = 1 265 266let neverHasSideEffects = 1 in 267def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 268 "mfcr $rT", SprMFCR>, 269 PPC970_MicroCode, PPC970_Unit_CRU; 270 271let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 272 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 273 "#EH_SJLJ_SETJMP64", 274 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 275 Requires<[In64BitMode]>; 276 let isTerminator = 1 in 277 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf), 278 "#EH_SJLJ_LONGJMP64", 279 [(PPCeh_sjlj_longjmp addr:$buf)]>, 280 Requires<[In64BitMode]>; 281} 282 283//===----------------------------------------------------------------------===// 284// 64-bit SPR manipulation instrs. 285 286let Uses = [CTR8] in { 287def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 288 "mfctr $rT", SprMFSPR>, 289 PPC970_DGroup_First, PPC970_Unit_FXU; 290} 291let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 292def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 293 "mtctr $rS", SprMTSPR>, 294 PPC970_DGroup_First, PPC970_Unit_FXU; 295} 296let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR8] in { 297let Pattern = [(int_ppc_mtctr i64:$rS)] in 298def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 299 "mtctr $rS", SprMTSPR>, 300 PPC970_DGroup_First, PPC970_Unit_FXU; 301} 302 303let Pattern = [(set i64:$rT, readcyclecounter)] in 304def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 305 "mfspr $rT, 268", SprMFTB>, 306 PPC970_DGroup_First, PPC970_Unit_FXU; 307// Note that encoding mftb using mfspr is now the preferred form, 308// and has been since at least ISA v2.03. The mftb instruction has 309// now been phased out. Using mfspr, however, is known not to work on 310// the POWER3. 311 312let Defs = [X1], Uses = [X1] in 313def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 314 [(set i64:$result, 315 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 316 317let Defs = [LR8] in { 318def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 319 "mtlr $rS", SprMTSPR>, 320 PPC970_DGroup_First, PPC970_Unit_FXU; 321} 322let Uses = [LR8] in { 323def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 324 "mflr $rT", SprMFSPR>, 325 PPC970_DGroup_First, PPC970_Unit_FXU; 326} 327} // Interpretation64Bit 328 329//===----------------------------------------------------------------------===// 330// Fixed point instructions. 331// 332 333let PPC970_Unit = 1 in { // FXU Operations. 334let Interpretation64Bit = 1 in { 335let neverHasSideEffects = 1 in { 336 337let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 338def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 339 "li $rD, $imm", IntSimple, 340 [(set i64:$rD, imm64SExt16:$imm)]>; 341def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 342 "lis $rD, $imm", IntSimple, 343 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 344} 345 346// Logical ops. 347defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 348 "nand", "$rA, $rS, $rB", IntSimple, 349 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 350defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 351 "and", "$rA, $rS, $rB", IntSimple, 352 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 353defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 354 "andc", "$rA, $rS, $rB", IntSimple, 355 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 356defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 357 "or", "$rA, $rS, $rB", IntSimple, 358 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 359defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 360 "nor", "$rA, $rS, $rB", IntSimple, 361 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 362defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 363 "orc", "$rA, $rS, $rB", IntSimple, 364 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 365defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 366 "eqv", "$rA, $rS, $rB", IntSimple, 367 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 368defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 369 "xor", "$rA, $rS, $rB", IntSimple, 370 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 371 372// Logical ops with immediate. 373let Defs = [CR0] in { 374def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 375 "andi. $dst, $src1, $src2", IntGeneral, 376 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 377 isDOT; 378def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 379 "andis. $dst, $src1, $src2", IntGeneral, 380 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 381 isDOT; 382} 383def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 384 "ori $dst, $src1, $src2", IntSimple, 385 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 386def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 387 "oris $dst, $src1, $src2", IntSimple, 388 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 389def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 390 "xori $dst, $src1, $src2", IntSimple, 391 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 392def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 393 "xoris $dst, $src1, $src2", IntSimple, 394 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 395 396defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 397 "add", "$rT, $rA, $rB", IntSimple, 398 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 399// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 400// initial-exec thread-local storage model. 401let isCodeGenOnly = 1 in 402def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 403 "add $rT, $rA, $rB@tls", IntSimple, 404 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 405 406defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 407 "addc", "$rT, $rA, $rB", IntGeneral, 408 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 409 PPC970_DGroup_Cracked; 410let Defs = [CARRY] in 411def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 412 "addic $rD, $rA, $imm", IntGeneral, 413 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 414def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 415 "addi $rD, $rA, $imm", IntSimple, 416 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 417def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 418 "addis $rD, $rA, $imm", IntSimple, 419 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 420 421let Defs = [CARRY] in { 422def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 423 "subfic $rD, $rA, $imm", IntGeneral, 424 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 425defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 426 "subfc", "$rT, $rA, $rB", IntGeneral, 427 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 428 PPC970_DGroup_Cracked; 429} 430defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 431 "subf", "$rT, $rA, $rB", IntGeneral, 432 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 433defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 434 "neg", "$rT, $rA", IntSimple, 435 [(set i64:$rT, (ineg i64:$rA))]>; 436let Uses = [CARRY] in { 437defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 438 "adde", "$rT, $rA, $rB", IntGeneral, 439 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 440defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 441 "addme", "$rT, $rA", IntGeneral, 442 [(set i64:$rT, (adde i64:$rA, -1))]>; 443defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 444 "addze", "$rT, $rA", IntGeneral, 445 [(set i64:$rT, (adde i64:$rA, 0))]>; 446defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 447 "subfe", "$rT, $rA, $rB", IntGeneral, 448 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 449defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 450 "subfme", "$rT, $rA", IntGeneral, 451 [(set i64:$rT, (sube -1, i64:$rA))]>; 452defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 453 "subfze", "$rT, $rA", IntGeneral, 454 [(set i64:$rT, (sube 0, i64:$rA))]>; 455} 456 457 458defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 459 "mulhd", "$rT, $rA, $rB", IntMulHW, 460 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 461defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 462 "mulhdu", "$rT, $rA, $rB", IntMulHWU, 463 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 464} 465} // Interpretation64Bit 466 467let isCompare = 1, neverHasSideEffects = 1 in { 468 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 469 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 470 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 471 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 472 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm:$imm), 473 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 474 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm:$src2), 475 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 476} 477 478let neverHasSideEffects = 1 in { 479defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 480 "sld", "$rA, $rS, $rB", IntRotateD, 481 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 482defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 483 "srd", "$rA, $rS, $rB", IntRotateD, 484 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 485defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 486 "srad", "$rA, $rS, $rB", IntRotateD, 487 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 488 489let Interpretation64Bit = 1 in { 490defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 491 "extsb", "$rA, $rS", IntSimple, 492 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 493defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 494 "extsh", "$rA, $rS", IntSimple, 495 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 496} // Interpretation64Bit 497 498defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 499 "extsw", "$rA, $rS", IntSimple, 500 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 501let Interpretation64Bit = 1 in 502defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 503 "extsw", "$rA, $rS", IntSimple, 504 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 505 506defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 507 "sradi", "$rA, $rS, $SH", IntRotateDI, 508 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 509defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 510 "cntlzd", "$rA, $rS", IntGeneral, 511 [(set i64:$rA, (ctlz i64:$rS))]>; 512defm POPCNTD : XForm_11r<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 513 "popcntd", "$rA, $rS", IntGeneral, 514 [(set i64:$rA, (ctpop i64:$rS))]>; 515 516// popcntw also does a population count on the high 32 bits (storing the 517// results in the high 32-bits of the output). We'll ignore that here (which is 518// safe because we never separately use the high part of the 64-bit registers). 519defm POPCNTW : XForm_11r<31, 378, (outs gprc:$rA), (ins gprc:$rS), 520 "popcntw", "$rA, $rS", IntGeneral, 521 [(set i32:$rA, (ctpop i32:$rS))]>; 522 523defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 524 "divd", "$rT, $rA, $rB", IntDivD, 525 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64, 526 PPC970_DGroup_First, PPC970_DGroup_Cracked; 527defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 528 "divdu", "$rT, $rA, $rB", IntDivD, 529 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64, 530 PPC970_DGroup_First, PPC970_DGroup_Cracked; 531defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 532 "mulld", "$rT, $rA, $rB", IntMulHD, 533 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 534} 535 536let neverHasSideEffects = 1 in { 537let isCommutable = 1 in { 538defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 539 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 540 "rldimi", "$rA, $rS, $SH, $MBE", IntRotateDI, 541 []>, isPPC64, RegConstraint<"$rSi = $rA">, 542 NoEncode<"$rSi">; 543} 544 545// Rotate instructions. 546defm RLDCL : MDSForm_1r<30, 8, 547 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 548 "rldcl", "$rA, $rS, $rB, $MBE", IntRotateD, 549 []>, isPPC64; 550defm RLDCR : MDSForm_1r<30, 9, 551 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 552 "rldcr", "$rA, $rS, $rB, $MBE", IntRotateD, 553 []>, isPPC64; 554defm RLDICL : MDForm_1r<30, 0, 555 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 556 "rldicl", "$rA, $rS, $SH, $MBE", IntRotateDI, 557 []>, isPPC64; 558defm RLDICR : MDForm_1r<30, 1, 559 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 560 "rldicr", "$rA, $rS, $SH, $MBE", IntRotateDI, 561 []>, isPPC64; 562defm RLDIC : MDForm_1r<30, 2, 563 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 564 "rldic", "$rA, $rS, $SH, $MBE", IntRotateDI, 565 []>, isPPC64; 566 567let Interpretation64Bit = 1 in { 568defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 569 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 570 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IntGeneral, 571 []>; 572 573let isSelect = 1 in 574def ISEL8 : AForm_4<31, 15, 575 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 576 "isel $rT, $rA, $rB, $cond", IntGeneral, 577 []>; 578} // Interpretation64Bit 579} // neverHasSideEffects = 1 580} // End FXU Operations. 581 582 583//===----------------------------------------------------------------------===// 584// Load/Store instructions. 585// 586 587 588// Sign extending loads. 589let canFoldAsLoad = 1, PPC970_Unit = 2 in { 590let Interpretation64Bit = 1 in 591def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 592 "lha $rD, $src", LdStLHA, 593 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 594 PPC970_DGroup_Cracked; 595def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 596 "lwa $rD, $src", LdStLWA, 597 [(set i64:$rD, 598 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, 599 PPC970_DGroup_Cracked; 600let Interpretation64Bit = 1 in 601def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src), 602 "lhax $rD, $src", LdStLHA, 603 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 604 PPC970_DGroup_Cracked; 605def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src), 606 "lwax $rD, $src", LdStLHA, 607 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 608 PPC970_DGroup_Cracked; 609 610// Update forms. 611let mayLoad = 1, neverHasSideEffects = 1 in { 612let Interpretation64Bit = 1 in 613def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 614 (ins memri:$addr), 615 "lhau $rD, $addr", LdStLHAU, 616 []>, RegConstraint<"$addr.reg = $ea_result">, 617 NoEncode<"$ea_result">; 618// NO LWAU! 619 620let Interpretation64Bit = 1 in 621def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 622 (ins memrr:$addr), 623 "lhaux $rD, $addr", LdStLHAU, 624 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 625 NoEncode<"$ea_result">; 626def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 627 (ins memrr:$addr), 628 "lwaux $rD, $addr", LdStLHAU, 629 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 630 NoEncode<"$ea_result">, isPPC64; 631} 632} 633 634let Interpretation64Bit = 1 in { 635// Zero extending loads. 636let canFoldAsLoad = 1, PPC970_Unit = 2 in { 637def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 638 "lbz $rD, $src", LdStLoad, 639 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 640def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 641 "lhz $rD, $src", LdStLoad, 642 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 643def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 644 "lwz $rD, $src", LdStLoad, 645 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 646 647def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src), 648 "lbzx $rD, $src", LdStLoad, 649 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 650def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src), 651 "lhzx $rD, $src", LdStLoad, 652 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 653def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src), 654 "lwzx $rD, $src", LdStLoad, 655 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 656 657 658// Update forms. 659let mayLoad = 1, neverHasSideEffects = 1 in { 660def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 661 "lbzu $rD, $addr", LdStLoadUpd, 662 []>, RegConstraint<"$addr.reg = $ea_result">, 663 NoEncode<"$ea_result">; 664def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 665 "lhzu $rD, $addr", LdStLoadUpd, 666 []>, RegConstraint<"$addr.reg = $ea_result">, 667 NoEncode<"$ea_result">; 668def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 669 "lwzu $rD, $addr", LdStLoadUpd, 670 []>, RegConstraint<"$addr.reg = $ea_result">, 671 NoEncode<"$ea_result">; 672 673def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 674 (ins memrr:$addr), 675 "lbzux $rD, $addr", LdStLoadUpd, 676 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 677 NoEncode<"$ea_result">; 678def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 679 (ins memrr:$addr), 680 "lhzux $rD, $addr", LdStLoadUpd, 681 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 682 NoEncode<"$ea_result">; 683def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 684 (ins memrr:$addr), 685 "lwzux $rD, $addr", LdStLoadUpd, 686 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 687 NoEncode<"$ea_result">; 688} 689} 690} // Interpretation64Bit 691 692 693// Full 8-byte loads. 694let canFoldAsLoad = 1, PPC970_Unit = 2 in { 695def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 696 "ld $rD, $src", LdStLD, 697 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; 698// The following three definitions are selected for small code model only. 699// Otherwise, we need to create two instructions to form a 32-bit offset, 700// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 701def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 702 "#LDtoc", 703 [(set i64:$rD, 704 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 705def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 706 "#LDtocJTI", 707 [(set i64:$rD, 708 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 709def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 710 "#LDtocCPT", 711 [(set i64:$rD, 712 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 713 714let hasSideEffects = 1, isCodeGenOnly = 1 in { 715let RST = 2, DS = 2 in 716def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg), 717 "ld 2, 8($reg)", LdStLD, 718 [(PPCload_toc i64:$reg)]>, isPPC64; 719 720let RST = 2, DS = 10, RA = 1 in 721def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins), 722 "ld 2, 40(1)", LdStLD, 723 [(PPCtoc_restore)]>, isPPC64; 724} 725def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src), 726 "ldx $rD, $src", LdStLD, 727 [(set i64:$rD, (load xaddr:$src))]>, isPPC64; 728def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src), 729 "ldbrx $rD, $src", LdStLoad, 730 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 731 732let mayLoad = 1, neverHasSideEffects = 1 in { 733def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr), 734 "ldu $rD, $addr", LdStLDU, 735 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 736 NoEncode<"$ea_result">; 737 738def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 739 (ins memrr:$addr), 740 "ldux $rD, $addr", LdStLDU, 741 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 742 NoEncode<"$ea_result">, isPPC64; 743} 744} 745 746def : Pat<(PPCload ixaddr:$src), 747 (LD ixaddr:$src)>; 748def : Pat<(PPCload xaddr:$src), 749 (LDX xaddr:$src)>; 750 751// Support for medium and large code model. 752def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 753 "#ADDIStocHA", 754 [(set i64:$rD, 755 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>, 756 isPPC64; 757def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 758 "#LDtocL", 759 [(set i64:$rD, 760 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64; 761def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 762 "#ADDItocL", 763 [(set i64:$rD, 764 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64; 765 766// Support for thread-local storage. 767def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 768 "#ADDISgotTprelHA", 769 [(set i64:$rD, 770 (PPCaddisGotTprelHA i64:$reg, 771 tglobaltlsaddr:$disp))]>, 772 isPPC64; 773def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 774 "#LDgotTprelL", 775 [(set i64:$rD, 776 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 777 isPPC64; 778def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 779 (ADD8TLS $in, tglobaltlsaddr:$g)>; 780def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 781 "#ADDIStlsgdHA", 782 [(set i64:$rD, 783 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 784 isPPC64; 785def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 786 "#ADDItlsgdL", 787 [(set i64:$rD, 788 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 789 isPPC64; 790def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 791 "#GETtlsADDR", 792 [(set i64:$rD, 793 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 794 isPPC64; 795def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 796 "#ADDIStlsldHA", 797 [(set i64:$rD, 798 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 799 isPPC64; 800def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 801 "#ADDItlsldL", 802 [(set i64:$rD, 803 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 804 isPPC64; 805def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 806 "#GETtlsldADDR", 807 [(set i64:$rD, 808 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 809 isPPC64; 810def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 811 "#ADDISdtprelHA", 812 [(set i64:$rD, 813 (PPCaddisDtprelHA i64:$reg, 814 tglobaltlsaddr:$disp))]>, 815 isPPC64; 816def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 817 "#ADDIdtprelL", 818 [(set i64:$rD, 819 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 820 isPPC64; 821 822let PPC970_Unit = 2 in { 823let Interpretation64Bit = 1 in { 824// Truncating stores. 825def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 826 "stb $rS, $src", LdStStore, 827 [(truncstorei8 i64:$rS, iaddr:$src)]>; 828def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 829 "sth $rS, $src", LdStStore, 830 [(truncstorei16 i64:$rS, iaddr:$src)]>; 831def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 832 "stw $rS, $src", LdStStore, 833 [(truncstorei32 i64:$rS, iaddr:$src)]>; 834def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 835 "stbx $rS, $dst", LdStStore, 836 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 837 PPC970_DGroup_Cracked; 838def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 839 "sthx $rS, $dst", LdStStore, 840 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 841 PPC970_DGroup_Cracked; 842def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 843 "stwx $rS, $dst", LdStStore, 844 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 845 PPC970_DGroup_Cracked; 846} // Interpretation64Bit 847 848// Normal 8-byte stores. 849def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 850 "std $rS, $dst", LdStSTD, 851 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64; 852def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 853 "stdx $rS, $dst", LdStSTD, 854 [(store i64:$rS, xaddr:$dst)]>, isPPC64, 855 PPC970_DGroup_Cracked; 856def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 857 "stdbrx $rS, $dst", LdStStore, 858 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 859 PPC970_DGroup_Cracked; 860} 861 862// Stores with Update (pre-inc). 863let PPC970_Unit = 2, mayStore = 1 in { 864let Interpretation64Bit = 1 in { 865def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 866 "stbu $rS, $dst", LdStStoreUpd, []>, 867 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 868def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 869 "sthu $rS, $dst", LdStStoreUpd, []>, 870 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 871def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 872 "stwu $rS, $dst", LdStStoreUpd, []>, 873 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 874def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst), 875 "stdu $rS, $dst", LdStSTDU, []>, 876 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 877 isPPC64; 878 879def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 880 "stbux $rS, $dst", LdStStoreUpd, []>, 881 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 882 PPC970_DGroup_Cracked; 883def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 884 "sthux $rS, $dst", LdStStoreUpd, []>, 885 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 886 PPC970_DGroup_Cracked; 887def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 888 "stwux $rS, $dst", LdStStoreUpd, []>, 889 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 890 PPC970_DGroup_Cracked; 891} // Interpretation64Bit 892 893def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 894 "stdux $rS, $dst", LdStSTDU, []>, 895 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 896 PPC970_DGroup_Cracked, isPPC64; 897} 898 899// Patterns to match the pre-inc stores. We can't put the patterns on 900// the instruction definitions directly as ISel wants the address base 901// and offset to be separate operands, not a single complex operand. 902def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 903 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 904def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 905 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 906def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 907 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 908def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 909 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 910 911def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 912 (STBUX8 $rS, $ptrreg, $ptroff)>; 913def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 914 (STHUX8 $rS, $ptrreg, $ptroff)>; 915def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 916 (STWUX8 $rS, $ptrreg, $ptroff)>; 917def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 918 (STDUX $rS, $ptrreg, $ptroff)>; 919 920 921//===----------------------------------------------------------------------===// 922// Floating point instructions. 923// 924 925 926let PPC970_Unit = 3, neverHasSideEffects = 1, 927 Uses = [RM] in { // FPU Operations. 928defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 929 "fcfid", "$frD, $frB", FPGeneral, 930 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 931defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 932 "fctidz", "$frD, $frB", FPGeneral, 933 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 934 935defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 936 "fcfidu", "$frD, $frB", FPGeneral, 937 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 938defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 939 "fcfids", "$frD, $frB", FPGeneral, 940 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 941defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 942 "fcfidus", "$frD, $frB", FPGeneral, 943 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 944defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 945 "fctiduz", "$frD, $frB", FPGeneral, 946 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 947defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 948 "fctiwuz", "$frD, $frB", FPGeneral, 949 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 950} 951 952 953//===----------------------------------------------------------------------===// 954// Instruction Patterns 955// 956 957// Extensions and truncates to/from 32-bit regs. 958def : Pat<(i64 (zext i32:$in)), 959 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 960 0, 32)>; 961def : Pat<(i64 (anyext i32:$in)), 962 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 963def : Pat<(i32 (trunc i64:$in)), 964 (EXTRACT_SUBREG $in, sub_32)>; 965 966// Extending loads with i64 targets. 967def : Pat<(zextloadi1 iaddr:$src), 968 (LBZ8 iaddr:$src)>; 969def : Pat<(zextloadi1 xaddr:$src), 970 (LBZX8 xaddr:$src)>; 971def : Pat<(extloadi1 iaddr:$src), 972 (LBZ8 iaddr:$src)>; 973def : Pat<(extloadi1 xaddr:$src), 974 (LBZX8 xaddr:$src)>; 975def : Pat<(extloadi8 iaddr:$src), 976 (LBZ8 iaddr:$src)>; 977def : Pat<(extloadi8 xaddr:$src), 978 (LBZX8 xaddr:$src)>; 979def : Pat<(extloadi16 iaddr:$src), 980 (LHZ8 iaddr:$src)>; 981def : Pat<(extloadi16 xaddr:$src), 982 (LHZX8 xaddr:$src)>; 983def : Pat<(extloadi32 iaddr:$src), 984 (LWZ8 iaddr:$src)>; 985def : Pat<(extloadi32 xaddr:$src), 986 (LWZX8 xaddr:$src)>; 987 988// Standard shifts. These are represented separately from the real shifts above 989// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 990// amounts. 991def : Pat<(sra i64:$rS, i32:$rB), 992 (SRAD $rS, $rB)>; 993def : Pat<(srl i64:$rS, i32:$rB), 994 (SRD $rS, $rB)>; 995def : Pat<(shl i64:$rS, i32:$rB), 996 (SLD $rS, $rB)>; 997 998// SHL/SRL 999def : Pat<(shl i64:$in, (i32 imm:$imm)), 1000 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1001def : Pat<(srl i64:$in, (i32 imm:$imm)), 1002 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1003 1004// ROTL 1005def : Pat<(rotl i64:$in, i32:$sh), 1006 (RLDCL $in, $sh, 0)>; 1007def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1008 (RLDICL $in, imm:$imm, 0)>; 1009 1010// Hi and Lo for Darwin Global Addresses. 1011def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1012def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1013def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1014def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1015def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1016def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1017def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1018def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1019def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1020 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1021def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1022 (ADDI8 $in, tglobaltlsaddr:$g)>; 1023def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1024 (ADDIS8 $in, tglobaladdr:$g)>; 1025def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1026 (ADDIS8 $in, tconstpool:$g)>; 1027def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1028 (ADDIS8 $in, tjumptable:$g)>; 1029def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1030 (ADDIS8 $in, tblockaddress:$g)>; 1031 1032// Patterns to match r+r indexed loads and stores for 1033// addresses without at least 4-byte alignment. 1034def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1035 (LWAX xoaddr:$src)>; 1036def : Pat<(i64 (unaligned4load xoaddr:$src)), 1037 (LDX xoaddr:$src)>; 1038def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1039 (STDX $rS, xoaddr:$dst)>; 1040 1041