1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20 let EncoderMethod = "getImm16Encoding"; 21 let ParserMatchClass = PPCS16ImmAsmOperand; 22 let DecoderMethod = "decodeSImmOperand<16>"; 23} 24def u16imm64 : Operand<i64> { 25 let PrintMethod = "printU16ImmOperand"; 26 let EncoderMethod = "getImm16Encoding"; 27 let ParserMatchClass = PPCU16ImmAsmOperand; 28 let DecoderMethod = "decodeUImmOperand<16>"; 29} 30def s17imm64 : Operand<i64> { 31 // This operand type is used for addis/lis to allow the assembler parser 32 // to accept immediates in the range -65536..65535 for compatibility with 33 // the GNU assembler. The operand is treated as 16-bit otherwise. 34 let PrintMethod = "printS16ImmOperand"; 35 let EncoderMethod = "getImm16Encoding"; 36 let ParserMatchClass = PPCS17ImmAsmOperand; 37 let DecoderMethod = "decodeSImmOperand<16>"; 38} 39def tocentry : Operand<iPTR> { 40 let MIOperandInfo = (ops i64imm:$imm); 41} 42def tlsreg : Operand<i64> { 43 let EncoderMethod = "getTLSRegEncoding"; 44 let ParserMatchClass = PPCTLSRegOperand; 45} 46def tlsgd : Operand<i64> {} 47def tlscall : Operand<i64> { 48 let PrintMethod = "printTLSCall"; 49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 50 let EncoderMethod = "getTLSCallEncoding"; 51} 52 53//===----------------------------------------------------------------------===// 54// 64-bit transformation functions. 55// 56 57def SHL64 : SDNodeXForm<imm, [{ 58 // Transformation function: 63 - imm 59 return getI32Imm(63 - N->getZExtValue(), SDLoc(N)); 60}]>; 61 62def SRL64 : SDNodeXForm<imm, [{ 63 // Transformation function: 64 - imm 64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N)) 65 : getI32Imm(0, SDLoc(N)); 66}]>; 67 68 69//===----------------------------------------------------------------------===// 70// Calls. 71// 72 73let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 74let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 75 let isReturn = 1, Uses = [LR8, RM] in 76 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 77 [(retflag)]>, Requires<[In64BitMode]>; 78 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 79 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 80 []>, 81 Requires<[In64BitMode]>; 82 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 83 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 84 []>, 85 Requires<[In64BitMode]>; 86 87 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 88 "bcctr 12, $bi, 0", IIC_BrB, []>, 89 Requires<[In64BitMode]>; 90 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 91 "bcctr 4, $bi, 0", IIC_BrB, []>, 92 Requires<[In64BitMode]>; 93 } 94} 95 96let Defs = [LR8] in 97 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 98 PPC970_Unit_BRU; 99 100let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 101 let Defs = [CTR8], Uses = [CTR8] in { 102 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 103 "bdz $dst">; 104 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 105 "bdnz $dst">; 106 } 107 108 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 109 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 110 "bdzlr", IIC_BrB, []>; 111 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 112 "bdnzlr", IIC_BrB, []>; 113 } 114} 115 116 117 118let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 119 // Convenient aliases for call instructions 120 let Uses = [RM] in { 121 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 122 "bl $func", IIC_BrB, []>; // See Pat patterns below. 123 124 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 125 "bl $func", IIC_BrB, []>; 126 127 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 128 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; 129 } 130 let Uses = [RM], isCodeGenOnly = 1 in { 131 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 132 (outs), (ins calltarget:$func), 133 "bl $func\n\tnop", IIC_BrB, []>; 134 135 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 136 (outs), (ins tlscall:$func), 137 "bl $func\n\tnop", IIC_BrB, []>; 138 139 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 140 (outs), (ins abscalltarget:$func), 141 "bla $func\n\tnop", IIC_BrB, 142 [(PPCcall_nop (i64 imm:$func))]>; 143 } 144 let Uses = [CTR8, RM] in { 145 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 146 "bctrl", IIC_BrB, [(PPCbctrl)]>, 147 Requires<[In64BitMode]>; 148 149 let isCodeGenOnly = 1 in { 150 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 151 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 152 []>, 153 Requires<[In64BitMode]>; 154 155 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 156 "bcctrl 12, $bi, 0", IIC_BrB, []>, 157 Requires<[In64BitMode]>; 158 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 159 "bcctrl 4, $bi, 0", IIC_BrB, []>, 160 Requires<[In64BitMode]>; 161 } 162 } 163} 164 165let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 166 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in { 167 def BCTRL8_LDinto_toc : 168 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs), 169 (ins memrix:$src), 170 "bctrl\n\tld 2, $src", IIC_BrB, 171 [(PPCbctrl_load_toc ixaddr:$src)]>, 172 Requires<[In64BitMode]>; 173} 174 175} // Interpretation64Bit 176 177// FIXME: Duplicating this for the asm parser should be unnecessary, but the 178// previous definition must be marked as CodeGen only to prevent decoding 179// conflicts. 180let Interpretation64Bit = 1, isAsmParserOnly = 1 in 181let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in 182def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), 183 "bl $func", IIC_BrB, []>; 184 185// Calls 186def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 187 (BL8 tglobaladdr:$dst)>; 188def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 189 (BL8_NOP tglobaladdr:$dst)>; 190 191def : Pat<(PPCcall (i64 texternalsym:$dst)), 192 (BL8 texternalsym:$dst)>; 193def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 194 (BL8_NOP texternalsym:$dst)>; 195 196// Atomic operations 197// FIXME: some of these might be used with constant operands. This will result 198// in constant materialization instructions that may be redundant. We currently 199// clean this up in PPCMIPeephole with calls to 200// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 201// in the first place. 202let usesCustomInserter = 1 in { 203 let Defs = [CR0] in { 204 def ATOMIC_LOAD_ADD_I64 : Pseudo< 205 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 206 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 207 def ATOMIC_LOAD_SUB_I64 : Pseudo< 208 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 209 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 210 def ATOMIC_LOAD_OR_I64 : Pseudo< 211 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 212 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 213 def ATOMIC_LOAD_XOR_I64 : Pseudo< 214 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 215 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 216 def ATOMIC_LOAD_AND_I64 : Pseudo< 217 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 218 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 219 def ATOMIC_LOAD_NAND_I64 : Pseudo< 220 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 221 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 222 def ATOMIC_LOAD_MIN_I64 : Pseudo< 223 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64", 224 [(set i64:$dst, (atomic_load_min_64 xoaddr:$ptr, i64:$incr))]>; 225 def ATOMIC_LOAD_MAX_I64 : Pseudo< 226 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64", 227 [(set i64:$dst, (atomic_load_max_64 xoaddr:$ptr, i64:$incr))]>; 228 def ATOMIC_LOAD_UMIN_I64 : Pseudo< 229 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64", 230 [(set i64:$dst, (atomic_load_umin_64 xoaddr:$ptr, i64:$incr))]>; 231 def ATOMIC_LOAD_UMAX_I64 : Pseudo< 232 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64", 233 [(set i64:$dst, (atomic_load_umax_64 xoaddr:$ptr, i64:$incr))]>; 234 235 def ATOMIC_CMP_SWAP_I64 : Pseudo< 236 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 237 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 238 239 def ATOMIC_SWAP_I64 : Pseudo< 240 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 241 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 242 } 243} 244 245// Instructions to support atomic operations 246let mayLoad = 1, hasSideEffects = 0 in { 247def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 248 "ldarx $rD, $ptr", IIC_LdStLDARX, []>; 249 250// Instruction to support lock versions of atomics 251// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 252def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 253 "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT; 254 255let hasExtraDefRegAllocReq = 1 in 256def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), 257 "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, 258 Requires<[IsISA3_0]>; 259} 260 261let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 262def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 263 "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT; 264 265let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 266def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), 267 "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, 268 Requires<[IsISA3_0]>; 269 270let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 271let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 272def TCRETURNdi8 :Pseudo< (outs), 273 (ins calltarget:$dst, i32imm:$offset), 274 "#TC_RETURNd8 $dst $offset", 275 []>; 276 277let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 278def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 279 "#TC_RETURNa8 $func $offset", 280 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 281 282let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 283def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 284 "#TC_RETURNr8 $dst $offset", 285 []>; 286 287let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 288 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 289def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 290 []>, 291 Requires<[In64BitMode]>; 292 293let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 294 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 295def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 296 "b $dst", IIC_BrB, 297 []>; 298 299let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 300 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 301def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 302 "ba $dst", IIC_BrB, 303 []>; 304} // Interpretation64Bit 305 306def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 307 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 308 309def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 310 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 311 312def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 313 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 314 315 316// 64-bit CR instructions 317let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 318let hasSideEffects = 0 in { 319// mtocrf's input needs to be prepared by shifting by an amount dependent 320// on the cr register selected. Thus, post-ra anti-dep breaking must not 321// later change that register assignment. 322let hasExtraDefRegAllocReq = 1 in { 323def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 324 "mtocrf $FXM, $ST", IIC_BrMCRX>, 325 PPC970_DGroup_First, PPC970_Unit_CRU; 326 327// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 328// is dependent on the cr fields being set. 329def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 330 "mtcrf $FXM, $rS", IIC_BrMCRX>, 331 PPC970_MicroCode, PPC970_Unit_CRU; 332} // hasExtraDefRegAllocReq = 1 333 334// mfocrf's input needs to be prepared by shifting by an amount dependent 335// on the cr register selected. Thus, post-ra anti-dep breaking must not 336// later change that register assignment. 337let hasExtraSrcRegAllocReq = 1 in { 338def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 339 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 340 PPC970_DGroup_First, PPC970_Unit_CRU; 341 342// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 343// is dependent on the cr fields being copied. 344def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 345 "mfcr $rT", IIC_SprMFCR>, 346 PPC970_MicroCode, PPC970_Unit_CRU; 347} // hasExtraSrcRegAllocReq = 1 348} // hasSideEffects = 0 349 350let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 351 let Defs = [CTR8] in 352 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 353 "#EH_SJLJ_SETJMP64", 354 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 355 Requires<[In64BitMode]>; 356 let isTerminator = 1 in 357 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf), 358 "#EH_SJLJ_LONGJMP64", 359 [(PPCeh_sjlj_longjmp addr:$buf)]>, 360 Requires<[In64BitMode]>; 361} 362 363def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), 364 "mfspr $RT, $SPR", IIC_SprMFSPR>; 365def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), 366 "mtspr $SPR, $RT", IIC_SprMTSPR>; 367 368 369//===----------------------------------------------------------------------===// 370// 64-bit SPR manipulation instrs. 371 372let Uses = [CTR8] in { 373def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 374 "mfctr $rT", IIC_SprMFSPR>, 375 PPC970_DGroup_First, PPC970_Unit_FXU; 376} 377let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 378def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 379 "mtctr $rS", IIC_SprMTSPR>, 380 PPC970_DGroup_First, PPC970_Unit_FXU; 381} 382let hasSideEffects = 1, Defs = [CTR8] in { 383let Pattern = [(int_ppc_mtctr i64:$rS)] in 384def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 385 "mtctr $rS", IIC_SprMTSPR>, 386 PPC970_DGroup_First, PPC970_Unit_FXU; 387} 388 389let Pattern = [(set i64:$rT, readcyclecounter)] in 390def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 391 "mfspr $rT, 268", IIC_SprMFTB>, 392 PPC970_DGroup_First, PPC970_Unit_FXU; 393// Note that encoding mftb using mfspr is now the preferred form, 394// and has been since at least ISA v2.03. The mftb instruction has 395// now been phased out. Using mfspr, however, is known not to work on 396// the POWER3. 397 398let Defs = [X1], Uses = [X1] in 399def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 400 [(set i64:$result, 401 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 402def DYNAREAOFFSET8 : Pseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", 403 [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 404 405let Defs = [LR8] in { 406def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 407 "mtlr $rS", IIC_SprMTSPR>, 408 PPC970_DGroup_First, PPC970_Unit_FXU; 409} 410let Uses = [LR8] in { 411def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 412 "mflr $rT", IIC_SprMFSPR>, 413 PPC970_DGroup_First, PPC970_Unit_FXU; 414} 415} // Interpretation64Bit 416 417//===----------------------------------------------------------------------===// 418// Fixed point instructions. 419// 420 421let PPC970_Unit = 1 in { // FXU Operations. 422let Interpretation64Bit = 1 in { 423let hasSideEffects = 0 in { 424let isCodeGenOnly = 1 in { 425 426let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 427def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 428 "li $rD, $imm", IIC_IntSimple, 429 [(set i64:$rD, imm64SExt16:$imm)]>; 430def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 431 "lis $rD, $imm", IIC_IntSimple, 432 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 433} 434 435// Logical ops. 436let isCommutable = 1 in { 437defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 438 "nand", "$rA, $rS, $rB", IIC_IntSimple, 439 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 440defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 441 "and", "$rA, $rS, $rB", IIC_IntSimple, 442 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 443} // isCommutable 444defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 445 "andc", "$rA, $rS, $rB", IIC_IntSimple, 446 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 447let isCommutable = 1 in { 448defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 449 "or", "$rA, $rS, $rB", IIC_IntSimple, 450 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 451defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 452 "nor", "$rA, $rS, $rB", IIC_IntSimple, 453 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 454} // isCommutable 455defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 456 "orc", "$rA, $rS, $rB", IIC_IntSimple, 457 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 458let isCommutable = 1 in { 459defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 460 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 461 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 462defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 463 "xor", "$rA, $rS, $rB", IIC_IntSimple, 464 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 465} // let isCommutable = 1 466 467// Logical ops with immediate. 468let Defs = [CR0] in { 469def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 470 "andi. $dst, $src1, $src2", IIC_IntGeneral, 471 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 472 isDOT; 473def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 474 "andis. $dst, $src1, $src2", IIC_IntGeneral, 475 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 476 isDOT; 477} 478def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 479 "ori $dst, $src1, $src2", IIC_IntSimple, 480 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 481def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 482 "oris $dst, $src1, $src2", IIC_IntSimple, 483 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 484def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 485 "xori $dst, $src1, $src2", IIC_IntSimple, 486 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 487def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), 488 "xoris $dst, $src1, $src2", IIC_IntSimple, 489 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 490 491let isCommutable = 1 in 492defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 493 "add", "$rT, $rA, $rB", IIC_IntSimple, 494 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 495// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 496// initial-exec thread-local storage model. We need to forbid r0 here - 497// while it works for add just fine, the linker can relax this to local-exec 498// addi, which won't work for r0. 499def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), 500 "add $rT, $rA, $rB", IIC_IntSimple, 501 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 502let mayLoad = 1 in { 503def LBZXTLS : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 504 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 505def LHZXTLS : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 506 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 507def LWZXTLS : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 508 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 509def LDXTLS : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 510 "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; 511def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 512 "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; 513def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 514 "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; 515def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), 516 "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; 517 518} 519 520let mayStore = 1 in { 521def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 522 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 523 PPC970_DGroup_Cracked; 524def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 525 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 526 PPC970_DGroup_Cracked; 527def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 528 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 529 PPC970_DGroup_Cracked; 530def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 531 "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, 532 PPC970_DGroup_Cracked; 533def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 534 "stbx $rS, $rA, $rB", IIC_LdStStore, []>, 535 PPC970_DGroup_Cracked; 536def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 537 "sthx $rS, $rA, $rB", IIC_LdStStore, []>, 538 PPC970_DGroup_Cracked; 539def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), 540 "stwx $rS, $rA, $rB", IIC_LdStStore, []>, 541 PPC970_DGroup_Cracked; 542 543} 544 545let isCommutable = 1 in 546defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 547 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 548 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 549 PPC970_DGroup_Cracked; 550 551let Defs = [CARRY] in 552def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 553 "addic $rD, $rA, $imm", IIC_IntGeneral, 554 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 555def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 556 "addi $rD, $rA, $imm", IIC_IntSimple, 557 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 558def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 559 "addis $rD, $rA, $imm", IIC_IntSimple, 560 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 561 562let Defs = [CARRY] in { 563def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 564 "subfic $rD, $rA, $imm", IIC_IntGeneral, 565 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 566} 567defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 568 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 569 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 570 PPC970_DGroup_Cracked; 571defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 572 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 573 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 574defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 575 "neg", "$rT, $rA", IIC_IntSimple, 576 [(set i64:$rT, (ineg i64:$rA))]>; 577let Uses = [CARRY] in { 578let isCommutable = 1 in 579defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 580 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 581 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 582defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 583 "addme", "$rT, $rA", IIC_IntGeneral, 584 [(set i64:$rT, (adde i64:$rA, -1))]>; 585defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 586 "addze", "$rT, $rA", IIC_IntGeneral, 587 [(set i64:$rT, (adde i64:$rA, 0))]>; 588defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 589 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 590 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 591defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 592 "subfme", "$rT, $rA", IIC_IntGeneral, 593 [(set i64:$rT, (sube -1, i64:$rA))]>; 594defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 595 "subfze", "$rT, $rA", IIC_IntGeneral, 596 [(set i64:$rT, (sube 0, i64:$rA))]>; 597} 598} // isCodeGenOnly 599 600// FIXME: Duplicating this for the asm parser should be unnecessary, but the 601// previous definition must be marked as CodeGen only to prevent decoding 602// conflicts. 603let isAsmParserOnly = 1 in 604def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 605 "add $rT, $rA, $rB", IIC_IntSimple, []>; 606 607let isCommutable = 1 in { 608defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 609 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, 610 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 611defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 612 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, 613 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 614} // isCommutable 615} 616} // Interpretation64Bit 617 618let isCompare = 1, hasSideEffects = 0 in { 619 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 620 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 621 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 622 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; 623 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), 624 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; 625 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), 626 "cmpldi $dst, $src1, $src2", 627 IIC_IntCompare>, isPPC64; 628 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 629 def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF), 630 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 631 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 632 Requires<[IsISA3_0]>; 633 def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crbitrc:$BF), 634 (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", 635 IIC_IntCompare, []>, Requires<[IsISA3_0]>; 636} 637 638let hasSideEffects = 0 in { 639defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 640 "sld", "$rA, $rS, $rB", IIC_IntRotateD, 641 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 642defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 643 "srd", "$rA, $rS, $rB", IIC_IntRotateD, 644 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 645defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 646 "srad", "$rA, $rS, $rB", IIC_IntRotateD, 647 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 648 649let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 650defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), 651 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>; 652defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), 653 "cnttzw", "$rA, $rS", IIC_IntGeneral, []>, 654 Requires<[IsISA3_0]>; 655 656defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 657 "extsb", "$rA, $rS", IIC_IntSimple, 658 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 659defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 660 "extsh", "$rA, $rS", IIC_IntSimple, 661 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 662 663defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 664 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 665defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 666 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>; 667} // Interpretation64Bit 668 669// For fast-isel: 670let isCodeGenOnly = 1 in { 671def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), 672 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64; 673def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), 674 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64; 675} // isCodeGenOnly for fast-isel 676 677defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 678 "extsw", "$rA, $rS", IIC_IntSimple, 679 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 680let Interpretation64Bit = 1, isCodeGenOnly = 1 in 681defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 682 "extsw", "$rA, $rS", IIC_IntSimple, 683 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 684let isCodeGenOnly = 1 in 685def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS), 686 "extsw $rA, $rS", IIC_IntSimple, 687 []>, isPPC64; 688 689defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 690 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, 691 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 692 693defm EXTSWSLI : XSForm_1r<31, 445, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 694 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, 695 []>, isPPC64; 696 697// For fast-isel: 698let isCodeGenOnly = 1, Defs = [CARRY] in 699def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH), 700 "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64; 701 702defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 703 "cntlzd", "$rA, $rS", IIC_IntGeneral, 704 [(set i64:$rA, (ctlz i64:$rS))]>; 705defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), 706 "cnttzd", "$rA, $rS", IIC_IntGeneral, 707 [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>; 708def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 709 "popcntd $rA, $rS", IIC_IntGeneral, 710 [(set i64:$rA, (ctpop i64:$rS))]>; 711def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 712 "bpermd $rA, $rS, $rB", IIC_IntGeneral, 713 [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, 714 isPPC64, Requires<[HasBPERMD]>; 715 716let isCodeGenOnly = 1, isCommutable = 1 in 717def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 718 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 719 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; 720 721// popcntw also does a population count on the high 32 bits (storing the 722// results in the high 32-bits of the output). We'll ignore that here (which is 723// safe because we never separately use the high part of the 64-bit registers). 724def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), 725 "popcntw $rA, $rS", IIC_IntGeneral, 726 [(set i32:$rA, (ctpop i32:$rS))]>; 727 728def POPCNTB : XForm_11<31, 122, (outs gprc:$rA), (ins gprc:$rS), 729 "popcntb $rA, $rS", IIC_IntGeneral, []>; 730 731defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 732 "divd", "$rT, $rA, $rB", IIC_IntDivD, 733 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; 734defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 735 "divdu", "$rT, $rA, $rB", IIC_IntDivD, 736 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; 737def DIVDE : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 738 "divde $rT, $rA, $rB", IIC_IntDivD, 739 [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, 740 isPPC64, Requires<[HasExtDiv]>; 741 742let Predicates = [IsISA3_0] in { 743def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 744 "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 745def MADDHDU : VAForm_1a<49, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 746 "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 747def MADDLD : VAForm_1a<51, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), 748 "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; 749def SETB : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA), 750 "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; 751def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins i32imm:$L), 752 "darn $RT, $L", IIC_LdStLD>, isPPC64; 753def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D), 754 "addpcis $RT, $D", IIC_BrB, []>, isPPC64; 755def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 756 "modsd $rT, $rA, $rB", IIC_IntDivW, 757 [(set i64:$rT, (srem i64:$rA, i64:$rB))]>; 758def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 759 "modud $rT, $rA, $rB", IIC_IntDivW, 760 [(set i64:$rT, (urem i64:$rA, i64:$rB))]>; 761} 762 763let Defs = [CR0] in 764def DIVDEo : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 765 "divde. $rT, $rA, $rB", IIC_IntDivD, 766 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 767 isPPC64, Requires<[HasExtDiv]>; 768def DIVDEU : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 769 "divdeu $rT, $rA, $rB", IIC_IntDivD, 770 [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, 771 isPPC64, Requires<[HasExtDiv]>; 772let Defs = [CR0] in 773def DIVDEUo : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 774 "divdeu. $rT, $rA, $rB", IIC_IntDivD, 775 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 776 isPPC64, Requires<[HasExtDiv]>; 777let isCommutable = 1 in 778defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 779 "mulld", "$rT, $rA, $rB", IIC_IntMulHD, 780 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 781let Interpretation64Bit = 1, isCodeGenOnly = 1 in 782def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 783 "mulli $rD, $rA, $imm", IIC_IntMulLI, 784 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 785} 786 787let hasSideEffects = 0 in { 788defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 789 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 790 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 791 []>, isPPC64, RegConstraint<"$rSi = $rA">, 792 NoEncode<"$rSi">; 793 794// Rotate instructions. 795defm RLDCL : MDSForm_1r<30, 8, 796 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 797 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 798 []>, isPPC64; 799defm RLDCR : MDSForm_1r<30, 9, 800 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 801 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, 802 []>, isPPC64; 803defm RLDICL : MDForm_1r<30, 0, 804 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 805 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 806 []>, isPPC64; 807// For fast-isel: 808let isCodeGenOnly = 1 in 809def RLDICL_32_64 : MDForm_1<30, 0, 810 (outs g8rc:$rA), 811 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 812 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 813 []>, isPPC64; 814// End fast-isel. 815let Interpretation64Bit = 1, isCodeGenOnly = 1 in 816defm RLDICL_32 : MDForm_1r<30, 0, 817 (outs gprc:$rA), 818 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 819 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 820 []>, isPPC64; 821defm RLDICR : MDForm_1r<30, 1, 822 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 823 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 824 []>, isPPC64; 825let isCodeGenOnly = 1 in 826def RLDICR_32 : MDForm_1<30, 1, 827 (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), 828 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI, 829 []>, isPPC64; 830defm RLDIC : MDForm_1r<30, 2, 831 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 832 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, 833 []>, isPPC64; 834 835let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 836defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 837 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 838 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 839 []>; 840 841defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), 842 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), 843 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 844 []>; 845 846// RLWIMI can be commuted if the rotate amount is zero. 847let Interpretation64Bit = 1, isCodeGenOnly = 1 in 848defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), 849 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, 850 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 851 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 852 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 853 854let isSelect = 1 in 855def ISEL8 : AForm_4<31, 15, 856 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 857 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 858 []>; 859} // Interpretation64Bit 860} // hasSideEffects = 0 861} // End FXU Operations. 862 863 864//===----------------------------------------------------------------------===// 865// Load/Store instructions. 866// 867 868 869// Sign extending loads. 870let PPC970_Unit = 2 in { 871let Interpretation64Bit = 1, isCodeGenOnly = 1 in 872def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 873 "lha $rD, $src", IIC_LdStLHA, 874 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 875 PPC970_DGroup_Cracked; 876def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 877 "lwa $rD, $src", IIC_LdStLWA, 878 [(set i64:$rD, 879 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, 880 PPC970_DGroup_Cracked; 881let Interpretation64Bit = 1, isCodeGenOnly = 1 in 882def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src), 883 "lhax $rD, $src", IIC_LdStLHA, 884 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 885 PPC970_DGroup_Cracked; 886def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src), 887 "lwax $rD, $src", IIC_LdStLHA, 888 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 889 PPC970_DGroup_Cracked; 890// For fast-isel: 891let isCodeGenOnly = 1, mayLoad = 1 in { 892def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), 893 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, 894 PPC970_DGroup_Cracked; 895def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src), 896 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, 897 PPC970_DGroup_Cracked; 898} // end fast-isel isCodeGenOnly 899 900// Update forms. 901let mayLoad = 1, hasSideEffects = 0 in { 902let Interpretation64Bit = 1, isCodeGenOnly = 1 in 903def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 904 (ins memri:$addr), 905 "lhau $rD, $addr", IIC_LdStLHAU, 906 []>, RegConstraint<"$addr.reg = $ea_result">, 907 NoEncode<"$ea_result">; 908// NO LWAU! 909 910let Interpretation64Bit = 1, isCodeGenOnly = 1 in 911def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 912 (ins memrr:$addr), 913 "lhaux $rD, $addr", IIC_LdStLHAUX, 914 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 915 NoEncode<"$ea_result">; 916def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 917 (ins memrr:$addr), 918 "lwaux $rD, $addr", IIC_LdStLHAUX, 919 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 920 NoEncode<"$ea_result">, isPPC64; 921} 922} 923 924let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 925// Zero extending loads. 926let PPC970_Unit = 2 in { 927def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 928 "lbz $rD, $src", IIC_LdStLoad, 929 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 930def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 931 "lhz $rD, $src", IIC_LdStLoad, 932 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 933def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 934 "lwz $rD, $src", IIC_LdStLoad, 935 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 936 937def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src), 938 "lbzx $rD, $src", IIC_LdStLoad, 939 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 940def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src), 941 "lhzx $rD, $src", IIC_LdStLoad, 942 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 943def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src), 944 "lwzx $rD, $src", IIC_LdStLoad, 945 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 946 947 948// Update forms. 949let mayLoad = 1, hasSideEffects = 0 in { 950def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 951 (ins memri:$addr), 952 "lbzu $rD, $addr", IIC_LdStLoadUpd, 953 []>, RegConstraint<"$addr.reg = $ea_result">, 954 NoEncode<"$ea_result">; 955def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 956 (ins memri:$addr), 957 "lhzu $rD, $addr", IIC_LdStLoadUpd, 958 []>, RegConstraint<"$addr.reg = $ea_result">, 959 NoEncode<"$ea_result">; 960def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 961 (ins memri:$addr), 962 "lwzu $rD, $addr", IIC_LdStLoadUpd, 963 []>, RegConstraint<"$addr.reg = $ea_result">, 964 NoEncode<"$ea_result">; 965 966def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 967 (ins memrr:$addr), 968 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 969 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 970 NoEncode<"$ea_result">; 971def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 972 (ins memrr:$addr), 973 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 974 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 975 NoEncode<"$ea_result">; 976def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 977 (ins memrr:$addr), 978 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 979 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 980 NoEncode<"$ea_result">; 981} 982} 983} // Interpretation64Bit 984 985 986// Full 8-byte loads. 987let PPC970_Unit = 2 in { 988def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 989 "ld $rD, $src", IIC_LdStLD, 990 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; 991// The following four definitions are selected for small code model only. 992// Otherwise, we need to create two instructions to form a 32-bit offset, 993// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 994def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 995 "#LDtoc", 996 [(set i64:$rD, 997 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 998def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 999 "#LDtocJTI", 1000 [(set i64:$rD, 1001 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 1002def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1003 "#LDtocCPT", 1004 [(set i64:$rD, 1005 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 1006def LDtocBA: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 1007 "#LDtocCPT", 1008 [(set i64:$rD, 1009 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; 1010 1011def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src), 1012 "ldx $rD, $src", IIC_LdStLD, 1013 [(set i64:$rD, (load xaddr:$src))]>, isPPC64; 1014def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src), 1015 "ldbrx $rD, $src", IIC_LdStLoad, 1016 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 1017 1018let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { 1019def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src), 1020 "lhbrx $rD, $src", IIC_LdStLoad, []>; 1021def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src), 1022 "lwbrx $rD, $src", IIC_LdStLoad, []>; 1023} 1024 1025let mayLoad = 1, hasSideEffects = 0 in { 1026def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1027 (ins memrix:$addr), 1028 "ldu $rD, $addr", IIC_LdStLDU, 1029 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 1030 NoEncode<"$ea_result">; 1031 1032def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 1033 (ins memrr:$addr), 1034 "ldux $rD, $addr", IIC_LdStLDUX, 1035 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1036 NoEncode<"$ea_result">, isPPC64; 1037 1038def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src), 1039 "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64, 1040 Requires<[IsISA3_0]>; 1041} 1042} 1043 1044// Support for medium and large code model. 1045let hasSideEffects = 0 in { 1046let isReMaterializable = 1 in { 1047def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1048 "#ADDIStocHA", []>, isPPC64; 1049def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 1050 "#ADDItocL", []>, isPPC64; 1051} 1052let mayLoad = 1 in 1053def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 1054 "#LDtocL", []>, isPPC64; 1055} 1056 1057// Support for thread-local storage. 1058def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1059 "#ADDISgotTprelHA", 1060 [(set i64:$rD, 1061 (PPCaddisGotTprelHA i64:$reg, 1062 tglobaltlsaddr:$disp))]>, 1063 isPPC64; 1064def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 1065 "#LDgotTprelL", 1066 [(set i64:$rD, 1067 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 1068 isPPC64; 1069 1070let isPseudo = 1, Defs = [CR7], Itinerary = IIC_LdStSync in 1071def CFENCE8 : Pseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>; 1072 1073def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 1074 (ADD8TLS $in, tglobaltlsaddr:$g)>; 1075def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1076 "#ADDIStlsgdHA", 1077 [(set i64:$rD, 1078 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 1079 isPPC64; 1080def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1081 "#ADDItlsgdL", 1082 [(set i64:$rD, 1083 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 1084 isPPC64; 1085// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1086// explicitly defined when this op is created, so not mentioned here. 1087// This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be 1088// correct because the branch select pass is relying on it. 1089let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, Size = 8, 1090 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1091def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1092 "#GETtlsADDR", 1093 [(set i64:$rD, 1094 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1095 isPPC64; 1096// Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 1097// are true defines while the rest of the Defs are clobbers. 1098let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1099 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1100 in 1101def ADDItlsgdLADDR : Pseudo<(outs g8rc:$rD), 1102 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1103 "#ADDItlsgdLADDR", 1104 [(set i64:$rD, 1105 (PPCaddiTlsgdLAddr i64:$reg, 1106 tglobaltlsaddr:$disp, 1107 tglobaltlsaddr:$sym))]>, 1108 isPPC64; 1109def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1110 "#ADDIStlsldHA", 1111 [(set i64:$rD, 1112 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 1113 isPPC64; 1114def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1115 "#ADDItlsldL", 1116 [(set i64:$rD, 1117 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 1118 isPPC64; 1119// LR8 is a true define, while the rest of the Defs are clobbers. X3 is 1120// explicitly defined when this op is created, so not mentioned here. 1121let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1122 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in 1123def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 1124 "#GETtlsldADDR", 1125 [(set i64:$rD, 1126 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 1127 isPPC64; 1128// Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 1129// are true defines, while the rest of the Defs are clobbers. 1130let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 1131 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] 1132 in 1133def ADDItlsldLADDR : Pseudo<(outs g8rc:$rD), 1134 (ins g8rc_nox0:$reg, s16imm64:$disp, tlsgd:$sym), 1135 "#ADDItlsldLADDR", 1136 [(set i64:$rD, 1137 (PPCaddiTlsldLAddr i64:$reg, 1138 tglobaltlsaddr:$disp, 1139 tglobaltlsaddr:$sym))]>, 1140 isPPC64; 1141def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1142 "#ADDISdtprelHA", 1143 [(set i64:$rD, 1144 (PPCaddisDtprelHA i64:$reg, 1145 tglobaltlsaddr:$disp))]>, 1146 isPPC64; 1147def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 1148 "#ADDIdtprelL", 1149 [(set i64:$rD, 1150 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 1151 isPPC64; 1152 1153let PPC970_Unit = 2 in { 1154let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1155// Truncating stores. 1156def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 1157 "stb $rS, $src", IIC_LdStStore, 1158 [(truncstorei8 i64:$rS, iaddr:$src)]>; 1159def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 1160 "sth $rS, $src", IIC_LdStStore, 1161 [(truncstorei16 i64:$rS, iaddr:$src)]>; 1162def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 1163 "stw $rS, $src", IIC_LdStStore, 1164 [(truncstorei32 i64:$rS, iaddr:$src)]>; 1165def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 1166 "stbx $rS, $dst", IIC_LdStStore, 1167 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 1168 PPC970_DGroup_Cracked; 1169def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 1170 "sthx $rS, $dst", IIC_LdStStore, 1171 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 1172 PPC970_DGroup_Cracked; 1173def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 1174 "stwx $rS, $dst", IIC_LdStStore, 1175 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 1176 PPC970_DGroup_Cracked; 1177} // Interpretation64Bit 1178 1179// Normal 8-byte stores. 1180def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 1181 "std $rS, $dst", IIC_LdStSTD, 1182 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64; 1183def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 1184 "stdx $rS, $dst", IIC_LdStSTD, 1185 [(store i64:$rS, xaddr:$dst)]>, isPPC64, 1186 PPC970_DGroup_Cracked; 1187def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 1188 "stdbrx $rS, $dst", IIC_LdStStore, 1189 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 1190 PPC970_DGroup_Cracked; 1191} 1192 1193// Stores with Update (pre-inc). 1194let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 1195let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1196def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1197 "stbu $rS, $dst", IIC_LdStStoreUpd, []>, 1198 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1199def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1200 "sthu $rS, $dst", IIC_LdStStoreUpd, []>, 1201 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1202def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 1203 "stwu $rS, $dst", IIC_LdStStoreUpd, []>, 1204 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1205 1206def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 1207 (ins g8rc:$rS, memrr:$dst), 1208 "stbux $rS, $dst", IIC_LdStStoreUpd, []>, 1209 RegConstraint<"$dst.ptrreg = $ea_res">, 1210 NoEncode<"$ea_res">, 1211 PPC970_DGroup_Cracked; 1212def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 1213 (ins g8rc:$rS, memrr:$dst), 1214 "sthux $rS, $dst", IIC_LdStStoreUpd, []>, 1215 RegConstraint<"$dst.ptrreg = $ea_res">, 1216 NoEncode<"$ea_res">, 1217 PPC970_DGroup_Cracked; 1218def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 1219 (ins g8rc:$rS, memrr:$dst), 1220 "stwux $rS, $dst", IIC_LdStStoreUpd, []>, 1221 RegConstraint<"$dst.ptrreg = $ea_res">, 1222 NoEncode<"$ea_res">, 1223 PPC970_DGroup_Cracked; 1224} // Interpretation64Bit 1225 1226def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), 1227 (ins g8rc:$rS, memrix:$dst), 1228 "stdu $rS, $dst", IIC_LdStSTDU, []>, 1229 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 1230 isPPC64; 1231 1232def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), 1233 (ins g8rc:$rS, memrr:$dst), 1234 "stdux $rS, $dst", IIC_LdStSTDUX, []>, 1235 RegConstraint<"$dst.ptrreg = $ea_res">, 1236 NoEncode<"$ea_res">, 1237 PPC970_DGroup_Cracked, isPPC64; 1238} 1239 1240// Patterns to match the pre-inc stores. We can't put the patterns on 1241// the instruction definitions directly as ISel wants the address base 1242// and offset to be separate operands, not a single complex operand. 1243def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1244 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1245def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1246 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1247def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1248 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 1249def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1250 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 1251 1252def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1253 (STBUX8 $rS, $ptrreg, $ptroff)>; 1254def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1255 (STHUX8 $rS, $ptrreg, $ptroff)>; 1256def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1257 (STWUX8 $rS, $ptrreg, $ptroff)>; 1258def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1259 (STDUX $rS, $ptrreg, $ptroff)>; 1260 1261 1262//===----------------------------------------------------------------------===// 1263// Floating point instructions. 1264// 1265 1266 1267let PPC970_Unit = 3, hasSideEffects = 0, 1268 Uses = [RM] in { // FPU Operations. 1269defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 1270 "fcfid", "$frD, $frB", IIC_FPGeneral, 1271 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 1272defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), 1273 "fctid", "$frD, $frB", IIC_FPGeneral, 1274 []>, isPPC64; 1275defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB), 1276 "fctidu", "$frD, $frB", IIC_FPGeneral, 1277 []>, isPPC64; 1278defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 1279 "fctidz", "$frD, $frB", IIC_FPGeneral, 1280 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 1281 1282defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 1283 "fcfidu", "$frD, $frB", IIC_FPGeneral, 1284 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 1285defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 1286 "fcfids", "$frD, $frB", IIC_FPGeneral, 1287 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 1288defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 1289 "fcfidus", "$frD, $frB", IIC_FPGeneral, 1290 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 1291defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 1292 "fctiduz", "$frD, $frB", IIC_FPGeneral, 1293 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 1294defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 1295 "fctiwuz", "$frD, $frB", IIC_FPGeneral, 1296 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 1297} 1298 1299 1300//===----------------------------------------------------------------------===// 1301// Instruction Patterns 1302// 1303 1304// Extensions and truncates to/from 32-bit regs. 1305def : Pat<(i64 (zext i32:$in)), 1306 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 1307 0, 32)>; 1308def : Pat<(i64 (anyext i32:$in)), 1309 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 1310def : Pat<(i32 (trunc i64:$in)), 1311 (EXTRACT_SUBREG $in, sub_32)>; 1312 1313// Implement the 'not' operation with the NOR instruction. 1314// (we could use the default xori pattern, but nor has lower latency on some 1315// cores (such as the A2)). 1316def i64not : OutPatFrag<(ops node:$in), 1317 (NOR8 $in, $in)>; 1318def : Pat<(not i64:$in), 1319 (i64not $in)>; 1320 1321// Extending loads with i64 targets. 1322def : Pat<(zextloadi1 iaddr:$src), 1323 (LBZ8 iaddr:$src)>; 1324def : Pat<(zextloadi1 xaddr:$src), 1325 (LBZX8 xaddr:$src)>; 1326def : Pat<(extloadi1 iaddr:$src), 1327 (LBZ8 iaddr:$src)>; 1328def : Pat<(extloadi1 xaddr:$src), 1329 (LBZX8 xaddr:$src)>; 1330def : Pat<(extloadi8 iaddr:$src), 1331 (LBZ8 iaddr:$src)>; 1332def : Pat<(extloadi8 xaddr:$src), 1333 (LBZX8 xaddr:$src)>; 1334def : Pat<(extloadi16 iaddr:$src), 1335 (LHZ8 iaddr:$src)>; 1336def : Pat<(extloadi16 xaddr:$src), 1337 (LHZX8 xaddr:$src)>; 1338def : Pat<(extloadi32 iaddr:$src), 1339 (LWZ8 iaddr:$src)>; 1340def : Pat<(extloadi32 xaddr:$src), 1341 (LWZX8 xaddr:$src)>; 1342 1343// Standard shifts. These are represented separately from the real shifts above 1344// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1345// amounts. 1346def : Pat<(sra i64:$rS, i32:$rB), 1347 (SRAD $rS, $rB)>; 1348def : Pat<(srl i64:$rS, i32:$rB), 1349 (SRD $rS, $rB)>; 1350def : Pat<(shl i64:$rS, i32:$rB), 1351 (SLD $rS, $rB)>; 1352 1353// SUBFIC 1354def : Pat<(sub imm64SExt16:$imm, i64:$in), 1355 (SUBFIC8 $in, imm:$imm)>; 1356 1357// SHL/SRL 1358def : Pat<(shl i64:$in, (i32 imm:$imm)), 1359 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1360def : Pat<(srl i64:$in, (i32 imm:$imm)), 1361 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1362 1363// ROTL 1364def : Pat<(rotl i64:$in, i32:$sh), 1365 (RLDCL $in, $sh, 0)>; 1366def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1367 (RLDICL $in, imm:$imm, 0)>; 1368 1369// Hi and Lo for Darwin Global Addresses. 1370def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1371def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1372def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1373def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1374def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1375def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1376def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1377def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1378def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1379 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1380def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1381 (ADDI8 $in, tglobaltlsaddr:$g)>; 1382def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1383 (ADDIS8 $in, tglobaladdr:$g)>; 1384def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1385 (ADDIS8 $in, tconstpool:$g)>; 1386def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1387 (ADDIS8 $in, tjumptable:$g)>; 1388def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1389 (ADDIS8 $in, tblockaddress:$g)>; 1390 1391// Patterns to match r+r indexed loads and stores for 1392// addresses without at least 4-byte alignment. 1393def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1394 (LWAX xoaddr:$src)>; 1395def : Pat<(i64 (unaligned4load xoaddr:$src)), 1396 (LDX xoaddr:$src)>; 1397def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1398 (STDX $rS, xoaddr:$dst)>; 1399 1400// 64-bits atomic loads and stores 1401def : Pat<(atomic_load_64 ixaddr:$src), (LD memrix:$src)>; 1402def : Pat<(atomic_load_64 xaddr:$src), (LDX memrr:$src)>; 1403 1404def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; 1405def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; 1406 1407let Predicates = [IsISA3_0] in { 1408 1409class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty, 1410 InstrItinClass itin, list<dag> pattern> 1411 : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L), 1412 !strconcat(opc, " $rA, $rB, $L"), itin, pattern>; 1413 1414let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1415def CP_COPY8 : X_L1_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; 1416def CP_PASTE8 : X_L1_RA5_RB5<31, 902, "paste" , g8rc, IIC_LdStPASTE, []>; 1417def CP_PASTE8o : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isDOT; 1418} 1419 1420// SLB Invalidate Entry Global 1421def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), 1422 "slbieg $RS, $RB", IIC_SprSLBIEG, []>; 1423// SLB Synchronize 1424def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; 1425 1426} // IsISA3_0 1427